Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1639

1

T1

5

T2

1

T5

1

auto[1]

1734

1

T1

2

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T1	1		T2	1		T8	2
auto[134217728:268435455]	101	1			T6	1		T46	1		T125	1
auto[268435456:402653183]	102	1			T1	1		T16	1		T18	2
auto[402653184:536870911]	97	1			T1	1		T5	1		T15	1
auto[536870912:671088639]	123	1			T15	1		T83	1		T189	1
auto[671088640:805306367]	92	1			T1	1		T119	2		T65	1
auto[805306368:939524095]	111	1			T15	1		T16	1		T18	1
auto[939524096:1073741823]	122	1			T6	1		T46	1		T55	1
auto[1073741824:1207959551]	97	1			T15	1		T83	1		T49	1
auto[1207959552:1342177279]	92	1			T6	1		T46	2		T47	1
auto[1342177280:1476395007]	112	1			T15	1		T83	1		T6	2
auto[1476395008:1610612735]	103	1			T1	1		T3	1		T6	2
auto[1610612736:1744830463]	105	1			T1	1		T15	1		T18	2
auto[1744830464:1879048191]	116	1			T18	2		T6	1		T46	2
auto[1879048192:2013265919]	103	1			T5	1		T14	1		T15	2
auto[2013265920:2147483647]	104	1			T16	1		T37	1		T6	1
auto[2147483648:2281701375]	111	1			T14	1		T15	1		T6	3
auto[2281701376:2415919103]	110	1			T34	1		T6	1		T46	2
auto[2415919104:2550136831]	86	1			T14	1		T15	2		T6	2
auto[2550136832:2684354559]	105	1			T15	1		T18	1		T6	2
auto[2684354560:2818572287]	109	1			T16	1		T37	1		T6	1
auto[2818572288:2952790015]	112	1			T34	1		T6	1		T46	1
auto[2952790016:3087007743]	91	1			T37	1		T6	1		T46	2
auto[3087007744:3221225471]	104	1			T15	1		T46	2		T192	1
auto[3221225472:3355443199]	115	1			T14	1		T15	1		T6	2
auto[3355443200:3489660927]	93	1			T1	1		T15	1		T46	2
auto[3489660928:3623878655]	117	1			T34	1		T6	4		T46	3
auto[3623878656:3758096383]	95	1			T14	1		T46	1		T7	1
auto[3758096384:3892314111]	105	1			T46	1		T55	1		T7	1
auto[3892314112:4026531839]	105	1			T83	1		T6	1		T46	2
auto[4026531840:4160749567]	115	1			T18	1		T6	1		T60	1
auto[4160749568:4294967295]	105	1			T18	2		T37	1		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T1	1		T2	1		T8	1
auto[0:134217727]	auto[1]	57	1			T8	1		T80	1		T47	2
auto[134217728:268435455]	auto[0]	37	1			T46	1		T8	1		T80	1
auto[134217728:268435455]	auto[1]	64	1			T6	1		T125	1		T47	1
auto[268435456:402653183]	auto[0]	61	1			T1	1		T16	1		T18	1
auto[268435456:402653183]	auto[1]	41	1			T18	1		T248	1		T352	1
auto[402653184:536870911]	auto[0]	46	1			T1	1		T125	1		T50	1
auto[402653184:536870911]	auto[1]	51	1			T5	1		T15	1		T62	1
auto[536870912:671088639]	auto[0]	47	1			T15	1		T189	1		T60	1
auto[536870912:671088639]	auto[1]	76	1			T83	1		T8	1		T61	2
auto[671088640:805306367]	auto[0]	48	1			T119	1		T375	1		T398	1
auto[671088640:805306367]	auto[1]	44	1			T1	1		T119	1		T65	1
auto[805306368:939524095]	auto[0]	60	1			T16	1		T18	1		T46	1
auto[805306368:939524095]	auto[1]	51	1			T15	1		T6	1		T47	1
auto[939524096:1073741823]	auto[0]	57	1			T6	1		T46	1		T55	1
auto[939524096:1073741823]	auto[1]	65	1			T47	2		T119	1		T128	1
auto[1073741824:1207959551]	auto[0]	43	1			T83	1		T49	1		T6	1
auto[1073741824:1207959551]	auto[1]	54	1			T15	1		T7	1		T311	1
auto[1207959552:1342177279]	auto[0]	42	1			T47	1		T122	1		T123	1
auto[1207959552:1342177279]	auto[1]	50	1			T6	1		T46	2		T61	2
auto[1342177280:1476395007]	auto[0]	52	1			T15	1		T6	1		T67	1
auto[1342177280:1476395007]	auto[1]	60	1			T83	1		T6	1		T7	1
auto[1476395008:1610612735]	auto[0]	52	1			T1	1		T77	1		T82	1
auto[1476395008:1610612735]	auto[1]	51	1			T3	1		T6	2		T46	1
auto[1610612736:1744830463]	auto[0]	54	1			T1	1		T18	2		T46	2
auto[1610612736:1744830463]	auto[1]	51	1			T15	1		T7	1		T47	1
auto[1744830464:1879048191]	auto[0]	56	1			T46	1		T47	1		T119	1
auto[1744830464:1879048191]	auto[1]	60	1			T18	2		T6	1		T46	1
auto[1879048192:2013265919]	auto[0]	54	1			T5	1		T15	1		T18	1
auto[1879048192:2013265919]	auto[1]	49	1			T14	1		T15	1		T49	1
auto[2013265920:2147483647]	auto[0]	48	1			T16	1		T6	1		T46	1
auto[2013265920:2147483647]	auto[1]	56	1			T37	1		T80	1		T47	1
auto[2147483648:2281701375]	auto[0]	51	1			T15	1		T6	1		T60	1
auto[2147483648:2281701375]	auto[1]	60	1			T14	1		T6	2		T7	1
auto[2281701376:2415919103]	auto[0]	56	1			T46	2		T82	1		T427	1
auto[2281701376:2415919103]	auto[1]	54	1			T34	1		T6	1		T7	1
auto[2415919104:2550136831]	auto[0]	47	1			T46	1		T67	1		T352	1
auto[2415919104:2550136831]	auto[1]	39	1			T14	1		T15	2		T6	2
auto[2550136832:2684354559]	auto[0]	63	1			T18	1		T6	1		T46	2
auto[2550136832:2684354559]	auto[1]	42	1			T15	1		T6	1		T47	1
auto[2684354560:2818572287]	auto[0]	56	1			T37	1		T7	1		T47	1
auto[2684354560:2818572287]	auto[1]	53	1			T16	1		T6	1		T189	1
auto[2818572288:2952790015]	auto[0]	54	1			T34	1		T6	1		T55	1
auto[2818572288:2952790015]	auto[1]	58	1			T46	1		T7	1		T8	1
auto[2952790016:3087007743]	auto[0]	42	1			T37	1		T6	1		T46	2
auto[2952790016:3087007743]	auto[1]	49	1			T7	1		T47	1		T126	1
auto[3087007744:3221225471]	auto[0]	51	1			T46	2		T8	1		T47	2
auto[3087007744:3221225471]	auto[1]	53	1			T15	1		T192	1		T7	2
auto[3221225472:3355443199]	auto[0]	50	1			T6	1		T125	1		T82	1
auto[3221225472:3355443199]	auto[1]	65	1			T14	1		T15	1		T6	1
auto[3355443200:3489660927]	auto[0]	48	1			T46	2		T311	1		T67	1
auto[3355443200:3489660927]	auto[1]	45	1			T1	1		T15	1		T7	1
auto[3489660928:3623878655]	auto[0]	56	1			T6	1		T46	2		T47	1
auto[3489660928:3623878655]	auto[1]	61	1			T34	1		T6	3		T46	1
auto[3623878656:3758096383]	auto[0]	52	1			T177	1		T180	1		T120	1
auto[3623878656:3758096383]	auto[1]	43	1			T14	1		T46	1		T7	1
auto[3758096384:3892314111]	auto[0]	49	1			T55	1		T10	1		T182	1
auto[3758096384:3892314111]	auto[1]	56	1			T46	1		T7	1		T47	1
auto[3892314112:4026531839]	auto[0]	44	1			T6	1		T46	1		T8	1
auto[3892314112:4026531839]	auto[1]	61	1			T83	1		T46	1		T8	1
auto[4026531840:4160749567]	auto[0]	61	1			T60	1		T46	1		T8	1
auto[4026531840:4160749567]	auto[1]	54	1			T18	1		T6	1		T46	1
auto[4160749568:4294967295]	auto[0]	44	1			T18	1		T37	1		T6	1
auto[4160749568:4294967295]	auto[1]	61	1			T18	1		T6	1		T7	1