Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T1

5

T2

1

T5

1

auto[1]

1771

1

T1

2

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T1	1		T5	1		T18	1
auto[134217728:268435455]	100	1			T16	1		T6	1		T60	1
auto[268435456:402653183]	96	1			T18	1		T49	1		T7	1
auto[402653184:536870911]	108	1			T37	1		T189	1		T46	1
auto[536870912:671088639]	123	1			T15	1		T6	1		T46	2
auto[671088640:805306367]	111	1			T37	1		T6	3		T46	1
auto[805306368:939524095]	100	1			T16	1		T83	1		T6	1
auto[939524096:1073741823]	106	1			T14	1		T15	1		T46	1
auto[1073741824:1207959551]	110	1			T14	1		T16	2		T37	1
auto[1207959552:1342177279]	95	1			T18	1		T46	2		T47	1
auto[1342177280:1476395007]	132	1			T15	1		T34	1		T6	2
auto[1476395008:1610612735]	105	1			T34	1		T6	1		T55	1
auto[1610612736:1744830463]	101	1			T14	1		T49	1		T6	1
auto[1744830464:1879048191]	100	1			T15	1		T6	1		T9	1
auto[1879048192:2013265919]	106	1			T6	1		T46	1		T7	1
auto[2013265920:2147483647]	101	1			T15	1		T83	1		T6	2
auto[2147483648:2281701375]	110	1			T34	1		T6	1		T7	1
auto[2281701376:2415919103]	102	1			T2	1		T15	1		T6	1
auto[2415919104:2550136831]	104	1			T15	1		T18	1		T46	2
auto[2550136832:2684354559]	90	1			T3	1		T15	1		T7	1
auto[2684354560:2818572287]	116	1			T18	1		T6	1		T46	3
auto[2818572288:2952790015]	110	1			T15	1		T18	1		T6	2
auto[2952790016:3087007743]	117	1			T6	2		T46	1		T7	1
auto[3087007744:3221225471]	130	1			T1	1		T15	2		T18	1
auto[3221225472:3355443199]	92	1			T1	1		T18	2		T46	1
auto[3355443200:3489660927]	98	1			T1	2		T15	1		T83	1
auto[3489660928:3623878655]	102	1			T6	2		T46	4		T192	1
auto[3623878656:3758096383]	97	1			T14	1		T6	1		T189	1
auto[3758096384:3892314111]	104	1			T1	1		T15	3		T6	2
auto[3892314112:4026531839]	110	1			T18	2		T192	1		T7	2
auto[4026531840:4160749567]	110	1			T1	1		T18	1		T6	3
auto[4160749568:4294967295]	82	1			T5	1		T14	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T1	1		T18	1		T46	1
auto[0:134217727]	auto[1]	52	1			T5	1		T6	1		T80	1
auto[134217728:268435455]	auto[0]	40	1			T16	1		T55	1		T82	1
auto[134217728:268435455]	auto[1]	60	1			T6	1		T60	1		T46	1
auto[268435456:402653183]	auto[0]	48	1			T18	1		T47	1		T126	1
auto[268435456:402653183]	auto[1]	48	1			T49	1		T7	1		T50	1
auto[402653184:536870911]	auto[0]	48	1			T37	1		T189	1		T46	1
auto[402653184:536870911]	auto[1]	60	1			T7	1		T119	1		T177	1
auto[536870912:671088639]	auto[0]	66	1			T6	1		T46	2		T55	1
auto[536870912:671088639]	auto[1]	57	1			T15	1		T7	3		T48	1
auto[671088640:805306367]	auto[0]	53	1			T37	1		T6	2		T46	1
auto[671088640:805306367]	auto[1]	58	1			T6	1		T47	3		T65	1
auto[805306368:939524095]	auto[0]	59	1			T16	1		T6	1		T8	1
auto[805306368:939524095]	auto[1]	41	1			T83	1		T47	1		T119	2
auto[939524096:1073741823]	auto[0]	55	1			T15	1		T46	1		T47	1
auto[939524096:1073741823]	auto[1]	51	1			T14	1		T62	1		T128	1
auto[1073741824:1207959551]	auto[0]	56	1			T14	1		T16	1		T46	1
auto[1073741824:1207959551]	auto[1]	54	1			T16	1		T37	1		T80	1
auto[1207959552:1342177279]	auto[0]	48	1			T46	2		T47	1		T375	1
auto[1207959552:1342177279]	auto[1]	47	1			T18	1		T129	1		T428	1
auto[1342177280:1476395007]	auto[0]	62	1			T6	2		T47	1		T119	2
auto[1342177280:1476395007]	auto[1]	70	1			T15	1		T34	1		T46	2
auto[1476395008:1610612735]	auto[0]	55	1			T47	2		T247	1		T122	1
auto[1476395008:1610612735]	auto[1]	50	1			T34	1		T6	1		T55	1
auto[1610612736:1744830463]	auto[0]	41	1			T46	1		T47	1		T120	1
auto[1610612736:1744830463]	auto[1]	60	1			T14	1		T49	1		T6	1
auto[1744830464:1879048191]	auto[0]	46	1			T6	1		T9	1		T8	1
auto[1744830464:1879048191]	auto[1]	54	1			T15	1		T120	1		T247	1
auto[1879048192:2013265919]	auto[0]	44	1			T6	1		T46	1		T7	1
auto[1879048192:2013265919]	auto[1]	62	1			T54	1		T8	1		T47	1
auto[2013265920:2147483647]	auto[0]	39	1			T15	1		T6	1		T8	1
auto[2013265920:2147483647]	auto[1]	62	1			T83	1		T6	1		T46	2
auto[2147483648:2281701375]	auto[0]	49	1			T34	1		T6	1		T47	1
auto[2147483648:2281701375]	auto[1]	61	1			T7	1		T127	1		T121	1
auto[2281701376:2415919103]	auto[0]	54	1			T2	1		T55	1		T47	2
auto[2281701376:2415919103]	auto[1]	48	1			T15	1		T6	1		T125	2
auto[2415919104:2550136831]	auto[0]	54	1			T18	1		T46	2		T55	1
auto[2415919104:2550136831]	auto[1]	50	1			T15	1		T8	1		T119	1
auto[2550136832:2684354559]	auto[0]	39	1			T15	1		T8	1		T80	1
auto[2550136832:2684354559]	auto[1]	51	1			T3	1		T7	1		T47	1
auto[2684354560:2818572287]	auto[0]	59	1			T46	3		T47	2		T283	1
auto[2684354560:2818572287]	auto[1]	57	1			T18	1		T6	1		T7	2
auto[2818572288:2952790015]	auto[0]	51	1			T15	1		T18	1		T6	1
auto[2818572288:2952790015]	auto[1]	59	1			T6	1		T46	1		T61	1
auto[2952790016:3087007743]	auto[0]	56	1			T46	1		T7	1		T177	1
auto[2952790016:3087007743]	auto[1]	61	1			T6	2		T8	1		T47	2
auto[3087007744:3221225471]	auto[0]	67	1			T1	1		T37	1		T46	1
auto[3087007744:3221225471]	auto[1]	63	1			T15	2		T18	1		T83	1
auto[3221225472:3355443199]	auto[0]	49	1			T18	2		T46	1		T119	1
auto[3221225472:3355443199]	auto[1]	43	1			T1	1		T7	1		T119	1
auto[3355443200:3489660927]	auto[0]	41	1			T1	2		T46	1		T47	1
auto[3355443200:3489660927]	auto[1]	57	1			T15	1		T83	1		T6	2
auto[3489660928:3623878655]	auto[0]	38	1			T46	1		T192	1		T48	1
auto[3489660928:3623878655]	auto[1]	64	1			T6	2		T46	3		T7	1
auto[3623878656:3758096383]	auto[0]	41	1			T8	1		T67	1		T122	1
auto[3623878656:3758096383]	auto[1]	56	1			T14	1		T6	1		T189	1
auto[3758096384:3892314111]	auto[0]	51	1			T8	3		T82	1		T47	1
auto[3758096384:3892314111]	auto[1]	53	1			T1	1		T15	3		T6	2
auto[3892314112:4026531839]	auto[0]	55	1			T80	1		T201	1		T180	1
auto[3892314112:4026531839]	auto[1]	55	1			T18	2		T192	1		T7	2
auto[4026531840:4160749567]	auto[0]	54	1			T1	1		T60	2		T125	1
auto[4026531840:4160749567]	auto[1]	56	1			T18	1		T6	3		T125	1
auto[4160749568:4294967295]	auto[0]	31	1			T5	1		T46	2		T245	1
auto[4160749568:4294967295]	auto[1]	51	1			T14	1		T6	1		T46	1