dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4544 1 T1 8 T14 2 T15 18
auto[1] 2202 1 T1 6 T2 2 T3 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 210 1 T6 6 T46 2 T125 2
auto[134217728:268435455] 224 1 T1 2 T18 4 T6 4
auto[268435456:402653183] 232 1 T18 2 T46 2 T192 2
auto[402653184:536870911] 210 1 T2 2 T46 2 T7 4
auto[536870912:671088639] 216 1 T8 2 T47 8 T61 2
auto[671088640:805306367] 202 1 T5 2 T49 2 T6 2
auto[805306368:939524095] 202 1 T15 4 T34 2 T83 2
auto[939524096:1073741823] 210 1 T1 2 T15 2 T16 2
auto[1073741824:1207959551] 238 1 T15 4 T83 2 T6 8
auto[1207959552:1342177279] 178 1 T5 2 T16 2 T6 2
auto[1342177280:1476395007] 188 1 T15 2 T18 2 T49 2
auto[1476395008:1610612735] 228 1 T1 2 T3 2 T6 2
auto[1610612736:1744830463] 212 1 T6 4 T46 2 T7 2
auto[1744830464:1879048191] 210 1 T14 2 T6 4 T55 2
auto[1879048192:2013265919] 208 1 T14 4 T15 2 T189 2
auto[2013265920:2147483647] 190 1 T1 2 T15 2 T34 2
auto[2147483648:2281701375] 216 1 T15 2 T18 4 T46 2
auto[2281701376:2415919103] 200 1 T16 2 T37 2 T6 2
auto[2415919104:2550136831] 230 1 T14 2 T6 4 T46 2
auto[2550136832:2684354559] 230 1 T55 2 T8 4 T120 4
auto[2684354560:2818572287] 182 1 T6 2 T46 2 T61 2
auto[2818572288:2952790015] 178 1 T46 2 T8 2 T80 4
auto[2952790016:3087007743] 240 1 T1 2 T15 2 T37 2
auto[3087007744:3221225471] 204 1 T15 2 T6 2 T46 8
auto[3221225472:3355443199] 182 1 T15 2 T6 6 T8 6
auto[3355443200:3489660927] 218 1 T15 4 T18 2 T6 2
auto[3489660928:3623878655] 236 1 T1 4 T6 4 T46 2
auto[3623878656:3758096383] 232 1 T15 2 T18 4 T34 2
auto[3758096384:3892314111] 202 1 T14 2 T55 2 T7 2
auto[3892314112:4026531839] 222 1 T16 2 T18 2 T83 2
auto[4026531840:4160749567] 216 1 T83 2 T46 6 T192 2
auto[4160749568:4294967295] 200 1 T18 4 T37 2 T46 4



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 152 1 T6 2 T125 2 T54 2
auto[0:134217727] auto[1] 58 1 T6 4 T46 2 T47 2
auto[134217728:268435455] auto[0] 158 1 T18 2 T6 4 T7 2
auto[134217728:268435455] auto[1] 66 1 T1 2 T18 2 T119 4
auto[268435456:402653183] auto[0] 158 1 T18 2 T46 2 T47 2
auto[268435456:402653183] auto[1] 74 1 T192 2 T201 2 T47 2
auto[402653184:536870911] auto[0] 138 1 T7 4 T47 2 T119 2
auto[402653184:536870911] auto[1] 72 1 T2 2 T46 2 T47 6
auto[536870912:671088639] auto[0] 158 1 T61 2 T237 2 T311 4
auto[536870912:671088639] auto[1] 58 1 T8 2 T47 8 T177 2
auto[671088640:805306367] auto[0] 130 1 T6 2 T46 4 T47 2
auto[671088640:805306367] auto[1] 72 1 T5 2 T49 2 T7 2
auto[805306368:939524095] auto[0] 132 1 T15 2 T83 2 T46 2
auto[805306368:939524095] auto[1] 70 1 T15 2 T34 2 T47 2
auto[939524096:1073741823] auto[0] 140 1 T1 2 T15 2 T16 2
auto[939524096:1073741823] auto[1] 70 1 T6 2 T7 2 T47 2
auto[1073741824:1207959551] auto[0] 156 1 T15 2 T83 2 T6 2
auto[1073741824:1207959551] auto[1] 82 1 T15 2 T6 6 T46 2
auto[1207959552:1342177279] auto[0] 116 1 T16 2 T6 2 T46 2
auto[1207959552:1342177279] auto[1] 62 1 T5 2 T8 2 T80 2
auto[1342177280:1476395007] auto[0] 132 1 T15 2 T18 2 T6 2
auto[1342177280:1476395007] auto[1] 56 1 T49 2 T47 2 T237 2
auto[1476395008:1610612735] auto[0] 142 1 T6 2 T46 2 T7 2
auto[1476395008:1610612735] auto[1] 86 1 T1 2 T3 2 T8 2
auto[1610612736:1744830463] auto[0] 140 1 T6 4 T46 2 T7 2
auto[1610612736:1744830463] auto[1] 72 1 T10 2 T61 2 T230 2
auto[1744830464:1879048191] auto[0] 142 1 T14 2 T6 4 T55 2
auto[1744830464:1879048191] auto[1] 68 1 T9 2 T47 4 T119 2
auto[1879048192:2013265919] auto[0] 132 1 T60 2 T119 2 T121 4
auto[1879048192:2013265919] auto[1] 76 1 T14 4 T15 2 T189 2
auto[2013265920:2147483647] auto[0] 130 1 T34 2 T55 2 T125 2
auto[2013265920:2147483647] auto[1] 60 1 T1 2 T15 2 T7 2
auto[2147483648:2281701375] auto[0] 132 1 T15 2 T18 4 T8 2
auto[2147483648:2281701375] auto[1] 84 1 T46 2 T180 2 T245 2
auto[2281701376:2415919103] auto[0] 158 1 T16 2 T37 2 T6 2
auto[2281701376:2415919103] auto[1] 42 1 T189 2 T47 4 T61 2
auto[2415919104:2550136831] auto[0] 162 1 T6 4 T82 2 T47 2
auto[2415919104:2550136831] auto[1] 68 1 T14 2 T46 2 T47 2
auto[2550136832:2684354559] auto[0] 152 1 T55 2 T8 4 T120 2
auto[2550136832:2684354559] auto[1] 78 1 T120 2 T247 2 T89 4
auto[2684354560:2818572287] auto[0] 114 1 T6 2 T46 2 T121 4
auto[2684354560:2818572287] auto[1] 68 1 T61 2 T120 2 T121 2
auto[2818572288:2952790015] auto[0] 126 1 T46 2 T8 2 T80 2
auto[2818572288:2952790015] auto[1] 52 1 T80 2 T47 2 T120 2
auto[2952790016:3087007743] auto[0] 162 1 T1 2 T37 2 T6 6
auto[2952790016:3087007743] auto[1] 78 1 T15 2 T46 2 T8 2
auto[3087007744:3221225471] auto[0] 138 1 T15 2 T46 2 T55 2
auto[3087007744:3221225471] auto[1] 66 1 T6 2 T46 6 T47 2
auto[3221225472:3355443199] auto[0] 130 1 T15 2 T6 6 T8 4
auto[3221225472:3355443199] auto[1] 52 1 T8 2 T119 2 T121 2
auto[3355443200:3489660927] auto[0] 138 1 T15 2 T18 2 T6 2
auto[3355443200:3489660927] auto[1] 80 1 T15 2 T47 2 T120 2
auto[3489660928:3623878655] auto[0] 158 1 T1 4 T6 2 T46 2
auto[3489660928:3623878655] auto[1] 78 1 T6 2 T230 2 T245 2
auto[3623878656:3758096383] auto[0] 170 1 T15 2 T18 2 T34 2
auto[3623878656:3758096383] auto[1] 62 1 T18 2 T55 2 T8 2
auto[3758096384:3892314111] auto[0] 130 1 T8 2 T47 2 T61 2
auto[3758096384:3892314111] auto[1] 72 1 T14 2 T55 2 T7 2
auto[3892314112:4026531839] auto[0] 136 1 T16 2 T18 2 T83 2
auto[3892314112:4026531839] auto[1] 86 1 T6 2 T46 2 T47 4
auto[4026531840:4160749567] auto[0] 150 1 T83 2 T46 2 T192 2
auto[4026531840:4160749567] auto[1] 66 1 T46 4 T180 2 T375 2
auto[4160749568:4294967295] auto[0] 132 1 T18 4 T37 2 T46 4
auto[4160749568:4294967295] auto[1] 68 1 T8 2 T26 2 T67 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%