Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.11 98.65 100.00 99.02 98.41 91.17


Total test records in report: 1085
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1005 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3767350511 Jun 25 05:21:45 PM PDT 24 Jun 25 05:22:00 PM PDT 24 1436561147 ps
T1006 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2602057271 Jun 25 05:20:56 PM PDT 24 Jun 25 05:20:59 PM PDT 24 726801995 ps
T1007 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1767406008 Jun 25 05:21:54 PM PDT 24 Jun 25 05:21:58 PM PDT 24 48071105 ps
T1008 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3385001276 Jun 25 05:21:54 PM PDT 24 Jun 25 05:21:58 PM PDT 24 35751987 ps
T1009 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.63055025 Jun 25 05:21:16 PM PDT 24 Jun 25 05:21:21 PM PDT 24 2154200037 ps
T1010 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2637770850 Jun 25 05:20:49 PM PDT 24 Jun 25 05:20:59 PM PDT 24 2086454863 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1426084837 Jun 25 05:21:47 PM PDT 24 Jun 25 05:21:55 PM PDT 24 172140924 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3463086397 Jun 25 05:21:28 PM PDT 24 Jun 25 05:21:30 PM PDT 24 24863993 ps
T1013 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1558964774 Jun 25 05:22:01 PM PDT 24 Jun 25 05:22:03 PM PDT 24 31849039 ps
T1014 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.369764922 Jun 25 05:21:45 PM PDT 24 Jun 25 05:21:53 PM PDT 24 722253646 ps
T1015 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2533319440 Jun 25 05:21:04 PM PDT 24 Jun 25 05:21:15 PM PDT 24 464164824 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1333511474 Jun 25 05:21:35 PM PDT 24 Jun 25 05:21:36 PM PDT 24 29736809 ps
T1017 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1989357067 Jun 25 05:20:57 PM PDT 24 Jun 25 05:21:00 PM PDT 24 388685775 ps
T1018 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2264154411 Jun 25 05:22:04 PM PDT 24 Jun 25 05:22:07 PM PDT 24 24451234 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2497687915 Jun 25 05:21:07 PM PDT 24 Jun 25 05:21:10 PM PDT 24 60096288 ps
T1020 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1204207133 Jun 25 05:21:36 PM PDT 24 Jun 25 05:21:38 PM PDT 24 17361235 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.70832442 Jun 25 05:20:50 PM PDT 24 Jun 25 05:20:53 PM PDT 24 78680288 ps
T1022 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1950614584 Jun 25 05:21:06 PM PDT 24 Jun 25 05:21:10 PM PDT 24 49839948 ps
T1023 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2695785052 Jun 25 05:21:54 PM PDT 24 Jun 25 05:22:05 PM PDT 24 693480188 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1821231734 Jun 25 05:21:27 PM PDT 24 Jun 25 05:21:31 PM PDT 24 19581900 ps
T161 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4190354861 Jun 25 05:21:37 PM PDT 24 Jun 25 05:21:48 PM PDT 24 264836990 ps
T1025 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3427225118 Jun 25 05:21:27 PM PDT 24 Jun 25 05:21:31 PM PDT 24 175246052 ps
T1026 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3786635574 Jun 25 05:21:05 PM PDT 24 Jun 25 05:21:08 PM PDT 24 102998014 ps
T1027 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3959530897 Jun 25 05:22:02 PM PDT 24 Jun 25 05:22:04 PM PDT 24 35388380 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.287306826 Jun 25 05:21:07 PM PDT 24 Jun 25 05:21:13 PM PDT 24 371194515 ps
T156 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.194122834 Jun 25 05:21:33 PM PDT 24 Jun 25 05:21:43 PM PDT 24 231843533 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3660510167 Jun 25 05:21:04 PM PDT 24 Jun 25 05:21:16 PM PDT 24 514598749 ps
T1030 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.64020011 Jun 25 05:22:03 PM PDT 24 Jun 25 05:22:06 PM PDT 24 11054916 ps
T1031 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1263268728 Jun 25 05:21:04 PM PDT 24 Jun 25 05:21:05 PM PDT 24 44815301 ps
T1032 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.197147537 Jun 25 05:21:35 PM PDT 24 Jun 25 05:21:43 PM PDT 24 299891777 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1769024879 Jun 25 05:21:40 PM PDT 24 Jun 25 05:21:42 PM PDT 24 18959857 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2173093745 Jun 25 05:21:40 PM PDT 24 Jun 25 05:21:43 PM PDT 24 48250632 ps
T1035 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3954623243 Jun 25 05:21:32 PM PDT 24 Jun 25 05:21:35 PM PDT 24 77004896 ps
T1036 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1248230461 Jun 25 05:21:06 PM PDT 24 Jun 25 05:21:11 PM PDT 24 32549766 ps
T1037 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3030154712 Jun 25 05:20:50 PM PDT 24 Jun 25 05:20:52 PM PDT 24 24515059 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2019015656 Jun 25 05:21:07 PM PDT 24 Jun 25 05:21:09 PM PDT 24 11662399 ps
T1039 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.116843533 Jun 25 05:21:36 PM PDT 24 Jun 25 05:21:47 PM PDT 24 797765018 ps
T1040 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.291003561 Jun 25 05:21:43 PM PDT 24 Jun 25 05:21:45 PM PDT 24 58534784 ps
T1041 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4040001762 Jun 25 05:21:53 PM PDT 24 Jun 25 05:21:56 PM PDT 24 101148313 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4266597553 Jun 25 05:20:58 PM PDT 24 Jun 25 05:21:09 PM PDT 24 8143549417 ps
T1043 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3374056404 Jun 25 05:21:54 PM PDT 24 Jun 25 05:21:59 PM PDT 24 167750083 ps
T1044 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3296285866 Jun 25 05:21:33 PM PDT 24 Jun 25 05:21:36 PM PDT 24 170263109 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.869935337 Jun 25 05:21:34 PM PDT 24 Jun 25 05:21:38 PM PDT 24 75718057 ps
T1046 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1927227238 Jun 25 05:21:47 PM PDT 24 Jun 25 05:21:50 PM PDT 24 37936082 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.328339971 Jun 25 05:21:30 PM PDT 24 Jun 25 05:21:34 PM PDT 24 676642855 ps
T1048 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2322985031 Jun 25 05:21:44 PM PDT 24 Jun 25 05:21:49 PM PDT 24 725608873 ps
T1049 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1608109934 Jun 25 05:20:57 PM PDT 24 Jun 25 05:21:00 PM PDT 24 150541654 ps
T1050 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2443796031 Jun 25 05:21:46 PM PDT 24 Jun 25 05:21:51 PM PDT 24 120317946 ps
T170 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2466382537 Jun 25 05:22:00 PM PDT 24 Jun 25 05:22:07 PM PDT 24 401158759 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1877037991 Jun 25 05:20:57 PM PDT 24 Jun 25 05:20:58 PM PDT 24 11470436 ps
T1052 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.606497826 Jun 25 05:21:27 PM PDT 24 Jun 25 05:21:31 PM PDT 24 98125311 ps
T1053 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1877328597 Jun 25 05:21:58 PM PDT 24 Jun 25 05:22:00 PM PDT 24 11661088 ps
T1054 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3695126462 Jun 25 05:21:16 PM PDT 24 Jun 25 05:21:21 PM PDT 24 182600112 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4226129500 Jun 25 05:21:27 PM PDT 24 Jun 25 05:21:32 PM PDT 24 155814592 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.16792600 Jun 25 05:21:35 PM PDT 24 Jun 25 05:21:38 PM PDT 24 83027145 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2049127246 Jun 25 05:21:41 PM PDT 24 Jun 25 05:21:48 PM PDT 24 136949215 ps
T1058 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1790751177 Jun 25 05:21:56 PM PDT 24 Jun 25 05:21:58 PM PDT 24 17751580 ps
T1059 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1791554656 Jun 25 05:21:56 PM PDT 24 Jun 25 05:21:59 PM PDT 24 31437071 ps
T1060 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3484072700 Jun 25 05:21:45 PM PDT 24 Jun 25 05:21:48 PM PDT 24 19798455 ps
T1061 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3165151647 Jun 25 05:22:03 PM PDT 24 Jun 25 05:22:06 PM PDT 24 13808351 ps
T1062 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1376971089 Jun 25 05:21:49 PM PDT 24 Jun 25 05:21:55 PM PDT 24 317194872 ps
T1063 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4101370239 Jun 25 05:20:49 PM PDT 24 Jun 25 05:20:50 PM PDT 24 9986491 ps
T1064 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3212627803 Jun 25 05:21:16 PM PDT 24 Jun 25 05:21:20 PM PDT 24 90142350 ps
T164 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3827110982 Jun 25 05:21:16 PM PDT 24 Jun 25 05:21:22 PM PDT 24 337237893 ps
T1065 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1346002106 Jun 25 05:21:15 PM PDT 24 Jun 25 05:21:19 PM PDT 24 55934308 ps
T1066 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.875441713 Jun 25 05:22:03 PM PDT 24 Jun 25 05:22:06 PM PDT 24 15481616 ps
T1067 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1091607471 Jun 25 05:21:03 PM PDT 24 Jun 25 05:21:05 PM PDT 24 52130205 ps
T1068 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.436122712 Jun 25 05:22:03 PM PDT 24 Jun 25 05:22:06 PM PDT 24 16920646 ps
T1069 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2054235514 Jun 25 05:21:04 PM PDT 24 Jun 25 05:21:15 PM PDT 24 308012308 ps
T1070 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1229098545 Jun 25 05:21:40 PM PDT 24 Jun 25 05:21:48 PM PDT 24 149220792 ps
T1071 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2608771911 Jun 25 05:21:15 PM PDT 24 Jun 25 05:21:32 PM PDT 24 6330850569 ps
T1072 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2575689807 Jun 25 05:22:01 PM PDT 24 Jun 25 05:22:04 PM PDT 24 56607690 ps
T1073 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2270110874 Jun 25 05:21:16 PM PDT 24 Jun 25 05:21:20 PM PDT 24 261156012 ps
T1074 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.611351659 Jun 25 05:22:05 PM PDT 24 Jun 25 05:22:07 PM PDT 24 44940849 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1025942541 Jun 25 05:21:19 PM PDT 24 Jun 25 05:21:31 PM PDT 24 971765159 ps
T1076 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2513989216 Jun 25 05:21:13 PM PDT 24 Jun 25 05:21:17 PM PDT 24 87867229 ps
T1077 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.235585591 Jun 25 05:21:17 PM PDT 24 Jun 25 05:21:22 PM PDT 24 139096032 ps
T1078 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2698527421 Jun 25 05:21:29 PM PDT 24 Jun 25 05:21:32 PM PDT 24 87424278 ps
T1079 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.161896430 Jun 25 05:21:59 PM PDT 24 Jun 25 05:22:03 PM PDT 24 39102523 ps
T1080 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2874690572 Jun 25 05:20:57 PM PDT 24 Jun 25 05:21:05 PM PDT 24 2294189311 ps
T1081 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3951324050 Jun 25 05:21:47 PM PDT 24 Jun 25 05:21:49 PM PDT 24 11980076 ps
T1082 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.942931567 Jun 25 05:21:06 PM PDT 24 Jun 25 05:21:15 PM PDT 24 651154454 ps
T1083 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1342687063 Jun 25 05:21:05 PM PDT 24 Jun 25 05:21:09 PM PDT 24 159252328 ps
T1084 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3777129222 Jun 25 05:20:58 PM PDT 24 Jun 25 05:21:11 PM PDT 24 463424687 ps
T1085 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3342942646 Jun 25 05:21:53 PM PDT 24 Jun 25 05:21:56 PM PDT 24 12134711 ps

Test location /workspace/coverage/default/5.keymgr_stress_all.156279476
Short name T1
Test name
Test status
Simulation time 405705961 ps
CPU time 18.67 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 220572 kb
Host smart-08b04fc6-e92c-4166-b5d3-5edddf3e4899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156279476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.156279476
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.245652637
Short name T47
Test name
Test status
Simulation time 8898821341 ps
CPU time 66.65 seconds
Started Jun 25 05:25:15 PM PDT 24
Finished Jun 25 05:26:25 PM PDT 24
Peak memory 216208 kb
Host smart-cbea708a-25ad-4bac-b8e2-9cabb412bbd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245652637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.245652637
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.178822992
Short name T6
Test name
Test status
Simulation time 35411219203 ps
CPU time 96.9 seconds
Started Jun 25 05:23:16 PM PDT 24
Finished Jun 25 05:24:54 PM PDT 24
Peak memory 222516 kb
Host smart-54e0fe64-05ce-4973-ad5a-dce03e1cf529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178822992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.178822992
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1693621497
Short name T15
Test name
Test status
Simulation time 974113645 ps
CPU time 13.97 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 222484 kb
Host smart-863fc40f-aea6-4056-b47d-eaefd2204fe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693621497 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1693621497
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1543800758
Short name T12
Test name
Test status
Simulation time 2210872402 ps
CPU time 7.3 seconds
Started Jun 25 05:23:15 PM PDT 24
Finished Jun 25 05:23:24 PM PDT 24
Peak memory 229320 kb
Host smart-c3a95fd0-5ede-40cc-aca1-ea9180aadcd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543800758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1543800758
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.633040210
Short name T67
Test name
Test status
Simulation time 2983676781 ps
CPU time 33.04 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 222420 kb
Host smart-3185ec58-ee80-4b6f-82bf-055afe4666c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633040210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.633040210
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.849224860
Short name T122
Test name
Test status
Simulation time 1832595518 ps
CPU time 13.09 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 222520 kb
Host smart-7b6375bc-8ab2-4f53-87d8-533e83e48829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849224860 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.849224860
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1629185887
Short name T9
Test name
Test status
Simulation time 1061343270 ps
CPU time 14.3 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:24:07 PM PDT 24
Peak memory 222080 kb
Host smart-0e58c077-02e1-4504-bb34-84d840d80c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629185887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1629185887
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.239079337
Short name T113
Test name
Test status
Simulation time 1178546571 ps
CPU time 7.98 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:38 PM PDT 24
Peak memory 214012 kb
Host smart-645d4404-d6fd-4d24-82f2-b67e4df9491c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239079337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.239079337
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1401971173
Short name T283
Test name
Test status
Simulation time 122839820 ps
CPU time 4.04 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:34 PM PDT 24
Peak memory 214164 kb
Host smart-74b697be-1abc-4782-b217-0973b07a5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401971173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1401971173
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.725956523
Short name T128
Test name
Test status
Simulation time 1840982410 ps
CPU time 90.5 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:25:05 PM PDT 24
Peak memory 215112 kb
Host smart-38b46e5b-73ec-410e-9825-b0bbd59c11c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725956523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.725956523
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3007525383
Short name T414
Test name
Test status
Simulation time 4024442247 ps
CPU time 54.7 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:25:26 PM PDT 24
Peak memory 214304 kb
Host smart-7df8d9dd-17c9-49a2-bb24-927ae25ecc52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007525383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3007525383
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.826807482
Short name T82
Test name
Test status
Simulation time 288338888 ps
CPU time 8.2 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 215868 kb
Host smart-4d991f92-929f-406e-ac0f-abb5bb2b4f44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826807482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.826807482
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4248180663
Short name T27
Test name
Test status
Simulation time 377221234 ps
CPU time 5.59 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:10 PM PDT 24
Peak memory 220956 kb
Host smart-d73b6148-da59-426d-af5a-89315c15791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248180663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4248180663
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.328729816
Short name T215
Test name
Test status
Simulation time 3717766102 ps
CPU time 69.73 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 222216 kb
Host smart-07abaaab-e839-4e24-9836-23bc75c7df07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328729816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.328729816
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1604214043
Short name T357
Test name
Test status
Simulation time 244367837 ps
CPU time 8.41 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:31 PM PDT 24
Peak memory 214384 kb
Host smart-2745adeb-6378-4178-8670-9a9d918f25a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604214043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1604214043
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.45143036
Short name T7
Test name
Test status
Simulation time 509448106 ps
CPU time 22.67 seconds
Started Jun 25 05:23:48 PM PDT 24
Finished Jun 25 05:24:13 PM PDT 24
Peak memory 215872 kb
Host smart-a9df1c61-049d-46d8-8797-4e1b98fd606b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45143036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.45143036
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2524211032
Short name T327
Test name
Test status
Simulation time 243881816 ps
CPU time 6.89 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 222404 kb
Host smart-208e1159-9ebf-4178-a275-b2467cf07cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524211032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2524211032
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3913625369
Short name T43
Test name
Test status
Simulation time 261182304 ps
CPU time 3.71 seconds
Started Jun 25 05:24:24 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 209584 kb
Host smart-62911b1d-2457-4861-8820-30428f066c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913625369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3913625369
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2402874044
Short name T72
Test name
Test status
Simulation time 28109686098 ps
CPU time 66.57 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:25:43 PM PDT 24
Peak memory 222576 kb
Host smart-65d7f342-3fb8-4779-8f9a-2072753fded0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402874044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2402874044
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2788420979
Short name T119
Test name
Test status
Simulation time 256276033 ps
CPU time 16.48 seconds
Started Jun 25 05:24:03 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 222612 kb
Host smart-c953710e-a9f3-408f-8353-64ae06d68c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788420979 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2788420979
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3692847635
Short name T410
Test name
Test status
Simulation time 259276817 ps
CPU time 14.15 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:11 PM PDT 24
Peak memory 215512 kb
Host smart-4c3eee9d-02db-47fb-a02d-e1fd5b2de6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692847635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3692847635
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2431908825
Short name T3
Test name
Test status
Simulation time 69798753 ps
CPU time 1.94 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:05 PM PDT 24
Peak memory 215472 kb
Host smart-c20b3aa5-44ea-4304-b0f3-f7ae627dfd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431908825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2431908825
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1220648967
Short name T23
Test name
Test status
Simulation time 189488420 ps
CPU time 2.32 seconds
Started Jun 25 05:23:42 PM PDT 24
Finished Jun 25 05:23:46 PM PDT 24
Peak memory 214704 kb
Host smart-6d148b44-c301-4203-af78-188514e2b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220648967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1220648967
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1961013175
Short name T39
Test name
Test status
Simulation time 106823943 ps
CPU time 2.99 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 214372 kb
Host smart-39daad5e-dbad-4adb-a715-65723c089d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961013175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1961013175
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3435063429
Short name T129
Test name
Test status
Simulation time 188655473 ps
CPU time 4.61 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 215376 kb
Host smart-0858491b-d48f-4e2d-970d-26a5728b0063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435063429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3435063429
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1659395113
Short name T112
Test name
Test status
Simulation time 295080096 ps
CPU time 2.86 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:21:00 PM PDT 24
Peak memory 214008 kb
Host smart-4c33bddf-b62c-4c63-9c3e-933aaec56642
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659395113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1659395113
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.258120785
Short name T96
Test name
Test status
Simulation time 2626043315 ps
CPU time 25.61 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:41 PM PDT 24
Peak memory 209424 kb
Host smart-fef21c41-8433-496f-ab2c-e07d6e399f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258120785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.258120785
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.194329431
Short name T46
Test name
Test status
Simulation time 18512093838 ps
CPU time 193.36 seconds
Started Jun 25 05:23:32 PM PDT 24
Finished Jun 25 05:26:46 PM PDT 24
Peak memory 216696 kb
Host smart-64840aee-142d-4e26-8d26-43f2109a4251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194329431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.194329431
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.329826977
Short name T30
Test name
Test status
Simulation time 162771268 ps
CPU time 3.66 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 210460 kb
Host smart-9294e9dd-8e13-4edc-bb3d-f78b7ede7607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329826977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.329826977
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.194122834
Short name T156
Test name
Test status
Simulation time 231843533 ps
CPU time 9.03 seconds
Started Jun 25 05:21:33 PM PDT 24
Finished Jun 25 05:21:43 PM PDT 24
Peak memory 213708 kb
Host smart-decfb582-b7f8-41e0-9eea-e05f48dfe692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194122834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.194122834
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1051417699
Short name T300
Test name
Test status
Simulation time 102941368 ps
CPU time 5.95 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:30 PM PDT 24
Peak memory 215108 kb
Host smart-9e17737f-f34c-4679-a42e-073a5042ae87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051417699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1051417699
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3397552930
Short name T238
Test name
Test status
Simulation time 2553855688 ps
CPU time 24.88 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 215344 kb
Host smart-9cb98300-4daf-4892-b450-19e563e5d894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397552930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3397552930
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4090333335
Short name T16
Test name
Test status
Simulation time 987376032 ps
CPU time 14.38 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:42 PM PDT 24
Peak memory 215468 kb
Host smart-f22b7191-6450-4a12-8c3e-5dfdef9a1fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090333335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4090333335
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1011076575
Short name T85
Test name
Test status
Simulation time 197617077 ps
CPU time 3.4 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:25 PM PDT 24
Peak memory 222512 kb
Host smart-67591f39-d6c3-47ba-84f0-d7ce3381eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011076575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1011076575
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1609117263
Short name T458
Test name
Test status
Simulation time 46979050 ps
CPU time 0.77 seconds
Started Jun 25 05:23:42 PM PDT 24
Finished Jun 25 05:23:44 PM PDT 24
Peak memory 205948 kb
Host smart-ed8054e1-32ac-4557-b2b5-d4b6fba82c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609117263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1609117263
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2087616245
Short name T210
Test name
Test status
Simulation time 907251214 ps
CPU time 23.09 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:25:09 PM PDT 24
Peak memory 222612 kb
Host smart-e5322a72-55ab-4c35-8030-003affb4a174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087616245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2087616245
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2670045208
Short name T361
Test name
Test status
Simulation time 9481072613 ps
CPU time 127.07 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:27:06 PM PDT 24
Peak memory 222516 kb
Host smart-823d428d-18cc-4f1b-9608-2d0957d23822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670045208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2670045208
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1140237127
Short name T62
Test name
Test status
Simulation time 1029425325 ps
CPU time 4.4 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 218540 kb
Host smart-01288feb-c0f5-424f-99f9-9e6e32ea6c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140237127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1140237127
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.98986080
Short name T89
Test name
Test status
Simulation time 54668124 ps
CPU time 3.17 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:49 PM PDT 24
Peak memory 214252 kb
Host smart-9ce35efa-4ca2-4bea-8c74-a11e8c018cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98986080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.98986080
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3092794279
Short name T224
Test name
Test status
Simulation time 1255792738 ps
CPU time 48.16 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:25:02 PM PDT 24
Peak memory 221904 kb
Host smart-6a0f43c0-e383-40f9-9d0c-a5ae6d598ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092794279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3092794279
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1976529035
Short name T142
Test name
Test status
Simulation time 347952105 ps
CPU time 4.23 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:15 PM PDT 24
Peak memory 217816 kb
Host smart-1ac7ef5e-9c75-46c6-aec8-6d01ae6a0214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976529035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1976529035
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1886970303
Short name T213
Test name
Test status
Simulation time 9335318894 ps
CPU time 65.63 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 216240 kb
Host smart-9e20f5db-1ebb-4b27-8ed7-386811292f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886970303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1886970303
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4190354861
Short name T161
Test name
Test status
Simulation time 264836990 ps
CPU time 10.15 seconds
Started Jun 25 05:21:37 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 205424 kb
Host smart-ba03f869-bfb2-4ad2-ba8d-65952d2cc285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190354861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4190354861
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1614782224
Short name T144
Test name
Test status
Simulation time 79350157 ps
CPU time 3.34 seconds
Started Jun 25 05:24:49 PM PDT 24
Finished Jun 25 05:24:54 PM PDT 24
Peak memory 218496 kb
Host smart-d6963e0d-08df-4692-973d-567fcfb651e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614782224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1614782224
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3872760169
Short name T149
Test name
Test status
Simulation time 432281496 ps
CPU time 3.62 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:21:01 PM PDT 24
Peak memory 205420 kb
Host smart-90c5d11c-846b-45ee-ad1d-3983488fb1d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872760169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3872760169
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.53506280
Short name T140
Test name
Test status
Simulation time 86704964 ps
CPU time 3.25 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 217120 kb
Host smart-64314ec2-65c4-4d6a-bd9a-36bf50368bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53506280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.53506280
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2436803717
Short name T332
Test name
Test status
Simulation time 16754491811 ps
CPU time 531.07 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:32:04 PM PDT 24
Peak memory 222540 kb
Host smart-87959fe6-c414-4447-b103-05201f3d410a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436803717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2436803717
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1641620967
Short name T285
Test name
Test status
Simulation time 73632924 ps
CPU time 4.58 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 214324 kb
Host smart-dca0fc07-f340-4060-9c41-acc4ee81161f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641620967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1641620967
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3310014740
Short name T261
Test name
Test status
Simulation time 95918229 ps
CPU time 3.35 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:25 PM PDT 24
Peak memory 221320 kb
Host smart-f422b73a-c4eb-41e1-89c2-f8c303d4cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310014740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3310014740
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.290768777
Short name T18
Test name
Test status
Simulation time 688395297 ps
CPU time 11.7 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 222448 kb
Host smart-06db0fd2-8cc9-4452-b11d-092a5dafd3b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290768777 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.290768777
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.673538938
Short name T93
Test name
Test status
Simulation time 228093138 ps
CPU time 4.97 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:51 PM PDT 24
Peak memory 208704 kb
Host smart-72f6321b-f344-4742-ad3b-0edf482ddd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673538938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.673538938
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1863637249
Short name T165
Test name
Test status
Simulation time 800895088 ps
CPU time 11 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 210948 kb
Host smart-00687999-a6b4-4ad8-b2c6-1232c6ecb984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863637249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1863637249
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2099241504
Short name T752
Test name
Test status
Simulation time 39166809 ps
CPU time 1.64 seconds
Started Jun 25 05:23:03 PM PDT 24
Finished Jun 25 05:23:05 PM PDT 24
Peak memory 217196 kb
Host smart-ba974ddc-1764-468a-9490-675df314ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099241504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2099241504
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2077052174
Short name T44
Test name
Test status
Simulation time 656919804 ps
CPU time 14.73 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:20 PM PDT 24
Peak memory 234560 kb
Host smart-99b8641f-873b-41e9-ac3d-ac9a7536b6c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077052174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2077052174
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2368843438
Short name T53
Test name
Test status
Simulation time 329262615 ps
CPU time 2.51 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:12 PM PDT 24
Peak memory 214608 kb
Host smart-be22751c-9f5c-43a4-a3b4-b6b25e7c692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368843438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2368843438
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.507387565
Short name T22
Test name
Test status
Simulation time 47640485 ps
CPU time 2.78 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 222836 kb
Host smart-a8d7c315-9d36-4f22-8a2a-a9d7d0d7033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507387565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.507387565
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2007292455
Short name T256
Test name
Test status
Simulation time 325127048 ps
CPU time 3.18 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:18 PM PDT 24
Peak memory 222440 kb
Host smart-ebbebdbf-0cfe-4c13-b3a8-7d807fed153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007292455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2007292455
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3973074699
Short name T302
Test name
Test status
Simulation time 37482512 ps
CPU time 2.52 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 207684 kb
Host smart-beb07aca-8bae-4624-946e-2036dfbf44d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973074699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3973074699
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.871191203
Short name T14
Test name
Test status
Simulation time 32481963 ps
CPU time 2.44 seconds
Started Jun 25 05:23:16 PM PDT 24
Finished Jun 25 05:23:19 PM PDT 24
Peak memory 214256 kb
Host smart-b7734604-aabf-47e2-a8f2-e036d6d801d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871191203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.871191203
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3444809095
Short name T865
Test name
Test status
Simulation time 460009917 ps
CPU time 3.36 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 214276 kb
Host smart-09fc4555-112d-4d10-b45e-500fb5f21551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444809095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3444809095
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1094288676
Short name T58
Test name
Test status
Simulation time 469384519 ps
CPU time 4.45 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:48 PM PDT 24
Peak memory 210100 kb
Host smart-6f46589a-c59c-4f0a-ad74-531d0b9af1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094288676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1094288676
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.4216889856
Short name T301
Test name
Test status
Simulation time 213034545 ps
CPU time 4.48 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 214308 kb
Host smart-98063afc-9769-4fa5-94c5-b481bc74d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216889856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.4216889856
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2409583223
Short name T228
Test name
Test status
Simulation time 2512511962 ps
CPU time 64.58 seconds
Started Jun 25 05:25:30 PM PDT 24
Finished Jun 25 05:26:37 PM PDT 24
Peak memory 214380 kb
Host smart-07b54076-cf7e-4fba-acec-9bf9c53bde9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409583223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2409583223
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1141867676
Short name T348
Test name
Test status
Simulation time 2869720212 ps
CPU time 6.5 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 214376 kb
Host smart-31ce66c7-a66c-4559-bed9-9cc3867d6b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141867676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1141867676
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.839249342
Short name T143
Test name
Test status
Simulation time 107902014 ps
CPU time 4.88 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:28 PM PDT 24
Peak memory 222696 kb
Host smart-18178f3f-123f-4a26-b30e-e74108871a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839249342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.839249342
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3135968276
Short name T141
Test name
Test status
Simulation time 55317417 ps
CPU time 1.81 seconds
Started Jun 25 05:23:15 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 213596 kb
Host smart-00b1335b-21bd-4bc0-a787-48deb2d29ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135968276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3135968276
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2040005300
Short name T139
Test name
Test status
Simulation time 1083879064 ps
CPU time 6.5 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 218588 kb
Host smart-0904248b-f660-49c7-a96c-6041fbf4fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040005300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2040005300
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2599775100
Short name T268
Test name
Test status
Simulation time 239107119 ps
CPU time 10.78 seconds
Started Jun 25 05:23:38 PM PDT 24
Finished Jun 25 05:23:51 PM PDT 24
Peak memory 222512 kb
Host smart-9a384bbf-dc33-4407-b7eb-14d798c34508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599775100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2599775100
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3962219522
Short name T211
Test name
Test status
Simulation time 2669108948 ps
CPU time 62.74 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:24:57 PM PDT 24
Peak memory 222596 kb
Host smart-ee2167d6-7290-476f-88be-809235de3fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962219522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3962219522
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.568268779
Short name T376
Test name
Test status
Simulation time 53796043 ps
CPU time 2.98 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:25 PM PDT 24
Peak memory 208104 kb
Host smart-b9eeb57a-dbbf-4c89-85a4-2556c98b6680
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568268779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.568268779
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.796562974
Short name T303
Test name
Test status
Simulation time 125150114 ps
CPU time 3.76 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 209900 kb
Host smart-01087a68-86d7-426d-a0d9-54bd59da20ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796562974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.796562974
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2576087164
Short name T421
Test name
Test status
Simulation time 413613056 ps
CPU time 4.4 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:24:56 PM PDT 24
Peak memory 222496 kb
Host smart-edcc4883-7ebd-42be-99da-1c1637f776f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2576087164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2576087164
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2419665908
Short name T91
Test name
Test status
Simulation time 1586195521 ps
CPU time 38.36 seconds
Started Jun 25 05:24:47 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 214240 kb
Host smart-4bc2dbbd-8eb4-4c9d-858b-c0771e86c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419665908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2419665908
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4107954408
Short name T336
Test name
Test status
Simulation time 813091483 ps
CPU time 11.88 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 214340 kb
Host smart-7ff62467-4244-4f13-9d6b-c89f0f17e8c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107954408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4107954408
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1336728118
Short name T148
Test name
Test status
Simulation time 796142063 ps
CPU time 6.19 seconds
Started Jun 25 05:21:48 PM PDT 24
Finished Jun 25 05:21:56 PM PDT 24
Peak memory 215944 kb
Host smart-10636276-1b16-4c18-a6bb-cbdb1d90d979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336728118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1336728118
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.713663877
Short name T159
Test name
Test status
Simulation time 1379612404 ps
CPU time 8.17 seconds
Started Jun 25 05:21:45 PM PDT 24
Finished Jun 25 05:21:55 PM PDT 24
Peak memory 213716 kb
Host smart-5095b840-83ab-48f6-9c08-58182635d706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713663877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.713663877
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.24252191
Short name T163
Test name
Test status
Simulation time 451566080 ps
CPU time 3.73 seconds
Started Jun 25 05:21:53 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 213672 kb
Host smart-946623d4-2afa-4f75-9939-28845d6c4611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24252191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.24252191
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.775276834
Short name T153
Test name
Test status
Simulation time 147105784 ps
CPU time 5.29 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:22:02 PM PDT 24
Peak memory 214844 kb
Host smart-29d92a4c-fead-432d-8d70-cc0c35407c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775276834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.775276834
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3827110982
Short name T164
Test name
Test status
Simulation time 337237893 ps
CPU time 4.34 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:22 PM PDT 24
Peak memory 213636 kb
Host smart-cf38ffd9-ab18-41a5-86e7-0f64ec244aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827110982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3827110982
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4142197758
Short name T162
Test name
Test status
Simulation time 148868780 ps
CPU time 2 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:13 PM PDT 24
Peak memory 210052 kb
Host smart-4b6926c5-ce31-4e70-8317-10246675fdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142197758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4142197758
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3141127808
Short name T147
Test name
Test status
Simulation time 112991292 ps
CPU time 2.84 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:27 PM PDT 24
Peak memory 210496 kb
Host smart-b0b8a736-a578-489a-a067-5362ea309416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141127808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3141127808
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2711917615
Short name T77
Test name
Test status
Simulation time 160480202 ps
CPU time 2.21 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:13 PM PDT 24
Peak memory 216388 kb
Host smart-e543405c-82e9-41b4-8813-da1f6757b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711917615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2711917615
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2336790143
Short name T380
Test name
Test status
Simulation time 138169514 ps
CPU time 2.62 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:08 PM PDT 24
Peak memory 214424 kb
Host smart-979bf4fc-4063-4d21-9953-e4b4fb1436ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336790143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2336790143
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2336340613
Short name T490
Test name
Test status
Simulation time 95296219 ps
CPU time 2.38 seconds
Started Jun 25 05:23:03 PM PDT 24
Finished Jun 25 05:23:06 PM PDT 24
Peak memory 207420 kb
Host smart-5fe9169e-3183-4bec-aa9c-b5dbf3cf8779
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336340613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2336340613
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1806042384
Short name T364
Test name
Test status
Simulation time 46621037 ps
CPU time 2.33 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:57 PM PDT 24
Peak memory 214236 kb
Host smart-54ac97dc-a55b-42ce-b65e-f900e69420b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806042384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1806042384
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.47284391
Short name T231
Test name
Test status
Simulation time 34699645 ps
CPU time 2.13 seconds
Started Jun 25 05:24:13 PM PDT 24
Finished Jun 25 05:24:16 PM PDT 24
Peak memory 214148 kb
Host smart-795476c4-4ade-4cd0-8d4c-525ab21a848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47284391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.47284391
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_sideload.283312640
Short name T378
Test name
Test status
Simulation time 119347320 ps
CPU time 3.49 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:16 PM PDT 24
Peak memory 206732 kb
Host smart-1b3daba3-b6f4-4cd4-b13a-603ea3ac7c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283312640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.283312640
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1031307559
Short name T75
Test name
Test status
Simulation time 1028607652 ps
CPU time 19.66 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 222612 kb
Host smart-84c52d95-e6fc-4837-8178-d8f1211ef155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031307559 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1031307559
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_random.3238443253
Short name T312
Test name
Test status
Simulation time 1984673979 ps
CPU time 46.49 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 218300 kb
Host smart-5e61ef03-4a27-4997-a354-d81e22caadc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238443253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3238443253
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1537527544
Short name T345
Test name
Test status
Simulation time 299879394 ps
CPU time 4.92 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:40 PM PDT 24
Peak memory 222436 kb
Host smart-5d5a79c3-90b5-4a73-a8e6-8caa671ae035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537527544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1537527544
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2488072522
Short name T232
Test name
Test status
Simulation time 131725267 ps
CPU time 3.26 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 214184 kb
Host smart-0cbcd946-2614-49e4-96c1-9bb737619f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488072522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2488072522
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_random.1790105336
Short name T189
Test name
Test status
Simulation time 317014578 ps
CPU time 4.11 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 209912 kb
Host smart-2a739e88-1f17-42de-a88f-b0ebe74a98ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790105336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1790105336
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3619724988
Short name T225
Test name
Test status
Simulation time 2271804428 ps
CPU time 42.51 seconds
Started Jun 25 05:25:00 PM PDT 24
Finished Jun 25 05:25:44 PM PDT 24
Peak memory 215172 kb
Host smart-df42970c-a76c-4caf-b96f-42bb87598725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619724988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3619724988
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1545104286
Short name T217
Test name
Test status
Simulation time 85172271 ps
CPU time 4.78 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 220276 kb
Host smart-0a1fcbe8-14e3-4c32-8b87-c5779d4b7eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545104286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1545104286
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1360149236
Short name T208
Test name
Test status
Simulation time 5198074131 ps
CPU time 153.47 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:28:01 PM PDT 24
Peak memory 217392 kb
Host smart-ca6ecf8e-186b-40cc-a4cf-f3fe35ce87f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360149236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1360149236
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_random.1980176452
Short name T375
Test name
Test status
Simulation time 77405915 ps
CPU time 3.47 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 209488 kb
Host smart-c9933d0f-280f-4a4f-ac1a-db02f4828ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980176452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1980176452
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3524450868
Short name T54
Test name
Test status
Simulation time 42859504 ps
CPU time 2.8 seconds
Started Jun 25 05:23:30 PM PDT 24
Finished Jun 25 05:23:34 PM PDT 24
Peak memory 217128 kb
Host smart-32a5b8d9-3859-4dd0-9c08-39f99ee61f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524450868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3524450868
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4217658808
Short name T131
Test name
Test status
Simulation time 804781579 ps
CPU time 14.59 seconds
Started Jun 25 05:20:53 PM PDT 24
Finished Jun 25 05:21:08 PM PDT 24
Peak memory 205512 kb
Host smart-83269416-1c12-4ff2-af8a-665e5d13c67f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217658808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
217658808
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2637770850
Short name T1010
Test name
Test status
Simulation time 2086454863 ps
CPU time 9.52 seconds
Started Jun 25 05:20:49 PM PDT 24
Finished Jun 25 05:20:59 PM PDT 24
Peak memory 205408 kb
Host smart-fe074be9-289c-46db-91e4-fb2e84aceeab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637770850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
637770850
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3573289066
Short name T1000
Test name
Test status
Simulation time 21189007 ps
CPU time 1.01 seconds
Started Jun 25 05:20:51 PM PDT 24
Finished Jun 25 05:20:53 PM PDT 24
Peak memory 205476 kb
Host smart-21f18be4-e6a5-4b00-a6cb-cf4336e9b4f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573289066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
573289066
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3618434427
Short name T987
Test name
Test status
Simulation time 17264981 ps
CPU time 1.28 seconds
Started Jun 25 05:20:54 PM PDT 24
Finished Jun 25 05:20:57 PM PDT 24
Peak memory 213624 kb
Host smart-d6ccbb0d-02f4-40a3-a3d3-18a9dc270992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618434427 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3618434427
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3030154712
Short name T1037
Test name
Test status
Simulation time 24515059 ps
CPU time 1.14 seconds
Started Jun 25 05:20:50 PM PDT 24
Finished Jun 25 05:20:52 PM PDT 24
Peak memory 205408 kb
Host smart-03792a97-e459-4043-a703-62e295fd436f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030154712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3030154712
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4101370239
Short name T1063
Test name
Test status
Simulation time 9986491 ps
CPU time 0.78 seconds
Started Jun 25 05:20:49 PM PDT 24
Finished Jun 25 05:20:50 PM PDT 24
Peak memory 205292 kb
Host smart-790d203f-4096-4687-bcc3-17426d8d2bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101370239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4101370239
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2602057271
Short name T1006
Test name
Test status
Simulation time 726801995 ps
CPU time 1.56 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:20:59 PM PDT 24
Peak memory 205436 kb
Host smart-7363244c-b222-4a13-be28-f0588a9e258a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602057271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2602057271
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3021774048
Short name T950
Test name
Test status
Simulation time 156627922 ps
CPU time 1.63 seconds
Started Jun 25 05:20:51 PM PDT 24
Finished Jun 25 05:20:53 PM PDT 24
Peak memory 214004 kb
Host smart-bbf73182-f4b8-4264-bab3-d3800701531c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021774048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3021774048
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1354827974
Short name T986
Test name
Test status
Simulation time 412099519 ps
CPU time 4.35 seconds
Started Jun 25 05:20:49 PM PDT 24
Finished Jun 25 05:20:54 PM PDT 24
Peak memory 214028 kb
Host smart-2f00b344-9d44-4739-b0f0-fd5e6b4e0845
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354827974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1354827974
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.70832442
Short name T1021
Test name
Test status
Simulation time 78680288 ps
CPU time 1.69 seconds
Started Jun 25 05:20:50 PM PDT 24
Finished Jun 25 05:20:53 PM PDT 24
Peak memory 214752 kb
Host smart-57bba546-ea37-4fde-af6d-4743ed170292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70832442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.70832442
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.71443450
Short name T386
Test name
Test status
Simulation time 77765098 ps
CPU time 3.58 seconds
Started Jun 25 05:20:47 PM PDT 24
Finished Jun 25 05:20:51 PM PDT 24
Peak memory 213588 kb
Host smart-7e44dc45-2135-4aba-b586-a35a6be42d2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71443450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.71443450
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2874690572
Short name T1080
Test name
Test status
Simulation time 2294189311 ps
CPU time 7.34 seconds
Started Jun 25 05:20:57 PM PDT 24
Finished Jun 25 05:21:05 PM PDT 24
Peak memory 205468 kb
Host smart-b5a82445-debd-4b98-b092-fb3cffb9796f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874690572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
874690572
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3777129222
Short name T1084
Test name
Test status
Simulation time 463424687 ps
CPU time 12.34 seconds
Started Jun 25 05:20:58 PM PDT 24
Finished Jun 25 05:21:11 PM PDT 24
Peak memory 205212 kb
Host smart-d00551eb-05c9-41f8-868a-208a4b2b3c69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777129222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
777129222
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2227345730
Short name T998
Test name
Test status
Simulation time 24865330 ps
CPU time 1.05 seconds
Started Jun 25 05:20:57 PM PDT 24
Finished Jun 25 05:20:59 PM PDT 24
Peak memory 205476 kb
Host smart-9abe30e7-d85a-4d5f-ad36-a9dcba8d5fd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227345730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
227345730
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2162171022
Short name T997
Test name
Test status
Simulation time 229275602 ps
CPU time 1.85 seconds
Started Jun 25 05:21:03 PM PDT 24
Finished Jun 25 05:21:06 PM PDT 24
Peak memory 213748 kb
Host smart-bcebdbb7-a975-4c1e-915b-785ffbf5bd3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162171022 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2162171022
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2369987818
Short name T1001
Test name
Test status
Simulation time 71632608 ps
CPU time 1.17 seconds
Started Jun 25 05:20:59 PM PDT 24
Finished Jun 25 05:21:01 PM PDT 24
Peak memory 205604 kb
Host smart-9495b7b3-8878-4603-ae1a-eccc7b958d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369987818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2369987818
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1877037991
Short name T1051
Test name
Test status
Simulation time 11470436 ps
CPU time 0.73 seconds
Started Jun 25 05:20:57 PM PDT 24
Finished Jun 25 05:20:58 PM PDT 24
Peak memory 205656 kb
Host smart-49bf4b60-ca37-47a9-8254-918b500133e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877037991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1877037991
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1989357067
Short name T1017
Test name
Test status
Simulation time 388685775 ps
CPU time 2.46 seconds
Started Jun 25 05:20:57 PM PDT 24
Finished Jun 25 05:21:00 PM PDT 24
Peak memory 205496 kb
Host smart-28c3bc6d-5520-48ab-9cf2-bbce1f0d9fd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989357067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1989357067
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3441679058
Short name T135
Test name
Test status
Simulation time 1023855810 ps
CPU time 5.54 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:21:02 PM PDT 24
Peak memory 214044 kb
Host smart-9a9b8ebf-eab4-419d-b442-ba8a6ded09c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441679058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3441679058
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3618904826
Short name T978
Test name
Test status
Simulation time 98734348 ps
CPU time 3.27 seconds
Started Jun 25 05:20:58 PM PDT 24
Finished Jun 25 05:21:02 PM PDT 24
Peak memory 213508 kb
Host smart-0dda951e-2c1c-411b-94df-c12e39ab1915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618904826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3618904826
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1759513710
Short name T943
Test name
Test status
Simulation time 28888434 ps
CPU time 1.11 seconds
Started Jun 25 05:21:34 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 205412 kb
Host smart-872a9970-9964-4ca2-9e47-d60e84af46d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759513710 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1759513710
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1213491690
Short name T138
Test name
Test status
Simulation time 24992297 ps
CPU time 0.93 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:39 PM PDT 24
Peak memory 205316 kb
Host smart-7d1bd68c-596b-4318-bfad-a29269ead4ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213491690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1213491690
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4263808825
Short name T949
Test name
Test status
Simulation time 23008891 ps
CPU time 0.86 seconds
Started Jun 25 05:21:35 PM PDT 24
Finished Jun 25 05:21:37 PM PDT 24
Peak memory 205384 kb
Host smart-bb1b53e9-592b-42c6-9fe8-3174cc9a7d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263808825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4263808825
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3954623243
Short name T1035
Test name
Test status
Simulation time 77004896 ps
CPU time 1.62 seconds
Started Jun 25 05:21:32 PM PDT 24
Finished Jun 25 05:21:35 PM PDT 24
Peak memory 205404 kb
Host smart-529be32b-f428-4125-8ccc-ac61d618512f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954623243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3954623243
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3162293539
Short name T984
Test name
Test status
Simulation time 65127935 ps
CPU time 1.73 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:39 PM PDT 24
Peak memory 213988 kb
Host smart-dbd57777-23d7-4099-858c-5a357df46993
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162293539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3162293539
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2620435667
Short name T952
Test name
Test status
Simulation time 646692656 ps
CPU time 9.01 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 213932 kb
Host smart-705e7edd-e973-4ec5-af3b-f64250919e44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620435667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2620435667
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2173093745
Short name T1034
Test name
Test status
Simulation time 48250632 ps
CPU time 1.66 seconds
Started Jun 25 05:21:40 PM PDT 24
Finished Jun 25 05:21:43 PM PDT 24
Peak memory 213792 kb
Host smart-ffc7300d-7556-4814-a152-8fded6dc0fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173093745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2173093745
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.485010960
Short name T1002
Test name
Test status
Simulation time 107671733 ps
CPU time 1.67 seconds
Started Jun 25 05:21:35 PM PDT 24
Finished Jun 25 05:21:38 PM PDT 24
Peak memory 213636 kb
Host smart-ac8281e2-b8c0-48dc-9829-5cb9ac26af42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485010960 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.485010960
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.930530744
Short name T132
Test name
Test status
Simulation time 82055412 ps
CPU time 1.48 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:39 PM PDT 24
Peak memory 205532 kb
Host smart-f7002e66-d7bf-4b19-ad25-50e2a27eaa66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930530744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.930530744
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2091674913
Short name T930
Test name
Test status
Simulation time 42496103 ps
CPU time 0.7 seconds
Started Jun 25 05:21:40 PM PDT 24
Finished Jun 25 05:21:42 PM PDT 24
Peak memory 205372 kb
Host smart-baf2fa6d-461b-482a-9af3-00b6133ae9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091674913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2091674913
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2733055044
Short name T972
Test name
Test status
Simulation time 21660498 ps
CPU time 1.43 seconds
Started Jun 25 05:21:34 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 205396 kb
Host smart-c6bc6559-ad46-4975-bdd5-1878fb6642e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733055044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2733055044
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3296285866
Short name T1044
Test name
Test status
Simulation time 170263109 ps
CPU time 1.82 seconds
Started Jun 25 05:21:33 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 214064 kb
Host smart-fc848359-e262-4ede-a70c-914e852e6731
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296285866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3296285866
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1886036881
Short name T971
Test name
Test status
Simulation time 304529576 ps
CPU time 3.75 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:41 PM PDT 24
Peak memory 219992 kb
Host smart-b6d16408-df14-4569-811b-f93fed74aad0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886036881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1886036881
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3666273622
Short name T942
Test name
Test status
Simulation time 57642760 ps
CPU time 1.9 seconds
Started Jun 25 05:21:37 PM PDT 24
Finished Jun 25 05:21:40 PM PDT 24
Peak memory 213756 kb
Host smart-adc309bc-42fb-49bd-80de-bb165dc9d30a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666273622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3666273622
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.869935337
Short name T1045
Test name
Test status
Simulation time 75718057 ps
CPU time 3.21 seconds
Started Jun 25 05:21:34 PM PDT 24
Finished Jun 25 05:21:38 PM PDT 24
Peak memory 205504 kb
Host smart-997f4d18-82a5-461c-b26b-f9cd7922f9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869935337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.869935337
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.16792600
Short name T1056
Test name
Test status
Simulation time 83027145 ps
CPU time 2.06 seconds
Started Jun 25 05:21:35 PM PDT 24
Finished Jun 25 05:21:38 PM PDT 24
Peak memory 213768 kb
Host smart-5d57bebe-4ab9-4462-bb8a-7522bfc6de7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792600 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.16792600
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1769024879
Short name T1033
Test name
Test status
Simulation time 18959857 ps
CPU time 0.83 seconds
Started Jun 25 05:21:40 PM PDT 24
Finished Jun 25 05:21:42 PM PDT 24
Peak memory 205416 kb
Host smart-e5663995-23b9-4f3b-a52a-f647e54177ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769024879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1769024879
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1333511474
Short name T1016
Test name
Test status
Simulation time 29736809 ps
CPU time 0.73 seconds
Started Jun 25 05:21:35 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 205368 kb
Host smart-99497993-a4fe-4499-b2e6-0211e56b9924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333511474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1333511474
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1003264066
Short name T953
Test name
Test status
Simulation time 172137916 ps
CPU time 2.53 seconds
Started Jun 25 05:21:41 PM PDT 24
Finished Jun 25 05:21:44 PM PDT 24
Peak memory 205396 kb
Host smart-4228a185-d0e5-4e90-ba6c-c5e9682a166e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003264066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1003264066
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1717827402
Short name T111
Test name
Test status
Simulation time 325029999 ps
CPU time 2.13 seconds
Started Jun 25 05:21:37 PM PDT 24
Finished Jun 25 05:21:41 PM PDT 24
Peak memory 214072 kb
Host smart-42a3b121-4ccc-4919-ae80-ca1a8e963bca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717827402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1717827402
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.116843533
Short name T1039
Test name
Test status
Simulation time 797765018 ps
CPU time 9.37 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 214008 kb
Host smart-8573e2f3-c7a4-4ed2-8eff-2e51ac21548c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116843533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.116843533
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.197147537
Short name T1032
Test name
Test status
Simulation time 299891777 ps
CPU time 5.6 seconds
Started Jun 25 05:21:35 PM PDT 24
Finished Jun 25 05:21:43 PM PDT 24
Peak memory 213712 kb
Host smart-58705211-8246-4d10-9a6f-e37a75cf5d64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197147537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.197147537
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2527198215
Short name T933
Test name
Test status
Simulation time 103464862 ps
CPU time 1.79 seconds
Started Jun 25 05:21:45 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 213624 kb
Host smart-8828ec52-9bca-4819-9383-37f440b7a414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527198215 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2527198215
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.291003561
Short name T1040
Test name
Test status
Simulation time 58534784 ps
CPU time 1 seconds
Started Jun 25 05:21:43 PM PDT 24
Finished Jun 25 05:21:45 PM PDT 24
Peak memory 205388 kb
Host smart-8bae9e19-ec1b-4036-96f1-65ca91ae0b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291003561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.291003561
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1204207133
Short name T1020
Test name
Test status
Simulation time 17361235 ps
CPU time 0.71 seconds
Started Jun 25 05:21:36 PM PDT 24
Finished Jun 25 05:21:38 PM PDT 24
Peak memory 205268 kb
Host smart-3d46b6f6-7a6b-4020-a0cb-f6b5732e6915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204207133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1204207133
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2443796031
Short name T1050
Test name
Test status
Simulation time 120317946 ps
CPU time 3.97 seconds
Started Jun 25 05:21:46 PM PDT 24
Finished Jun 25 05:21:51 PM PDT 24
Peak memory 205484 kb
Host smart-dcba919d-e99b-4499-b258-4f1f43b6d63c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443796031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2443796031
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1163861001
Short name T979
Test name
Test status
Simulation time 128397567 ps
CPU time 3.9 seconds
Started Jun 25 05:21:37 PM PDT 24
Finished Jun 25 05:21:42 PM PDT 24
Peak memory 218484 kb
Host smart-07085eda-8971-4225-b5eb-7e91c5bfd60c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163861001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1163861001
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1229098545
Short name T1070
Test name
Test status
Simulation time 149220792 ps
CPU time 6.62 seconds
Started Jun 25 05:21:40 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 220020 kb
Host smart-7c6ba275-7100-42c4-b0c1-87de282b9dea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229098545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1229098545
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3422791308
Short name T176
Test name
Test status
Simulation time 593245766 ps
CPU time 4.6 seconds
Started Jun 25 05:21:41 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 213616 kb
Host smart-bc75a5fd-e513-4757-8785-0addd537faa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422791308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3422791308
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2049127246
Short name T1057
Test name
Test status
Simulation time 136949215 ps
CPU time 5.57 seconds
Started Jun 25 05:21:41 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 213552 kb
Host smart-95745b5a-d1ba-4d0a-846d-b921da6a54c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049127246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2049127246
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.523412785
Short name T936
Test name
Test status
Simulation time 122242442 ps
CPU time 1.35 seconds
Started Jun 25 05:21:44 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 214032 kb
Host smart-9f7ec753-7f44-4fd3-8c33-82fc597fd60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523412785 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.523412785
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.33034216
Short name T934
Test name
Test status
Simulation time 353247682 ps
CPU time 1.32 seconds
Started Jun 25 05:21:46 PM PDT 24
Finished Jun 25 05:21:49 PM PDT 24
Peak memory 205476 kb
Host smart-ce661a13-2d4d-448b-b6f3-5b46a2b699c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.33034216
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.748035647
Short name T985
Test name
Test status
Simulation time 13634933 ps
CPU time 0.82 seconds
Started Jun 25 05:21:46 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 205292 kb
Host smart-a7a86f57-9045-4683-9e02-2d4f60ea61ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748035647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.748035647
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2322985031
Short name T1048
Test name
Test status
Simulation time 725608873 ps
CPU time 2.74 seconds
Started Jun 25 05:21:44 PM PDT 24
Finished Jun 25 05:21:49 PM PDT 24
Peak memory 205340 kb
Host smart-a8c427bf-bc9b-4279-8c00-6423ee67ee76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322985031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2322985031
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2214152286
Short name T117
Test name
Test status
Simulation time 52983904 ps
CPU time 2.37 seconds
Started Jun 25 05:21:47 PM PDT 24
Finished Jun 25 05:21:51 PM PDT 24
Peak memory 214104 kb
Host smart-083d5fe9-6e8e-4b8c-afb7-53a1d4c22cf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214152286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2214152286
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.32277100
Short name T965
Test name
Test status
Simulation time 163040626 ps
CPU time 5.18 seconds
Started Jun 25 05:21:44 PM PDT 24
Finished Jun 25 05:21:50 PM PDT 24
Peak memory 213972 kb
Host smart-3a46ed2b-3829-4d22-bc53-4ef0ac15fa34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_shadow_reg_errors_with_csr_rw.32277100
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3886570447
Short name T996
Test name
Test status
Simulation time 200943923 ps
CPU time 3.14 seconds
Started Jun 25 05:21:46 PM PDT 24
Finished Jun 25 05:21:50 PM PDT 24
Peak memory 213772 kb
Host smart-8f12dd1b-3485-4297-933d-ce9e105ce55c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886570447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3886570447
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2080259923
Short name T939
Test name
Test status
Simulation time 30499979 ps
CPU time 2.53 seconds
Started Jun 25 05:21:45 PM PDT 24
Finished Jun 25 05:21:49 PM PDT 24
Peak memory 213800 kb
Host smart-a0883ed9-fe83-4ce9-b66a-2e20514c6d13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080259923 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2080259923
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1618170553
Short name T134
Test name
Test status
Simulation time 58889893 ps
CPU time 1.19 seconds
Started Jun 25 05:21:44 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 205400 kb
Host smart-1029eae0-ccfc-4a2a-b34a-ecf19b600587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618170553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1618170553
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3438013979
Short name T941
Test name
Test status
Simulation time 18419513 ps
CPU time 0.71 seconds
Started Jun 25 05:21:48 PM PDT 24
Finished Jun 25 05:21:51 PM PDT 24
Peak memory 205292 kb
Host smart-43ed720f-8b09-4872-a20e-de4f56d2c965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438013979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3438013979
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3484072700
Short name T1060
Test name
Test status
Simulation time 19798455 ps
CPU time 1.43 seconds
Started Jun 25 05:21:45 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 205500 kb
Host smart-a21ec652-e471-42fd-bf20-203a2c9c9afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484072700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3484072700
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1376971089
Short name T1062
Test name
Test status
Simulation time 317194872 ps
CPU time 4.69 seconds
Started Jun 25 05:21:49 PM PDT 24
Finished Jun 25 05:21:55 PM PDT 24
Peak memory 214012 kb
Host smart-c05a6fe1-4f30-4bae-8515-65a78ee6988d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376971089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1376971089
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1426084837
Short name T1011
Test name
Test status
Simulation time 172140924 ps
CPU time 7.17 seconds
Started Jun 25 05:21:47 PM PDT 24
Finished Jun 25 05:21:55 PM PDT 24
Peak memory 214204 kb
Host smart-527c43ee-5bcf-48bd-a214-887f7ffc0b90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426084837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1426084837
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.369764922
Short name T1014
Test name
Test status
Simulation time 722253646 ps
CPU time 6.31 seconds
Started Jun 25 05:21:45 PM PDT 24
Finished Jun 25 05:21:53 PM PDT 24
Peak memory 215748 kb
Host smart-5081a612-9890-437e-b3f2-2c90a96f6a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369764922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.369764922
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2178191396
Short name T168
Test name
Test status
Simulation time 736885984 ps
CPU time 8.31 seconds
Started Jun 25 05:21:47 PM PDT 24
Finished Jun 25 05:21:57 PM PDT 24
Peak memory 215308 kb
Host smart-aeaa169c-1eb5-4a53-b825-0a6aedb33048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178191396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2178191396
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4040001762
Short name T1041
Test name
Test status
Simulation time 101148313 ps
CPU time 1.37 seconds
Started Jun 25 05:21:53 PM PDT 24
Finished Jun 25 05:21:56 PM PDT 24
Peak memory 213840 kb
Host smart-b7fa9d77-e307-4b94-9315-257311efa4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040001762 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.4040001762
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3148044932
Short name T150
Test name
Test status
Simulation time 28134867 ps
CPU time 0.98 seconds
Started Jun 25 05:21:46 PM PDT 24
Finished Jun 25 05:21:49 PM PDT 24
Peak memory 205432 kb
Host smart-ba305da3-5b1a-4e0e-9e4c-a6b8d656ef19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148044932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3148044932
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3951324050
Short name T1081
Test name
Test status
Simulation time 11980076 ps
CPU time 0.75 seconds
Started Jun 25 05:21:47 PM PDT 24
Finished Jun 25 05:21:49 PM PDT 24
Peak memory 205292 kb
Host smart-9e5a9c20-54cf-4862-8cc9-1bb48e19d3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951324050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3951324050
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1927227238
Short name T1046
Test name
Test status
Simulation time 37936082 ps
CPU time 1.39 seconds
Started Jun 25 05:21:47 PM PDT 24
Finished Jun 25 05:21:50 PM PDT 24
Peak memory 205504 kb
Host smart-5e092a36-a9dd-417e-985b-09b054dec295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927227238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1927227238
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.265474993
Short name T115
Test name
Test status
Simulation time 742407215 ps
CPU time 3.3 seconds
Started Jun 25 05:21:43 PM PDT 24
Finished Jun 25 05:21:48 PM PDT 24
Peak memory 213932 kb
Host smart-9e3aebb0-b3d3-4c30-bf35-28a879b30f5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265474993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.265474993
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3767350511
Short name T1005
Test name
Test status
Simulation time 1436561147 ps
CPU time 13.03 seconds
Started Jun 25 05:21:45 PM PDT 24
Finished Jun 25 05:22:00 PM PDT 24
Peak memory 214008 kb
Host smart-8e0ce2e1-71af-459d-852a-d232c53e8286
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767350511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3767350511
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2962850660
Short name T974
Test name
Test status
Simulation time 43356364 ps
CPU time 1.74 seconds
Started Jun 25 05:21:44 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 213644 kb
Host smart-ed6bd722-fc2e-4c1b-ba1d-9d461a438122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962850660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2962850660
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1767406008
Short name T1007
Test name
Test status
Simulation time 48071105 ps
CPU time 1.56 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 213704 kb
Host smart-cf4c2249-6df2-48b9-9bc9-11dd3f0a1dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767406008 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1767406008
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2396699406
Short name T966
Test name
Test status
Simulation time 11717821 ps
CPU time 0.98 seconds
Started Jun 25 05:22:00 PM PDT 24
Finished Jun 25 05:22:02 PM PDT 24
Peak memory 205432 kb
Host smart-ff8f29d2-9d5d-4c58-9ccc-248eff3dbb43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396699406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2396699406
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2946563635
Short name T960
Test name
Test status
Simulation time 26986394 ps
CPU time 0.72 seconds
Started Jun 25 05:21:55 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 205356 kb
Host smart-78f36ad1-88d4-43ff-b953-c2171258c16e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946563635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2946563635
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2734862721
Short name T999
Test name
Test status
Simulation time 43249503 ps
CPU time 1.8 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 204508 kb
Host smart-13204d27-8b35-4c14-a65e-327e31e04c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734862721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2734862721
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1760016731
Short name T114
Test name
Test status
Simulation time 110498163 ps
CPU time 3.55 seconds
Started Jun 25 05:21:46 PM PDT 24
Finished Jun 25 05:21:51 PM PDT 24
Peak memory 213972 kb
Host smart-6912f6c5-1c16-41f3-94cc-65b9883fc5f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760016731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1760016731
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2346637578
Short name T975
Test name
Test status
Simulation time 291017659 ps
CPU time 8.05 seconds
Started Jun 25 05:21:44 PM PDT 24
Finished Jun 25 05:21:54 PM PDT 24
Peak memory 213964 kb
Host smart-c0f5fb1e-042b-4566-9e34-4d65426c0d5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346637578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2346637578
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.949924814
Short name T940
Test name
Test status
Simulation time 455360561 ps
CPU time 4.2 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:22:01 PM PDT 24
Peak memory 213580 kb
Host smart-9a9135eb-4193-4783-98a6-07bae3cabb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949924814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.949924814
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3629798848
Short name T964
Test name
Test status
Simulation time 175563080 ps
CPU time 2.32 seconds
Started Jun 25 05:22:00 PM PDT 24
Finished Jun 25 05:22:04 PM PDT 24
Peak memory 213768 kb
Host smart-20694693-3a7b-4e9c-a511-ff5090756399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629798848 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3629798848
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2165517834
Short name T982
Test name
Test status
Simulation time 74602317 ps
CPU time 1.25 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 205424 kb
Host smart-9c4bf82a-9f72-46c8-b4dd-0a9ae817432c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165517834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2165517834
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1790751177
Short name T1058
Test name
Test status
Simulation time 17751580 ps
CPU time 0.73 seconds
Started Jun 25 05:21:56 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 205368 kb
Host smart-c1614493-64d4-4ecf-b040-8b49231e547c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790751177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1790751177
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3374056404
Short name T1043
Test name
Test status
Simulation time 167750083 ps
CPU time 2.54 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:59 PM PDT 24
Peak memory 205500 kb
Host smart-95733a70-defe-4cbc-a46c-65dfd582568f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374056404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3374056404
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.427074066
Short name T963
Test name
Test status
Simulation time 147711980 ps
CPU time 3.43 seconds
Started Jun 25 05:21:53 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 213996 kb
Host smart-99587049-97d7-4f73-82c1-1d5acc43a9cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427074066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.427074066
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.971978001
Short name T970
Test name
Test status
Simulation time 203163966 ps
CPU time 7.89 seconds
Started Jun 25 05:21:53 PM PDT 24
Finished Jun 25 05:22:03 PM PDT 24
Peak memory 214000 kb
Host smart-a7b149c4-fb5d-444a-80f6-48ac8d5453d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971978001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.971978001
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.161896430
Short name T1079
Test name
Test status
Simulation time 39102523 ps
CPU time 2.81 seconds
Started Jun 25 05:21:59 PM PDT 24
Finished Jun 25 05:22:03 PM PDT 24
Peak memory 213868 kb
Host smart-e20c3bab-84f0-4655-8705-c85134633ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161896430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.161896430
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1791554656
Short name T1059
Test name
Test status
Simulation time 31437071 ps
CPU time 1.32 seconds
Started Jun 25 05:21:56 PM PDT 24
Finished Jun 25 05:21:59 PM PDT 24
Peak memory 213748 kb
Host smart-45e36cf8-fac3-4ea0-816e-f421a1741f05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791554656 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1791554656
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.819717610
Short name T973
Test name
Test status
Simulation time 49042373 ps
CPU time 1.26 seconds
Started Jun 25 05:21:53 PM PDT 24
Finished Jun 25 05:21:56 PM PDT 24
Peak memory 205480 kb
Host smart-8cd78de5-ed5b-4fe7-a637-8bbcd3a33355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819717610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.819717610
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3249982815
Short name T957
Test name
Test status
Simulation time 9230073 ps
CPU time 0.83 seconds
Started Jun 25 05:21:52 PM PDT 24
Finished Jun 25 05:21:54 PM PDT 24
Peak memory 205236 kb
Host smart-d3803f4e-2820-4497-96ae-0357c29c35ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249982815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3249982815
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3385001276
Short name T1008
Test name
Test status
Simulation time 35751987 ps
CPU time 2.17 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 205424 kb
Host smart-98bc91d5-fa1c-41ad-8c97-fb76c288c67f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385001276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3385001276
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3130223030
Short name T118
Test name
Test status
Simulation time 471537253 ps
CPU time 2.58 seconds
Started Jun 25 05:21:59 PM PDT 24
Finished Jun 25 05:22:02 PM PDT 24
Peak memory 213960 kb
Host smart-020a8285-431f-44ad-9d6f-23f49197b1df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130223030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3130223030
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2695785052
Short name T1023
Test name
Test status
Simulation time 693480188 ps
CPU time 8.63 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:22:05 PM PDT 24
Peak memory 214076 kb
Host smart-0ae2b150-5394-43dc-953d-6102cccd3a8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695785052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2695785052
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3900574838
Short name T993
Test name
Test status
Simulation time 78223141 ps
CPU time 2.36 seconds
Started Jun 25 05:21:56 PM PDT 24
Finished Jun 25 05:22:00 PM PDT 24
Peak memory 213716 kb
Host smart-f8d5dc66-9dc9-4ff3-8df6-fde2587ce2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900574838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3900574838
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2466382537
Short name T170
Test name
Test status
Simulation time 401158759 ps
CPU time 5.36 seconds
Started Jun 25 05:22:00 PM PDT 24
Finished Jun 25 05:22:07 PM PDT 24
Peak memory 213756 kb
Host smart-a13c74d3-787a-4b35-986f-337c2f5ba609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466382537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2466382537
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2533319440
Short name T1015
Test name
Test status
Simulation time 464164824 ps
CPU time 9.27 seconds
Started Jun 25 05:21:04 PM PDT 24
Finished Jun 25 05:21:15 PM PDT 24
Peak memory 205540 kb
Host smart-64960c5e-7ba5-4bbb-87f8-b0a275501591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533319440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
533319440
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4266597553
Short name T1042
Test name
Test status
Simulation time 8143549417 ps
CPU time 9.74 seconds
Started Jun 25 05:20:58 PM PDT 24
Finished Jun 25 05:21:09 PM PDT 24
Peak memory 205272 kb
Host smart-4d2b8110-5d57-43ff-bcad-3e063ea8c607
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266597553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
266597553
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.230897542
Short name T931
Test name
Test status
Simulation time 111583996 ps
CPU time 1.39 seconds
Started Jun 25 05:20:55 PM PDT 24
Finished Jun 25 05:20:58 PM PDT 24
Peak memory 205404 kb
Host smart-f9574d5e-7e0d-4fe5-9686-d0c65272f0b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230897542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.230897542
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1950614584
Short name T1022
Test name
Test status
Simulation time 49839948 ps
CPU time 1.74 seconds
Started Jun 25 05:21:06 PM PDT 24
Finished Jun 25 05:21:10 PM PDT 24
Peak memory 213700 kb
Host smart-8fabe309-e5ce-41f6-9b53-21f81cf9feae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950614584 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1950614584
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1224260037
Short name T945
Test name
Test status
Simulation time 15784326 ps
CPU time 1.18 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:20:58 PM PDT 24
Peak memory 205440 kb
Host smart-78badb98-0048-4858-bdb9-aa4b4226b89e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224260037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1224260037
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1263268728
Short name T1031
Test name
Test status
Simulation time 44815301 ps
CPU time 0.79 seconds
Started Jun 25 05:21:04 PM PDT 24
Finished Jun 25 05:21:05 PM PDT 24
Peak memory 205292 kb
Host smart-29bef479-9466-408e-af40-ce08bb88ae1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263268728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1263268728
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1248230461
Short name T1036
Test name
Test status
Simulation time 32549766 ps
CPU time 2.46 seconds
Started Jun 25 05:21:06 PM PDT 24
Finished Jun 25 05:21:11 PM PDT 24
Peak memory 205368 kb
Host smart-355f3b21-105c-4827-9c5e-cf95c00172c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248230461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1248230461
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1608109934
Short name T1049
Test name
Test status
Simulation time 150541654 ps
CPU time 2.47 seconds
Started Jun 25 05:20:57 PM PDT 24
Finished Jun 25 05:21:00 PM PDT 24
Peak memory 213832 kb
Host smart-b4e37943-d2e0-4aed-b5b4-d36d70778cc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608109934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1608109934
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1618962621
Short name T990
Test name
Test status
Simulation time 330675545 ps
CPU time 8.05 seconds
Started Jun 25 05:20:57 PM PDT 24
Finished Jun 25 05:21:06 PM PDT 24
Peak memory 213992 kb
Host smart-61acaebc-0437-4ea6-bd10-d82d6f9f7db2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618962621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1618962621
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1400545498
Short name T932
Test name
Test status
Simulation time 162239484 ps
CPU time 3.67 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:21:00 PM PDT 24
Peak memory 213628 kb
Host smart-ec67aa55-547d-4d5f-bf22-d0456e8268a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400545498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1400545498
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1307010283
Short name T167
Test name
Test status
Simulation time 414291200 ps
CPU time 6.44 seconds
Started Jun 25 05:20:56 PM PDT 24
Finished Jun 25 05:21:03 PM PDT 24
Peak memory 213592 kb
Host smart-b7068c83-bd4d-431e-b7c7-61d2265102c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307010283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1307010283
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.190062354
Short name T921
Test name
Test status
Simulation time 44459628 ps
CPU time 0.73 seconds
Started Jun 25 05:21:52 PM PDT 24
Finished Jun 25 05:21:54 PM PDT 24
Peak memory 205372 kb
Host smart-6e745d1a-3b70-47a7-8fd3-bef7a9ce4991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190062354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.190062354
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3897100856
Short name T967
Test name
Test status
Simulation time 55776146 ps
CPU time 0.77 seconds
Started Jun 25 05:21:59 PM PDT 24
Finished Jun 25 05:22:01 PM PDT 24
Peak memory 205380 kb
Host smart-1fd2a88a-320a-4324-bdb4-e259731f7b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897100856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3897100856
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1877328597
Short name T1053
Test name
Test status
Simulation time 11661088 ps
CPU time 0.73 seconds
Started Jun 25 05:21:58 PM PDT 24
Finished Jun 25 05:22:00 PM PDT 24
Peak memory 205296 kb
Host smart-a261fbf8-0d08-4bf5-a2d7-5132cb468f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877328597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1877328597
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.618764347
Short name T958
Test name
Test status
Simulation time 12501274 ps
CPU time 0.78 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:57 PM PDT 24
Peak memory 204408 kb
Host smart-8cded1a6-252e-48e1-9abd-796de24864d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618764347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.618764347
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3342942646
Short name T1085
Test name
Test status
Simulation time 12134711 ps
CPU time 0.73 seconds
Started Jun 25 05:21:53 PM PDT 24
Finished Jun 25 05:21:56 PM PDT 24
Peak memory 205368 kb
Host smart-b1d194b2-3dd1-46bb-ac22-d688a413ee9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342942646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3342942646
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2216216280
Short name T968
Test name
Test status
Simulation time 97403360 ps
CPU time 0.89 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:57 PM PDT 24
Peak memory 205328 kb
Host smart-32a6da68-2ed0-465f-a9c2-d286802bed71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216216280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2216216280
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.686848370
Short name T925
Test name
Test status
Simulation time 37967612 ps
CPU time 0.7 seconds
Started Jun 25 05:21:57 PM PDT 24
Finished Jun 25 05:21:59 PM PDT 24
Peak memory 205296 kb
Host smart-c1f0caba-8acb-49ce-8d2d-16def4f00d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686848370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.686848370
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.269531222
Short name T951
Test name
Test status
Simulation time 55460298 ps
CPU time 0.71 seconds
Started Jun 25 05:21:51 PM PDT 24
Finished Jun 25 05:21:53 PM PDT 24
Peak memory 205332 kb
Host smart-dbd21e75-e9a4-491f-93dd-c28713542153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269531222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.269531222
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4204428405
Short name T927
Test name
Test status
Simulation time 45733298 ps
CPU time 0.7 seconds
Started Jun 25 05:21:56 PM PDT 24
Finished Jun 25 05:21:58 PM PDT 24
Peak memory 205336 kb
Host smart-68d968b5-eec8-4675-acaf-4770549254e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204428405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4204428405
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.842032469
Short name T954
Test name
Test status
Simulation time 33254788 ps
CPU time 0.85 seconds
Started Jun 25 05:21:54 PM PDT 24
Finished Jun 25 05:21:57 PM PDT 24
Peak memory 205288 kb
Host smart-66a094bb-53ba-4702-904a-723b26f6e2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842032469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.842032469
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3799014958
Short name T130
Test name
Test status
Simulation time 1385531997 ps
CPU time 14.45 seconds
Started Jun 25 05:21:07 PM PDT 24
Finished Jun 25 05:21:23 PM PDT 24
Peak memory 205516 kb
Host smart-72be15ce-bc15-468d-bcfb-6547b7a9b807
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799014958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
799014958
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3117864967
Short name T393
Test name
Test status
Simulation time 5116883451 ps
CPU time 17.81 seconds
Started Jun 25 05:21:07 PM PDT 24
Finished Jun 25 05:21:26 PM PDT 24
Peak memory 205492 kb
Host smart-18ecdf0f-a0f6-4624-8422-fc8abeb099d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117864967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
117864967
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3786635574
Short name T1026
Test name
Test status
Simulation time 102998014 ps
CPU time 0.96 seconds
Started Jun 25 05:21:05 PM PDT 24
Finished Jun 25 05:21:08 PM PDT 24
Peak memory 205356 kb
Host smart-828ee62d-fc0e-4413-9556-4a8ee13c3f43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786635574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
786635574
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2591495218
Short name T956
Test name
Test status
Simulation time 55500485 ps
CPU time 1.75 seconds
Started Jun 25 05:21:04 PM PDT 24
Finished Jun 25 05:21:07 PM PDT 24
Peak memory 213628 kb
Host smart-6d26172a-f191-42d6-9f0a-470f71d16463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591495218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2591495218
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2497687915
Short name T1019
Test name
Test status
Simulation time 60096288 ps
CPU time 1.2 seconds
Started Jun 25 05:21:07 PM PDT 24
Finished Jun 25 05:21:10 PM PDT 24
Peak memory 205372 kb
Host smart-f04986e6-1b3f-4348-824f-8fc6f6cae8e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497687915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2497687915
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2019015656
Short name T1038
Test name
Test status
Simulation time 11662399 ps
CPU time 0.77 seconds
Started Jun 25 05:21:07 PM PDT 24
Finished Jun 25 05:21:09 PM PDT 24
Peak memory 205380 kb
Host smart-e292bd63-1f49-4cc3-858d-a35040bc1be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019015656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2019015656
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2591722633
Short name T137
Test name
Test status
Simulation time 253818914 ps
CPU time 2.06 seconds
Started Jun 25 05:21:05 PM PDT 24
Finished Jun 25 05:21:09 PM PDT 24
Peak memory 205492 kb
Host smart-811acaf0-b36f-4a38-94ac-fb3705b298e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591722633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2591722633
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1342687063
Short name T1083
Test name
Test status
Simulation time 159252328 ps
CPU time 2.47 seconds
Started Jun 25 05:21:05 PM PDT 24
Finished Jun 25 05:21:09 PM PDT 24
Peak memory 214064 kb
Host smart-1077fb86-76c2-4c91-b1a8-2c550d73e9e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342687063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1342687063
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2054235514
Short name T1069
Test name
Test status
Simulation time 308012308 ps
CPU time 8.85 seconds
Started Jun 25 05:21:04 PM PDT 24
Finished Jun 25 05:21:15 PM PDT 24
Peak memory 220116 kb
Host smart-7f80fdbd-9178-4357-bf30-60b043a3830e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054235514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2054235514
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.287306826
Short name T1028
Test name
Test status
Simulation time 371194515 ps
CPU time 4.01 seconds
Started Jun 25 05:21:07 PM PDT 24
Finished Jun 25 05:21:13 PM PDT 24
Peak memory 213724 kb
Host smart-88fcdbc8-b619-4613-a259-b0c5b29b566b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287306826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.287306826
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3660510167
Short name T1029
Test name
Test status
Simulation time 514598749 ps
CPU time 9.72 seconds
Started Jun 25 05:21:04 PM PDT 24
Finished Jun 25 05:21:16 PM PDT 24
Peak memory 213592 kb
Host smart-5007fc68-9509-4c8c-95fc-8ff430fdfbb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660510167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3660510167
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1558964774
Short name T1013
Test name
Test status
Simulation time 31849039 ps
CPU time 0.79 seconds
Started Jun 25 05:22:01 PM PDT 24
Finished Jun 25 05:22:03 PM PDT 24
Peak memory 205368 kb
Host smart-6b4c93c7-e931-4b63-b9a6-7daf8bdbc490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558964774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1558964774
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.64020011
Short name T1030
Test name
Test status
Simulation time 11054916 ps
CPU time 0.77 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205296 kb
Host smart-179fe1d5-17fa-463d-b28b-c128e550f05a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64020011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.64020011
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4072571714
Short name T955
Test name
Test status
Simulation time 34049194 ps
CPU time 0.7 seconds
Started Jun 25 05:22:02 PM PDT 24
Finished Jun 25 05:22:05 PM PDT 24
Peak memory 205260 kb
Host smart-67ecb2d4-bb0c-49b2-84d8-659a693a16dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072571714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4072571714
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3339648007
Short name T946
Test name
Test status
Simulation time 69724573 ps
CPU time 0.73 seconds
Started Jun 25 05:22:02 PM PDT 24
Finished Jun 25 05:22:04 PM PDT 24
Peak memory 205288 kb
Host smart-4c4d908d-94c6-4f34-87a7-af0788f36d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339648007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3339648007
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.611351659
Short name T1074
Test name
Test status
Simulation time 44940849 ps
CPU time 0.68 seconds
Started Jun 25 05:22:05 PM PDT 24
Finished Jun 25 05:22:07 PM PDT 24
Peak memory 205292 kb
Host smart-92175879-38c4-4653-b5ce-57ea829d36e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611351659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.611351659
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.107519744
Short name T922
Test name
Test status
Simulation time 48722637 ps
CPU time 0.87 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205388 kb
Host smart-1f472290-ccb9-4bd1-978c-61df7d6fe48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107519744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.107519744
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.794495937
Short name T938
Test name
Test status
Simulation time 20784872 ps
CPU time 0.76 seconds
Started Jun 25 05:22:07 PM PDT 24
Finished Jun 25 05:22:08 PM PDT 24
Peak memory 205340 kb
Host smart-4c820a29-bced-4afb-90cc-f0b9809ce167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794495937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.794495937
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.436122712
Short name T1068
Test name
Test status
Simulation time 16920646 ps
CPU time 0.84 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205372 kb
Host smart-1bb7a56f-f087-4c9d-a611-59b8abcf3712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436122712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.436122712
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2246550589
Short name T928
Test name
Test status
Simulation time 7849727 ps
CPU time 0.73 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205368 kb
Host smart-67cf0dac-bfb4-4c87-9833-67aa6bfa8b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246550589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2246550589
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1205016770
Short name T944
Test name
Test status
Simulation time 45340465 ps
CPU time 0.79 seconds
Started Jun 25 05:22:02 PM PDT 24
Finished Jun 25 05:22:05 PM PDT 24
Peak memory 205360 kb
Host smart-b36732e0-b7a2-49ad-a9ee-73bf2c772eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205016770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1205016770
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1025942541
Short name T1075
Test name
Test status
Simulation time 971765159 ps
CPU time 11.01 seconds
Started Jun 25 05:21:19 PM PDT 24
Finished Jun 25 05:21:31 PM PDT 24
Peak memory 205404 kb
Host smart-8b34178c-2f06-47a4-955f-6ca76bc3e904
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025942541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
025942541
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2240126802
Short name T145
Test name
Test status
Simulation time 3184439156 ps
CPU time 16.89 seconds
Started Jun 25 05:21:17 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 205484 kb
Host smart-10c48ec2-5212-4d44-b512-453b7b3f5b80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240126802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
240126802
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2357879619
Short name T991
Test name
Test status
Simulation time 59377694 ps
CPU time 1.01 seconds
Started Jun 25 05:21:14 PM PDT 24
Finished Jun 25 05:21:17 PM PDT 24
Peak memory 205332 kb
Host smart-9c57b04b-e1e8-4b9e-82a0-e7f317680e0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357879619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
357879619
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1854712422
Short name T146
Test name
Test status
Simulation time 59883543 ps
CPU time 1.2 seconds
Started Jun 25 05:21:14 PM PDT 24
Finished Jun 25 05:21:17 PM PDT 24
Peak memory 205560 kb
Host smart-ed87022f-7080-4c27-807c-bad178bcfe60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854712422 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1854712422
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4236411547
Short name T937
Test name
Test status
Simulation time 21179342 ps
CPU time 1.26 seconds
Started Jun 25 05:21:15 PM PDT 24
Finished Jun 25 05:21:17 PM PDT 24
Peak memory 205404 kb
Host smart-afb918cc-1b89-42f8-b66d-fba73cfea254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236411547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4236411547
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.349318088
Short name T977
Test name
Test status
Simulation time 51564166 ps
CPU time 0.71 seconds
Started Jun 25 05:21:06 PM PDT 24
Finished Jun 25 05:21:08 PM PDT 24
Peak memory 205364 kb
Host smart-70a4833b-f20a-4c48-af99-cbc16e782e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349318088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.349318088
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2513989216
Short name T1076
Test name
Test status
Simulation time 87867229 ps
CPU time 3.51 seconds
Started Jun 25 05:21:13 PM PDT 24
Finished Jun 25 05:21:17 PM PDT 24
Peak memory 205352 kb
Host smart-03fabbeb-e765-4d78-8b7c-52cfc3492a9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513989216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2513989216
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1091607471
Short name T1067
Test name
Test status
Simulation time 52130205 ps
CPU time 1.77 seconds
Started Jun 25 05:21:03 PM PDT 24
Finished Jun 25 05:21:05 PM PDT 24
Peak memory 214000 kb
Host smart-e187c553-529d-4348-b8d9-8f75318c8b9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091607471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1091607471
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.942931567
Short name T1082
Test name
Test status
Simulation time 651154454 ps
CPU time 7.87 seconds
Started Jun 25 05:21:06 PM PDT 24
Finished Jun 25 05:21:15 PM PDT 24
Peak memory 213836 kb
Host smart-b593e04c-5531-4c3f-8f9a-449e0320ee83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942931567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.942931567
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3602938667
Short name T1003
Test name
Test status
Simulation time 45652137 ps
CPU time 2.69 seconds
Started Jun 25 05:21:05 PM PDT 24
Finished Jun 25 05:21:09 PM PDT 24
Peak memory 213712 kb
Host smart-69028d9d-2dfb-45f0-a30f-abf1885b7d27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602938667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3602938667
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3112378211
Short name T155
Test name
Test status
Simulation time 793355165 ps
CPU time 2.92 seconds
Started Jun 25 05:21:07 PM PDT 24
Finished Jun 25 05:21:11 PM PDT 24
Peak memory 214936 kb
Host smart-bbcad533-1078-4559-a78e-087ce2d816d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112378211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3112378211
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3596326119
Short name T962
Test name
Test status
Simulation time 89101376 ps
CPU time 0.82 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205284 kb
Host smart-f234490a-3218-4479-855b-ee614d513ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596326119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3596326119
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1820564532
Short name T923
Test name
Test status
Simulation time 47465218 ps
CPU time 0.7 seconds
Started Jun 25 05:22:14 PM PDT 24
Finished Jun 25 05:22:16 PM PDT 24
Peak memory 205364 kb
Host smart-8f2a6500-a970-4446-bcf3-f504c2baa5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820564532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1820564532
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3959530897
Short name T1027
Test name
Test status
Simulation time 35388380 ps
CPU time 0.88 seconds
Started Jun 25 05:22:02 PM PDT 24
Finished Jun 25 05:22:04 PM PDT 24
Peak memory 205308 kb
Host smart-2907df6b-8f4d-4d4b-ae5b-445ca02c8069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959530897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3959530897
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2575689807
Short name T1072
Test name
Test status
Simulation time 56607690 ps
CPU time 0.94 seconds
Started Jun 25 05:22:01 PM PDT 24
Finished Jun 25 05:22:04 PM PDT 24
Peak memory 205372 kb
Host smart-9249e4df-bbff-4613-915e-a2fa92817782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575689807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2575689807
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2241904021
Short name T926
Test name
Test status
Simulation time 11731720 ps
CPU time 0.94 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205372 kb
Host smart-6daa6d39-3af1-47f1-b3f4-5bbe997d4bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241904021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2241904021
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2264154411
Short name T1018
Test name
Test status
Simulation time 24451234 ps
CPU time 0.89 seconds
Started Jun 25 05:22:04 PM PDT 24
Finished Jun 25 05:22:07 PM PDT 24
Peak memory 205284 kb
Host smart-56d3163e-eb16-415a-b75a-070f11e2df18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264154411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2264154411
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1005979314
Short name T929
Test name
Test status
Simulation time 8710006 ps
CPU time 0.82 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205292 kb
Host smart-395d47ab-4d91-4ac6-a63d-c6129c24e83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005979314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1005979314
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4234241536
Short name T924
Test name
Test status
Simulation time 10342638 ps
CPU time 0.75 seconds
Started Jun 25 05:22:01 PM PDT 24
Finished Jun 25 05:22:04 PM PDT 24
Peak memory 205184 kb
Host smart-e6cd32ed-b27b-4af2-a684-6c3fdca4fe39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234241536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4234241536
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3165151647
Short name T1061
Test name
Test status
Simulation time 13808351 ps
CPU time 0.86 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205384 kb
Host smart-6057d023-2234-47d5-b6eb-aa6bf4c73cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165151647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3165151647
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.875441713
Short name T1066
Test name
Test status
Simulation time 15481616 ps
CPU time 0.73 seconds
Started Jun 25 05:22:03 PM PDT 24
Finished Jun 25 05:22:06 PM PDT 24
Peak memory 205368 kb
Host smart-19b5ba81-21e3-4c97-91f7-cdc941aa6ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875441713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.875441713
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3635349080
Short name T976
Test name
Test status
Simulation time 31123307 ps
CPU time 1.17 seconds
Started Jun 25 05:21:14 PM PDT 24
Finished Jun 25 05:21:16 PM PDT 24
Peak memory 205388 kb
Host smart-b9114579-95b7-4501-b8c9-d3414d359b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635349080 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3635349080
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3008318561
Short name T392
Test name
Test status
Simulation time 77281798 ps
CPU time 1.08 seconds
Started Jun 25 05:21:17 PM PDT 24
Finished Jun 25 05:21:20 PM PDT 24
Peak memory 205416 kb
Host smart-8181432f-cbe5-4088-b962-ec6f98bb4a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008318561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3008318561
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.987452804
Short name T995
Test name
Test status
Simulation time 9463067 ps
CPU time 0.86 seconds
Started Jun 25 05:21:15 PM PDT 24
Finished Jun 25 05:21:18 PM PDT 24
Peak memory 205388 kb
Host smart-3490b297-95cd-4deb-a30b-0edc9a975b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987452804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.987452804
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3138204358
Short name T969
Test name
Test status
Simulation time 103118379 ps
CPU time 3.88 seconds
Started Jun 25 05:21:17 PM PDT 24
Finished Jun 25 05:21:22 PM PDT 24
Peak memory 205484 kb
Host smart-4ef750fe-7993-4612-99f5-8f9dfca8d72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138204358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3138204358
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3695126462
Short name T1054
Test name
Test status
Simulation time 182600112 ps
CPU time 2.8 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:21 PM PDT 24
Peak memory 213720 kb
Host smart-e48a38fc-b4e5-41e7-8d58-8dd3d816dc4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695126462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3695126462
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2344940943
Short name T136
Test name
Test status
Simulation time 622351902 ps
CPU time 7.32 seconds
Started Jun 25 05:21:18 PM PDT 24
Finished Jun 25 05:21:27 PM PDT 24
Peak memory 214008 kb
Host smart-44e9377a-6849-450b-b6ec-1610079efa81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344940943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2344940943
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1078570210
Short name T961
Test name
Test status
Simulation time 54921533 ps
CPU time 1.74 seconds
Started Jun 25 05:21:14 PM PDT 24
Finished Jun 25 05:21:16 PM PDT 24
Peak memory 213724 kb
Host smart-e26e4598-2a42-4224-b216-85725d1acc5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078570210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1078570210
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.540252285
Short name T151
Test name
Test status
Simulation time 352586787 ps
CPU time 4.32 seconds
Started Jun 25 05:21:18 PM PDT 24
Finished Jun 25 05:21:24 PM PDT 24
Peak memory 205500 kb
Host smart-847f6b08-813b-4b24-bd58-17e61fd634ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540252285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
540252285
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2923935746
Short name T1004
Test name
Test status
Simulation time 57566719 ps
CPU time 1.94 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:20 PM PDT 24
Peak memory 213728 kb
Host smart-be0e7478-0bd7-41a7-b596-5637230d2a8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923935746 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2923935746
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.643793894
Short name T994
Test name
Test status
Simulation time 61147405 ps
CPU time 1.23 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:19 PM PDT 24
Peak memory 205656 kb
Host smart-d5e36779-e628-4bcf-abce-f9c740d6f675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643793894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.643793894
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2223457779
Short name T935
Test name
Test status
Simulation time 40309685 ps
CPU time 0.72 seconds
Started Jun 25 05:21:17 PM PDT 24
Finished Jun 25 05:21:19 PM PDT 24
Peak memory 205292 kb
Host smart-390a27da-feda-4451-bade-d48027943419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223457779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2223457779
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3212627803
Short name T1064
Test name
Test status
Simulation time 90142350 ps
CPU time 1.52 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:20 PM PDT 24
Peak memory 205352 kb
Host smart-7f7f3147-4660-476e-8ba7-e1a302c787c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212627803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3212627803
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1346002106
Short name T1065
Test name
Test status
Simulation time 55934308 ps
CPU time 2.26 seconds
Started Jun 25 05:21:15 PM PDT 24
Finished Jun 25 05:21:19 PM PDT 24
Peak memory 213756 kb
Host smart-d0aeb0f5-13fb-4f3c-9c94-05c0e09079d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346002106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1346002106
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2608771911
Short name T1071
Test name
Test status
Simulation time 6330850569 ps
CPU time 15.96 seconds
Started Jun 25 05:21:15 PM PDT 24
Finished Jun 25 05:21:32 PM PDT 24
Peak memory 221256 kb
Host smart-b6e18f2f-3ec7-480b-b78b-d092139e1b2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608771911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2608771911
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.63055025
Short name T1009
Test name
Test status
Simulation time 2154200037 ps
CPU time 2.95 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:21 PM PDT 24
Peak memory 213828 kb
Host smart-118d84fa-23fc-419d-ad4c-f1c4023fa870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63055025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.63055025
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2056943300
Short name T989
Test name
Test status
Simulation time 26351810 ps
CPU time 1.73 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:30 PM PDT 24
Peak memory 213768 kb
Host smart-6f3052aa-4e5c-4571-8b16-6ef9a695e628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056943300 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2056943300
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1821231734
Short name T1024
Test name
Test status
Simulation time 19581900 ps
CPU time 1.25 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:31 PM PDT 24
Peak memory 205476 kb
Host smart-ac2af569-93d0-4d15-974b-11867b10291d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821231734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1821231734
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3463086397
Short name T1012
Test name
Test status
Simulation time 24863993 ps
CPU time 0.74 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:30 PM PDT 24
Peak memory 205380 kb
Host smart-48819d14-69f1-47de-90c7-7e8daa352549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463086397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3463086397
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2802023709
Short name T992
Test name
Test status
Simulation time 39144347 ps
CPU time 2.47 seconds
Started Jun 25 05:21:29 PM PDT 24
Finished Jun 25 05:21:33 PM PDT 24
Peak memory 205484 kb
Host smart-7b1259a3-e47e-4a3e-b500-4517a5f4a315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802023709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2802023709
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2270110874
Short name T1073
Test name
Test status
Simulation time 261156012 ps
CPU time 2.29 seconds
Started Jun 25 05:21:16 PM PDT 24
Finished Jun 25 05:21:20 PM PDT 24
Peak memory 214008 kb
Host smart-677a440b-cba7-4786-ad2e-f221fdd80b15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270110874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2270110874
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.235585591
Short name T1077
Test name
Test status
Simulation time 139096032 ps
CPU time 3.6 seconds
Started Jun 25 05:21:17 PM PDT 24
Finished Jun 25 05:21:22 PM PDT 24
Peak memory 213856 kb
Host smart-4c90dcac-833f-4783-8cbe-0dd599b3ab64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235585591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.235585591
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.356352875
Short name T983
Test name
Test status
Simulation time 117175915 ps
CPU time 1.82 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:33 PM PDT 24
Peak memory 213620 kb
Host smart-c7bb320a-c657-43c3-aa1d-29693806b7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356352875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.356352875
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1039476858
Short name T169
Test name
Test status
Simulation time 3165342434 ps
CPU time 8.17 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 216572 kb
Host smart-26bf12f2-6752-414a-aeba-0238b478666c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039476858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1039476858
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2964054131
Short name T948
Test name
Test status
Simulation time 32598064 ps
CPU time 2.6 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:32 PM PDT 24
Peak memory 213812 kb
Host smart-591a1124-09b6-4cea-bb23-19aac86a0398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964054131 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2964054131
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.300343732
Short name T133
Test name
Test status
Simulation time 19603600 ps
CPU time 1.03 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:30 PM PDT 24
Peak memory 205264 kb
Host smart-2420f15b-5d40-46a1-bc40-2fa06f57c43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300343732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.300343732
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2698527421
Short name T1078
Test name
Test status
Simulation time 87424278 ps
CPU time 0.76 seconds
Started Jun 25 05:21:29 PM PDT 24
Finished Jun 25 05:21:32 PM PDT 24
Peak memory 205372 kb
Host smart-24bf02b9-3e93-4df9-9234-7d8662fd4413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698527421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2698527421
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3427225118
Short name T1025
Test name
Test status
Simulation time 175246052 ps
CPU time 3.74 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:31 PM PDT 24
Peak memory 205288 kb
Host smart-c9c94639-89b6-4981-b581-e9515808657c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427225118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3427225118
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.606497826
Short name T1052
Test name
Test status
Simulation time 98125311 ps
CPU time 3.09 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:31 PM PDT 24
Peak memory 214040 kb
Host smart-9be12400-861e-4ad4-b3d3-a499d19f7d38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606497826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.606497826
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4226129500
Short name T1055
Test name
Test status
Simulation time 155814592 ps
CPU time 3.91 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:32 PM PDT 24
Peak memory 213964 kb
Host smart-42f76308-b7b4-4c65-a909-370f63f28939
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226129500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4226129500
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1931115004
Short name T988
Test name
Test status
Simulation time 312310539 ps
CPU time 5.42 seconds
Started Jun 25 05:21:29 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 213676 kb
Host smart-b2c97f8f-1507-4aae-b361-7b1341cd94a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931115004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1931115004
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3234323655
Short name T152
Test name
Test status
Simulation time 557544619 ps
CPU time 7.03 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:36 PM PDT 24
Peak memory 205748 kb
Host smart-fe099c0c-73a1-43cd-a603-5e837b6e7f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234323655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3234323655
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1262498604
Short name T947
Test name
Test status
Simulation time 60824193 ps
CPU time 1.54 seconds
Started Jun 25 05:21:29 PM PDT 24
Finished Jun 25 05:21:33 PM PDT 24
Peak memory 213724 kb
Host smart-ce249d0d-077a-4b50-ae56-cd99e5fe4d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262498604 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1262498604
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.881429453
Short name T980
Test name
Test status
Simulation time 167325965 ps
CPU time 1.06 seconds
Started Jun 25 05:21:29 PM PDT 24
Finished Jun 25 05:21:32 PM PDT 24
Peak memory 205416 kb
Host smart-a7083ab2-7702-4014-b91c-d423c0baee4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881429453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.881429453
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3324840416
Short name T959
Test name
Test status
Simulation time 48141192 ps
CPU time 0.83 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:31 PM PDT 24
Peak memory 205384 kb
Host smart-4276bce4-9e7e-4170-8da9-f637b46ca3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324840416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3324840416
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4079244978
Short name T981
Test name
Test status
Simulation time 233747462 ps
CPU time 2.66 seconds
Started Jun 25 05:21:29 PM PDT 24
Finished Jun 25 05:21:34 PM PDT 24
Peak memory 213668 kb
Host smart-7f3e4b85-6a17-484c-b77c-b89adbad7a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079244978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4079244978
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2772982854
Short name T116
Test name
Test status
Simulation time 261772195 ps
CPU time 2.69 seconds
Started Jun 25 05:21:28 PM PDT 24
Finished Jun 25 05:21:33 PM PDT 24
Peak memory 213912 kb
Host smart-a3ce5e08-a7b2-4be2-aaec-5d045659e130
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772982854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2772982854
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.328339971
Short name T1047
Test name
Test status
Simulation time 676642855 ps
CPU time 1.8 seconds
Started Jun 25 05:21:30 PM PDT 24
Finished Jun 25 05:21:34 PM PDT 24
Peak memory 213616 kb
Host smart-e05c741c-8e56-44ab-81ad-8e207e241561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328339971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.328339971
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3945376788
Short name T154
Test name
Test status
Simulation time 77388014 ps
CPU time 2.71 seconds
Started Jun 25 05:21:27 PM PDT 24
Finished Jun 25 05:21:31 PM PDT 24
Peak memory 213600 kb
Host smart-a7ed4473-13dc-492f-b6c4-5aa21e6f7a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945376788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3945376788
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2354319845
Short name T743
Test name
Test status
Simulation time 55651478 ps
CPU time 0.76 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:07 PM PDT 24
Peak memory 205948 kb
Host smart-5869f3b0-3194-4b04-a2b9-a0cc16a2e95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354319845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2354319845
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3575368832
Short name T415
Test name
Test status
Simulation time 175913441 ps
CPU time 3.76 seconds
Started Jun 25 05:23:06 PM PDT 24
Finished Jun 25 05:23:10 PM PDT 24
Peak memory 214224 kb
Host smart-55b56fb3-f6cd-4f36-995d-cd11852de31f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575368832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3575368832
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2965318613
Short name T673
Test name
Test status
Simulation time 168586005 ps
CPU time 2.33 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:07 PM PDT 24
Peak memory 207284 kb
Host smart-2af633ad-79f5-4e60-b097-3baa4fd1911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965318613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2965318613
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3707388206
Short name T904
Test name
Test status
Simulation time 109535424 ps
CPU time 2.7 seconds
Started Jun 25 05:23:03 PM PDT 24
Finished Jun 25 05:23:06 PM PDT 24
Peak memory 220688 kb
Host smart-2b4143f6-721b-4992-997b-6496a66d01da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707388206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3707388206
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1686252576
Short name T832
Test name
Test status
Simulation time 395071233 ps
CPU time 5.37 seconds
Started Jun 25 05:23:06 PM PDT 24
Finished Jun 25 05:23:12 PM PDT 24
Peak memory 222488 kb
Host smart-a3f47109-7f2b-47db-b16f-a1a5892d3669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686252576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1686252576
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.89060354
Short name T473
Test name
Test status
Simulation time 456135526 ps
CPU time 4.46 seconds
Started Jun 25 05:23:06 PM PDT 24
Finished Jun 25 05:23:12 PM PDT 24
Peak memory 207276 kb
Host smart-0f136d63-54f5-4e25-bc20-dca51d9d8e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89060354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.89060354
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3631022137
Short name T35
Test name
Test status
Simulation time 285649826 ps
CPU time 3.42 seconds
Started Jun 25 05:23:02 PM PDT 24
Finished Jun 25 05:23:06 PM PDT 24
Peak memory 208584 kb
Host smart-4fffd2bf-2ddd-4208-b015-ada1fe716674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631022137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3631022137
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.916077139
Short name T903
Test name
Test status
Simulation time 175144201 ps
CPU time 3.47 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:10 PM PDT 24
Peak memory 208840 kb
Host smart-a21b26cc-8046-4180-81e3-ee445d46414c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916077139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.916077139
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3470545316
Short name T768
Test name
Test status
Simulation time 47759939 ps
CPU time 2.86 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:09 PM PDT 24
Peak memory 206864 kb
Host smart-84af31e8-0a1c-4658-8a6a-c56854dc8d4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470545316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3470545316
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1392460481
Short name T625
Test name
Test status
Simulation time 211675293 ps
CPU time 3.19 seconds
Started Jun 25 05:23:06 PM PDT 24
Finished Jun 25 05:23:10 PM PDT 24
Peak memory 208680 kb
Host smart-f86fda54-5792-4806-bbc3-5a9b3061f250
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392460481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1392460481
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.485833370
Short name T659
Test name
Test status
Simulation time 364358287 ps
CPU time 2.79 seconds
Started Jun 25 05:23:03 PM PDT 24
Finished Jun 25 05:23:07 PM PDT 24
Peak memory 209116 kb
Host smart-0315e790-6316-42fa-a8a1-269e30e25dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485833370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.485833370
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.707808128
Short name T407
Test name
Test status
Simulation time 212256716 ps
CPU time 5.55 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:12 PM PDT 24
Peak memory 206748 kb
Host smart-0a6f62ff-7125-4f68-b38f-817aa0b3112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707808128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.707808128
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2111464094
Short name T222
Test name
Test status
Simulation time 4385909656 ps
CPU time 87.14 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 216104 kb
Host smart-632b107c-f3e8-443c-a619-ce2fb28089b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111464094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2111464094
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2348490596
Short name T818
Test name
Test status
Simulation time 1484097318 ps
CPU time 14.4 seconds
Started Jun 25 05:23:08 PM PDT 24
Finished Jun 25 05:23:23 PM PDT 24
Peak memory 208420 kb
Host smart-eee27ed3-b64d-43e7-a564-cc21ab339173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348490596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2348490596
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1010157371
Short name T573
Test name
Test status
Simulation time 383982887 ps
CPU time 3.27 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:09 PM PDT 24
Peak memory 209932 kb
Host smart-60dfe7bb-ffd9-4ae9-8b39-ee6ae0c4a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010157371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1010157371
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3909655190
Short name T498
Test name
Test status
Simulation time 19697499 ps
CPU time 0.93 seconds
Started Jun 25 05:23:18 PM PDT 24
Finished Jun 25 05:23:20 PM PDT 24
Peak memory 206064 kb
Host smart-830b40dd-b47d-473c-92b1-352f1530b791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909655190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3909655190
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1451874107
Short name T352
Test name
Test status
Simulation time 41770624 ps
CPU time 2.99 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:08 PM PDT 24
Peak memory 215312 kb
Host smart-ecf57358-6420-4d86-82e5-351a98043e3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451874107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1451874107
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.850297686
Short name T532
Test name
Test status
Simulation time 249758096 ps
CPU time 2.42 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 216704 kb
Host smart-80077cd0-8288-41f8-9ad9-ee629cefa4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850297686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.850297686
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2970772561
Short name T418
Test name
Test status
Simulation time 6151652682 ps
CPU time 28.61 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:34 PM PDT 24
Peak memory 214388 kb
Host smart-fac99986-b1b0-4bca-b5b6-467c3da4c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970772561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2970772561
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1771996191
Short name T523
Test name
Test status
Simulation time 202994845 ps
CPU time 8.4 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:13 PM PDT 24
Peak memory 210772 kb
Host smart-35c85c3b-6c95-41cb-bf11-b9b6e8084728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771996191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1771996191
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.4146349182
Short name T646
Test name
Test status
Simulation time 568885749 ps
CPU time 5.34 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:11 PM PDT 24
Peak memory 214216 kb
Host smart-c745cf2a-c4c6-473c-a872-9f176b5ba80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146349182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4146349182
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3401606142
Short name T45
Test name
Test status
Simulation time 1780033101 ps
CPU time 34.54 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:46 PM PDT 24
Peak memory 234380 kb
Host smart-66087390-9043-44e5-97e0-30e06a632b75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401606142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3401606142
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3741953759
Short name T183
Test name
Test status
Simulation time 225739113 ps
CPU time 4.62 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:11 PM PDT 24
Peak memory 207692 kb
Host smart-db925ebb-9a9f-4a39-9736-73d75b4b6d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741953759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3741953759
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4154657575
Short name T529
Test name
Test status
Simulation time 24612481 ps
CPU time 1.98 seconds
Started Jun 25 05:23:07 PM PDT 24
Finished Jun 25 05:23:10 PM PDT 24
Peak memory 207020 kb
Host smart-d6c0ab4b-a3be-46ef-9659-36fe4412e7fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154657575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4154657575
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2029143967
Short name T902
Test name
Test status
Simulation time 151570649 ps
CPU time 3.08 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:08 PM PDT 24
Peak memory 208980 kb
Host smart-f009c000-db8a-43db-8b49-35d65db87930
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029143967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2029143967
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2128857366
Short name T488
Test name
Test status
Simulation time 354125664 ps
CPU time 3.91 seconds
Started Jun 25 05:23:19 PM PDT 24
Finished Jun 25 05:23:23 PM PDT 24
Peak memory 208736 kb
Host smart-63e7eed8-3598-4c6a-9332-112c97f9bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128857366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2128857366
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.902051123
Short name T585
Test name
Test status
Simulation time 269093586 ps
CPU time 3.04 seconds
Started Jun 25 05:23:05 PM PDT 24
Finished Jun 25 05:23:09 PM PDT 24
Peak memory 206960 kb
Host smart-75bd21b3-adea-457b-b3fe-2325eb1ac545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902051123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.902051123
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1744249919
Short name T496
Test name
Test status
Simulation time 191063406 ps
CPU time 4.66 seconds
Started Jun 25 05:23:04 PM PDT 24
Finished Jun 25 05:23:10 PM PDT 24
Peak memory 207512 kb
Host smart-1d8a5f0f-85cf-4223-ba1c-0a8e43e0163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744249919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1744249919
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.187323521
Short name T57
Test name
Test status
Simulation time 874246721 ps
CPU time 2.33 seconds
Started Jun 25 05:23:14 PM PDT 24
Finished Jun 25 05:23:18 PM PDT 24
Peak memory 211084 kb
Host smart-ac3d2339-efb9-4762-91b4-2f3a8aca40f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187323521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.187323521
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2318240616
Short name T530
Test name
Test status
Simulation time 14920573 ps
CPU time 0.78 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 205940 kb
Host smart-14444b9d-6447-4ab9-aaf7-364dfe081bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318240616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2318240616
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2357506318
Short name T286
Test name
Test status
Simulation time 151369150 ps
CPU time 3.55 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 215472 kb
Host smart-274548fd-e414-4742-a991-4e455f39f67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357506318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2357506318
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.425542069
Short name T843
Test name
Test status
Simulation time 149977718 ps
CPU time 2.93 seconds
Started Jun 25 05:23:37 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 210360 kb
Host smart-73e55dd1-52b5-4d01-9420-584eb17dd47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425542069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.425542069
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3788858723
Short name T437
Test name
Test status
Simulation time 151160941 ps
CPU time 4.04 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:43 PM PDT 24
Peak memory 214216 kb
Host smart-c88a1429-1ba8-43c6-be8b-262545b60139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788858723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3788858723
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1796095258
Short name T365
Test name
Test status
Simulation time 32713229 ps
CPU time 2.36 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 214344 kb
Host smart-9ff88b10-15a1-4396-a9b4-f32fdf634800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796095258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1796095258
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.594967006
Short name T543
Test name
Test status
Simulation time 31278516 ps
CPU time 2.18 seconds
Started Jun 25 05:23:38 PM PDT 24
Finished Jun 25 05:23:43 PM PDT 24
Peak memory 214276 kb
Host smart-0c497c1c-fc5b-453a-ae0c-3ac1514984b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594967006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.594967006
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2477626467
Short name T631
Test name
Test status
Simulation time 394482888 ps
CPU time 4.83 seconds
Started Jun 25 05:23:39 PM PDT 24
Finished Jun 25 05:23:46 PM PDT 24
Peak memory 220176 kb
Host smart-4804153a-2e12-4ce1-95d8-deb42f959587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477626467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2477626467
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2971531439
Short name T566
Test name
Test status
Simulation time 88120850 ps
CPU time 3.07 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:39 PM PDT 24
Peak memory 218204 kb
Host smart-c2460453-b9a3-4e38-b90a-da142e1a9c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971531439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2971531439
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3955237421
Short name T604
Test name
Test status
Simulation time 710940200 ps
CPU time 8 seconds
Started Jun 25 05:23:38 PM PDT 24
Finished Jun 25 05:23:49 PM PDT 24
Peak memory 207124 kb
Host smart-93944df3-585c-4b10-a2c0-eeb58727df12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955237421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3955237421
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.85939516
Short name T294
Test name
Test status
Simulation time 631581031 ps
CPU time 3.29 seconds
Started Jun 25 05:23:38 PM PDT 24
Finished Jun 25 05:23:44 PM PDT 24
Peak memory 206868 kb
Host smart-abb4a207-7d6e-438f-a5d6-3591ed825bde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85939516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.85939516
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.674742765
Short name T909
Test name
Test status
Simulation time 39155706 ps
CPU time 2.58 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 208816 kb
Host smart-45343284-0e72-4a56-a918-a3e8ad71ad2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674742765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.674742765
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1836320378
Short name T668
Test name
Test status
Simulation time 474747707 ps
CPU time 5.82 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:45 PM PDT 24
Peak memory 218312 kb
Host smart-d86a2617-edc4-44eb-af20-e68e823029d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836320378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1836320378
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.595315397
Short name T200
Test name
Test status
Simulation time 495787212 ps
CPU time 4.15 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 208688 kb
Host smart-ee5f038c-2c8a-413a-9a51-b75c1f24c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595315397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.595315397
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2299038973
Short name T64
Test name
Test status
Simulation time 87897017045 ps
CPU time 422.47 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:30:42 PM PDT 24
Peak memory 219796 kb
Host smart-94e14a2b-7848-47e9-9b79-4e98edc9264a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299038973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2299038973
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3014933222
Short name T589
Test name
Test status
Simulation time 225233022 ps
CPU time 7.57 seconds
Started Jun 25 05:23:37 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 222360 kb
Host smart-dd92c493-ae7b-4436-bb61-dbbdaa4bf442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014933222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3014933222
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2447672556
Short name T405
Test name
Test status
Simulation time 56734610 ps
CPU time 3.14 seconds
Started Jun 25 05:23:39 PM PDT 24
Finished Jun 25 05:23:44 PM PDT 24
Peak memory 208036 kb
Host smart-8b9ebdfd-4518-46b0-8d7a-3a7706462267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447672556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2447672556
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.948867169
Short name T503
Test name
Test status
Simulation time 60262603 ps
CPU time 2.8 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 210140 kb
Host smart-f9fc156f-7083-4b36-8e76-4f6bf2c90032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948867169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.948867169
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.187032143
Short name T349
Test name
Test status
Simulation time 36449222 ps
CPU time 2.36 seconds
Started Jun 25 05:23:39 PM PDT 24
Finished Jun 25 05:23:43 PM PDT 24
Peak memory 209780 kb
Host smart-3dbb32e0-0f6b-4d1e-9edf-7a92a6fbde4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187032143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.187032143
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2844022606
Short name T94
Test name
Test status
Simulation time 134821867 ps
CPU time 3.47 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 214228 kb
Host smart-43fc5141-586b-4d9c-a450-cdd0a2846ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844022606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2844022606
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1915593293
Short name T803
Test name
Test status
Simulation time 31526194 ps
CPU time 2.31 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:40 PM PDT 24
Peak memory 214284 kb
Host smart-7a071bf6-00a1-41e4-86b5-a7c41ac5a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915593293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1915593293
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2926872814
Short name T212
Test name
Test status
Simulation time 88040911 ps
CPU time 4.46 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:44 PM PDT 24
Peak memory 220240 kb
Host smart-96b15605-5671-4479-a376-8b33ed7b1a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926872814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2926872814
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1952782419
Short name T201
Test name
Test status
Simulation time 56753450 ps
CPU time 3.01 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 207004 kb
Host smart-347432fc-83fa-4bfb-a44f-700d56d8c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952782419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1952782419
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1637832206
Short name T630
Test name
Test status
Simulation time 342212716 ps
CPU time 3.14 seconds
Started Jun 25 05:23:39 PM PDT 24
Finished Jun 25 05:23:44 PM PDT 24
Peak memory 207364 kb
Host smart-2e5c83c2-e9c7-4dff-8b19-a2616817a0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637832206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1637832206
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3284802873
Short name T664
Test name
Test status
Simulation time 129497089 ps
CPU time 4.8 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 208496 kb
Host smart-5626215c-4a4f-414e-8765-879cce2b9efa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284802873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3284802873
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.83810791
Short name T739
Test name
Test status
Simulation time 263022442 ps
CPU time 9.29 seconds
Started Jun 25 05:23:41 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 206848 kb
Host smart-8b4a44f7-0686-44d0-80be-154bffe15ab8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83810791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.83810791
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1164318818
Short name T508
Test name
Test status
Simulation time 220461850 ps
CPU time 5.18 seconds
Started Jun 25 05:23:41 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 208828 kb
Host smart-cf2013cb-0fc6-4589-9549-2fe6e603325e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164318818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1164318818
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3153893269
Short name T537
Test name
Test status
Simulation time 6390314094 ps
CPU time 21.4 seconds
Started Jun 25 05:23:41 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 214388 kb
Host smart-74ff7ddc-7b42-47dc-abc1-2f271c2089e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153893269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3153893269
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.972495667
Short name T747
Test name
Test status
Simulation time 547780744 ps
CPU time 3.5 seconds
Started Jun 25 05:23:41 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 206792 kb
Host smart-84f3583c-b499-4b9a-ae6a-755b15baf90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972495667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.972495667
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3306143812
Short name T307
Test name
Test status
Simulation time 2815971436 ps
CPU time 23.79 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:24:09 PM PDT 24
Peak memory 215848 kb
Host smart-ba511733-b874-4389-871b-152e1f405dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306143812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3306143812
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1874205511
Short name T175
Test name
Test status
Simulation time 743302266 ps
CPU time 12.7 seconds
Started Jun 25 05:23:47 PM PDT 24
Finished Jun 25 05:24:01 PM PDT 24
Peak memory 222556 kb
Host smart-138eaa04-e159-4a15-9c40-8f126ce7eebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874205511 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1874205511
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4146383288
Short name T663
Test name
Test status
Simulation time 660310637 ps
CPU time 13.03 seconds
Started Jun 25 05:23:37 PM PDT 24
Finished Jun 25 05:23:53 PM PDT 24
Peak memory 207824 kb
Host smart-0adbc8c6-846f-429c-b8c6-de182a7611e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146383288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4146383288
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.188862674
Short name T771
Test name
Test status
Simulation time 167438317 ps
CPU time 2.26 seconds
Started Jun 25 05:23:46 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 210300 kb
Host smart-b08e52a9-73bb-40d4-ae42-6c3e621be16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188862674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.188862674
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2932792367
Short name T629
Test name
Test status
Simulation time 18895804 ps
CPU time 0.89 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 206052 kb
Host smart-a3beb640-9967-4adb-88c0-f2c556be0537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932792367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2932792367
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.429290586
Short name T821
Test name
Test status
Simulation time 202133191 ps
CPU time 2.92 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 214360 kb
Host smart-da7af66d-e2e2-46fd-b3b1-e70bbc2edcf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429290586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.429290586
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1138182483
Short name T21
Test name
Test status
Simulation time 453413035 ps
CPU time 5.69 seconds
Started Jun 25 05:23:48 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 222576 kb
Host smart-9e5130ba-4013-438f-9b30-c2230c391a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138182483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1138182483
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.966431185
Short name T613
Test name
Test status
Simulation time 132718848 ps
CPU time 3.99 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 208680 kb
Host smart-800dacd2-c7d4-4a7a-bfe7-29c1612d62fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966431185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.966431185
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1511443261
Short name T368
Test name
Test status
Simulation time 62613223 ps
CPU time 1.46 seconds
Started Jun 25 05:23:47 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 214264 kb
Host smart-1e1c8863-6da3-4bf2-b79e-2904af17d6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511443261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1511443261
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1391082300
Short name T330
Test name
Test status
Simulation time 30765747 ps
CPU time 2.46 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 209376 kb
Host smart-48f564d1-4aca-4b01-8c54-0b2b6f1e6ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391082300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1391082300
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2421374099
Short name T373
Test name
Test status
Simulation time 290665530 ps
CPU time 3.35 seconds
Started Jun 25 05:23:45 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 214320 kb
Host smart-87ffe895-ea44-4572-b3f8-84d67bd0439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421374099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2421374099
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1783574435
Short name T272
Test name
Test status
Simulation time 198642986 ps
CPU time 2.83 seconds
Started Jun 25 05:23:43 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 208640 kb
Host smart-d42e1606-613e-49c2-b03b-dddd0dc37514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783574435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1783574435
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.399876751
Short name T802
Test name
Test status
Simulation time 77225501 ps
CPU time 2.36 seconds
Started Jun 25 05:23:45 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 206916 kb
Host smart-1605bc44-c697-4fa5-ac64-b1580420aacc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399876751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.399876751
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3996315173
Short name T400
Test name
Test status
Simulation time 58079108 ps
CPU time 3.13 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 206892 kb
Host smart-99ae2667-52a1-4322-88ca-bedabdbc17f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996315173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3996315173
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3962763572
Short name T292
Test name
Test status
Simulation time 30338227 ps
CPU time 2.32 seconds
Started Jun 25 05:23:49 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 207036 kb
Host smart-c27705ea-ca8e-48f4-8967-ca10b49a04e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962763572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3962763572
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3152086210
Short name T553
Test name
Test status
Simulation time 685650428 ps
CPU time 4.58 seconds
Started Jun 25 05:23:40 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 218148 kb
Host smart-b83a95dc-b8ac-4d15-af65-13920a176fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152086210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3152086210
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1569873933
Short name T748
Test name
Test status
Simulation time 250564764 ps
CPU time 4.97 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 206912 kb
Host smart-f9bb3e5c-1f81-458d-8562-210072ae9824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569873933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1569873933
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.920935665
Short name T319
Test name
Test status
Simulation time 629031867 ps
CPU time 6.22 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 216520 kb
Host smart-61c34947-bc11-4f1d-975a-329be5b6ccac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920935665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.920935665
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.635127215
Short name T681
Test name
Test status
Simulation time 236880744 ps
CPU time 4.2 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 207512 kb
Host smart-c1436e0a-f800-4386-a666-e5b6c433d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635127215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.635127215
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2340931561
Short name T550
Test name
Test status
Simulation time 389245328 ps
CPU time 2.9 seconds
Started Jun 25 05:23:42 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 210352 kb
Host smart-c0e60c73-0db5-4bdb-b4a6-7486b5f365d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340931561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2340931561
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.122953958
Short name T436
Test name
Test status
Simulation time 43674952 ps
CPU time 0.77 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:54 PM PDT 24
Peak memory 205928 kb
Host smart-2037777a-fd9f-4159-b6f8-1b1a566557ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122953958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.122953958
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2599504285
Short name T786
Test name
Test status
Simulation time 104407085 ps
CPU time 4.2 seconds
Started Jun 25 05:23:43 PM PDT 24
Finished Jun 25 05:23:49 PM PDT 24
Peak memory 222852 kb
Host smart-e2cf23c6-9076-4e84-97a3-70057175e9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599504285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2599504285
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.849980674
Short name T363
Test name
Test status
Simulation time 44296252 ps
CPU time 2.09 seconds
Started Jun 25 05:23:46 PM PDT 24
Finished Jun 25 05:23:49 PM PDT 24
Peak memory 218180 kb
Host smart-4ac2a6e5-2880-4ee6-b1f9-c0b34231ab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849980674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.849980674
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1714469937
Short name T280
Test name
Test status
Simulation time 126287132 ps
CPU time 2.28 seconds
Started Jun 25 05:23:47 PM PDT 24
Finished Jun 25 05:23:51 PM PDT 24
Peak memory 214324 kb
Host smart-91846d1d-3087-4418-893b-b05c6b90ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714469937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1714469937
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2215716916
Short name T262
Test name
Test status
Simulation time 360268976 ps
CPU time 3.33 seconds
Started Jun 25 05:23:48 PM PDT 24
Finished Jun 25 05:23:53 PM PDT 24
Peak memory 214264 kb
Host smart-2766deaf-d328-4cc1-b65d-ccd695c4c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215716916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2215716916
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3562693751
Short name T866
Test name
Test status
Simulation time 57028980 ps
CPU time 2.84 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 208044 kb
Host smart-22dead7a-90ed-4a08-832b-bf8f787b348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562693751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3562693751
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2468262445
Short name T882
Test name
Test status
Simulation time 133174828 ps
CPU time 6.4 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 217320 kb
Host smart-c5a2746c-dc5a-4742-85af-6d7ec5d02bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468262445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2468262445
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2538984870
Short name T439
Test name
Test status
Simulation time 40110322 ps
CPU time 1.79 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 206964 kb
Host smart-7d5eacc7-c02e-40b2-b05c-53bcbfdda5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538984870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2538984870
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3483548182
Short name T521
Test name
Test status
Simulation time 1069911950 ps
CPU time 8 seconds
Started Jun 25 05:23:43 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 208980 kb
Host smart-c0f95e74-e2b4-48c0-a936-df92a314a2bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483548182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3483548182
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.109921996
Short name T539
Test name
Test status
Simulation time 2514130695 ps
CPU time 45.39 seconds
Started Jun 25 05:23:43 PM PDT 24
Finished Jun 25 05:24:30 PM PDT 24
Peak memory 209200 kb
Host smart-78f51fed-b350-4799-b135-4886b14af281
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109921996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.109921996
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3764862507
Short name T871
Test name
Test status
Simulation time 121846990 ps
CPU time 3.34 seconds
Started Jun 25 05:23:48 PM PDT 24
Finished Jun 25 05:23:53 PM PDT 24
Peak memory 206828 kb
Host smart-8ced6e3d-cc08-4c22-8bf1-6516260d6d8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764862507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3764862507
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2010739100
Short name T737
Test name
Test status
Simulation time 78532955 ps
CPU time 2.14 seconds
Started Jun 25 05:23:47 PM PDT 24
Finished Jun 25 05:23:51 PM PDT 24
Peak memory 214332 kb
Host smart-6d656d25-2490-4f3e-bf47-77952241b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010739100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2010739100
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3135070349
Short name T399
Test name
Test status
Simulation time 166754380 ps
CPU time 3.56 seconds
Started Jun 25 05:23:48 PM PDT 24
Finished Jun 25 05:23:53 PM PDT 24
Peak memory 208212 kb
Host smart-f6f12d48-53b5-4abf-ac79-50a82cbcce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135070349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3135070349
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3485744232
Short name T533
Test name
Test status
Simulation time 103369981 ps
CPU time 4.55 seconds
Started Jun 25 05:23:46 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 219796 kb
Host smart-c6315969-cef5-427c-a436-fd7c0f0e32e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485744232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3485744232
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.688740016
Short name T193
Test name
Test status
Simulation time 73681710 ps
CPU time 2.03 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 210252 kb
Host smart-11571390-a177-4468-8849-e1ad054aee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688740016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.688740016
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2685947884
Short name T774
Test name
Test status
Simulation time 56941727 ps
CPU time 0.77 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:54 PM PDT 24
Peak memory 205924 kb
Host smart-4834fa64-5287-4e4d-90e3-cf9416481ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685947884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2685947884
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3301520944
Short name T315
Test name
Test status
Simulation time 41944401 ps
CPU time 2.91 seconds
Started Jun 25 05:23:47 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 215128 kb
Host smart-56a88fca-c858-4bd7-88ae-f32fbf0ecd87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301520944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3301520944
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1445677497
Short name T822
Test name
Test status
Simulation time 117880299 ps
CPU time 1.41 seconds
Started Jun 25 05:23:45 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 215552 kb
Host smart-6949a4b8-904c-4851-993d-c647d4eedd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445677497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1445677497
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1179293061
Short name T749
Test name
Test status
Simulation time 41704242 ps
CPU time 1.99 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 207332 kb
Host smart-aacba99a-79cf-446d-8e21-af035e24768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179293061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1179293061
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.685902667
Short name T678
Test name
Test status
Simulation time 85256798 ps
CPU time 1.99 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 214356 kb
Host smart-9c1abf14-cc47-4f3e-a585-44cafce26eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685902667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.685902667
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4036112641
Short name T609
Test name
Test status
Simulation time 157858736 ps
CPU time 6.51 seconds
Started Jun 25 05:23:48 PM PDT 24
Finished Jun 25 05:23:57 PM PDT 24
Peak memory 222436 kb
Host smart-3a5fe921-2f6d-4c14-bd78-3a66264be926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036112641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4036112641
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1501259914
Short name T600
Test name
Test status
Simulation time 360311628 ps
CPU time 3.76 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 216676 kb
Host smart-129a52b0-5132-489c-9512-f277eca68a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501259914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1501259914
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3127590625
Short name T179
Test name
Test status
Simulation time 51643578 ps
CPU time 3.31 seconds
Started Jun 25 05:23:43 PM PDT 24
Finished Jun 25 05:23:48 PM PDT 24
Peak memory 207744 kb
Host smart-81f9b021-9098-457e-afaf-3a668dfcaef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127590625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3127590625
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2520332599
Short name T688
Test name
Test status
Simulation time 159936826 ps
CPU time 2.27 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 206816 kb
Host smart-294bb372-cc4e-4273-bec6-d34edcba796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520332599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2520332599
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.608457324
Short name T484
Test name
Test status
Simulation time 40254590 ps
CPU time 2.75 seconds
Started Jun 25 05:23:45 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 208556 kb
Host smart-e7f49614-911b-432a-a5da-8ac0149bb852
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608457324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.608457324
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.165098216
Short name T104
Test name
Test status
Simulation time 81629342 ps
CPU time 2.68 seconds
Started Jun 25 05:23:45 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 208740 kb
Host smart-86f8d5ce-f084-40dc-9d5f-e0e14e8bc2c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165098216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.165098216
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3970156797
Short name T480
Test name
Test status
Simulation time 128108930 ps
CPU time 4.11 seconds
Started Jun 25 05:23:44 PM PDT 24
Finished Jun 25 05:23:49 PM PDT 24
Peak memory 206904 kb
Host smart-8606ff9a-56bb-47c7-a67d-4fce7615c37e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970156797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3970156797
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2865365679
Short name T369
Test name
Test status
Simulation time 85443634 ps
CPU time 3 seconds
Started Jun 25 05:23:46 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 218296 kb
Host smart-334f23c6-7305-4b08-8c24-b22515f22024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865365679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2865365679
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3598362436
Short name T449
Test name
Test status
Simulation time 1273834449 ps
CPU time 8.94 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:24:01 PM PDT 24
Peak memory 206932 kb
Host smart-bd4316a5-c1ef-41f0-b3e3-fdcdd62bfaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598362436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3598362436
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2423638876
Short name T338
Test name
Test status
Simulation time 219466902 ps
CPU time 2.48 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 209648 kb
Host smart-c5d45f7f-6073-415d-87e4-ea72939a84c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423638876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2423638876
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3623226301
Short name T124
Test name
Test status
Simulation time 610156369 ps
CPU time 17.72 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:24:12 PM PDT 24
Peak memory 222620 kb
Host smart-a65e0433-2152-43c0-be1a-fc1f5aec9791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623226301 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3623226301
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2600509113
Short name T416
Test name
Test status
Simulation time 128349257 ps
CPU time 3.37 seconds
Started Jun 25 05:23:45 PM PDT 24
Finished Jun 25 05:23:50 PM PDT 24
Peak memory 208400 kb
Host smart-ef2219c2-ac24-46f5-9b35-85b1b233d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600509113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2600509113
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.646647832
Short name T391
Test name
Test status
Simulation time 54753402 ps
CPU time 2.51 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 210076 kb
Host smart-6e4ace8c-9531-4bff-8f1b-fa4f394eaa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646647832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.646647832
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2814974026
Short name T828
Test name
Test status
Simulation time 15947297 ps
CPU time 0.93 seconds
Started Jun 25 05:23:49 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 205964 kb
Host smart-49d2fa54-25b6-4106-a167-22ecc584031b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814974026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2814974026
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.841774625
Short name T32
Test name
Test status
Simulation time 406851127 ps
CPU time 8.54 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 214336 kb
Host smart-db637a21-ef39-4d34-807b-f1d57d397c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841774625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.841774625
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3031929518
Short name T255
Test name
Test status
Simulation time 134975720 ps
CPU time 3.82 seconds
Started Jun 25 05:23:57 PM PDT 24
Finished Jun 25 05:24:01 PM PDT 24
Peak memory 207636 kb
Host smart-f0a83985-0a0b-4c36-8636-892a661db734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031929518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3031929518
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2396831463
Short name T50
Test name
Test status
Simulation time 266331183 ps
CPU time 1.97 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 214404 kb
Host smart-51ac07d9-a8c5-4875-b9fc-cd82072e93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396831463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2396831463
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1379043890
Short name T895
Test name
Test status
Simulation time 93564624 ps
CPU time 5.15 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 221096 kb
Host smart-1a4378d5-1630-4637-8790-d3f0dcf7f22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379043890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1379043890
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2790842318
Short name T308
Test name
Test status
Simulation time 366869676 ps
CPU time 7.26 seconds
Started Jun 25 05:23:55 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 214324 kb
Host smart-e7c71b8f-7e78-4782-aca0-0fa58811e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790842318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2790842318
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3976164043
Short name T502
Test name
Test status
Simulation time 542821859 ps
CPU time 6.91 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:24:01 PM PDT 24
Peak memory 218328 kb
Host smart-ee2e3fc2-3ca5-4b5e-b3db-17201c2cdc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976164043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3976164043
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2588772079
Short name T808
Test name
Test status
Simulation time 6048076903 ps
CPU time 59.48 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 208704 kb
Host smart-f9350837-b316-4aa2-9651-8d02a9fd2905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588772079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2588772079
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1591544213
Short name T249
Test name
Test status
Simulation time 272393396 ps
CPU time 3.51 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:57 PM PDT 24
Peak memory 206952 kb
Host smart-32fdca86-4670-41ef-b715-c096beaa1d1e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591544213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1591544213
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4141563469
Short name T693
Test name
Test status
Simulation time 115708790 ps
CPU time 3.74 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:57 PM PDT 24
Peak memory 206856 kb
Host smart-9f8def74-e34a-42b7-ade5-c1e2eeef3108
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141563469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4141563469
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.567885421
Short name T670
Test name
Test status
Simulation time 198233064 ps
CPU time 4.44 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 208720 kb
Host smart-282d359d-b291-469a-94be-6d55dd8d509a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567885421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.567885421
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1335000592
Short name T561
Test name
Test status
Simulation time 199112353 ps
CPU time 2.63 seconds
Started Jun 25 05:23:54 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 209000 kb
Host smart-b4de0af4-b936-4fb5-8bbf-299cec0654e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335000592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1335000592
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3767036017
Short name T511
Test name
Test status
Simulation time 598502722 ps
CPU time 10.67 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 208156 kb
Host smart-bef0409c-8386-4db6-94b9-b78d11a7c68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767036017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3767036017
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.894293965
Short name T354
Test name
Test status
Simulation time 608161668 ps
CPU time 25.83 seconds
Started Jun 25 05:23:54 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 215940 kb
Host smart-629eeab5-7259-4732-92f0-cfd04acaa96d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894293965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.894293965
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2163201277
Short name T157
Test name
Test status
Simulation time 430300081 ps
CPU time 14.08 seconds
Started Jun 25 05:23:54 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 222672 kb
Host smart-88059561-1fee-415e-b62e-36b4ec4643e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163201277 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2163201277
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3830276928
Short name T358
Test name
Test status
Simulation time 32469385 ps
CPU time 2.51 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 207632 kb
Host smart-02c43740-24c5-4e1f-a448-f74321e2884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830276928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3830276928
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.299037790
Short name T571
Test name
Test status
Simulation time 311162156 ps
CPU time 2.34 seconds
Started Jun 25 05:23:53 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 210280 kb
Host smart-ddedb7c3-1547-4a53-9608-0a4ded09a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299037790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.299037790
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3779391836
Short name T745
Test name
Test status
Simulation time 11547804 ps
CPU time 0.75 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 206076 kb
Host smart-174e99b5-9475-477b-a8a5-f2ce8e7940e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779391836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3779391836
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1369296434
Short name T396
Test name
Test status
Simulation time 35853321 ps
CPU time 2.97 seconds
Started Jun 25 05:23:55 PM PDT 24
Finished Jun 25 05:24:00 PM PDT 24
Peak memory 214336 kb
Host smart-b6a09a24-14ff-4e58-8f04-82a64dcaae3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369296434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1369296434
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1457003880
Short name T834
Test name
Test status
Simulation time 338162987 ps
CPU time 8.13 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:24:01 PM PDT 24
Peak memory 209208 kb
Host smart-227fdf4e-c730-4fbb-8027-ea7861a45329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457003880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1457003880
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.310034883
Short name T880
Test name
Test status
Simulation time 227161457 ps
CPU time 3.22 seconds
Started Jun 25 05:23:52 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 214464 kb
Host smart-a43fdcb2-9fea-4e01-8185-916d7802281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310034883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.310034883
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3821150962
Short name T838
Test name
Test status
Simulation time 55695036 ps
CPU time 2.14 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 220184 kb
Host smart-5ea61388-21fd-43f5-82b1-9090283f756b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821150962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3821150962
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.564805131
Short name T270
Test name
Test status
Simulation time 2015983234 ps
CPU time 39.78 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:24:34 PM PDT 24
Peak memory 214408 kb
Host smart-d04e55c0-1ad6-4aca-8ca6-b26860159d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564805131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.564805131
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.329307290
Short name T274
Test name
Test status
Simulation time 159884289 ps
CPU time 2.52 seconds
Started Jun 25 05:23:49 PM PDT 24
Finished Jun 25 05:23:54 PM PDT 24
Peak memory 206112 kb
Host smart-2fade99a-17b3-492b-b64e-08338f2c6d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329307290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.329307290
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2609277513
Short name T448
Test name
Test status
Simulation time 42757788 ps
CPU time 2.42 seconds
Started Jun 25 05:23:54 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 207036 kb
Host smart-f933495e-64d1-411a-a213-6c849b2558c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609277513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2609277513
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3673789979
Short name T434
Test name
Test status
Simulation time 1032972997 ps
CPU time 5.83 seconds
Started Jun 25 05:23:55 PM PDT 24
Finished Jun 25 05:24:02 PM PDT 24
Peak memory 207088 kb
Host smart-37f189eb-046e-41fe-b6e7-4ddc5c86e643
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673789979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3673789979
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.179598129
Short name T735
Test name
Test status
Simulation time 111227031 ps
CPU time 2.92 seconds
Started Jun 25 05:23:53 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 207092 kb
Host smart-9ffd36b9-71aa-422f-a63f-c495538e296b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179598129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.179598129
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3859109407
Short name T907
Test name
Test status
Simulation time 85894846 ps
CPU time 2.31 seconds
Started Jun 25 05:23:54 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 215300 kb
Host smart-40885f04-407f-4113-82e1-dfff3cdff3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859109407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3859109407
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1283092160
Short name T740
Test name
Test status
Simulation time 692888437 ps
CPU time 4.62 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:57 PM PDT 24
Peak memory 208492 kb
Host smart-ad0c10f4-214b-45dd-86eb-4df2f1eb94fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283092160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1283092160
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1009643069
Short name T322
Test name
Test status
Simulation time 693048657 ps
CPU time 12.18 seconds
Started Jun 25 05:23:55 PM PDT 24
Finished Jun 25 05:24:09 PM PDT 24
Peak memory 219972 kb
Host smart-342768d7-6197-4ccd-9b9a-61e22ff456f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009643069 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1009643069
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2457424822
Short name T622
Test name
Test status
Simulation time 103676466 ps
CPU time 2.3 seconds
Started Jun 25 05:23:54 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 207480 kb
Host smart-1eeef6f3-4643-4877-ae76-46fdb0cd9b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457424822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2457424822
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.296684161
Short name T166
Test name
Test status
Simulation time 921024628 ps
CPU time 2 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 209728 kb
Host smart-bf2e60a7-469a-4e0c-a377-6ea53cce85dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296684161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.296684161
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.562349949
Short name T472
Test name
Test status
Simulation time 29657031 ps
CPU time 0.82 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 205896 kb
Host smart-ef2bf9f8-cced-4edd-9e06-33a4db903a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562349949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.562349949
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1080074322
Short name T394
Test name
Test status
Simulation time 142204512 ps
CPU time 7.42 seconds
Started Jun 25 05:23:59 PM PDT 24
Finished Jun 25 05:24:07 PM PDT 24
Peak memory 214324 kb
Host smart-808d35b6-7375-4065-8683-0df617113184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080074322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1080074322
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3912954335
Short name T20
Test name
Test status
Simulation time 210559492 ps
CPU time 3.76 seconds
Started Jun 25 05:24:01 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 222880 kb
Host smart-edc5de8a-9303-4fe0-9c5b-3e76d208396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912954335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3912954335
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2478932894
Short name T60
Test name
Test status
Simulation time 122394886 ps
CPU time 2.27 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 207720 kb
Host smart-5e4b4dfb-f591-4e36-aa3a-fbbc46b79f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478932894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2478932894
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.525825660
Short name T279
Test name
Test status
Simulation time 282727731 ps
CPU time 2.65 seconds
Started Jun 25 05:24:01 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 214256 kb
Host smart-307c0079-a1ce-40a7-afe4-3a9d2741561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525825660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.525825660
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2829492945
Short name T318
Test name
Test status
Simulation time 529393849 ps
CPU time 5.56 seconds
Started Jun 25 05:24:03 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 214160 kb
Host smart-e51cf338-ab08-44c9-8ef8-f256275ddf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829492945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2829492945
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2746927883
Short name T840
Test name
Test status
Simulation time 85962314 ps
CPU time 4.12 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:07 PM PDT 24
Peak memory 207192 kb
Host smart-29df1449-2201-414d-adeb-bb0d784d4ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746927883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2746927883
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.549424015
Short name T254
Test name
Test status
Simulation time 467819478 ps
CPU time 6.5 seconds
Started Jun 25 05:24:00 PM PDT 24
Finished Jun 25 05:24:08 PM PDT 24
Peak memory 218396 kb
Host smart-84149049-3a34-46f9-858a-efcfd7a6ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549424015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.549424015
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2871484021
Short name T489
Test name
Test status
Simulation time 110429547 ps
CPU time 2.95 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 208524 kb
Host smart-1ca2be2d-6b3f-4ef5-82a0-ea5b6050ead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871484021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2871484021
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3161307673
Short name T581
Test name
Test status
Simulation time 98353457 ps
CPU time 3.85 seconds
Started Jun 25 05:23:51 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 208804 kb
Host smart-15552a91-71e9-4328-80dc-46ad1bab0fa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161307673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3161307673
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.98706314
Short name T731
Test name
Test status
Simulation time 1395178056 ps
CPU time 26.3 seconds
Started Jun 25 05:23:56 PM PDT 24
Finished Jun 25 05:24:23 PM PDT 24
Peak memory 208444 kb
Host smart-b978cc8a-dc64-4091-aafe-9d7bc6086e97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98706314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.98706314
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3571462712
Short name T531
Test name
Test status
Simulation time 159340201 ps
CPU time 6.14 seconds
Started Jun 25 05:23:50 PM PDT 24
Finished Jun 25 05:23:58 PM PDT 24
Peak memory 206820 kb
Host smart-06d36ab7-ae1b-4e4f-9be8-2e99a673b048
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571462712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3571462712
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3506571076
Short name T879
Test name
Test status
Simulation time 158256930 ps
CPU time 1.69 seconds
Started Jun 25 05:24:01 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 208160 kb
Host smart-ff277f95-8882-4c98-a4a5-11f65ce343d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506571076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3506571076
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2403758361
Short name T870
Test name
Test status
Simulation time 306172801 ps
CPU time 3.46 seconds
Started Jun 25 05:23:53 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 208540 kb
Host smart-b328794d-b061-474c-b7c3-b82d55c37f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403758361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2403758361
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1560659283
Short name T187
Test name
Test status
Simulation time 925158668 ps
CPU time 30.54 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:34 PM PDT 24
Peak memory 220108 kb
Host smart-04eb0b23-7360-4985-a402-2a90d8c76fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560659283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1560659283
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2251024106
Short name T807
Test name
Test status
Simulation time 30068951 ps
CPU time 2.35 seconds
Started Jun 25 05:24:00 PM PDT 24
Finished Jun 25 05:24:03 PM PDT 24
Peak memory 206940 kb
Host smart-286ff749-504e-489f-86c1-d07742ff23bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251024106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2251024106
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2472786843
Short name T160
Test name
Test status
Simulation time 91717004 ps
CPU time 3.43 seconds
Started Jun 25 05:24:03 PM PDT 24
Finished Jun 25 05:24:07 PM PDT 24
Peak memory 210036 kb
Host smart-4f016764-510a-49d1-95fe-9c25fd0e2f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472786843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2472786843
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.827419744
Short name T466
Test name
Test status
Simulation time 14598062 ps
CPU time 0.97 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:04 PM PDT 24
Peak memory 206056 kb
Host smart-3367f320-f415-4b7f-837c-147c1e78ef46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827419744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.827419744
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.772420847
Short name T320
Test name
Test status
Simulation time 141468840 ps
CPU time 3.28 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 215176 kb
Host smart-85f98ecf-93e4-4a7c-abb9-6cc1e8f5a0d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772420847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.772420847
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2020371632
Short name T31
Test name
Test status
Simulation time 111245461 ps
CPU time 1.98 seconds
Started Jun 25 05:24:05 PM PDT 24
Finished Jun 25 05:24:08 PM PDT 24
Peak memory 217120 kb
Host smart-6b085ea0-8eeb-437a-ae6c-6270589ca49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020371632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2020371632
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2784865393
Short name T177
Test name
Test status
Simulation time 133118762 ps
CPU time 2.63 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 209344 kb
Host smart-f000d9f7-eebb-4cac-ab28-02c40d01b3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784865393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2784865393
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.4285680892
Short name T98
Test name
Test status
Simulation time 353993491 ps
CPU time 3.85 seconds
Started Jun 25 05:24:05 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 219352 kb
Host smart-82b728b2-0bb5-4540-a391-f058380532a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285680892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.4285680892
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.41657977
Short name T719
Test name
Test status
Simulation time 40399160 ps
CPU time 2.02 seconds
Started Jun 25 05:24:06 PM PDT 24
Finished Jun 25 05:24:09 PM PDT 24
Peak memory 214256 kb
Host smart-db9f6370-62c4-462e-860b-edca10224b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41657977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.41657977
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2317168614
Short name T674
Test name
Test status
Simulation time 128987579 ps
CPU time 3.93 seconds
Started Jun 25 05:24:05 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 222484 kb
Host smart-5b0d5db4-c5e3-4b3e-8700-3a406ab85966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317168614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2317168614
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2944278317
Short name T248
Test name
Test status
Simulation time 215036951 ps
CPU time 3.1 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 207372 kb
Host smart-6ec0e0b5-322c-43be-b8ea-f49d164b4621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944278317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2944278317
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2585564012
Short name T811
Test name
Test status
Simulation time 308538402 ps
CPU time 3.16 seconds
Started Jun 25 05:23:59 PM PDT 24
Finished Jun 25 05:24:03 PM PDT 24
Peak memory 206740 kb
Host smart-ce6efbb7-e216-4f30-87f8-ed4eafc861d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585564012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2585564012
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3425834586
Short name T756
Test name
Test status
Simulation time 1835525032 ps
CPU time 62.17 seconds
Started Jun 25 05:24:05 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 208676 kb
Host smart-fd5d5e41-72c8-4a36-85b5-42bd42466192
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425834586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3425834586
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2840386733
Short name T846
Test name
Test status
Simulation time 546234616 ps
CPU time 6.82 seconds
Started Jun 25 05:24:05 PM PDT 24
Finished Jun 25 05:24:12 PM PDT 24
Peak memory 208824 kb
Host smart-4208a050-95ff-4a90-b063-4fe44b0be1b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840386733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2840386733
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1686466359
Short name T876
Test name
Test status
Simulation time 81952385 ps
CPU time 3.64 seconds
Started Jun 25 05:24:00 PM PDT 24
Finished Jun 25 05:24:05 PM PDT 24
Peak memory 208924 kb
Host smart-a29ba9f2-5126-4a99-b380-b01e27f69b9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686466359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1686466359
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.176000193
Short name T462
Test name
Test status
Simulation time 248856409 ps
CPU time 3.51 seconds
Started Jun 25 05:24:03 PM PDT 24
Finished Jun 25 05:24:08 PM PDT 24
Peak memory 208292 kb
Host smart-c38561f0-0caf-412f-aa34-10498923dc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176000193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.176000193
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2232233395
Short name T574
Test name
Test status
Simulation time 193495160 ps
CPU time 4.3 seconds
Started Jun 25 05:24:01 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 206900 kb
Host smart-1819c4fe-9093-49bb-b2a8-9fa1e9dc60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232233395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2232233395
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2727559096
Short name T587
Test name
Test status
Simulation time 137429842 ps
CPU time 6.33 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 210112 kb
Host smart-e22ceb69-e289-434d-8be2-4efa20e64917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727559096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2727559096
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1272713951
Short name T751
Test name
Test status
Simulation time 392085146 ps
CPU time 2.17 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:05 PM PDT 24
Peak memory 209712 kb
Host smart-b1340e5b-598f-497c-b64c-75feb28e4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272713951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1272713951
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1787735387
Short name T461
Test name
Test status
Simulation time 21920205 ps
CPU time 0.88 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 206060 kb
Host smart-58c4d58f-e1fd-42cd-95e5-f92839098345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787735387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1787735387
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.930405192
Short name T406
Test name
Test status
Simulation time 54874644 ps
CPU time 4.34 seconds
Started Jun 25 05:24:03 PM PDT 24
Finished Jun 25 05:24:08 PM PDT 24
Peak memory 215704 kb
Host smart-25c67be3-9d5b-4e78-ad67-6e8b1a580669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930405192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.930405192
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3284011804
Short name T29
Test name
Test status
Simulation time 134506253 ps
CPU time 3.68 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:15 PM PDT 24
Peak memory 222732 kb
Host smart-cde6dcb4-67cc-4236-a48f-d2ea21125da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284011804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3284011804
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3168188986
Short name T65
Test name
Test status
Simulation time 661169243 ps
CPU time 9.96 seconds
Started Jun 25 05:24:00 PM PDT 24
Finished Jun 25 05:24:11 PM PDT 24
Peak memory 208696 kb
Host smart-2261405f-67b1-47eb-83ab-0d56c5719893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168188986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3168188986
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2053313321
Short name T830
Test name
Test status
Simulation time 1038483442 ps
CPU time 3.18 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:16 PM PDT 24
Peak memory 209720 kb
Host smart-97ff4476-15aa-4c5d-9f52-eb34160e3fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053313321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2053313321
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.244144697
Short name T919
Test name
Test status
Simulation time 38481766 ps
CPU time 2.88 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 219132 kb
Host smart-2800dc56-02da-43ec-9612-2dfeb7e42fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244144697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.244144697
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3813838703
Short name T428
Test name
Test status
Simulation time 227510197 ps
CPU time 10.95 seconds
Started Jun 25 05:24:06 PM PDT 24
Finished Jun 25 05:24:18 PM PDT 24
Peak memory 220336 kb
Host smart-4b0b74b3-265a-4556-a313-459ed5fc4330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813838703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3813838703
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1788296469
Short name T230
Test name
Test status
Simulation time 384460496 ps
CPU time 9.86 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:13 PM PDT 24
Peak memory 218288 kb
Host smart-5ba012ab-178e-416b-aa56-a35ae4c3a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788296469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1788296469
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3175804386
Short name T658
Test name
Test status
Simulation time 282121268 ps
CPU time 6.16 seconds
Started Jun 25 05:24:00 PM PDT 24
Finished Jun 25 05:24:07 PM PDT 24
Peak memory 208672 kb
Host smart-3e53c129-1fe3-4280-8dd7-306d5c29c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175804386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3175804386
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2817974751
Short name T444
Test name
Test status
Simulation time 124304213 ps
CPU time 4.05 seconds
Started Jun 25 05:24:03 PM PDT 24
Finished Jun 25 05:24:08 PM PDT 24
Peak memory 206852 kb
Host smart-67791e1a-5cdd-4437-bf30-83d04739802e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817974751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2817974751
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3784606083
Short name T869
Test name
Test status
Simulation time 717120144 ps
CPU time 5.36 seconds
Started Jun 25 05:24:02 PM PDT 24
Finished Jun 25 05:24:08 PM PDT 24
Peak memory 208184 kb
Host smart-8ad2d4f2-1f5a-4406-8fe6-474c784a31c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784606083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3784606083
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2364363216
Short name T628
Test name
Test status
Simulation time 215696169 ps
CPU time 3.16 seconds
Started Jun 25 05:24:01 PM PDT 24
Finished Jun 25 05:24:05 PM PDT 24
Peak memory 207360 kb
Host smart-cd28ed29-68e1-4707-9f02-00261b4ad0e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364363216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2364363216
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2436300983
Short name T853
Test name
Test status
Simulation time 6575427287 ps
CPU time 27.41 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:40 PM PDT 24
Peak memory 214240 kb
Host smart-fadd979a-b9b2-47e6-af9f-48dc551c60d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436300983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2436300983
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3045179356
Short name T641
Test name
Test status
Simulation time 100519406 ps
CPU time 2.83 seconds
Started Jun 25 05:23:59 PM PDT 24
Finished Jun 25 05:24:02 PM PDT 24
Peak memory 206940 kb
Host smart-149f6578-fd54-4c89-a11e-ec58a36d7cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045179356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3045179356
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.924831125
Short name T334
Test name
Test status
Simulation time 477246842 ps
CPU time 9.33 seconds
Started Jun 25 05:24:13 PM PDT 24
Finished Jun 25 05:24:24 PM PDT 24
Peak memory 222388 kb
Host smart-2dd24de5-2579-4a4c-ba4c-a75c5ad48729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924831125 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.924831125
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2573795772
Short name T311
Test name
Test status
Simulation time 113888703 ps
CPU time 4.16 seconds
Started Jun 25 05:24:01 PM PDT 24
Finished Jun 25 05:24:06 PM PDT 24
Peak memory 214432 kb
Host smart-862895d0-35c2-4c9b-b984-7072fae9a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573795772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2573795772
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.582803328
Short name T627
Test name
Test status
Simulation time 95827315 ps
CPU time 2.24 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 210380 kb
Host smart-bb010702-11c8-4f18-866d-d1e4c1600186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582803328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.582803328
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1539990294
Short name T697
Test name
Test status
Simulation time 64788469 ps
CPU time 0.98 seconds
Started Jun 25 05:23:14 PM PDT 24
Finished Jun 25 05:23:16 PM PDT 24
Peak memory 206160 kb
Host smart-7bb03fad-c17a-4307-984f-8a778540c39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539990294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1539990294
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.820342387
Short name T237
Test name
Test status
Simulation time 133821078 ps
CPU time 2.77 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:16 PM PDT 24
Peak memory 215308 kb
Host smart-4fadcf1b-5107-47b3-a64e-e06104ca8842
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820342387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.820342387
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4164735101
Short name T10
Test name
Test status
Simulation time 518516671 ps
CPU time 2.09 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:15 PM PDT 24
Peak memory 214688 kb
Host smart-d86a7972-543b-44a4-9d11-d1fa48ddb0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164735101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4164735101
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3297585743
Short name T592
Test name
Test status
Simulation time 89028622 ps
CPU time 1.5 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:15 PM PDT 24
Peak memory 208328 kb
Host smart-52bb8446-07d3-4e9d-8135-69845e9f529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297585743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3297585743
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.874547055
Short name T100
Test name
Test status
Simulation time 138492220 ps
CPU time 4.2 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 220228 kb
Host smart-0fc39681-0371-4e74-be17-c3f63a765a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874547055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.874547055
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2574144180
Short name T55
Test name
Test status
Simulation time 92705372 ps
CPU time 3.11 seconds
Started Jun 25 05:23:14 PM PDT 24
Finished Jun 25 05:23:19 PM PDT 24
Peak memory 214232 kb
Host smart-4adf8d55-ede4-4ff8-a894-92e3ea5bd9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574144180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2574144180
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3521577842
Short name T891
Test name
Test status
Simulation time 250738059 ps
CPU time 3.62 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 209380 kb
Host smart-4edecf33-1fb3-4635-bf4e-f57a50b12f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521577842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3521577842
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2647569259
Short name T84
Test name
Test status
Simulation time 1227070030 ps
CPU time 5.09 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 207424 kb
Host smart-8ca3b512-9136-456d-bda0-5b14956e3e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647569259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2647569259
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2092818056
Short name T621
Test name
Test status
Simulation time 1855028628 ps
CPU time 14.54 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 207964 kb
Host smart-debcef79-f102-4a65-a0a0-a292e344142d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092818056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2092818056
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1928858150
Short name T738
Test name
Test status
Simulation time 38451148 ps
CPU time 2.34 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:16 PM PDT 24
Peak memory 206896 kb
Host smart-f494c4be-e765-48bb-9478-ff3cd597b3ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928858150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1928858150
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2176175077
Short name T861
Test name
Test status
Simulation time 1466534653 ps
CPU time 39.64 seconds
Started Jun 25 05:23:14 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 208912 kb
Host smart-630c7a88-7440-4e90-9292-c9c515004c81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176175077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2176175077
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4051097197
Short name T451
Test name
Test status
Simulation time 205465839 ps
CPU time 2.91 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:16 PM PDT 24
Peak memory 210092 kb
Host smart-95626505-41cc-4cf5-8216-92c997522274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051097197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4051097197
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4003089476
Short name T460
Test name
Test status
Simulation time 489822881 ps
CPU time 3.28 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:15 PM PDT 24
Peak memory 208216 kb
Host smart-bd65aac4-9654-41a0-9f33-e7af66127f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003089476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4003089476
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2947182539
Short name T898
Test name
Test status
Simulation time 65047143 ps
CPU time 2.47 seconds
Started Jun 25 05:23:14 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 207412 kb
Host smart-b7eaf7ab-5f3c-499b-a58c-30396abec722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947182539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2947182539
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3146118717
Short name T685
Test name
Test status
Simulation time 359440688 ps
CPU time 2.76 seconds
Started Jun 25 05:23:18 PM PDT 24
Finished Jun 25 05:23:22 PM PDT 24
Peak memory 210432 kb
Host smart-9c889c27-c797-4d3b-b9e1-99bb3b670bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146118717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3146118717
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3790570412
Short name T835
Test name
Test status
Simulation time 12237702 ps
CPU time 0.85 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:11 PM PDT 24
Peak memory 205956 kb
Host smart-5d9db6c2-e11e-497b-a1e9-0bbb9638b286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790570412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3790570412
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2521142189
Short name T372
Test name
Test status
Simulation time 83093200 ps
CPU time 3.37 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 214224 kb
Host smart-3f1c24ca-59d7-46cc-b61b-15e12cf4c283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521142189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2521142189
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.784338164
Short name T908
Test name
Test status
Simulation time 112855278 ps
CPU time 2.95 seconds
Started Jun 25 05:24:13 PM PDT 24
Finished Jun 25 05:24:18 PM PDT 24
Peak memory 218304 kb
Host smart-c47b7e1c-1292-42af-bada-0230b642d5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784338164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.784338164
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.766600333
Short name T784
Test name
Test status
Simulation time 690876496 ps
CPU time 8 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:19 PM PDT 24
Peak memory 214284 kb
Host smart-d23b5f09-d850-4f4a-a41e-c3140ee0b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766600333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.766600333
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2092791655
Short name T762
Test name
Test status
Simulation time 124738014 ps
CPU time 3.35 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:15 PM PDT 24
Peak memory 210268 kb
Host smart-24fce389-9094-4627-ad15-89b6a85646ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092791655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2092791655
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3671119427
Short name T541
Test name
Test status
Simulation time 676400182 ps
CPU time 6.03 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:16 PM PDT 24
Peak memory 214340 kb
Host smart-8d43048f-535d-43ca-9797-afffbea8b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671119427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3671119427
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3535170753
Short name T190
Test name
Test status
Simulation time 47793978 ps
CPU time 2.89 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 206228 kb
Host smart-a4417878-a7e9-4584-9b8b-fcf558a7dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535170753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3535170753
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4034378098
Short name T79
Test name
Test status
Simulation time 22481211489 ps
CPU time 51.26 seconds
Started Jun 25 05:24:16 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 208752 kb
Host smart-b7525099-19f2-4e9e-a147-6344e57c4af5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034378098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4034378098
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3247136230
Short name T916
Test name
Test status
Simulation time 374758566 ps
CPU time 3.43 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:24:17 PM PDT 24
Peak memory 208448 kb
Host smart-fa2bab39-c8e5-4929-8cd5-52f168afd253
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247136230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3247136230
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1270308845
Short name T506
Test name
Test status
Simulation time 1383084693 ps
CPU time 10.55 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 208008 kb
Host smart-ac7d1e5e-a134-4381-b212-f68d62db27ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270308845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1270308845
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3588530874
Short name T34
Test name
Test status
Simulation time 51627060 ps
CPU time 2.65 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:12 PM PDT 24
Peak memory 215844 kb
Host smart-7a5bd883-ae27-479d-8b12-1e172bcd9216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588530874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3588530874
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.71084137
Short name T603
Test name
Test status
Simulation time 202748640 ps
CPU time 2.59 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:24:16 PM PDT 24
Peak memory 207004 kb
Host smart-12705ccb-6c64-4b65-b445-c6554a8de6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71084137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.71084137
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4121558645
Short name T106
Test name
Test status
Simulation time 675986780 ps
CPU time 5.09 seconds
Started Jun 25 05:24:08 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 209688 kb
Host smart-1e4b2c92-d2b1-46a4-9f84-fb66c206454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121558645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4121558645
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2858343105
Short name T194
Test name
Test status
Simulation time 268426084 ps
CPU time 2.06 seconds
Started Jun 25 05:24:14 PM PDT 24
Finished Jun 25 05:24:17 PM PDT 24
Peak memory 209808 kb
Host smart-6a29d792-3b73-4ade-a6d3-d30223742957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858343105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2858343105
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1599181063
Short name T185
Test name
Test status
Simulation time 29144928 ps
CPU time 1.2 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 206048 kb
Host smart-64b6fb57-8670-4736-bde0-70782d88a89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599181063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1599181063
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2519430599
Short name T422
Test name
Test status
Simulation time 60670937 ps
CPU time 3.97 seconds
Started Jun 25 05:24:07 PM PDT 24
Finished Jun 25 05:24:12 PM PDT 24
Peak memory 214316 kb
Host smart-c99e5b8a-391f-4467-b40b-75ea5c73d05c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519430599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2519430599
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.77074621
Short name T331
Test name
Test status
Simulation time 83292971 ps
CPU time 2.05 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:12 PM PDT 24
Peak memory 207096 kb
Host smart-79ed6886-43f4-4e01-99a3-932ae32fb87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77074621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.77074621
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2494014948
Short name T899
Test name
Test status
Simulation time 104305824 ps
CPU time 2.03 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 214428 kb
Host smart-0c39cceb-73cf-45ff-b057-1e5239608fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494014948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2494014948
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3532900557
Short name T874
Test name
Test status
Simulation time 45074675 ps
CPU time 2.01 seconds
Started Jun 25 05:24:09 PM PDT 24
Finished Jun 25 05:24:13 PM PDT 24
Peak memory 214300 kb
Host smart-0962b2fd-ceda-452b-8ca9-f7437f298ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532900557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3532900557
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.1870924202
Short name T847
Test name
Test status
Simulation time 250419682 ps
CPU time 4 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:17 PM PDT 24
Peak memory 207456 kb
Host smart-7b5a9eea-4ca9-4c63-a7a0-fc4856b636cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870924202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1870924202
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.578792727
Short name T884
Test name
Test status
Simulation time 168884425 ps
CPU time 2.65 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:24:16 PM PDT 24
Peak memory 207020 kb
Host smart-b9c4dd10-fa35-42ce-91d4-7d48f064a18b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578792727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.578792727
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2719998979
Short name T514
Test name
Test status
Simulation time 525101113 ps
CPU time 4.46 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:24:18 PM PDT 24
Peak memory 208724 kb
Host smart-3f29aad0-2fbf-4b23-8dd1-8ee1eb061493
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719998979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2719998979
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3483971941
Short name T588
Test name
Test status
Simulation time 322423070 ps
CPU time 5.17 seconds
Started Jun 25 05:24:08 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 207996 kb
Host smart-b247a75c-631c-47e7-bb79-41c6d87c69d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483971941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3483971941
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2975809631
Short name T321
Test name
Test status
Simulation time 59680636 ps
CPU time 2.62 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 209976 kb
Host smart-670da374-15c9-41b7-b305-63ffd4ef78d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975809631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2975809631
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1660168559
Short name T598
Test name
Test status
Simulation time 5937226537 ps
CPU time 48.91 seconds
Started Jun 25 05:24:13 PM PDT 24
Finished Jun 25 05:25:03 PM PDT 24
Peak memory 208408 kb
Host smart-8295c5b5-997b-4aed-9944-496588e45fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660168559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1660168559
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3204576723
Short name T686
Test name
Test status
Simulation time 89295925 ps
CPU time 1 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:13 PM PDT 24
Peak memory 206112 kb
Host smart-6fe9920a-307e-4c7d-9c27-b24f93a7bfc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204576723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3204576723
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2487429362
Short name T49
Test name
Test status
Simulation time 131070670 ps
CPU time 8.82 seconds
Started Jun 25 05:24:12 PM PDT 24
Finished Jun 25 05:24:22 PM PDT 24
Peak memory 222180 kb
Host smart-a8569a4b-7742-4675-8c45-59a49aae2fb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487429362 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2487429362
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3813570154
Short name T277
Test name
Test status
Simulation time 45477866 ps
CPU time 2.93 seconds
Started Jun 25 05:24:10 PM PDT 24
Finished Jun 25 05:24:14 PM PDT 24
Peak memory 208448 kb
Host smart-bc1945d7-4aaf-4dfc-a53d-f20d33fa648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813570154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3813570154
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1929920124
Short name T920
Test name
Test status
Simulation time 94091480 ps
CPU time 0.8 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 205968 kb
Host smart-c49b4894-5a76-4578-adee-50cca5e371aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929920124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1929920124
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1840160938
Short name T204
Test name
Test status
Simulation time 60952266 ps
CPU time 4.39 seconds
Started Jun 25 05:24:18 PM PDT 24
Finished Jun 25 05:24:23 PM PDT 24
Peak memory 214308 kb
Host smart-d73781a8-6b28-4e77-9b1e-69987ef7f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840160938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1840160938
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3960816069
Short name T602
Test name
Test status
Simulation time 162934153 ps
CPU time 2.19 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:26 PM PDT 24
Peak memory 209548 kb
Host smart-ea6eebc1-d9d4-4b63-b9f1-902a0b42bde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960816069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3960816069
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3627594241
Short name T341
Test name
Test status
Simulation time 104761381 ps
CPU time 2.15 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:25 PM PDT 24
Peak memory 214284 kb
Host smart-d8b8b3cb-06d1-41e7-a3ee-acfaf251a081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627594241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3627594241
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.125693310
Short name T816
Test name
Test status
Simulation time 277918874 ps
CPU time 3.35 seconds
Started Jun 25 05:24:24 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 220400 kb
Host smart-cdeb846e-2d67-4fbd-94d0-a7e01244f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125693310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.125693310
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.552068007
Short name T640
Test name
Test status
Simulation time 762494798 ps
CPU time 9.02 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 208604 kb
Host smart-b0a345fd-72f6-46d2-bcb7-dd6e04cf69bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552068007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.552068007
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2329341631
Short name T491
Test name
Test status
Simulation time 20558098 ps
CPU time 1.61 seconds
Started Jun 25 05:24:08 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 206864 kb
Host smart-517881fe-ba15-494c-8a8a-1d9af7a7db3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329341631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2329341631
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2574252050
Short name T510
Test name
Test status
Simulation time 884045467 ps
CPU time 3.41 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:24 PM PDT 24
Peak memory 208480 kb
Host smart-048d9431-9a4a-48bb-a639-71d21ef1fb7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574252050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2574252050
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.327682760
Short name T306
Test name
Test status
Simulation time 1726727257 ps
CPU time 22.24 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 208344 kb
Host smart-fb0b3484-3fda-45a6-b9ba-91f7afa0e38c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327682760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.327682760
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.700335865
Short name T273
Test name
Test status
Simulation time 42508842 ps
CPU time 2.59 seconds
Started Jun 25 05:24:18 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 209996 kb
Host smart-5aa7315e-6891-4986-be70-16e4d7e6d9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700335865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.700335865
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1184453965
Short name T675
Test name
Test status
Simulation time 38682458 ps
CPU time 1.71 seconds
Started Jun 25 05:24:11 PM PDT 24
Finished Jun 25 05:24:15 PM PDT 24
Peak memory 206952 kb
Host smart-bbaaca17-e29d-43ab-b581-2fd9705f4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184453965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1184453965
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2964659626
Short name T805
Test name
Test status
Simulation time 48922150605 ps
CPU time 272.84 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:28:56 PM PDT 24
Peak memory 218656 kb
Host smart-d977bbd9-0bce-4eff-b5b7-4ce480a363c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964659626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2964659626
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.920673588
Short name T717
Test name
Test status
Simulation time 128423743 ps
CPU time 5.09 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:28 PM PDT 24
Peak memory 209276 kb
Host smart-8c8a92e6-3caf-487b-84c8-93c5786b1c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920673588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.920673588
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.645780718
Short name T568
Test name
Test status
Simulation time 24168094 ps
CPU time 0.87 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 205948 kb
Host smart-908c1ab3-6384-42a9-acd2-9174869de8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645780718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.645780718
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3779639343
Short name T782
Test name
Test status
Simulation time 32512514 ps
CPU time 2.06 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:26 PM PDT 24
Peak memory 208188 kb
Host smart-93c2a415-433e-4df7-b484-42e1c54b1051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779639343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3779639343
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.640137235
Short name T657
Test name
Test status
Simulation time 121039409 ps
CPU time 5.39 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 214216 kb
Host smart-5f57ab02-8232-47c5-8030-cd0b5e0c1696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640137235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.640137235
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.108867281
Short name T677
Test name
Test status
Simulation time 314164481 ps
CPU time 3.62 seconds
Started Jun 25 05:24:23 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 214240 kb
Host smart-5d4dbe13-2ff8-4124-97f8-25d2c10d809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108867281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.108867281
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2554148260
Short name T804
Test name
Test status
Simulation time 409914276 ps
CPU time 4.41 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:24 PM PDT 24
Peak memory 209804 kb
Host smart-ced2ef9f-20c5-4fe1-bede-9e6757a51e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554148260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2554148260
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.327357381
Short name T326
Test name
Test status
Simulation time 122056990 ps
CPU time 2.36 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:22 PM PDT 24
Peak memory 207236 kb
Host smart-90b5ec74-4f28-4197-816d-985a26305e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327357381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.327357381
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3084824941
Short name T696
Test name
Test status
Simulation time 246396950 ps
CPU time 3.47 seconds
Started Jun 25 05:24:23 PM PDT 24
Finished Jun 25 05:24:28 PM PDT 24
Peak memory 209036 kb
Host smart-91d27b5b-d7c5-459e-ab07-ef57b6e15367
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084824941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3084824941
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2186471902
Short name T475
Test name
Test status
Simulation time 119404739 ps
CPU time 2.48 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:23 PM PDT 24
Peak memory 206952 kb
Host smart-6019fc56-4a96-4013-b0b9-99a2f254578a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186471902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2186471902
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4216702082
Short name T240
Test name
Test status
Simulation time 359416535 ps
CPU time 5.56 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:27 PM PDT 24
Peak memory 208752 kb
Host smart-36382c56-8f81-4b5a-a691-12d1b1fd09e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216702082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4216702082
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.241433585
Short name T660
Test name
Test status
Simulation time 109080556 ps
CPU time 2.51 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:24 PM PDT 24
Peak memory 208096 kb
Host smart-0e4573c8-1944-47f0-8f02-0e62c668723a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241433585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.241433585
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3317352573
Short name T559
Test name
Test status
Simulation time 53108779 ps
CPU time 2.63 seconds
Started Jun 25 05:24:23 PM PDT 24
Finished Jun 25 05:24:28 PM PDT 24
Peak memory 208324 kb
Host smart-6952d147-75ee-4d42-ba55-038a62fd545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317352573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3317352573
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4216924361
Short name T51
Test name
Test status
Simulation time 616820058 ps
CPU time 22.44 seconds
Started Jun 25 05:24:23 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 218844 kb
Host smart-dbd2c1c9-3c56-43f8-8712-f32a64c4f086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216924361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4216924361
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3968870744
Short name T708
Test name
Test status
Simulation time 603431743 ps
CPU time 7.41 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 214256 kb
Host smart-6c4b36c3-48c8-4ed5-8d90-39d4b536a7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968870744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3968870744
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1299354708
Short name T820
Test name
Test status
Simulation time 207653476 ps
CPU time 1.94 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:23 PM PDT 24
Peak memory 210356 kb
Host smart-0feccbd3-9806-4e88-a137-9ba5c6c6c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299354708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1299354708
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1956333987
Short name T429
Test name
Test status
Simulation time 44588166 ps
CPU time 0.77 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:24 PM PDT 24
Peak memory 206044 kb
Host smart-ba490740-b961-4843-8248-962e42e90ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956333987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1956333987
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1526093141
Short name T760
Test name
Test status
Simulation time 140569766 ps
CPU time 4.4 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:27 PM PDT 24
Peak memory 214320 kb
Host smart-1f766d07-77ec-4d63-b878-62a1683bee1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526093141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1526093141
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1770068187
Short name T66
Test name
Test status
Simulation time 3318317453 ps
CPU time 21.3 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 214852 kb
Host smart-c816bc25-2cc0-4e63-951d-e4c1b83ee65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770068187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1770068187
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.158778599
Short name T917
Test name
Test status
Simulation time 202118595 ps
CPU time 3.72 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:27 PM PDT 24
Peak memory 208920 kb
Host smart-e01832de-741b-45b7-944b-4fca2af6e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158778599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.158778599
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2576913324
Short name T242
Test name
Test status
Simulation time 516964313 ps
CPU time 6.71 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:30 PM PDT 24
Peak memory 221120 kb
Host smart-dd95b544-de69-4d88-81fb-0480f710b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576913324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2576913324
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3881586543
Short name T265
Test name
Test status
Simulation time 309531076 ps
CPU time 4.02 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:27 PM PDT 24
Peak memory 214768 kb
Host smart-81590226-4564-437d-a985-c6785a826d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881586543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3881586543
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2329902020
Short name T623
Test name
Test status
Simulation time 164187384 ps
CPU time 2.13 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:26 PM PDT 24
Peak memory 220024 kb
Host smart-f7d30a12-6c7b-4a87-85c7-b512cc208d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329902020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2329902020
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3121733549
Short name T795
Test name
Test status
Simulation time 78821525 ps
CPU time 2.22 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:27 PM PDT 24
Peak memory 209744 kb
Host smart-389de32a-992c-49f0-8495-f841e85797bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121733549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3121733549
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2193605820
Short name T809
Test name
Test status
Simulation time 465962547 ps
CPU time 11.05 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:31 PM PDT 24
Peak memory 208220 kb
Host smart-6f5e2429-7430-49f8-ad72-3164d11d3088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193605820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2193605820
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4245117783
Short name T538
Test name
Test status
Simulation time 431690861 ps
CPU time 6.22 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:30 PM PDT 24
Peak memory 208088 kb
Host smart-30c6221a-9c6c-4b87-8905-62811f8c6433
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245117783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4245117783
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.160059071
Short name T860
Test name
Test status
Simulation time 310615422 ps
CPU time 3.35 seconds
Started Jun 25 05:24:24 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 206968 kb
Host smart-15e717ba-b4fa-497c-aa08-b61ca93b4bcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160059071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.160059071
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2853955655
Short name T483
Test name
Test status
Simulation time 200382660 ps
CPU time 2.86 seconds
Started Jun 25 05:24:23 PM PDT 24
Finished Jun 25 05:24:28 PM PDT 24
Peak memory 206740 kb
Host smart-80626030-368a-4430-8cc4-43dbdc70dfe5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853955655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2853955655
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1086102679
Short name T797
Test name
Test status
Simulation time 115320590 ps
CPU time 5.15 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:30 PM PDT 24
Peak memory 218716 kb
Host smart-26ac1e23-73f6-4341-b24c-b4f227f321e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086102679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1086102679
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.595123192
Short name T482
Test name
Test status
Simulation time 596780529 ps
CPU time 4.12 seconds
Started Jun 25 05:24:19 PM PDT 24
Finished Jun 25 05:24:25 PM PDT 24
Peak memory 206928 kb
Host smart-42448d7e-0c4f-4751-8467-c25a644b6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595123192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.595123192
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3876905882
Short name T188
Test name
Test status
Simulation time 29399261789 ps
CPU time 206 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:27:50 PM PDT 24
Peak memory 216256 kb
Host smart-a7d3e7dd-4827-4e04-9dd8-b4cd20e6fa69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876905882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3876905882
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.547684632
Short name T815
Test name
Test status
Simulation time 1049904001 ps
CPU time 7.85 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:29 PM PDT 24
Peak memory 209608 kb
Host smart-5d197345-47ee-4110-83ab-02bdb859615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547684632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.547684632
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2116112933
Short name T806
Test name
Test status
Simulation time 11697029 ps
CPU time 0.85 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 205916 kb
Host smart-c1c843d1-efcd-41f3-b5e2-97ff9617960a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116112933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2116112933
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3304184835
Short name T425
Test name
Test status
Simulation time 173911315 ps
CPU time 3.38 seconds
Started Jun 25 05:24:20 PM PDT 24
Finished Jun 25 05:24:25 PM PDT 24
Peak memory 215240 kb
Host smart-6c145901-e1f8-47a3-aebb-ab73305c41a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304184835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3304184835
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.4060895222
Short name T41
Test name
Test status
Simulation time 514223875 ps
CPU time 10.84 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 208900 kb
Host smart-ab7e4fa7-8b26-4016-a9ae-458232f471dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060895222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.4060895222
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4103090266
Short name T599
Test name
Test status
Simulation time 511194506 ps
CPU time 2.74 seconds
Started Jun 25 05:24:23 PM PDT 24
Finished Jun 25 05:24:28 PM PDT 24
Peak memory 208552 kb
Host smart-c81c84e4-75b8-479a-a0b6-7e6e6b6df951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103090266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4103090266
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2509874577
Short name T877
Test name
Test status
Simulation time 356693192 ps
CPU time 3.33 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 215604 kb
Host smart-b9d0286a-648a-48aa-a400-d9c5fdeee6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509874577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2509874577
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.227856612
Short name T669
Test name
Test status
Simulation time 118350203 ps
CPU time 3.62 seconds
Started Jun 25 05:24:26 PM PDT 24
Finished Jun 25 05:24:31 PM PDT 24
Peak memory 214168 kb
Host smart-277ee234-9232-4c0a-8e85-967be23b1b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227856612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.227856612
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2080026927
Short name T48
Test name
Test status
Simulation time 107439792 ps
CPU time 2.32 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 207916 kb
Host smart-8db8d9de-199b-43a1-9ca7-58ee15d7fe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080026927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2080026927
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3877632457
Short name T275
Test name
Test status
Simulation time 1180284415 ps
CPU time 6.85 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:31 PM PDT 24
Peak memory 209724 kb
Host smart-f215f693-44de-4d88-bac8-3c76a75f4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877632457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3877632457
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2113910033
Short name T608
Test name
Test status
Simulation time 2497888481 ps
CPU time 7.53 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 208948 kb
Host smart-55d81ff1-4367-4cc5-b231-8b98bbceddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113910033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2113910033
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2486739367
Short name T328
Test name
Test status
Simulation time 1810178989 ps
CPU time 23.82 seconds
Started Jun 25 05:24:21 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 208028 kb
Host smart-411dbc0d-92ae-4b33-bda7-278f4714cad5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486739367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2486739367
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1130214649
Short name T493
Test name
Test status
Simulation time 580981340 ps
CPU time 6.38 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:30 PM PDT 24
Peak memory 209020 kb
Host smart-e617f963-1029-4e44-b8f0-7e0f1a6bc927
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130214649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1130214649
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2950527299
Short name T653
Test name
Test status
Simulation time 125362049 ps
CPU time 2.59 seconds
Started Jun 25 05:24:22 PM PDT 24
Finished Jun 25 05:24:26 PM PDT 24
Peak memory 207548 kb
Host smart-09379dbf-30ce-40b5-8cd2-f9dcba18d28a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950527299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2950527299
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_smoke.574746036
Short name T578
Test name
Test status
Simulation time 1940042474 ps
CPU time 23.73 seconds
Started Jun 25 05:24:24 PM PDT 24
Finished Jun 25 05:24:49 PM PDT 24
Peak memory 207024 kb
Host smart-df5f6fb6-2053-4b1a-aa1f-6ad3cb7072a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574746036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.574746036
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3070872235
Short name T777
Test name
Test status
Simulation time 1982348177 ps
CPU time 22.21 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 222236 kb
Host smart-7c1100f6-51c3-49e9-bcda-8c0f956eef25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070872235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3070872235
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.166268800
Short name T721
Test name
Test status
Simulation time 928156090 ps
CPU time 3.67 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:24:40 PM PDT 24
Peak memory 207696 kb
Host smart-5ae68a19-833c-48b6-84bf-759c8f658b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166268800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.166268800
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3176108525
Short name T470
Test name
Test status
Simulation time 50874400 ps
CPU time 3.18 seconds
Started Jun 25 05:24:27 PM PDT 24
Finished Jun 25 05:24:31 PM PDT 24
Peak memory 210468 kb
Host smart-ae7d98ce-3635-4b2f-bbb0-47c727821373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176108525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3176108525
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2664302424
Short name T102
Test name
Test status
Simulation time 18314014 ps
CPU time 0.85 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 206056 kb
Host smart-d37daf64-8175-4ca0-9bc3-ea0399183f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664302424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2664302424
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1911083568
Short name T424
Test name
Test status
Simulation time 70290514 ps
CPU time 4.49 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 215128 kb
Host smart-d970ae1e-4588-4dcf-8fd0-edca96748723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911083568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1911083568
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1784735613
Short name T40
Test name
Test status
Simulation time 120549320 ps
CPU time 5.02 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 209572 kb
Host smart-a420a0b8-68ac-45a6-9ffa-cb1755e93a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784735613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1784735613
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3438612749
Short name T855
Test name
Test status
Simulation time 1536985494 ps
CPU time 45.8 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 208528 kb
Host smart-77527ebe-3a3b-46cb-b4e1-0d02211aff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438612749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3438612749
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.563138982
Short name T99
Test name
Test status
Simulation time 278792359 ps
CPU time 3.68 seconds
Started Jun 25 05:24:27 PM PDT 24
Finished Jun 25 05:24:31 PM PDT 24
Peak memory 222804 kb
Host smart-74d4550c-5ba4-4671-b873-e106bb04a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563138982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.563138982
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3858094070
Short name T260
Test name
Test status
Simulation time 78044645 ps
CPU time 2.61 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 214260 kb
Host smart-9c7bc48b-6883-40fc-8c4b-d6d05a50e872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858094070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3858094070
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3372098501
Short name T214
Test name
Test status
Simulation time 60527947 ps
CPU time 3.49 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:34 PM PDT 24
Peak memory 220784 kb
Host smart-166f0515-4051-4c03-a66c-42576b2125f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372098501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3372098501
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2457971941
Short name T287
Test name
Test status
Simulation time 114919365 ps
CPU time 3.16 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:38 PM PDT 24
Peak memory 208860 kb
Host smart-ab651ab7-7f1f-4566-b94d-0aed546a82c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457971941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2457971941
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2994928670
Short name T105
Test name
Test status
Simulation time 54139873 ps
CPU time 2.92 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 206892 kb
Host smart-f01f93c4-56b1-49f1-a487-044890dc4baf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994928670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2994928670
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.700422683
Short name T191
Test name
Test status
Simulation time 54684804 ps
CPU time 2.87 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 208780 kb
Host smart-e6d9f680-1821-4f02-91e3-07265621b056
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700422683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.700422683
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.159618673
Short name T620
Test name
Test status
Simulation time 57098354 ps
CPU time 2.91 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 208900 kb
Host smart-65370860-36b8-4277-9290-1c3ab1b15b5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159618673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.159618673
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2690045365
Short name T471
Test name
Test status
Simulation time 367630678 ps
CPU time 10.04 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 208892 kb
Host smart-784cc581-6a4f-4893-94ff-a6056bf6ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690045365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2690045365
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2797977057
Short name T591
Test name
Test status
Simulation time 124396094 ps
CPU time 2.23 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 207224 kb
Host smart-67aef0c2-598b-4d0f-86c5-171c9ce331de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797977057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2797977057
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.140405125
Short name T867
Test name
Test status
Simulation time 453196105 ps
CPU time 8.46 seconds
Started Jun 25 05:24:31 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 219748 kb
Host smart-91a2f8f9-caad-4cb7-ac86-295db07b21cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140405125 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.140405125
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2234089333
Short name T883
Test name
Test status
Simulation time 407750517 ps
CPU time 5.66 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 208060 kb
Host smart-1e2f1551-7fd3-49e6-915b-06bdc0b2a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234089333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2234089333
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2714423369
Short name T390
Test name
Test status
Simulation time 63819898 ps
CPU time 2.35 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 210052 kb
Host smart-4ba05834-a996-4385-8cb0-39019802ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714423369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2714423369
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3625202942
Short name T536
Test name
Test status
Simulation time 20168277 ps
CPU time 0.73 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 206036 kb
Host smart-2dc5c43e-8d58-4936-be48-0b27a895e2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625202942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3625202942
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1106469273
Short name T127
Test name
Test status
Simulation time 470801579 ps
CPU time 11.49 seconds
Started Jun 25 05:24:27 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 214880 kb
Host smart-6fbbb4c1-5da2-49ee-a1ae-2ae3b6fa7127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106469273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1106469273
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2355657679
Short name T24
Test name
Test status
Simulation time 182857965 ps
CPU time 2.21 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 216432 kb
Host smart-831bc5d8-966b-416b-bc01-e10f7a6c9584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355657679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2355657679
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2636840608
Short name T235
Test name
Test status
Simulation time 614668333 ps
CPU time 4.44 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:36 PM PDT 24
Peak memory 210256 kb
Host smart-2a880004-f5d0-4c78-ad72-39d9a629bc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636840608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2636840608
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4194819081
Short name T824
Test name
Test status
Simulation time 306607760 ps
CPU time 2.67 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 214412 kb
Host smart-9d8b63d4-b1eb-4c4a-96ae-10d3a20e22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194819081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4194819081
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.195547808
Short name T68
Test name
Test status
Simulation time 563177068 ps
CPU time 3.01 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:34 PM PDT 24
Peak memory 207780 kb
Host smart-f302f0af-6390-40a6-ae57-50c8d7d57f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195547808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.195547808
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1451733254
Short name T833
Test name
Test status
Simulation time 79946232 ps
CPU time 2.78 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 207944 kb
Host smart-f71fe0f2-1f39-441f-8c69-cc24dc0e7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451733254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1451733254
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.825954313
Short name T548
Test name
Test status
Simulation time 600135975 ps
CPU time 2.76 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 206880 kb
Host smart-ed0fdb16-a259-4eba-841c-ef76cb2572d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825954313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.825954313
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.229777786
Short name T913
Test name
Test status
Simulation time 24261921 ps
CPU time 1.92 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 207092 kb
Host smart-999422a2-403a-4d90-9780-7e56b2546b34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229777786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.229777786
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1614942537
Short name T516
Test name
Test status
Simulation time 782039905 ps
CPU time 8.14 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 208176 kb
Host smart-2507dfa5-5c5d-4f0a-aef3-2272ee17b453
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614942537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1614942537
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1237829233
Short name T476
Test name
Test status
Simulation time 218081218 ps
CPU time 2.99 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 207432 kb
Host smart-a0b99578-067d-4f9b-a1a9-64077b459e36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237829233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1237829233
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.591338649
Short name T652
Test name
Test status
Simulation time 1062063727 ps
CPU time 3.23 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 214264 kb
Host smart-1c7e7863-b0cf-431d-a056-a1918d47d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591338649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.591338649
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3490193445
Short name T432
Test name
Test status
Simulation time 2584997722 ps
CPU time 24.79 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 209008 kb
Host smart-5257b9fa-2cf7-4b25-bb28-5a638735db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490193445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3490193445
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1457811498
Short name T296
Test name
Test status
Simulation time 10668086088 ps
CPU time 62.16 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 215372 kb
Host smart-3d73804b-277f-4f92-9801-cceeb01068e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457811498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1457811498
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3536123892
Short name T335
Test name
Test status
Simulation time 369424996 ps
CPU time 4.6 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 214332 kb
Host smart-70faae05-7c2b-4fd2-a30a-a31fab69d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536123892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3536123892
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3575917470
Short name T385
Test name
Test status
Simulation time 56315458 ps
CPU time 1.46 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 209500 kb
Host smart-79237d20-7a69-4bbb-8464-891b6082ac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575917470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3575917470
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2746561577
Short name T759
Test name
Test status
Simulation time 7132898 ps
CPU time 0.71 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:36 PM PDT 24
Peak memory 205948 kb
Host smart-130e2128-5dd7-423b-94d2-4ca1615e869f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746561577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2746561577
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.194912403
Short name T750
Test name
Test status
Simulation time 100724979 ps
CPU time 2.01 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 208732 kb
Host smart-482c454e-4a44-4377-b36c-c53a6c6999c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194912403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.194912403
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4132452085
Short name T383
Test name
Test status
Simulation time 111615322 ps
CPU time 4.91 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 208232 kb
Host smart-3ce5db76-c86c-4afb-ac10-44281287d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132452085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4132452085
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2483732701
Short name T643
Test name
Test status
Simulation time 746154666 ps
CPU time 3.63 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:38 PM PDT 24
Peak memory 215900 kb
Host smart-f01a7ab1-a61e-4075-91ad-a358b86f917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483732701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2483732701
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3971800882
Short name T377
Test name
Test status
Simulation time 118913788 ps
CPU time 5.48 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 206812 kb
Host smart-c1715e05-34b9-41b6-b32f-3bc951453ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971800882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3971800882
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2503883947
Short name T305
Test name
Test status
Simulation time 21857202 ps
CPU time 1.9 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:33 PM PDT 24
Peak memory 206736 kb
Host smart-b21f020b-d212-4596-8e24-95aab426a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503883947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2503883947
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1755630306
Short name T647
Test name
Test status
Simulation time 553266146 ps
CPU time 2.99 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 206968 kb
Host smart-c30518fe-2c15-4cfe-97e3-8be42a27a857
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755630306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1755630306
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4124561231
Short name T453
Test name
Test status
Simulation time 258312353 ps
CPU time 2.95 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:35 PM PDT 24
Peak memory 206876 kb
Host smart-b2f8a26c-158f-4292-8ff5-5146b22581a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124561231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4124561231
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2868860845
Short name T682
Test name
Test status
Simulation time 314137463 ps
CPU time 7.84 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 208212 kb
Host smart-592efbd3-1eba-48fd-a1a3-1d6aacdb1e7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868860845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2868860845
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1190070876
Short name T825
Test name
Test status
Simulation time 681872846 ps
CPU time 7.11 seconds
Started Jun 25 05:24:28 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 220380 kb
Host smart-56e3e5d1-48de-4b8e-bd89-505555a7bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190070876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1190070876
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3680020473
Short name T558
Test name
Test status
Simulation time 2010084280 ps
CPU time 17.82 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:48 PM PDT 24
Peak memory 208056 kb
Host smart-507a8c42-7cb6-4530-baaf-a7041d2b7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680020473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3680020473
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3265048176
Short name T174
Test name
Test status
Simulation time 297240598 ps
CPU time 11.58 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:54 PM PDT 24
Peak memory 222612 kb
Host smart-ad2c5e3e-05e7-4a0b-bdab-65b8b5a89807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265048176 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3265048176
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2269560585
Short name T554
Test name
Test status
Simulation time 415627500 ps
CPU time 12.86 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:49 PM PDT 24
Peak memory 208420 kb
Host smart-da0b7537-337e-4071-b713-2d21d3913697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269560585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2269560585
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2067891115
Short name T817
Test name
Test status
Simulation time 397853378 ps
CPU time 2 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:36 PM PDT 24
Peak memory 210100 kb
Host smart-b7a4b281-f699-4eff-9fd8-717d0b5121af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067891115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2067891115
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.750365366
Short name T711
Test name
Test status
Simulation time 85741834 ps
CPU time 0.95 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 206028 kb
Host smart-ea50146b-50c9-45ab-a9ad-0b899563a1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750365366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.750365366
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2174650014
Short name T71
Test name
Test status
Simulation time 2473008930 ps
CPU time 5.81 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 207632 kb
Host smart-f1060dc7-a647-4ff1-a85f-272d813289a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174650014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2174650014
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2095788256
Short name T92
Test name
Test status
Simulation time 331255789 ps
CPU time 4.32 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 209616 kb
Host smart-5fb43042-020c-44c7-b8a2-5b9a2457810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095788256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2095788256
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3590141567
Short name T683
Test name
Test status
Simulation time 221073002 ps
CPU time 3.58 seconds
Started Jun 25 05:24:30 PM PDT 24
Finished Jun 25 05:24:36 PM PDT 24
Peak memory 209512 kb
Host smart-7dffa9a0-d19d-4b34-8aaf-b4f96b1ee806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590141567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3590141567
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3142755841
Short name T450
Test name
Test status
Simulation time 115069579 ps
CPU time 3.16 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:38 PM PDT 24
Peak memory 208392 kb
Host smart-0206c972-1170-4539-8943-f4bee61626e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142755841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3142755841
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3739117746
Short name T905
Test name
Test status
Simulation time 40477272 ps
CPU time 2.33 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 207124 kb
Host smart-37c5b56f-24a6-46dd-bab5-22e46e60faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739117746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3739117746
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3140891629
Short name T370
Test name
Test status
Simulation time 1716863160 ps
CPU time 5.79 seconds
Started Jun 25 05:24:29 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 207284 kb
Host smart-c2a7dadc-05e1-4922-820a-f08d22bc465d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140891629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3140891629
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1811272642
Short name T526
Test name
Test status
Simulation time 262586592 ps
CPU time 3.22 seconds
Started Jun 25 05:24:33 PM PDT 24
Finished Jun 25 05:24:38 PM PDT 24
Peak memory 208812 kb
Host smart-9764f0ad-4f32-4c7c-a394-479f08841527
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811272642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1811272642
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4048960448
Short name T892
Test name
Test status
Simulation time 194107027 ps
CPU time 3.16 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 207360 kb
Host smart-e9f927ee-f35c-4eb5-8dee-7174b611aa92
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048960448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4048960448
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3377214848
Short name T679
Test name
Test status
Simulation time 531042090 ps
CPU time 8.33 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 208724 kb
Host smart-c0d6656f-aff8-4c8a-88c0-68708818f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377214848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3377214848
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3198256385
Short name T650
Test name
Test status
Simulation time 268673265 ps
CPU time 1.9 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 207424 kb
Host smart-f36f6d45-5e99-4c23-9724-317ae5f9f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198256385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3198256385
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.839262456
Short name T379
Test name
Test status
Simulation time 15043095931 ps
CPU time 83.38 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:26:06 PM PDT 24
Peak memory 216448 kb
Host smart-d0f9b42d-58f8-41cf-a58f-2b70b8b593d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839262456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.839262456
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2133858905
Short name T121
Test name
Test status
Simulation time 1484012004 ps
CPU time 16.33 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 222540 kb
Host smart-54a0d552-2c79-4042-ade3-966397866cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133858905 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2133858905
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2964002760
Short name T290
Test name
Test status
Simulation time 826281138 ps
CPU time 9.46 seconds
Started Jun 25 05:24:32 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 219688 kb
Host smart-0c828868-304d-4af0-a206-83d38adc1441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964002760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2964002760
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3540833828
Short name T36
Test name
Test status
Simulation time 174039747 ps
CPU time 3.62 seconds
Started Jun 25 05:24:27 PM PDT 24
Finished Jun 25 05:24:32 PM PDT 24
Peak memory 209896 kb
Host smart-e13e88e6-566c-40fd-9383-40c16cbf1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540833828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3540833828
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3456169484
Short name T831
Test name
Test status
Simulation time 53166112 ps
CPU time 0.95 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:26 PM PDT 24
Peak memory 206192 kb
Host smart-83f8e6b3-0cf9-4312-b3f0-296f28c5df27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456169484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3456169484
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.744398232
Short name T419
Test name
Test status
Simulation time 74643900 ps
CPU time 2.87 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 214324 kb
Host smart-c1e27383-181f-497d-b110-1e9c9cb94246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744398232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.744398232
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.977222412
Short name T661
Test name
Test status
Simulation time 162900805 ps
CPU time 2.34 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:16 PM PDT 24
Peak memory 207900 kb
Host smart-a17bb580-c088-4fba-8ceb-766512be9f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977222412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.977222412
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3115817855
Short name T90
Test name
Test status
Simulation time 37338567 ps
CPU time 2.9 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:15 PM PDT 24
Peak memory 209984 kb
Host smart-f25b69be-4dfb-4944-ab1d-5a35d48aab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115817855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3115817855
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3316492346
Short name T259
Test name
Test status
Simulation time 251770693 ps
CPU time 3.45 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 214264 kb
Host smart-bd42ad19-29b0-4520-bb57-d25500240721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316492346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3316492346
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.829450193
Short name T402
Test name
Test status
Simulation time 215260485 ps
CPU time 2.12 seconds
Started Jun 25 05:23:15 PM PDT 24
Finished Jun 25 05:23:18 PM PDT 24
Peak memory 209460 kb
Host smart-c403e451-8a6d-4bc4-be61-7d311aa62b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829450193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.829450193
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2257549730
Short name T549
Test name
Test status
Simulation time 297654217 ps
CPU time 4.12 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:18 PM PDT 24
Peak memory 214324 kb
Host smart-1145c2bc-3f0c-4b4a-acf2-72b4ceabcad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257549730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2257549730
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4031594606
Short name T13
Test name
Test status
Simulation time 350119294 ps
CPU time 11.02 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:36 PM PDT 24
Peak memory 230520 kb
Host smart-2ee470a1-6f11-41e3-bece-02847db13a75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031594606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4031594606
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2352152880
Short name T814
Test name
Test status
Simulation time 1409137904 ps
CPU time 39.52 seconds
Started Jun 25 05:23:14 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 208184 kb
Host smart-8ab128b4-9901-4f90-8b27-9e2f423a6f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352152880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2352152880
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2273802636
Short name T577
Test name
Test status
Simulation time 1801783606 ps
CPU time 39.88 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:53 PM PDT 24
Peak memory 208124 kb
Host smart-e10b7e30-8daf-485c-b084-f30a34e30ff4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273802636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2273802636
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2059288283
Short name T584
Test name
Test status
Simulation time 142787058 ps
CPU time 5.09 seconds
Started Jun 25 05:23:11 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 207812 kb
Host smart-e0527b3d-8889-4e54-bc8b-a807d6495c2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059288283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2059288283
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.403200148
Short name T495
Test name
Test status
Simulation time 382595154 ps
CPU time 2.67 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:17 PM PDT 24
Peak memory 208720 kb
Host smart-8119ad3b-d74e-4f8b-b59a-e180ce1c7928
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403200148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.403200148
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2171310139
Short name T192
Test name
Test status
Simulation time 235956871 ps
CPU time 4.42 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:19 PM PDT 24
Peak memory 208428 kb
Host smart-f851eb07-f806-4a2e-9cb7-3a15f7e62e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171310139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2171310139
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2113692721
Short name T766
Test name
Test status
Simulation time 31311366 ps
CPU time 2.04 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:16 PM PDT 24
Peak memory 206788 kb
Host smart-70dfb691-1f4e-437b-8d2a-5195dc2ad9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113692721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2113692721
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1827339179
Short name T226
Test name
Test status
Simulation time 1118384542 ps
CPU time 29.15 seconds
Started Jun 25 05:23:13 PM PDT 24
Finished Jun 25 05:23:44 PM PDT 24
Peak memory 222320 kb
Host smart-d3a100d1-5d6f-4884-bb02-b1bf1d2ac8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827339179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1827339179
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.600988589
Short name T781
Test name
Test status
Simulation time 5346307253 ps
CPU time 38.33 seconds
Started Jun 25 05:23:12 PM PDT 24
Finished Jun 25 05:23:52 PM PDT 24
Peak memory 222192 kb
Host smart-e2c9ff66-3909-42a9-b2e9-3df066e912a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600988589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.600988589
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2329127948
Short name T454
Test name
Test status
Simulation time 45235135 ps
CPU time 0.75 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 206072 kb
Host smart-7266acff-29f7-4b33-9a69-b7cbecb16368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329127948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2329127948
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2204749814
Short name T703
Test name
Test status
Simulation time 247599986 ps
CPU time 4.23 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 214336 kb
Host smart-a7982b8b-616a-4b22-8f89-66d66944f54f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204749814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2204749814
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2860106064
Short name T70
Test name
Test status
Simulation time 40207381 ps
CPU time 2.26 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 209172 kb
Host smart-ba46cfc8-b618-41a8-8831-e11514431c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860106064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2860106064
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3657309120
Short name T611
Test name
Test status
Simulation time 43081731 ps
CPU time 2.79 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 214164 kb
Host smart-ee76cd35-8019-4d99-aa67-a14908cdfea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657309120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3657309120
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2442196382
Short name T216
Test name
Test status
Simulation time 691947398 ps
CPU time 4.67 seconds
Started Jun 25 05:24:36 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 222528 kb
Host smart-5be49696-b1e9-4f5a-bf74-67c9d2cec00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442196382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2442196382
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1554920096
Short name T893
Test name
Test status
Simulation time 101540022 ps
CPU time 4.79 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 209020 kb
Host smart-5f1f5cad-c926-4cfd-bef6-05714e99da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554920096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1554920096
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2140707040
Short name T614
Test name
Test status
Simulation time 459587264 ps
CPU time 6.21 seconds
Started Jun 25 05:24:36 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 207780 kb
Host smart-3c656cad-a6b2-4cf5-adea-b12e5004025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140707040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2140707040
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.4099404683
Short name T447
Test name
Test status
Simulation time 78894123 ps
CPU time 3.07 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 206872 kb
Host smart-c1485f0f-ca49-4f6d-9958-77a4e40d6db3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099404683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.4099404683
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2509518414
Short name T110
Test name
Test status
Simulation time 276292575 ps
CPU time 3.53 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 208252 kb
Host smart-64247072-5599-412c-b8b7-addcbce70f54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509518414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2509518414
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.430250688
Short name T469
Test name
Test status
Simulation time 206922490 ps
CPU time 2.87 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 206892 kb
Host smart-1bb77c99-5ab7-4d4d-8f05-e2c765692c8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430250688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.430250688
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3960573378
Short name T720
Test name
Test status
Simulation time 86711555 ps
CPU time 2.48 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 207848 kb
Host smart-5f10a35f-22f2-413c-a4dc-cfa7f758a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960573378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3960573378
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.677315821
Short name T433
Test name
Test status
Simulation time 131001455 ps
CPU time 4.15 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 206884 kb
Host smart-58d70bbc-5822-4d47-9820-9ba18fdc0bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677315821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.677315821
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2777350899
Short name T220
Test name
Test status
Simulation time 10897105909 ps
CPU time 32.3 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:25:11 PM PDT 24
Peak memory 216068 kb
Host smart-df558d4d-bd4b-4359-832a-a08802aa943b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777350899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2777350899
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.907312203
Short name T171
Test name
Test status
Simulation time 806470702 ps
CPU time 19.95 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:25:02 PM PDT 24
Peak memory 222628 kb
Host smart-419cc719-9b69-4526-92ea-d79936450341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907312203 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.907312203
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2176731653
Short name T513
Test name
Test status
Simulation time 3800189260 ps
CPU time 5.93 seconds
Started Jun 25 05:24:34 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 207680 kb
Host smart-026b05a1-650c-4ff1-bdc8-29e993d925f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176731653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2176731653
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1576871866
Short name T736
Test name
Test status
Simulation time 186272061 ps
CPU time 2.45 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:40 PM PDT 24
Peak memory 209672 kb
Host smart-4ab718d8-003d-4950-9e9c-813ed3d94158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576871866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1576871866
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.726383124
Short name T494
Test name
Test status
Simulation time 88701103 ps
CPU time 0.73 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 206048 kb
Host smart-54164baa-68ef-4d49-ab07-ccc7c0630aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726383124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.726383124
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3784919512
Short name T395
Test name
Test status
Simulation time 270933269 ps
CPU time 3.68 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:50 PM PDT 24
Peak memory 214952 kb
Host smart-504ab713-8654-4d7b-8bfb-748360f4fb7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784919512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3784919512
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1135273268
Short name T563
Test name
Test status
Simulation time 564493483 ps
CPU time 3.06 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 221632 kb
Host smart-bfb9b69d-bf48-4650-8b2e-e20f23c6a20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135273268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1135273268
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3614318351
Short name T742
Test name
Test status
Simulation time 129853793 ps
CPU time 3.14 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 218488 kb
Host smart-288adaba-1d0c-4af0-8806-447afbf70fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614318351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3614318351
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1439061713
Short name T95
Test name
Test status
Simulation time 138519560 ps
CPU time 5.87 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 214360 kb
Host smart-36041254-26f8-485c-953b-db04aa4914a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439061713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1439061713
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1324161426
Short name T794
Test name
Test status
Simulation time 44109791 ps
CPU time 2.87 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 221464 kb
Host smart-60bf8d4f-6923-4e3d-bdd2-44883d35a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324161426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1324161426
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2876821819
Short name T791
Test name
Test status
Simulation time 45018006 ps
CPU time 2.9 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 207644 kb
Host smart-4f9e1605-891e-4ddc-8f0c-84192d1a9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876821819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2876821819
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4210848887
Short name T699
Test name
Test status
Simulation time 1098386015 ps
CPU time 7 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 207964 kb
Host smart-8dc1491b-5859-449d-bb5f-e0934771c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210848887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4210848887
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3789457605
Short name T486
Test name
Test status
Simulation time 178055389 ps
CPU time 3.37 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 208980 kb
Host smart-fb698e3e-a157-4371-ba27-af48db61b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789457605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3789457605
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1166229990
Short name T886
Test name
Test status
Simulation time 115250004 ps
CPU time 4.37 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 206828 kb
Host smart-bef7767c-ce12-4260-ba3d-c2bf9abae8fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166229990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1166229990
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3498637660
Short name T408
Test name
Test status
Simulation time 29245008 ps
CPU time 1.82 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 206904 kb
Host smart-d19dbd0d-52d8-4dc0-bbcf-f9a5c45af227
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498637660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3498637660
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3474131817
Short name T712
Test name
Test status
Simulation time 371339515 ps
CPU time 9.12 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 207924 kb
Host smart-8fa1fa85-1a36-4174-9236-ae19f215994a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474131817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3474131817
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3652484952
Short name T606
Test name
Test status
Simulation time 542967941 ps
CPU time 2.84 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 214316 kb
Host smart-90eca21a-e4e6-4c65-862c-ba48ac37639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652484952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3652484952
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2078962011
Short name T897
Test name
Test status
Simulation time 27817650 ps
CPU time 2.05 seconds
Started Jun 25 05:24:42 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 208616 kb
Host smart-d9e53493-ec21-40e9-a49a-6514fafff7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078962011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2078962011
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3649845776
Short name T456
Test name
Test status
Simulation time 12112471 ps
CPU time 0.74 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 206000 kb
Host smart-7f0c33ba-6e7c-44b7-9c4c-2358a46369a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649845776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3649845776
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.734517711
Short name T826
Test name
Test status
Simulation time 304278848 ps
CPU time 7.24 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 209336 kb
Host smart-4f9d15bc-7e0b-4f1e-b666-e8fc53b74d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734517711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.734517711
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.305723007
Short name T765
Test name
Test status
Simulation time 100326869 ps
CPU time 2.25 seconds
Started Jun 25 05:24:35 PM PDT 24
Finished Jun 25 05:24:39 PM PDT 24
Peak memory 209964 kb
Host smart-416744ce-f545-4741-bf16-7b1bb4730099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305723007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.305723007
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1459145240
Short name T467
Test name
Test status
Simulation time 30285764 ps
CPU time 0.73 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 206044 kb
Host smart-fcf45bc5-bfec-4c02-a92e-bc8efb6b62c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459145240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1459145240
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1681401937
Short name T126
Test name
Test status
Simulation time 188603805 ps
CPU time 3.75 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 214188 kb
Host smart-1e45dba9-c6ec-486d-b379-8245beee0ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681401937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1681401937
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.112756741
Short name T19
Test name
Test status
Simulation time 143419202 ps
CPU time 3.19 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:48 PM PDT 24
Peak memory 219276 kb
Host smart-a89f8456-548d-4ae4-b06a-f6a456cd9912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112756741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.112756741
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2140842980
Short name T316
Test name
Test status
Simulation time 206657797 ps
CPU time 2 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 209960 kb
Host smart-ee22973c-036f-49e5-a227-60e600aa99ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140842980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2140842980
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3061924711
Short name T342
Test name
Test status
Simulation time 562432827 ps
CPU time 3.76 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 214340 kb
Host smart-188ed5af-a1fa-4f5e-ac68-3b3e5cd85a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061924711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3061924711
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1475736762
Short name T918
Test name
Test status
Simulation time 261440144 ps
CPU time 3.83 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 206100 kb
Host smart-2641b61d-428d-4819-875a-e4776d313c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475736762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1475736762
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2779368696
Short name T776
Test name
Test status
Simulation time 30214778 ps
CPU time 2.42 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 219796 kb
Host smart-57f324f0-d939-44e4-ac34-3f1f37833c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779368696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2779368696
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3082957725
Short name T569
Test name
Test status
Simulation time 82261248 ps
CPU time 3.86 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 208296 kb
Host smart-d0f7458f-f5eb-428c-8968-c0a971521464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082957725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3082957725
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1647896454
Short name T202
Test name
Test status
Simulation time 48764104 ps
CPU time 2.69 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 208616 kb
Host smart-032696cb-c972-47ba-a7ba-260a63d6e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647896454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1647896454
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2395071214
Short name T293
Test name
Test status
Simulation time 199844622 ps
CPU time 6.56 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 208128 kb
Host smart-c8aac984-74af-414b-94c6-037a13ac70ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395071214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2395071214
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.852178750
Short name T250
Test name
Test status
Simulation time 322083202 ps
CPU time 11.15 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 208476 kb
Host smart-7956d517-a98d-4386-b9e4-4031e20f26a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852178750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.852178750
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3770618733
Short name T854
Test name
Test status
Simulation time 470544822 ps
CPU time 6 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:48 PM PDT 24
Peak memory 208608 kb
Host smart-50699ce3-7fb0-47ea-acc1-3a2507fdad7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770618733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3770618733
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2420967828
Short name T477
Test name
Test status
Simulation time 96856452 ps
CPU time 2.96 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 209016 kb
Host smart-c0e56f7d-aa5c-40f1-abd8-261870883896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420967828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2420967828
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2813056091
Short name T522
Test name
Test status
Simulation time 63198494 ps
CPU time 2.2 seconds
Started Jun 25 05:24:40 PM PDT 24
Finished Jun 25 05:24:45 PM PDT 24
Peak memory 206836 kb
Host smart-4bdf4576-9852-4b4e-aed8-981c80c85fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813056091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2813056091
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1438978648
Short name T267
Test name
Test status
Simulation time 537733026 ps
CPU time 22.33 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 222624 kb
Host smart-d0b23ae3-6b6e-4074-9a0d-908d1481c3d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438978648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1438978648
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.409535172
Short name T695
Test name
Test status
Simulation time 2096747989 ps
CPU time 35.28 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:25:21 PM PDT 24
Peak memory 208676 kb
Host smart-f6bea1c6-8126-4fc1-9162-a30580211948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409535172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.409535172
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3460723388
Short name T464
Test name
Test status
Simulation time 59311682 ps
CPU time 0.77 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:48 PM PDT 24
Peak memory 206040 kb
Host smart-889167c4-b81d-4560-9ad7-c38e2ca453a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460723388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3460723388
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2777480545
Short name T411
Test name
Test status
Simulation time 465117302 ps
CPU time 6.87 seconds
Started Jun 25 05:24:42 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 214704 kb
Host smart-af12a316-28c6-4ec4-833a-8aac16afad2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777480545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2777480545
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2705715104
Short name T700
Test name
Test status
Simulation time 990728021 ps
CPU time 3.31 seconds
Started Jun 25 05:24:39 PM PDT 24
Finished Jun 25 05:24:44 PM PDT 24
Peak memory 221488 kb
Host smart-38206ad0-10b7-44ed-b75d-86b69bf532cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705715104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2705715104
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3615613947
Short name T74
Test name
Test status
Simulation time 31344520 ps
CPU time 1.88 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:48 PM PDT 24
Peak memory 209104 kb
Host smart-7a4a131e-bbe4-4f94-bf03-4d724a6e66b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615613947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3615613947
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.550159125
Short name T297
Test name
Test status
Simulation time 27145883 ps
CPU time 1.77 seconds
Started Jun 25 05:24:37 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 214356 kb
Host smart-68fbd513-54ed-4f8d-a769-26100c723efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550159125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.550159125
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3896787786
Short name T346
Test name
Test status
Simulation time 107801187 ps
CPU time 5.28 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:50 PM PDT 24
Peak memory 222276 kb
Host smart-c13f527d-7626-45ef-8635-1b5212c0b717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896787786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3896787786
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3947476627
Short name T887
Test name
Test status
Simulation time 159350445 ps
CPU time 2.29 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:46 PM PDT 24
Peak memory 219936 kb
Host smart-7ba999ba-1438-46a2-aa23-2e62b0b070ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947476627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3947476627
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2296929253
Short name T269
Test name
Test status
Simulation time 442909885 ps
CPU time 3.71 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 214216 kb
Host smart-daf71d2e-ecce-46f1-80c3-0ba808430c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296929253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2296929253
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1620149753
Short name T181
Test name
Test status
Simulation time 630722073 ps
CPU time 3.81 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:51 PM PDT 24
Peak memory 208876 kb
Host smart-df935051-a889-4f07-b680-a55c52124df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620149753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1620149753
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.536962632
Short name T707
Test name
Test status
Simulation time 74948529 ps
CPU time 1.84 seconds
Started Jun 25 05:24:42 PM PDT 24
Finished Jun 25 05:24:47 PM PDT 24
Peak memory 206960 kb
Host smart-1f456fb9-ed7b-465f-b897-8c77be8bfd50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536962632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.536962632
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1150871213
Short name T788
Test name
Test status
Simulation time 1779878914 ps
CPU time 14.47 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 208196 kb
Host smart-e036f533-87c1-4ce9-a57c-773557ab3caa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150871213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1150871213
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2848316845
Short name T350
Test name
Test status
Simulation time 711543853 ps
CPU time 5.38 seconds
Started Jun 25 05:24:41 PM PDT 24
Finished Jun 25 05:24:50 PM PDT 24
Peak memory 208664 kb
Host smart-e6cbc4b6-6ade-47c7-a916-988211a4ca07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848316845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2848316845
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2707534774
Short name T672
Test name
Test status
Simulation time 200071079 ps
CPU time 3.32 seconds
Started Jun 25 05:24:44 PM PDT 24
Finished Jun 25 05:24:50 PM PDT 24
Peak memory 209432 kb
Host smart-4dd25cd7-7a01-4f5d-8f4d-89d2fef96f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707534774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2707534774
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.989713228
Short name T593
Test name
Test status
Simulation time 192608469 ps
CPU time 2.38 seconds
Started Jun 25 05:24:38 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 207204 kb
Host smart-be0f3bc6-2538-46cf-b6ec-dcf0507b76c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989713228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.989713228
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3738669678
Short name T401
Test name
Test status
Simulation time 1055300554 ps
CPU time 11.59 seconds
Started Jun 25 05:24:44 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 207936 kb
Host smart-aaf6813b-7245-4f88-854b-9a0426e89217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738669678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3738669678
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.606538612
Short name T362
Test name
Test status
Simulation time 610805597 ps
CPU time 6.46 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 207616 kb
Host smart-4dcb4431-92eb-487b-8350-b17874890195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606538612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.606538612
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3111899366
Short name T445
Test name
Test status
Simulation time 19514427 ps
CPU time 0.83 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 205976 kb
Host smart-79cc1c02-e614-41cb-98e6-0bb7f4c77eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111899366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3111899366
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.803907897
Short name T857
Test name
Test status
Simulation time 59103520 ps
CPU time 1.96 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:24:50 PM PDT 24
Peak memory 209732 kb
Host smart-6cba5de6-2131-4f2b-b0e7-9413ca453f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803907897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.803907897
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.875858338
Short name T691
Test name
Test status
Simulation time 176076113 ps
CPU time 3.02 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 207704 kb
Host smart-61e111cf-f964-431b-9f06-a3cf8369e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875858338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.875858338
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2698833834
Short name T107
Test name
Test status
Simulation time 288970390 ps
CPU time 2.73 seconds
Started Jun 25 05:24:47 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 214172 kb
Host smart-b3d1b8fa-5dca-4c0b-89d4-d319d3748e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698833834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2698833834
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1453893896
Short name T455
Test name
Test status
Simulation time 69928761 ps
CPU time 3.15 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 209616 kb
Host smart-08e95a81-fe76-4233-82c6-ee8d65320819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453893896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1453893896
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.697582783
Short name T878
Test name
Test status
Simulation time 94018231 ps
CPU time 3.71 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:03 PM PDT 24
Peak memory 207260 kb
Host smart-0e3aeb2b-8342-431a-8da9-f41998ab3714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697582783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.697582783
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2524467896
Short name T726
Test name
Test status
Simulation time 157003037 ps
CPU time 1.87 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:24:50 PM PDT 24
Peak memory 205968 kb
Host smart-53c73423-758c-4cac-a903-075eeb96734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524467896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2524467896
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2627546331
Short name T441
Test name
Test status
Simulation time 1825994232 ps
CPU time 6.29 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 208056 kb
Host smart-19a3dbcc-3634-4228-aa99-f507c582798f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627546331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2627546331
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3916946496
Short name T565
Test name
Test status
Simulation time 1525731410 ps
CPU time 7.42 seconds
Started Jun 25 05:24:47 PM PDT 24
Finished Jun 25 05:24:57 PM PDT 24
Peak memory 208200 kb
Host smart-d4896527-df00-4fd9-aac3-a46f6c754b3b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916946496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3916946496
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3024175582
Short name T710
Test name
Test status
Simulation time 350567627 ps
CPU time 9.1 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 208648 kb
Host smart-273dbb77-cc46-4d93-964f-a19a7647f26b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024175582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3024175582
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1860213285
Short name T271
Test name
Test status
Simulation time 539045886 ps
CPU time 2.4 seconds
Started Jun 25 05:24:43 PM PDT 24
Finished Jun 25 05:24:49 PM PDT 24
Peak memory 215656 kb
Host smart-a29a3a7c-a8fd-4c53-a557-b8ece3a5d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860213285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1860213285
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2657476852
Short name T618
Test name
Test status
Simulation time 11995811124 ps
CPU time 19.83 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 208368 kb
Host smart-010cf4d9-a2d7-48d1-a73d-eedadd21cedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657476852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2657476852
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1508256827
Short name T291
Test name
Test status
Simulation time 2120723719 ps
CPU time 20.78 seconds
Started Jun 25 05:24:47 PM PDT 24
Finished Jun 25 05:25:10 PM PDT 24
Peak memory 219984 kb
Host smart-ae9b2f9a-e118-49f9-a21c-a445c45f8c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508256827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1508256827
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4293182318
Short name T535
Test name
Test status
Simulation time 775125678 ps
CPU time 20.49 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:25:09 PM PDT 24
Peak memory 214332 kb
Host smart-2068de7f-fae8-4260-912b-1a00fa633e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293182318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4293182318
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2409400032
Short name T38
Test name
Test status
Simulation time 306296607 ps
CPU time 2.35 seconds
Started Jun 25 05:24:44 PM PDT 24
Finished Jun 25 05:24:49 PM PDT 24
Peak memory 210128 kb
Host smart-eb23c236-1f2e-483b-a59d-fa37738c7152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409400032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2409400032
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1430613497
Short name T839
Test name
Test status
Simulation time 41748166 ps
CPU time 0.83 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 205988 kb
Host smart-438920a5-569e-46bc-a3f2-1086199788a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430613497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1430613497
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2691897397
Short name T798
Test name
Test status
Simulation time 225130574 ps
CPU time 5.93 seconds
Started Jun 25 05:24:44 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 214312 kb
Host smart-84da34dd-5298-4b58-bb08-91b0ea92a44f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691897397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2691897397
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4253664727
Short name T474
Test name
Test status
Simulation time 1276049728 ps
CPU time 20.9 seconds
Started Jun 25 05:24:44 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 209080 kb
Host smart-37f451fd-960a-4643-ad68-fb2412aac184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253664727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4253664727
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1846985710
Short name T340
Test name
Test status
Simulation time 120408789 ps
CPU time 2.49 seconds
Started Jun 25 05:24:48 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 214348 kb
Host smart-196c3596-a46f-4728-ad18-25c34952c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846985710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1846985710
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3728125110
Short name T37
Test name
Test status
Simulation time 134698190 ps
CPU time 2.47 seconds
Started Jun 25 05:24:51 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 206700 kb
Host smart-3e8ffb6b-751d-45ac-a14b-c736e7a16d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728125110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3728125110
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3907064252
Short name T440
Test name
Test status
Simulation time 185311691 ps
CPU time 2.59 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:51 PM PDT 24
Peak memory 209044 kb
Host smart-e61aa53d-d696-4eaf-83a0-9559b87d4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907064252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3907064252
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3437420176
Short name T667
Test name
Test status
Simulation time 166389260 ps
CPU time 4.53 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 209868 kb
Host smart-4443be86-fa26-4c05-a2aa-cbb16f3a1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437420176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3437420176
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3374170474
Short name T229
Test name
Test status
Simulation time 53987181 ps
CPU time 2.66 seconds
Started Jun 25 05:24:52 PM PDT 24
Finished Jun 25 05:24:56 PM PDT 24
Peak memory 206748 kb
Host smart-745e3e3f-a3eb-4486-8303-115031cd9db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374170474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3374170474
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2230913766
Short name T540
Test name
Test status
Simulation time 182242767 ps
CPU time 2.8 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:24:51 PM PDT 24
Peak memory 208820 kb
Host smart-9f5430ea-8f9a-4a7e-8934-272c04701817
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230913766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2230913766
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3265553150
Short name T528
Test name
Test status
Simulation time 3085494152 ps
CPU time 21.28 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 208208 kb
Host smart-31411321-fc51-4f0d-8590-2093995be8a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265553150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3265553150
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3011001486
Short name T442
Test name
Test status
Simulation time 799674453 ps
CPU time 5.68 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 208916 kb
Host smart-22c1d3e6-77db-42e6-b4d9-e0d927f6d296
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011001486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3011001486
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1568376036
Short name T764
Test name
Test status
Simulation time 174901696 ps
CPU time 2.5 seconds
Started Jun 25 05:24:48 PM PDT 24
Finished Jun 25 05:24:52 PM PDT 24
Peak memory 214316 kb
Host smart-51520465-527c-4499-8164-de898175478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568376036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1568376036
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.109831892
Short name T651
Test name
Test status
Simulation time 113424782 ps
CPU time 2.94 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 208388 kb
Host smart-b30a70c4-0269-46e8-a3a2-bad5e597c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109831892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.109831892
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2907849611
Short name T205
Test name
Test status
Simulation time 3456438589 ps
CPU time 34.81 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 222444 kb
Host smart-e049fc5f-30ad-40db-818d-5172b340f454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907849611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2907849611
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3680021167
Short name T289
Test name
Test status
Simulation time 2130422213 ps
CPU time 23.84 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 220480 kb
Host smart-0e212051-2547-49d5-aaca-e16ff7c4cdae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680021167 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3680021167
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.644673217
Short name T594
Test name
Test status
Simulation time 641458517 ps
CPU time 9.23 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 210168 kb
Host smart-395fdeb5-51d8-4c07-9abb-29490a67397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644673217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.644673217
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1344806099
Short name T196
Test name
Test status
Simulation time 205162494 ps
CPU time 2.64 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:57 PM PDT 24
Peak memory 210256 kb
Host smart-35f99670-2039-4a8c-bdfe-aadae2ca3c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344806099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1344806099
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.9378279
Short name T481
Test name
Test status
Simulation time 20397207 ps
CPU time 1.06 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:24:57 PM PDT 24
Peak memory 206168 kb
Host smart-fa822526-d687-430a-94c6-bb3fdc6c4616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9378279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.9378279
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1573984234
Short name T314
Test name
Test status
Simulation time 275082003 ps
CPU time 4.87 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:24:53 PM PDT 24
Peak memory 215024 kb
Host smart-d4f69c06-6d1c-4ccd-9983-76f6d3ee86db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573984234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1573984234
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2839284692
Short name T520
Test name
Test status
Simulation time 210538429 ps
CPU time 5.12 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:24:57 PM PDT 24
Peak memory 208736 kb
Host smart-eac12e14-5cd3-4f8c-bfeb-27e6b6443db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839284692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2839284692
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3269763088
Short name T281
Test name
Test status
Simulation time 54223057 ps
CPU time 1.93 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:56 PM PDT 24
Peak memory 214708 kb
Host smart-b339f7d6-c37b-4807-97d9-6539fab31137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269763088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3269763088
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2148256917
Short name T317
Test name
Test status
Simulation time 208662516 ps
CPU time 5.38 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:05 PM PDT 24
Peak memory 220972 kb
Host smart-53a79a02-7ed8-47f0-b23a-19a049a82171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148256917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2148256917
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.887849518
Short name T207
Test name
Test status
Simulation time 62226061 ps
CPU time 3.4 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 215944 kb
Host smart-6a80ba07-c180-43e8-9088-92d506ab67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887849518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.887849518
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.284096825
Short name T108
Test name
Test status
Simulation time 189585562 ps
CPU time 6.99 seconds
Started Jun 25 05:24:52 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 214324 kb
Host smart-3cb2ac33-8677-4b60-a02d-005e6bc52c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284096825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.284096825
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2862785301
Short name T744
Test name
Test status
Simulation time 68021512 ps
CPU time 2.68 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:51 PM PDT 24
Peak memory 206828 kb
Host smart-157faec0-99c3-470f-834a-24b8ace6752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862785301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2862785301
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2150650459
Short name T801
Test name
Test status
Simulation time 185993725 ps
CPU time 2.77 seconds
Started Jun 25 05:24:52 PM PDT 24
Finished Jun 25 05:24:56 PM PDT 24
Peak memory 208760 kb
Host smart-bec49850-f9a3-4fd1-b951-751fe7c9463d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150650459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2150650459
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1550960408
Short name T619
Test name
Test status
Simulation time 47990678 ps
CPU time 2.78 seconds
Started Jun 25 05:24:45 PM PDT 24
Finished Jun 25 05:24:51 PM PDT 24
Peak memory 208480 kb
Host smart-8500e991-1cca-4536-8902-b13fabc9e8db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550960408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1550960408
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1213465439
Short name T755
Test name
Test status
Simulation time 694507699 ps
CPU time 5.13 seconds
Started Jun 25 05:24:46 PM PDT 24
Finished Jun 25 05:24:54 PM PDT 24
Peak memory 207964 kb
Host smart-564e9f86-6689-4570-854f-dab54e97f376
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213465439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1213465439
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3627130462
Short name T813
Test name
Test status
Simulation time 36771054 ps
CPU time 1.62 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 215832 kb
Host smart-f56d52a6-1a98-4388-ae7a-4244ab29ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627130462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3627130462
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.441856123
Short name T848
Test name
Test status
Simulation time 372262196 ps
CPU time 3.57 seconds
Started Jun 25 05:24:49 PM PDT 24
Finished Jun 25 05:24:54 PM PDT 24
Peak memory 208748 kb
Host smart-45465142-b4a1-4deb-b87f-fc2cf518c773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441856123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.441856123
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3193860178
Short name T243
Test name
Test status
Simulation time 1751198472 ps
CPU time 15.99 seconds
Started Jun 25 05:24:48 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 216012 kb
Host smart-ee3d36e6-d4b9-45bf-80bf-11d1b353ba97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193860178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3193860178
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2353484152
Short name T61
Test name
Test status
Simulation time 838228295 ps
CPU time 8.31 seconds
Started Jun 25 05:24:48 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 222644 kb
Host smart-5c32b215-0f05-479e-a956-53c7f67cbbb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353484152 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2353484152
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1936188503
Short name T517
Test name
Test status
Simulation time 850579777 ps
CPU time 7.34 seconds
Started Jun 25 05:24:50 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 218220 kb
Host smart-57ea1d37-8706-477a-b31a-c5e469a04352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936188503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1936188503
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3146560928
Short name T901
Test name
Test status
Simulation time 68267618 ps
CPU time 3.33 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:03 PM PDT 24
Peak memory 209840 kb
Host smart-9bb279ad-2337-4f9d-bd29-9254070ef737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146560928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3146560928
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1877024806
Short name T636
Test name
Test status
Simulation time 232147451 ps
CPU time 1.08 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:55 PM PDT 24
Peak memory 206180 kb
Host smart-5cf059cb-6c98-4477-8a92-6d85d64ea170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877024806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1877024806
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2954481282
Short name T423
Test name
Test status
Simulation time 3075238909 ps
CPU time 38.58 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 214312 kb
Host smart-f997b56d-28db-42e1-82ff-1d2f45d57c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954481282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2954481282
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3899972224
Short name T896
Test name
Test status
Simulation time 150199622 ps
CPU time 4.15 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 210696 kb
Host smart-b3d49d5e-81f7-4e4a-9660-6f97fc0e0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899972224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3899972224
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3383289559
Short name T339
Test name
Test status
Simulation time 63729962 ps
CPU time 2.51 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 208776 kb
Host smart-ab9858e4-c32b-44af-baa5-1240256481f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383289559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3383289559
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4293168173
Short name T86
Test name
Test status
Simulation time 42183383 ps
CPU time 2.89 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 215680 kb
Host smart-8a7de430-7d1d-4e19-878f-e0e63c7ea87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293168173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4293168173
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1352990354
Short name T298
Test name
Test status
Simulation time 95707899 ps
CPU time 1.73 seconds
Started Jun 25 05:24:56 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 214080 kb
Host smart-8648873a-e7db-44ae-b192-b5354c53783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352990354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1352990354
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3966618836
Short name T579
Test name
Test status
Simulation time 414333710 ps
CPU time 3.43 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 209616 kb
Host smart-ecc4a0bc-3875-4389-b6f9-673f1a4d590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966618836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3966618836
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2282708110
Short name T278
Test name
Test status
Simulation time 234387080 ps
CPU time 3.25 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 206904 kb
Host smart-9eef1056-8537-4186-8738-22b60fcde992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282708110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2282708110
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4189419768
Short name T371
Test name
Test status
Simulation time 850690239 ps
CPU time 4.59 seconds
Started Jun 25 05:24:52 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 209148 kb
Host smart-05a413c4-e1ce-4a92-9e41-23d27a0daa6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189419768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4189419768
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.321264463
Short name T875
Test name
Test status
Simulation time 132055683 ps
CPU time 3.59 seconds
Started Jun 25 05:24:56 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 206976 kb
Host smart-30588c03-358f-4e24-ace9-deb7db222baa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321264463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.321264463
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2969069403
Short name T545
Test name
Test status
Simulation time 148604256 ps
CPU time 4.55 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 208000 kb
Host smart-76499b69-7fe8-48f3-a1c0-e1aed92d0fde
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969069403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2969069403
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2896727698
Short name T734
Test name
Test status
Simulation time 387267102 ps
CPU time 3.75 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 218272 kb
Host smart-a4fd3aa3-0ddd-4fdf-b9c5-d5abffac4650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896727698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2896727698
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3382591041
Short name T556
Test name
Test status
Simulation time 64448450 ps
CPU time 2.31 seconds
Started Jun 25 05:24:56 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 206916 kb
Host smart-ea8f94c3-6a71-478a-8fe2-cea6d39d404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382591041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3382591041
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.402073615
Short name T203
Test name
Test status
Simulation time 2124185706 ps
CPU time 21.41 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 215448 kb
Host smart-898a4626-f322-4188-bdd8-fb1292880e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402073615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.402073615
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1191166240
Short name T796
Test name
Test status
Simulation time 1264913395 ps
CPU time 14.6 seconds
Started Jun 25 05:24:56 PM PDT 24
Finished Jun 25 05:25:12 PM PDT 24
Peak memory 220484 kb
Host smart-3894869e-a8b1-4641-92b2-0c8de2d78f59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191166240 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1191166240
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3881597051
Short name T872
Test name
Test status
Simulation time 162736634 ps
CPU time 3.24 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 207944 kb
Host smart-a4aa459a-e2a5-4304-bde3-c023c2e69913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881597051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3881597051
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1994255599
Short name T645
Test name
Test status
Simulation time 33737524 ps
CPU time 2.08 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 210084 kb
Host smart-360a0832-c2f6-4a21-ae18-e3afe4c45b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994255599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1994255599
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2178718152
Short name T582
Test name
Test status
Simulation time 33571030 ps
CPU time 0.79 seconds
Started Jun 25 05:24:56 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 205948 kb
Host smart-b0320ee8-db1c-4e77-9459-678a9b15ccd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178718152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2178718152
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1308509221
Short name T858
Test name
Test status
Simulation time 68215192 ps
CPU time 1.69 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:24:57 PM PDT 24
Peak memory 208860 kb
Host smart-9174cc43-78d9-496a-8a9a-bf9219c0aa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308509221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1308509221
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.71829921
Short name T583
Test name
Test status
Simulation time 159672646 ps
CPU time 2.18 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 222424 kb
Host smart-237fa904-3f5c-4b3a-b0e5-5054f7dc0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71829921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.71829921
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1163630727
Short name T562
Test name
Test status
Simulation time 644295598 ps
CPU time 2.68 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 214508 kb
Host smart-87fe5a17-938f-41d6-8533-04ad0443673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163630727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1163630727
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2659795001
Short name T26
Test name
Test status
Simulation time 99107842 ps
CPU time 2.17 seconds
Started Jun 25 05:24:52 PM PDT 24
Finished Jun 25 05:24:56 PM PDT 24
Peak memory 220876 kb
Host smart-f9a25d4b-80db-486d-9310-a40519c74862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659795001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2659795001
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1858397193
Short name T219
Test name
Test status
Simulation time 250904337 ps
CPU time 5.03 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:09 PM PDT 24
Peak memory 210044 kb
Host smart-fd96bf5e-9c82-473a-83b6-4663621e461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858397193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1858397193
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1394108901
Short name T252
Test name
Test status
Simulation time 287671499 ps
CPU time 8.52 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 209084 kb
Host smart-a1b834f8-f4b5-4da3-8d8f-472394cc3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394108901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1394108901
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4095719545
Short name T864
Test name
Test status
Simulation time 74327395 ps
CPU time 2.2 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 206868 kb
Host smart-e83d8251-f511-47a3-9536-2195d9e5cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095719545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4095719545
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3143746039
Short name T78
Test name
Test status
Simulation time 733866739 ps
CPU time 8.42 seconds
Started Jun 25 05:24:56 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 206896 kb
Host smart-b1b83ffc-c0b2-46ad-95af-099f0eb815e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143746039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3143746039
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4118587208
Short name T236
Test name
Test status
Simulation time 192909756 ps
CPU time 7.55 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 208904 kb
Host smart-bdd63c3d-e222-4440-9a59-105f2ca0a5d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118587208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4118587208
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3610602553
Short name T637
Test name
Test status
Simulation time 129908242 ps
CPU time 3.93 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 208536 kb
Host smart-380d2994-2fc7-445d-b6da-c7076feaf519
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610602553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3610602553
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1207767569
Short name T253
Test name
Test status
Simulation time 444258816 ps
CPU time 3.19 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 214332 kb
Host smart-33ac4e03-6a0e-455e-9e38-0c129f83fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207767569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1207767569
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1684447191
Short name T435
Test name
Test status
Simulation time 394570124 ps
CPU time 4.06 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 206792 kb
Host smart-899cf4e2-d2d2-4737-b6ed-d4130d98dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684447191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1684447191
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1816026277
Short name T223
Test name
Test status
Simulation time 4198037328 ps
CPU time 43.87 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 222568 kb
Host smart-c6b70e27-e879-48e3-8b2f-3cc7407e65cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816026277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1816026277
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3957433395
Short name T52
Test name
Test status
Simulation time 804923296 ps
CPU time 18.95 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:25:14 PM PDT 24
Peak memory 222516 kb
Host smart-9fe22701-65e7-48f4-89e6-ba31834267d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957433395 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3957433395
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.987448261
Short name T785
Test name
Test status
Simulation time 885741462 ps
CPU time 6.83 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 209148 kb
Host smart-7fb6d1b4-94e6-459f-96e5-cb82100dc47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987448261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.987448261
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1232263775
Short name T158
Test name
Test status
Simulation time 167909831 ps
CPU time 5.24 seconds
Started Jun 25 05:24:54 PM PDT 24
Finished Jun 25 05:25:00 PM PDT 24
Peak memory 210712 kb
Host smart-c9fb1454-0715-4149-bcf3-51b58fad552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232263775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1232263775
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.67576234
Short name T431
Test name
Test status
Simulation time 20062378 ps
CPU time 0.8 seconds
Started Jun 25 05:24:59 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 206016 kb
Host smart-c16bd99c-04f5-4007-9d4d-e83965ff7f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67576234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.67576234
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1140450590
Short name T850
Test name
Test status
Simulation time 43453139 ps
CPU time 2.68 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:02 PM PDT 24
Peak memory 214324 kb
Host smart-30b8a050-f53d-438e-b63f-7848c8adaf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140450590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1140450590
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1876960372
Short name T497
Test name
Test status
Simulation time 130813405 ps
CPU time 4.1 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:03 PM PDT 24
Peak memory 210288 kb
Host smart-b80d19af-2a2f-4850-a0d7-d88442b88731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876960372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1876960372
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2913486251
Short name T25
Test name
Test status
Simulation time 105192659 ps
CPU time 4.53 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 218376 kb
Host smart-b764b981-ec75-4486-8170-dec74ce0aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913486251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2913486251
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2661240776
Short name T87
Test name
Test status
Simulation time 156896078 ps
CPU time 3.25 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 214264 kb
Host smart-b7d766e4-7063-4e0f-9aeb-6a6a2a46dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661240776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2661240776
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1354211864
Short name T702
Test name
Test status
Simulation time 192727559 ps
CPU time 4.04 seconds
Started Jun 25 05:24:53 PM PDT 24
Finished Jun 25 05:24:59 PM PDT 24
Peak memory 214292 kb
Host smart-71036a36-06e0-4145-990f-d9dc905c65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354211864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1354211864
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2883442331
Short name T404
Test name
Test status
Simulation time 908026684 ps
CPU time 7.65 seconds
Started Jun 25 05:24:55 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 208820 kb
Host smart-4f72b199-baaa-42ce-8e21-7e9a043cdfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883442331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2883442331
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2730316901
Short name T241
Test name
Test status
Simulation time 5327353162 ps
CPU time 28.39 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 208476 kb
Host smart-ba03cb39-1e7f-4593-8dd7-dadc0554555d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730316901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2730316901
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.742692897
Short name T793
Test name
Test status
Simulation time 575128896 ps
CPU time 7.19 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 208836 kb
Host smart-44d221b2-f7cf-4ef2-985d-c1dbf2ef032b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742692897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.742692897
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1502925153
Short name T555
Test name
Test status
Simulation time 65511756 ps
CPU time 2.5 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:02 PM PDT 24
Peak memory 207448 kb
Host smart-0e3e56c5-36a9-4926-a7ee-77956f15ae9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502925153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1502925153
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.713899632
Short name T596
Test name
Test status
Simulation time 156346297 ps
CPU time 4.66 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 208884 kb
Host smart-83d52d6d-5752-4163-9464-c7ee91ea9ffd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713899632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.713899632
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.803907384
Short name T374
Test name
Test status
Simulation time 263649175 ps
CPU time 2.48 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:02 PM PDT 24
Peak memory 208408 kb
Host smart-c35db598-7f35-4033-9094-9cc962a9ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803907384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.803907384
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3464302732
Short name T430
Test name
Test status
Simulation time 33810415 ps
CPU time 2.18 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:01 PM PDT 24
Peak memory 207300 kb
Host smart-23bd6e11-ea17-4283-86e2-3fddf71806da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464302732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3464302732
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.488026064
Short name T172
Test name
Test status
Simulation time 955618398 ps
CPU time 14.33 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:17 PM PDT 24
Peak memory 222608 kb
Host smart-28099825-57b6-4cf8-9004-95491223dd77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488026064 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.488026064
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2385264874
Short name T769
Test name
Test status
Simulation time 768041834 ps
CPU time 5.81 seconds
Started Jun 25 05:24:57 PM PDT 24
Finished Jun 25 05:25:05 PM PDT 24
Peak memory 208592 kb
Host smart-1f0ac80b-1d16-40af-9d69-47c27f65e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385264874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2385264874
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2231393082
Short name T779
Test name
Test status
Simulation time 168104484 ps
CPU time 2.82 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:05 PM PDT 24
Peak memory 210268 kb
Host smart-48729270-c575-4aaa-a243-0520c310f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231393082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2231393082
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.514393802
Short name T624
Test name
Test status
Simulation time 11355144 ps
CPU time 0.87 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 206060 kb
Host smart-a1f0ac07-b5e2-4de1-887c-3b6e1d4e0235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514393802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.514393802
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1287493753
Short name T420
Test name
Test status
Simulation time 296016438 ps
CPU time 7.84 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 214696 kb
Host smart-215f4b0e-b6a5-4fbb-b7ad-2ddacc3cb181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287493753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1287493753
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4011522410
Short name T595
Test name
Test status
Simulation time 1001336409 ps
CPU time 3.95 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 222712 kb
Host smart-cbf22783-bbdb-4e30-9602-8d8b833d1ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011522410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4011522410
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3627829353
Short name T718
Test name
Test status
Simulation time 1556163703 ps
CPU time 8.86 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:37 PM PDT 24
Peak memory 209096 kb
Host smart-d3d0fbe0-c65f-455b-9e69-309ce45676e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627829353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3627829353
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3447340704
Short name T246
Test name
Test status
Simulation time 109892307 ps
CPU time 5.07 seconds
Started Jun 25 05:23:27 PM PDT 24
Finished Jun 25 05:23:35 PM PDT 24
Peak memory 208656 kb
Host smart-c14e203d-f502-4f5c-8c07-bed62c03c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447340704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3447340704
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_random.3269511843
Short name T732
Test name
Test status
Simulation time 119631167 ps
CPU time 2.72 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 218344 kb
Host smart-fd7672bf-cac8-42cc-8928-1aad35d8b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269511843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3269511843
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1083073884
Short name T11
Test name
Test status
Simulation time 1790073350 ps
CPU time 13.93 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 238092 kb
Host smart-3909cdc2-c7ba-4034-ae86-982c738b560a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083073884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1083073884
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1696134847
Short name T512
Test name
Test status
Simulation time 1584803415 ps
CPU time 29.11 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:56 PM PDT 24
Peak memory 206856 kb
Host smart-3d597cee-f06e-4b19-be40-d4526858de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696134847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1696134847
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.448758397
Short name T753
Test name
Test status
Simulation time 202062634 ps
CPU time 3.36 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 208584 kb
Host smart-7263b1ea-b533-42b3-9d93-53f541ef30fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448758397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.448758397
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1530222212
Short name T862
Test name
Test status
Simulation time 72257488 ps
CPU time 3.04 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 208460 kb
Host smart-a962eba2-c60f-40b6-a3ca-8d44afe87824
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530222212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1530222212
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2262233399
Short name T4
Test name
Test status
Simulation time 77359269 ps
CPU time 3.02 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 208376 kb
Host smart-864b9e72-523c-4edf-aa9f-b2f80a33f134
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262233399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2262233399
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1741096032
Short name T288
Test name
Test status
Simulation time 298691826 ps
CPU time 4.33 seconds
Started Jun 25 05:23:21 PM PDT 24
Finished Jun 25 05:23:27 PM PDT 24
Peak memory 218292 kb
Host smart-9545eeda-7d4c-40ed-bf9e-1daae8fe74e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741096032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1741096032
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.965841165
Short name T727
Test name
Test status
Simulation time 78029007 ps
CPU time 3.15 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 208408 kb
Host smart-ffa3b25a-b6f2-446d-86b0-a24200d07186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965841165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.965841165
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.687013854
Short name T324
Test name
Test status
Simulation time 1135563360 ps
CPU time 16.66 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 217308 kb
Host smart-b251c9d8-d232-4bbc-8909-3d6994fa1190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687013854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.687013854
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3088001108
Short name T337
Test name
Test status
Simulation time 445522128 ps
CPU time 6.79 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 209820 kb
Host smart-3ab3ca4a-0288-4af5-a1f8-496af5c32bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088001108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3088001108
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2749755519
Short name T388
Test name
Test status
Simulation time 82542057 ps
CPU time 1.58 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 210024 kb
Host smart-4dbc4df8-ca20-43d5-9306-777675e92c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749755519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2749755519
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2074032995
Short name T863
Test name
Test status
Simulation time 51305915 ps
CPU time 0.91 seconds
Started Jun 25 05:25:09 PM PDT 24
Finished Jun 25 05:25:13 PM PDT 24
Peak memory 206060 kb
Host smart-5f03b1fb-35e8-4795-a0cb-7048e636790c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074032995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2074032995
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1483507999
Short name T227
Test name
Test status
Simulation time 48482638 ps
CPU time 3.37 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:10 PM PDT 24
Peak memory 214320 kb
Host smart-138ddcf0-27df-44ae-a081-423ad4151375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483507999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1483507999
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3268772305
Short name T914
Test name
Test status
Simulation time 320417602 ps
CPU time 2.73 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 209796 kb
Host smart-87a18a80-e6b2-443f-b7c5-b4a3ba8e8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268772305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3268772305
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.876295525
Short name T258
Test name
Test status
Simulation time 87430048 ps
CPU time 3.91 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 221256 kb
Host smart-60f57393-b279-4145-9b91-3b3dc3507467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876295525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.876295525
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3342058632
Short name T366
Test name
Test status
Simulation time 63073417 ps
CPU time 2.25 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 214176 kb
Host smart-35765acc-f08e-4d52-a736-2c9e2ff1e3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342058632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3342058632
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.879239177
Short name T353
Test name
Test status
Simulation time 410953749 ps
CPU time 6.98 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:12 PM PDT 24
Peak memory 209608 kb
Host smart-73944f4d-6138-47d0-9e4f-9296bed650c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879239177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.879239177
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2444648671
Short name T597
Test name
Test status
Simulation time 146607725 ps
CPU time 3.85 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 208488 kb
Host smart-aaf1f086-d9bb-4386-a74d-51c3a7d32477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444648671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2444648671
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1747134556
Short name T799
Test name
Test status
Simulation time 217039078 ps
CPU time 5.91 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:10 PM PDT 24
Peak memory 208064 kb
Host smart-ad93033d-169e-4db5-a66b-52bd83ea7225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747134556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1747134556
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.768694365
Short name T438
Test name
Test status
Simulation time 315942469 ps
CPU time 2.51 seconds
Started Jun 25 05:25:10 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 206948 kb
Host smart-de92af8b-8191-421f-ab64-954077b349dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768694365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.768694365
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.494932400
Short name T542
Test name
Test status
Simulation time 3599474286 ps
CPU time 33.87 seconds
Started Jun 25 05:25:09 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 208728 kb
Host smart-6665e57e-3788-4048-9f47-ca54902b4d06
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494932400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.494932400
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3394761702
Short name T754
Test name
Test status
Simulation time 149255617 ps
CPU time 5.49 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:12 PM PDT 24
Peak memory 208516 kb
Host smart-34aac96d-fdc7-48f8-8f1e-6b67c0ac99c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394761702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3394761702
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2043561296
Short name T733
Test name
Test status
Simulation time 718143598 ps
CPU time 5.27 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 209280 kb
Host smart-3b438439-c969-4fd8-8720-7610be71f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043561296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2043561296
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.273829877
Short name T873
Test name
Test status
Simulation time 231763832 ps
CPU time 4.49 seconds
Started Jun 25 05:24:58 PM PDT 24
Finished Jun 25 05:25:05 PM PDT 24
Peak memory 208712 kb
Host smart-2fb90ac3-c833-4cd5-a9a7-3ad1a01c20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273829877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.273829877
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3121087764
Short name T5
Test name
Test status
Simulation time 2319521414 ps
CPU time 20.5 seconds
Started Jun 25 05:25:05 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 216064 kb
Host smart-11d3fddf-bf49-4b41-b9a5-2152408155d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121087764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3121087764
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1336275251
Short name T890
Test name
Test status
Simulation time 180558191 ps
CPU time 7.05 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:11 PM PDT 24
Peak memory 220044 kb
Host smart-9df1d1ef-0665-4be9-abd3-8f3cf67f5331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336275251 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1336275251
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3244702443
Short name T586
Test name
Test status
Simulation time 60053900 ps
CPU time 3.2 seconds
Started Jun 25 05:25:05 PM PDT 24
Finished Jun 25 05:25:10 PM PDT 24
Peak memory 208396 kb
Host smart-813a6f01-6067-4098-87c6-73266b5116ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244702443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3244702443
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3102302788
Short name T889
Test name
Test status
Simulation time 351940593 ps
CPU time 2.21 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:04 PM PDT 24
Peak memory 210084 kb
Host smart-08e040c7-86bf-43cd-8ac1-3a4df4450047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102302788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3102302788
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3471604403
Short name T792
Test name
Test status
Simulation time 189972902 ps
CPU time 0.89 seconds
Started Jun 25 05:25:09 PM PDT 24
Finished Jun 25 05:25:13 PM PDT 24
Peak memory 206068 kb
Host smart-5d5190d8-e79e-46e9-a9b4-9e463f34715e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471604403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3471604403
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1301654707
Short name T426
Test name
Test status
Simulation time 520079497 ps
CPU time 8.23 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:14 PM PDT 24
Peak memory 214244 kb
Host smart-c6ee94d1-11c6-41a0-8dcc-1563460116a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301654707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1301654707
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1331628879
Short name T689
Test name
Test status
Simulation time 84879651 ps
CPU time 1.98 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 214688 kb
Host smart-f3098954-6c7c-4766-a30c-376b01b35b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331628879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1331628879
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3907178
Short name T73
Test name
Test status
Simulation time 134916114 ps
CPU time 2.29 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 206760 kb
Host smart-66e97b25-17a3-482f-b169-747a51502ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3907178
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3378108316
Short name T97
Test name
Test status
Simulation time 118904936 ps
CPU time 5.28 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 219076 kb
Host smart-92b151a5-ef74-4f3e-b604-2f127c3f72d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378108316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3378108316
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2989097090
Short name T257
Test name
Test status
Simulation time 40548080 ps
CPU time 2.73 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 214292 kb
Host smart-e3f4d9d8-404d-4e1a-8a05-4bf0ad9c4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989097090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2989097090
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.646369040
Short name T206
Test name
Test status
Simulation time 252458954 ps
CPU time 3.44 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:09 PM PDT 24
Peak memory 209672 kb
Host smart-56d26f4f-01f1-413e-b17d-6bd86e4bcdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646369040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.646369040
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3928073291
Short name T547
Test name
Test status
Simulation time 259255342 ps
CPU time 6.27 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:09 PM PDT 24
Peak memory 207560 kb
Host smart-8b5d81ab-dd08-45c4-8863-e5399b651d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928073291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3928073291
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.643363820
Short name T580
Test name
Test status
Simulation time 19305368 ps
CPU time 1.74 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 206856 kb
Host smart-c6ccecd7-4534-4e21-97c6-c47ba2ef35cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643363820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.643363820
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3209934809
Short name T178
Test name
Test status
Simulation time 188299891 ps
CPU time 5.53 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 208640 kb
Host smart-c61e0e48-8132-4994-a379-c6fb59f4d2ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209934809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3209934809
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1949806534
Short name T572
Test name
Test status
Simulation time 23551220 ps
CPU time 1.92 seconds
Started Jun 25 05:25:02 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 207412 kb
Host smart-1eed547c-6113-4373-87cd-f574b7ebb309
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949806534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1949806534
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4119136059
Short name T841
Test name
Test status
Simulation time 122725241 ps
CPU time 3.26 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:08 PM PDT 24
Peak memory 206976 kb
Host smart-01f496c8-3f9a-42af-991e-8c46f9625b57
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119136059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4119136059
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1931235496
Short name T642
Test name
Test status
Simulation time 69481844 ps
CPU time 3.65 seconds
Started Jun 25 05:25:01 PM PDT 24
Finished Jun 25 05:25:06 PM PDT 24
Peak memory 209848 kb
Host smart-57b830c7-0e60-45ee-8c63-04430dbfb39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931235496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1931235496
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3995027368
Short name T704
Test name
Test status
Simulation time 206686562 ps
CPU time 4.81 seconds
Started Jun 25 05:25:06 PM PDT 24
Finished Jun 25 05:25:12 PM PDT 24
Peak memory 208416 kb
Host smart-f59c5cd8-724e-4182-81b9-e292e10f4467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995027368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3995027368
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3157895978
Short name T527
Test name
Test status
Simulation time 118659115 ps
CPU time 5.58 seconds
Started Jun 25 05:25:04 PM PDT 24
Finished Jun 25 05:25:11 PM PDT 24
Peak memory 208796 kb
Host smart-55e34481-ed8a-4e49-9244-ee6dd4a1c6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157895978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3157895978
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.249022432
Short name T198
Test name
Test status
Simulation time 84136810 ps
CPU time 1.48 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:07 PM PDT 24
Peak memory 209840 kb
Host smart-0ba0604d-0990-417e-a427-1f79c7ef53f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249022432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.249022432
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1431002290
Short name T468
Test name
Test status
Simulation time 102445233 ps
CPU time 0.9 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 206044 kb
Host smart-45918813-7b68-4e62-af1e-e6919b16033c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431002290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1431002290
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1063995592
Short name T125
Test name
Test status
Simulation time 121051679 ps
CPU time 4.36 seconds
Started Jun 25 05:25:14 PM PDT 24
Finished Jun 25 05:25:22 PM PDT 24
Peak memory 215244 kb
Host smart-50d82d9f-af28-4489-ac44-1e038ec368d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063995592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1063995592
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.840010529
Short name T33
Test name
Test status
Simulation time 62447113 ps
CPU time 4.01 seconds
Started Jun 25 05:25:15 PM PDT 24
Finished Jun 25 05:25:22 PM PDT 24
Peak memory 214652 kb
Host smart-4fe11ee7-548c-484b-a4dc-9e5e9bb0e9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840010529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.840010529
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2784457485
Short name T714
Test name
Test status
Simulation time 174229721 ps
CPU time 1.7 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:17 PM PDT 24
Peak memory 209816 kb
Host smart-e0b964cf-58fe-4a4c-b900-510e3820efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784457485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2784457485
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1460704073
Short name T263
Test name
Test status
Simulation time 40404139 ps
CPU time 2.39 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 222428 kb
Host smart-3230314e-a9b7-4ade-8e06-a86f94c1a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460704073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1460704073
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3760411631
Short name T728
Test name
Test status
Simulation time 171933698 ps
CPU time 3.4 seconds
Started Jun 25 05:25:10 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 208420 kb
Host smart-099d1e27-0ca1-4a8f-8e1a-a3dc9a3fa2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760411631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3760411631
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1476682422
Short name T701
Test name
Test status
Simulation time 154696377 ps
CPU time 2.97 seconds
Started Jun 25 05:25:14 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 210480 kb
Host smart-2bc47827-1d4e-4a4b-ac3f-b05c9b3f6c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476682422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1476682422
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1302788251
Short name T323
Test name
Test status
Simulation time 444905890 ps
CPU time 5.41 seconds
Started Jun 25 05:25:05 PM PDT 24
Finished Jun 25 05:25:12 PM PDT 24
Peak memory 208548 kb
Host smart-ba4cc497-6241-4bac-9339-b28d2284c3dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302788251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1302788251
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4181771346
Short name T616
Test name
Test status
Simulation time 224472796 ps
CPU time 3.39 seconds
Started Jun 25 05:25:03 PM PDT 24
Finished Jun 25 05:25:09 PM PDT 24
Peak memory 206968 kb
Host smart-ba3a7047-79de-4f00-9b5f-6e57f660d24c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181771346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4181771346
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.701792735
Short name T690
Test name
Test status
Simulation time 251474159 ps
CPU time 3.42 seconds
Started Jun 25 05:25:05 PM PDT 24
Finished Jun 25 05:25:10 PM PDT 24
Peak memory 208828 kb
Host smart-c7a46d20-16c7-4e4e-8560-530479cc5d80
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701792735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.701792735
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.711381832
Short name T780
Test name
Test status
Simulation time 91989206 ps
CPU time 1.99 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 214292 kb
Host smart-91bf35a9-54a6-41c1-9cc4-00e8cf0ea374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711381832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.711381832
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2623019453
Short name T773
Test name
Test status
Simulation time 2819890188 ps
CPU time 25.82 seconds
Started Jun 25 05:25:09 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 208600 kb
Host smart-9e6ec652-f01a-4a64-86aa-cdc5492e7b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623019453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2623019453
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3338116470
Short name T758
Test name
Test status
Simulation time 323371080 ps
CPU time 15.78 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:30 PM PDT 24
Peak memory 215384 kb
Host smart-3e676c49-17c0-45a5-b316-233f2f6ed6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338116470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3338116470
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.343416758
Short name T123
Test name
Test status
Simulation time 262933900 ps
CPU time 7.43 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 218904 kb
Host smart-5547bc94-57a9-4a0d-9fd3-36b61a34f963
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343416758 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.343416758
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3921624452
Short name T662
Test name
Test status
Simulation time 56741337 ps
CPU time 3.34 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 208300 kb
Host smart-168d221b-9af4-4779-8014-98a993645db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921624452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3921624452
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1953795512
Short name T635
Test name
Test status
Simulation time 86040088 ps
CPU time 1.69 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 209840 kb
Host smart-c8db0af8-c29d-44b9-9db1-cc28eecd439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953795512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1953795512
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1774519398
Short name T103
Test name
Test status
Simulation time 54858473 ps
CPU time 1.08 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 206072 kb
Host smart-45cc9149-6450-4dfa-8757-bf5b2c13d07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774519398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1774519398
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4058281296
Short name T276
Test name
Test status
Simulation time 185230434 ps
CPU time 3.64 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:21 PM PDT 24
Peak memory 215088 kb
Host smart-32560cc4-a6fc-4bf0-b7a8-6f6d12457fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058281296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4058281296
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3530961616
Short name T325
Test name
Test status
Simulation time 189705031 ps
CPU time 2.08 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 209308 kb
Host smart-0c567ed5-8bc3-48a5-81ab-508e4e1093ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530961616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3530961616
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1874895659
Short name T500
Test name
Test status
Simulation time 49149785 ps
CPU time 1.55 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:17 PM PDT 24
Peak memory 207212 kb
Host smart-03038197-9311-48d5-af03-cdd6dccc44cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874895659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1874895659
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.916397150
Short name T344
Test name
Test status
Simulation time 88156652 ps
CPU time 2.36 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 214324 kb
Host smart-965b4d65-54a6-4a7f-b4e2-355049afb0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916397150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.916397150
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.324060557
Short name T427
Test name
Test status
Simulation time 129756106 ps
CPU time 3.74 seconds
Started Jun 25 05:25:10 PM PDT 24
Finished Jun 25 05:25:17 PM PDT 24
Peak memory 214376 kb
Host smart-b160213d-ee8e-495e-a121-bc822bb9974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324060557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.324060557
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3552797425
Short name T209
Test name
Test status
Simulation time 38897919 ps
CPU time 3.08 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 222528 kb
Host smart-5697cab5-5ab4-4ba2-adb9-13025b018b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552797425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3552797425
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3006134833
Short name T644
Test name
Test status
Simulation time 59346589 ps
CPU time 2.34 seconds
Started Jun 25 05:25:10 PM PDT 24
Finished Jun 25 05:25:16 PM PDT 24
Peak memory 222584 kb
Host smart-9a906175-638b-4285-ac26-24d376dba655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006134833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3006134833
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2389418312
Short name T910
Test name
Test status
Simulation time 163951703 ps
CPU time 5.88 seconds
Started Jun 25 05:25:16 PM PDT 24
Finished Jun 25 05:25:25 PM PDT 24
Peak memory 208604 kb
Host smart-b8d84f9c-3533-4f87-be50-50b8f5b94b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389418312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2389418312
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2994657587
Short name T715
Test name
Test status
Simulation time 275242488 ps
CPU time 4.69 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:21 PM PDT 24
Peak memory 206964 kb
Host smart-9b9c4a73-3635-48dd-9b8b-4aeafaf75be3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994657587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2994657587
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.144971990
Short name T575
Test name
Test status
Simulation time 970236524 ps
CPU time 7.73 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 208720 kb
Host smart-28ff2a7a-c726-434c-9bb1-5faafbd0ff0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144971990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.144971990
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1070865279
Short name T81
Test name
Test status
Simulation time 920970625 ps
CPU time 28.19 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:43 PM PDT 24
Peak memory 208484 kb
Host smart-083619c2-0128-4034-b0d7-27ae5cb8969f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070865279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1070865279
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1623781310
Short name T109
Test name
Test status
Simulation time 93119475 ps
CPU time 2.87 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 214296 kb
Host smart-37dadcfe-3aa7-4f6f-a1e2-832eb02340b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623781310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1623781310
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3675592165
Short name T612
Test name
Test status
Simulation time 70251197 ps
CPU time 3.05 seconds
Started Jun 25 05:25:14 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 208532 kb
Host smart-a805d83b-552a-4679-a05f-1b85f81aacbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675592165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3675592165
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4117138002
Short name T8
Test name
Test status
Simulation time 1029234665 ps
CPU time 24.68 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 221940 kb
Host smart-5af0c31c-4e7f-4e3d-9f67-f2799a7c4d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117138002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4117138002
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2952056217
Short name T359
Test name
Test status
Simulation time 146598184 ps
CPU time 2.83 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 207376 kb
Host smart-ad78bb8e-2c8c-4004-a6c5-90a84257cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952056217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2952056217
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2862846898
Short name T195
Test name
Test status
Simulation time 339495844 ps
CPU time 3.33 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 210420 kb
Host smart-f22fc0cc-2efc-4a43-b96c-8d8df7f21931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862846898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2862846898
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.4139664251
Short name T698
Test name
Test status
Simulation time 86208030 ps
CPU time 1.07 seconds
Started Jun 25 05:25:14 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 206404 kb
Host smart-5029e58d-c053-4e85-985a-ecdd7ce5e811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139664251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.4139664251
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1489579681
Short name T778
Test name
Test status
Simulation time 88038941 ps
CPU time 3.29 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 214316 kb
Host smart-3716102a-cbd3-4dc9-be25-5261f212fcd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489579681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1489579681
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3486344081
Short name T725
Test name
Test status
Simulation time 1160315178 ps
CPU time 7.36 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:23 PM PDT 24
Peak memory 220212 kb
Host smart-c8fce3e9-c215-449f-9936-15c1d8309239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486344081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3486344081
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2877807213
Short name T284
Test name
Test status
Simulation time 1136333558 ps
CPU time 20.86 seconds
Started Jun 25 05:25:14 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 214348 kb
Host smart-8bc6193d-14a4-471d-b997-8070aca7a465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877807213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2877807213
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.93581585
Short name T787
Test name
Test status
Simulation time 83929850 ps
CPU time 2.88 seconds
Started Jun 25 05:25:15 PM PDT 24
Finished Jun 25 05:25:21 PM PDT 24
Peak memory 214540 kb
Host smart-8219fe0e-57c9-4f7d-a1f0-ff16e5307d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93581585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.93581585
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4143874045
Short name T800
Test name
Test status
Simulation time 143973201 ps
CPU time 3.15 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 221868 kb
Host smart-6c5a6158-eda1-4476-b93b-07c027eda724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143874045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4143874045
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2113795045
Short name T501
Test name
Test status
Simulation time 126577298 ps
CPU time 4.24 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:21 PM PDT 24
Peak memory 220220 kb
Host smart-c58943e4-fe28-4892-aaf6-5f4dca7bf7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113795045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2113795045
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1107615297
Short name T180
Test name
Test status
Simulation time 925762157 ps
CPU time 8.55 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:25 PM PDT 24
Peak memory 218384 kb
Host smart-0f57d204-8461-49bb-bc8c-506ad8a7c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107615297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1107615297
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2325681786
Short name T885
Test name
Test status
Simulation time 339981706 ps
CPU time 4.41 seconds
Started Jun 25 05:25:11 PM PDT 24
Finished Jun 25 05:25:19 PM PDT 24
Peak memory 206656 kb
Host smart-f9d4b040-0cb1-4da0-b8df-40435ddc98f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325681786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2325681786
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.901354877
Short name T789
Test name
Test status
Simulation time 220556052 ps
CPU time 3.2 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 208604 kb
Host smart-859a8515-a730-4934-98d8-6beb2e5fc772
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901354877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.901354877
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.937086115
Short name T856
Test name
Test status
Simulation time 649552175 ps
CPU time 4.69 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:21 PM PDT 24
Peak memory 206840 kb
Host smart-d8c3a0dd-867a-4367-87a6-2db8fa10d891
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937086115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.937086115
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3963422888
Short name T452
Test name
Test status
Simulation time 36984449 ps
CPU time 2.66 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 209024 kb
Host smart-d904d35b-632c-4019-9f21-0045599b2d9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963422888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3963422888
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.846692235
Short name T570
Test name
Test status
Simulation time 42628243 ps
CPU time 1.8 seconds
Started Jun 25 05:25:15 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 207940 kb
Host smart-fbc789f5-6fcc-4031-ac65-ad443ce507c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846692235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.846692235
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.265867931
Short name T515
Test name
Test status
Simulation time 230682266 ps
CPU time 2.73 seconds
Started Jun 25 05:25:12 PM PDT 24
Finished Jun 25 05:25:18 PM PDT 24
Peak memory 207820 kb
Host smart-e216f6df-bd72-46c3-9d4f-667cc329f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265867931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.265867931
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2663840969
Short name T724
Test name
Test status
Simulation time 932693495 ps
CPU time 6.53 seconds
Started Jun 25 05:25:13 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 208020 kb
Host smart-7826ca95-2698-4aee-92e2-ee4d23bafb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663840969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2663840969
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1627272200
Short name T509
Test name
Test status
Simulation time 77422125 ps
CPU time 2.03 seconds
Started Jun 25 05:25:15 PM PDT 24
Finished Jun 25 05:25:20 PM PDT 24
Peak memory 210324 kb
Host smart-49392d1e-9891-4321-8551-a9111d142461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627272200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1627272200
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3436178392
Short name T729
Test name
Test status
Simulation time 25829632 ps
CPU time 0.79 seconds
Started Jun 25 05:25:21 PM PDT 24
Finished Jun 25 05:25:23 PM PDT 24
Peak memory 206052 kb
Host smart-cad8f3e0-328d-40b5-830b-46be9f4ddaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436178392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3436178392
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2148244599
Short name T412
Test name
Test status
Simulation time 2968894061 ps
CPU time 65.66 seconds
Started Jun 25 05:25:20 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 215016 kb
Host smart-a4a24ceb-92b0-4e7f-8665-b44c14aa59ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148244599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2148244599
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2875014587
Short name T28
Test name
Test status
Simulation time 68045790 ps
CPU time 3.54 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 221012 kb
Host smart-0c9ecdde-21c5-41cc-9278-33f85467ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875014587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2875014587
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3239221302
Short name T610
Test name
Test status
Simulation time 264393252 ps
CPU time 3.22 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 214252 kb
Host smart-cbd9fef1-7c6b-48be-b1c9-88cf7eec7424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239221302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3239221302
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1504814853
Short name T264
Test name
Test status
Simulation time 83187623 ps
CPU time 2.67 seconds
Started Jun 25 05:25:19 PM PDT 24
Finished Jun 25 05:25:23 PM PDT 24
Peak memory 222524 kb
Host smart-d37be027-479c-4976-a9cb-5e7247562747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504814853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1504814853
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.380386757
Short name T772
Test name
Test status
Simulation time 180885910 ps
CPU time 1.96 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 214260 kb
Host smart-9cf3f17e-6d94-417b-8119-88fba3c0dc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380386757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.380386757
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3026788247
Short name T649
Test name
Test status
Simulation time 34084875 ps
CPU time 2.41 seconds
Started Jun 25 05:25:21 PM PDT 24
Finished Jun 25 05:25:25 PM PDT 24
Peak memory 214256 kb
Host smart-3c76572a-960e-43c8-9645-423e9fd79787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026788247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3026788247
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1108239177
Short name T333
Test name
Test status
Simulation time 126645533 ps
CPU time 5.37 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 208664 kb
Host smart-d5131428-4dbb-45de-b839-ce8bcea4b75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108239177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1108239177
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3324638044
Short name T459
Test name
Test status
Simulation time 159722486 ps
CPU time 2.6 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 208628 kb
Host smart-a399be42-a9f4-43a9-9bf5-438791576898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324638044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3324638044
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2687781559
Short name T403
Test name
Test status
Simulation time 466582528 ps
CPU time 4.51 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 206940 kb
Host smart-753987c8-77c2-44aa-a8f8-051a16705427
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687781559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2687781559
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1769868246
Short name T601
Test name
Test status
Simulation time 792043141 ps
CPU time 8.09 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:34 PM PDT 24
Peak memory 208260 kb
Host smart-84d9c91a-5751-407b-ac35-2c9ffb6d6969
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769868246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1769868246
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1281403891
Short name T557
Test name
Test status
Simulation time 391980249 ps
CPU time 5.16 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 206924 kb
Host smart-2c6e64fc-fd9c-4f2f-ad8c-dfe5a4b0b893
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281403891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1281403891
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1125732480
Short name T525
Test name
Test status
Simulation time 170788739 ps
CPU time 2.51 seconds
Started Jun 25 05:25:26 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 207680 kb
Host smart-acfc3b71-c783-47f4-ba9f-918b4d61a908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125732480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1125732480
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3533052669
Short name T184
Test name
Test status
Simulation time 31662994 ps
CPU time 2.07 seconds
Started Jun 25 05:25:20 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 206968 kb
Host smart-d5158363-3fb2-4256-83f3-2369a385d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533052669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3533052669
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2457697583
Short name T479
Test name
Test status
Simulation time 705523275 ps
CPU time 6.21 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 210288 kb
Host smart-8110b9c3-5fe5-4eeb-96bf-20a87e0d1d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457697583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2457697583
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.399723408
Short name T851
Test name
Test status
Simulation time 3307129938 ps
CPU time 13.36 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 217752 kb
Host smart-af3f451b-de1b-4e78-8e40-a2429d07ee7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399723408 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.399723408
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3539412450
Short name T626
Test name
Test status
Simulation time 41845749 ps
CPU time 2.92 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 208076 kb
Host smart-d0ae50b6-eeca-4fc5-b468-c0f58d02931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539412450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3539412450
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4035535902
Short name T723
Test name
Test status
Simulation time 1780507568 ps
CPU time 3.09 seconds
Started Jun 25 05:25:21 PM PDT 24
Finished Jun 25 05:25:26 PM PDT 24
Peak memory 210584 kb
Host smart-b2c77db0-6c12-483a-8f3d-5bce8d247a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035535902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4035535902
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2341784210
Short name T590
Test name
Test status
Simulation time 16327251 ps
CPU time 0.85 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:26 PM PDT 24
Peak memory 206044 kb
Host smart-c79bb35a-82b3-4cfe-a798-13877a2e208e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341784210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2341784210
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2949222059
Short name T397
Test name
Test status
Simulation time 192040948 ps
CPU time 3.41 seconds
Started Jun 25 05:25:19 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 210696 kb
Host smart-31329b97-7a13-4b0d-95d3-0a5bc0a6e75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949222059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2949222059
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3167234699
Short name T2
Test name
Test status
Simulation time 46239033 ps
CPU time 2.06 seconds
Started Jun 25 05:25:20 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 206972 kb
Host smart-9ab29513-1a5e-4f42-be3b-c1b3d8562473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167234699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3167234699
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1907104855
Short name T88
Test name
Test status
Simulation time 56375754 ps
CPU time 2.06 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 214332 kb
Host smart-424169aa-cf10-4dab-8a4d-a3e077ee7b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907104855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1907104855
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.878019148
Short name T836
Test name
Test status
Simulation time 84926400 ps
CPU time 2.15 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 221676 kb
Host smart-9b2c3030-1800-4c67-8838-18926d207204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878019148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.878019148
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1659540306
Short name T615
Test name
Test status
Simulation time 199457723 ps
CPU time 4.56 seconds
Started Jun 25 05:25:26 PM PDT 24
Finished Jun 25 05:25:34 PM PDT 24
Peak memory 214260 kb
Host smart-0054e6a6-9822-4624-9e5b-6af5db9729e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659540306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1659540306
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1633005471
Short name T894
Test name
Test status
Simulation time 98689790 ps
CPU time 4.33 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 208856 kb
Host smart-e101d3d6-1b2f-4625-82ce-faec7311cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633005471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1633005471
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.545850034
Short name T355
Test name
Test status
Simulation time 570241484 ps
CPU time 4.7 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 208432 kb
Host smart-0d94e4b3-ea15-4f37-a2f5-ee383c999a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545850034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.545850034
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1503570589
Short name T295
Test name
Test status
Simulation time 383736995 ps
CPU time 2.87 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 206800 kb
Host smart-5c5519b8-b2bb-4111-bd01-004e4c584607
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503570589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1503570589
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.728594932
Short name T656
Test name
Test status
Simulation time 547056234 ps
CPU time 2.57 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 207008 kb
Host smart-7671b6a2-617a-4118-a865-f4264af2a30e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728594932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.728594932
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.402640010
Short name T655
Test name
Test status
Simulation time 644822890 ps
CPU time 8.52 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 208548 kb
Host smart-e66afdcb-27e5-404b-b5fa-3ed5221e4f60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402640010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.402640010
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3091500122
Short name T639
Test name
Test status
Simulation time 83441199 ps
CPU time 3.36 seconds
Started Jun 25 05:25:26 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 209444 kb
Host smart-d7cdce9b-2705-47b3-b650-1c60b3329ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091500122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3091500122
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1275738095
Short name T844
Test name
Test status
Simulation time 3347758927 ps
CPU time 6.77 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 207128 kb
Host smart-066762a7-605f-4b31-9a41-ffa5b1c0f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275738095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1275738095
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1170289238
Short name T911
Test name
Test status
Simulation time 339656701 ps
CPU time 16.04 seconds
Started Jun 25 05:25:20 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 215868 kb
Host smart-19f47202-5830-46e6-90b5-471243ad3626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170289238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1170289238
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3134782395
Short name T551
Test name
Test status
Simulation time 138829249 ps
CPU time 3.62 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 207684 kb
Host smart-de893d7a-2886-4044-b584-819a54eabbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134782395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3134782395
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.395736156
Short name T42
Test name
Test status
Simulation time 64224941 ps
CPU time 2.07 seconds
Started Jun 25 05:25:20 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 209688 kb
Host smart-ab44edb7-d284-423d-acba-1a441ed17dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395736156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.395736156
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.855446812
Short name T837
Test name
Test status
Simulation time 28082473 ps
CPU time 0.87 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 206056 kb
Host smart-2f6c3ee7-95e2-4669-805c-d59923a16431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855446812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.855446812
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.633920917
Short name T309
Test name
Test status
Simulation time 1247620413 ps
CPU time 64.62 seconds
Started Jun 25 05:25:21 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 214340 kb
Host smart-4ed5be79-95de-46e9-85da-ddc688d8eb63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633920917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.633920917
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2092342687
Short name T632
Test name
Test status
Simulation time 401101979 ps
CPU time 3.31 seconds
Started Jun 25 05:25:30 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 210268 kb
Host smart-a472bbc1-f216-4e14-aa35-20289b925a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092342687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2092342687
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1547674520
Short name T605
Test name
Test status
Simulation time 137762306 ps
CPU time 2.62 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:30 PM PDT 24
Peak memory 214316 kb
Host smart-ebe5ccde-1762-429e-9313-9249568b2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547674520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1547674520
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3955984533
Short name T915
Test name
Test status
Simulation time 96907477 ps
CPU time 3.2 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 214232 kb
Host smart-802e866c-5175-4582-85a0-d5d330effeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955984533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3955984533
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1718339175
Short name T367
Test name
Test status
Simulation time 203646450 ps
CPU time 3.99 seconds
Started Jun 25 05:25:26 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 214252 kb
Host smart-57434b80-6834-4265-a27c-631c3854435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718339175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1718339175
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.806886820
Short name T888
Test name
Test status
Simulation time 99688020 ps
CPU time 2.87 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 220144 kb
Host smart-9cf6aceb-f85f-4215-9f2a-57ea151e7a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806886820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.806886820
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2621601195
Short name T351
Test name
Test status
Simulation time 729813763 ps
CPU time 6.07 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 209448 kb
Host smart-77b3de21-7faa-4250-bf54-9651b1f3368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621601195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2621601195
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2852113426
Short name T266
Test name
Test status
Simulation time 78542220 ps
CPU time 2.95 seconds
Started Jun 25 05:25:21 PM PDT 24
Finished Jun 25 05:25:26 PM PDT 24
Peak memory 208704 kb
Host smart-e1bc98c3-7d2d-4bee-85e9-1742d65207b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852113426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2852113426
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4170158645
Short name T546
Test name
Test status
Simulation time 43012435 ps
CPU time 2.41 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 208180 kb
Host smart-16ce0edb-9fc2-447a-b6fb-fd1ef5e23e10
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170158645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4170158645
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2036845089
Short name T687
Test name
Test status
Simulation time 221863126 ps
CPU time 5.88 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:34 PM PDT 24
Peak memory 208196 kb
Host smart-c5d550b2-f831-4efa-9f3f-6edcb5609fda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036845089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2036845089
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1323970246
Short name T567
Test name
Test status
Simulation time 57377090 ps
CPU time 2.32 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:30 PM PDT 24
Peak memory 206828 kb
Host smart-2cbc5af3-02c6-40c1-b708-29ffed0e0d9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323970246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1323970246
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.909612340
Short name T409
Test name
Test status
Simulation time 88688305 ps
CPU time 2.67 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 216028 kb
Host smart-bc434aca-f7d4-4272-9b2f-e247d0610657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909612340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.909612340
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.898603975
Short name T607
Test name
Test status
Simulation time 71699755 ps
CPU time 3.02 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 208592 kb
Host smart-bc138f9d-fffc-4913-bbfd-7bb9622ac6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898603975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.898603975
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2553123493
Short name T218
Test name
Test status
Simulation time 3842669617 ps
CPU time 58.59 seconds
Started Jun 25 05:25:20 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 222556 kb
Host smart-9340e112-e6e1-42c7-bb15-3c738c5b2d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553123493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2553123493
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.901517915
Short name T552
Test name
Test status
Simulation time 628600457 ps
CPU time 3.28 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 207268 kb
Host smart-a8938c8a-8259-452a-a42a-3f70e79bde69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901517915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.901517915
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2437342667
Short name T504
Test name
Test status
Simulation time 21546097 ps
CPU time 1.43 seconds
Started Jun 25 05:25:26 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 209668 kb
Host smart-2438fa25-45f5-4397-9b4f-43290e3e40c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437342667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2437342667
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4049393126
Short name T463
Test name
Test status
Simulation time 19214474 ps
CPU time 0.76 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 206060 kb
Host smart-81982fb0-5bb6-4257-9bdd-372835cad0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049393126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4049393126
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1544472202
Short name T654
Test name
Test status
Simulation time 36820153 ps
CPU time 1.73 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 209368 kb
Host smart-bb8dce67-9a6c-4611-9de2-a107e6b4135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544472202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1544472202
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2382436357
Short name T829
Test name
Test status
Simulation time 139318273 ps
CPU time 3.3 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 222296 kb
Host smart-38ae359d-3703-41f1-89a6-3dd9ec27423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382436357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2382436357
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4126949732
Short name T783
Test name
Test status
Simulation time 58529220 ps
CPU time 2.73 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 222380 kb
Host smart-7a104e41-4137-4d33-84df-07233558229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126949732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4126949732
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.26425532
Short name T83
Test name
Test status
Simulation time 344443697 ps
CPU time 6.67 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 214240 kb
Host smart-a1b9d4ce-d0dc-4481-b008-4576e763ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26425532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.26425532
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.451312317
Short name T648
Test name
Test status
Simulation time 80987628 ps
CPU time 3.53 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 206760 kb
Host smart-6e0e4252-c53f-49de-8282-7e994617dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451312317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.451312317
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3710123898
Short name T741
Test name
Test status
Simulation time 281273439 ps
CPU time 3.55 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 208712 kb
Host smart-4daf9832-f025-4598-be4c-2fc0b1989b1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710123898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3710123898
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3832323806
Short name T329
Test name
Test status
Simulation time 322302674 ps
CPU time 8.54 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 208840 kb
Host smart-d262b9e6-e30c-4f7d-ba55-fefc244da9e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832323806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3832323806
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.368099384
Short name T244
Test name
Test status
Simulation time 238996730 ps
CPU time 3.2 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:27 PM PDT 24
Peak memory 206772 kb
Host smart-ab5cef95-22cb-4dce-bf2a-906deae9a86e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368099384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.368099384
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.597070371
Short name T852
Test name
Test status
Simulation time 89168562 ps
CPU time 3.64 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 207936 kb
Host smart-68f45218-9550-42d4-ba33-cc0698b3833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597070371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.597070371
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3290720837
Short name T684
Test name
Test status
Simulation time 262475353 ps
CPU time 2.5 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 206708 kb
Host smart-b650f6a2-9cf5-4610-a6b3-cf8d998eb584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290720837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3290720837
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2845298806
Short name T173
Test name
Test status
Simulation time 311942618 ps
CPU time 12.55 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:43 PM PDT 24
Peak memory 222696 kb
Host smart-8ace8a11-236d-4939-8753-23552bf958b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845298806 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2845298806
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1749134657
Short name T485
Test name
Test status
Simulation time 455947343 ps
CPU time 8.84 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 214216 kb
Host smart-0dedc9e1-116b-48eb-9ddb-e1833dcc9192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749134657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1749134657
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4276033309
Short name T199
Test name
Test status
Simulation time 91753525 ps
CPU time 3.27 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:30 PM PDT 24
Peak memory 210608 kb
Host smart-819ca2ed-d493-44bc-9e21-265c3f1ec6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276033309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4276033309
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.675917238
Short name T465
Test name
Test status
Simulation time 12843212 ps
CPU time 0.9 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 206080 kb
Host smart-94485206-b00d-41f5-800c-c3e242f74418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675917238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.675917238
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.926384341
Short name T221
Test name
Test status
Simulation time 90381843 ps
CPU time 3.73 seconds
Started Jun 25 05:25:30 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 208976 kb
Host smart-f77e86ff-db41-4b9f-ab9d-52a67bfa7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926384341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.926384341
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.4119249305
Short name T680
Test name
Test status
Simulation time 973723321 ps
CPU time 10.34 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:41 PM PDT 24
Peak memory 214332 kb
Host smart-9abce6d6-0caa-4f55-a8b0-f59adc548e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119249305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4119249305
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1852825237
Short name T823
Test name
Test status
Simulation time 195580273 ps
CPU time 4.96 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 214328 kb
Host smart-107d8bfa-4e5f-4664-85a2-c84b1d352b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852825237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1852825237
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1821960662
Short name T233
Test name
Test status
Simulation time 218944537 ps
CPU time 2.95 seconds
Started Jun 25 05:25:29 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 214276 kb
Host smart-41492ab9-2e76-49c2-a8f4-0cb2098bcb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821960662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1821960662
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.609234072
Short name T80
Test name
Test status
Simulation time 46222120 ps
CPU time 2.08 seconds
Started Jun 25 05:25:29 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 220084 kb
Host smart-b586c4d6-821c-479a-9a20-5b39d24a2e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609234072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.609234072
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2816114233
Short name T560
Test name
Test status
Simulation time 96283262 ps
CPU time 2.52 seconds
Started Jun 25 05:25:25 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 207872 kb
Host smart-11582b77-47b7-4540-90fb-91acb652b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816114233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2816114233
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1796896515
Short name T671
Test name
Test status
Simulation time 224592555 ps
CPU time 3.14 seconds
Started Jun 25 05:25:22 PM PDT 24
Finished Jun 25 05:25:28 PM PDT 24
Peak memory 206744 kb
Host smart-818ceea2-35f6-41da-a344-9e930c516938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796896515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1796896515
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2682515892
Short name T564
Test name
Test status
Simulation time 1608969462 ps
CPU time 21.13 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:46 PM PDT 24
Peak memory 207796 kb
Host smart-e70788d8-5cd4-4879-b2e3-350f4ef15972
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682515892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2682515892
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2960895988
Short name T457
Test name
Test status
Simulation time 187323685 ps
CPU time 2.91 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 206936 kb
Host smart-09f0db73-5cf0-4d89-b392-a70d268dc3e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960895988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2960895988
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1481894972
Short name T767
Test name
Test status
Simulation time 371051739 ps
CPU time 5.48 seconds
Started Jun 25 05:25:24 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 206936 kb
Host smart-7751c061-0240-489c-b09d-5dad74af1b5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481894972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1481894972
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2421750470
Short name T790
Test name
Test status
Simulation time 222821662 ps
CPU time 1.79 seconds
Started Jun 25 05:25:38 PM PDT 24
Finished Jun 25 05:25:41 PM PDT 24
Peak memory 207232 kb
Host smart-549fd0e0-ecae-4fd9-a986-03449606074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421750470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2421750470
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.579959824
Short name T900
Test name
Test status
Simulation time 296572050 ps
CPU time 2.76 seconds
Started Jun 25 05:25:23 PM PDT 24
Finished Jun 25 05:25:29 PM PDT 24
Peak memory 208188 kb
Host smart-b0a8cea2-7daf-46aa-b65e-725328018c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579959824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.579959824
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3867033769
Short name T770
Test name
Test status
Simulation time 132669890 ps
CPU time 2.6 seconds
Started Jun 25 05:25:48 PM PDT 24
Finished Jun 25 05:25:52 PM PDT 24
Peak memory 219764 kb
Host smart-6a04daad-4baf-4428-8606-45278fed16fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867033769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3867033769
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2074228916
Short name T763
Test name
Test status
Simulation time 1608206870 ps
CPU time 4.84 seconds
Started Jun 25 05:25:26 PM PDT 24
Finished Jun 25 05:25:34 PM PDT 24
Peak memory 208124 kb
Host smart-3d8a0af4-30e9-433a-bf81-b2f17a80c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074228916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2074228916
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2582541931
Short name T912
Test name
Test status
Simulation time 63829217 ps
CPU time 2.55 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 210140 kb
Host smart-da193b52-36bf-4b81-9b88-7a36a11e3574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582541931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2582541931
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2754719011
Short name T692
Test name
Test status
Simulation time 45306332 ps
CPU time 0.92 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:27 PM PDT 24
Peak memory 205896 kb
Host smart-85800bd1-569a-4b34-8b3c-73e6b030dc16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754719011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2754719011
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3875613753
Short name T413
Test name
Test status
Simulation time 571762111 ps
CPU time 30.46 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:24:00 PM PDT 24
Peak memory 215608 kb
Host smart-e1e02ea9-89ad-4ae8-9b48-bd4e663e2ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875613753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3875613753
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1186085108
Short name T251
Test name
Test status
Simulation time 259525371 ps
CPU time 5.07 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 210000 kb
Host smart-02f174c3-27fe-4fb8-82ec-e1b561a5a004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186085108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1186085108
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1281829563
Short name T478
Test name
Test status
Simulation time 78742257 ps
CPU time 1.7 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:26 PM PDT 24
Peak memory 214316 kb
Host smart-06ad2297-1bab-434b-99b0-329af5c67538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281829563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1281829563
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.285425118
Short name T812
Test name
Test status
Simulation time 1868887952 ps
CPU time 26.5 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:51 PM PDT 24
Peak memory 222408 kb
Host smart-50b668da-dae7-4420-a387-d92181d5eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285425118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.285425118
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_sideload.490640031
Short name T507
Test name
Test status
Simulation time 132402667 ps
CPU time 3.92 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 208392 kb
Host smart-352f3bdc-f31d-4b44-9968-fdff49ab81da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490640031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.490640031
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2167302066
Short name T534
Test name
Test status
Simulation time 70693169 ps
CPU time 1.83 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:26 PM PDT 24
Peak memory 207332 kb
Host smart-2443ead0-b752-4801-bc3e-2c321bff70b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167302066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2167302066
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3927287761
Short name T519
Test name
Test status
Simulation time 1088864630 ps
CPU time 5.4 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 208532 kb
Host smart-a87565c7-936d-4739-ba68-6cd3484c32ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927287761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3927287761
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1488013374
Short name T709
Test name
Test status
Simulation time 59382153 ps
CPU time 2.34 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 206836 kb
Host smart-17c16baf-4c62-4b60-bf02-d7e6857698b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488013374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1488013374
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3814600555
Short name T492
Test name
Test status
Simulation time 437267437 ps
CPU time 3.33 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 208548 kb
Host smart-11fdd6ad-f213-4779-b5bc-6e92e2fa3ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814600555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3814600555
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1994567889
Short name T186
Test name
Test status
Simulation time 32662243 ps
CPU time 1.97 seconds
Started Jun 25 05:23:21 PM PDT 24
Finished Jun 25 05:23:25 PM PDT 24
Peak memory 206672 kb
Host smart-ef66be73-b72b-4c11-9327-5734244e3a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994567889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1994567889
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.767710634
Short name T730
Test name
Test status
Simulation time 75384331 ps
CPU time 3.38 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 209192 kb
Host smart-d584320b-96f2-441d-ae5f-aa4c89566e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767710634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.767710634
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1954432572
Short name T56
Test name
Test status
Simulation time 92474291 ps
CPU time 2.28 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 210016 kb
Host smart-228a7a1e-0cb0-44a9-972e-4eaae3c5fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954432572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1954432572
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2810066499
Short name T810
Test name
Test status
Simulation time 15867814 ps
CPU time 0.92 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 205892 kb
Host smart-35c06afb-dee8-41c0-89e3-8b87b92ad5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810066499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2810066499
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.660295436
Short name T842
Test name
Test status
Simulation time 114633713 ps
CPU time 3.46 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 222876 kb
Host smart-83498edd-04e1-46c1-9117-3921336e206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660295436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.660295436
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1673293570
Short name T247
Test name
Test status
Simulation time 87753589 ps
CPU time 3.06 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 214192 kb
Host smart-b8154fba-b897-449b-99ac-ad400cabc1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673293570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1673293570
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4120048875
Short name T706
Test name
Test status
Simulation time 68001677 ps
CPU time 2.5 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:26 PM PDT 24
Peak memory 214324 kb
Host smart-fb57573f-c529-45eb-936d-4daad1906b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120048875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4120048875
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2382207673
Short name T381
Test name
Test status
Simulation time 98409627 ps
CPU time 2.99 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 220948 kb
Host smart-55cefe2f-bee4-4b1d-a841-a3e6e555871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382207673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2382207673
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2046304336
Short name T63
Test name
Test status
Simulation time 427181323 ps
CPU time 3.7 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 220108 kb
Host smart-e7e0ef8a-48c3-4571-b585-e27035272e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046304336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2046304336
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4137509860
Short name T827
Test name
Test status
Simulation time 973293338 ps
CPU time 10.07 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:40 PM PDT 24
Peak memory 208680 kb
Host smart-67a4a9d8-825b-46bb-9721-c00666d0ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137509860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4137509860
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1984284819
Short name T310
Test name
Test status
Simulation time 266285744 ps
CPU time 2.85 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 206776 kb
Host smart-ed424a4d-c738-418e-bd6a-e876ec6aa472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984284819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1984284819
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.770298344
Short name T761
Test name
Test status
Simulation time 494715573 ps
CPU time 5.3 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 208432 kb
Host smart-15711501-c3ca-489a-bca5-e5b88dfd7aca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770298344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.770298344
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1126493290
Short name T868
Test name
Test status
Simulation time 481430013 ps
CPU time 12.75 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:40 PM PDT 24
Peak memory 208352 kb
Host smart-405fbe83-293b-4ceb-bf10-878fca29935f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126493290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1126493290
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2386432989
Short name T694
Test name
Test status
Simulation time 47581225 ps
CPU time 2.71 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 206732 kb
Host smart-908e778e-db79-4dab-b7a4-797aff38dcf0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386432989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2386432989
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.543367270
Short name T518
Test name
Test status
Simulation time 228934968 ps
CPU time 3.8 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 214236 kb
Host smart-ca3336ab-13ed-4738-b15a-ff0f9b164631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543367270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.543367270
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1799123926
Short name T638
Test name
Test status
Simulation time 198117632 ps
CPU time 2.4 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 206832 kb
Host smart-ad0973e9-a2a8-44a5-861e-717fbcd17064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799123926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1799123926
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.144600940
Short name T120
Test name
Test status
Simulation time 1305866984 ps
CPU time 9.84 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 219420 kb
Host smart-7a01ae04-f133-42c7-892f-e251535be3f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144600940 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.144600940
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3993435745
Short name T239
Test name
Test status
Simulation time 244230939 ps
CPU time 4.26 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:34 PM PDT 24
Peak memory 218496 kb
Host smart-2cad2c52-4ca1-465e-aebd-ba815ce08a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993435745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3993435745
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3661609769
Short name T197
Test name
Test status
Simulation time 57494115 ps
CPU time 2.53 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 209808 kb
Host smart-f995e7c9-42a5-4612-9f26-eef34d4872d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661609769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3661609769
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1999404889
Short name T505
Test name
Test status
Simulation time 53671793 ps
CPU time 0.72 seconds
Started Jun 25 05:23:32 PM PDT 24
Finished Jun 25 05:23:34 PM PDT 24
Peak memory 206004 kb
Host smart-35f352a9-8195-4fe7-a1da-c81d7bd517e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999404889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1999404889
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.552995999
Short name T182
Test name
Test status
Simulation time 33862160 ps
CPU time 2.19 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 214324 kb
Host smart-d18e1240-c2cb-418f-8486-42fe983d4da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552995999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.552995999
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2395185875
Short name T617
Test name
Test status
Simulation time 136301881 ps
CPU time 2 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:30 PM PDT 24
Peak memory 207552 kb
Host smart-ac961ea3-658a-4fa8-82a3-016d5049af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395185875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2395185875
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1370670756
Short name T757
Test name
Test status
Simulation time 9738961129 ps
CPU time 54.58 seconds
Started Jun 25 05:23:25 PM PDT 24
Finished Jun 25 05:24:23 PM PDT 24
Peak memory 214284 kb
Host smart-a8ff391f-0417-4b88-8047-45c64c4deb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370670756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1370670756
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.624345745
Short name T234
Test name
Test status
Simulation time 443117493 ps
CPU time 3.43 seconds
Started Jun 25 05:23:26 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 214264 kb
Host smart-f65d0491-ff21-4886-acee-552301ee7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624345745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.624345745
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2010177291
Short name T633
Test name
Test status
Simulation time 614378605 ps
CPU time 5.06 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 220248 kb
Host smart-b14b3857-f5ce-46d3-ab9d-cb28d0d98602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010177291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2010177291
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1819868122
Short name T499
Test name
Test status
Simulation time 195496335 ps
CPU time 4.65 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 218416 kb
Host smart-6e44f207-6b9a-4a7a-b844-da7854fe6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819868122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1819868122
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3364549779
Short name T634
Test name
Test status
Simulation time 304092103 ps
CPU time 3.39 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 206936 kb
Host smart-9d6c8ae5-f26e-426c-8fa3-e13b0336d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364549779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3364549779
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.422441856
Short name T676
Test name
Test status
Simulation time 206316024 ps
CPU time 5.79 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 208680 kb
Host smart-bda8d933-1109-4fd9-b07f-a9df8e2b0508
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422441856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.422441856
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1400498053
Short name T356
Test name
Test status
Simulation time 36105349 ps
CPU time 2.33 seconds
Started Jun 25 05:23:23 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 206956 kb
Host smart-20b229c1-3fd4-4c7b-aaf3-3f871f1450d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400498053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1400498053
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.198477840
Short name T819
Test name
Test status
Simulation time 228825361 ps
CPU time 7.76 seconds
Started Jun 25 05:23:27 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 207364 kb
Host smart-13adfc7a-38b5-44f1-a18e-fa01150d60bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198477840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.198477840
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4229653895
Short name T746
Test name
Test status
Simulation time 67897557 ps
CPU time 2.44 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:39 PM PDT 24
Peak memory 207340 kb
Host smart-f71c969c-f85b-4d36-aad4-7f236a567897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229653895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4229653895
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1047006770
Short name T666
Test name
Test status
Simulation time 79135764 ps
CPU time 2.64 seconds
Started Jun 25 05:23:24 PM PDT 24
Finished Jun 25 05:23:31 PM PDT 24
Peak memory 208172 kb
Host smart-ced19685-f016-448e-aaa5-222c68d60606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047006770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1047006770
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2601667173
Short name T881
Test name
Test status
Simulation time 7616012300 ps
CPU time 18.79 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 222540 kb
Host smart-a8bcff86-2207-41c1-8329-df3bb9e6174c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601667173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2601667173
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.261265580
Short name T398
Test name
Test status
Simulation time 385852327 ps
CPU time 4.56 seconds
Started Jun 25 05:23:22 PM PDT 24
Finished Jun 25 05:23:29 PM PDT 24
Peak memory 214552 kb
Host smart-19041dda-20f3-4799-8b90-25ec61ffbcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261265580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.261265580
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1351873873
Short name T389
Test name
Test status
Simulation time 1746639499 ps
CPU time 3.43 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:40 PM PDT 24
Peak memory 210008 kb
Host smart-3d3c509a-4fb0-4aa1-9d89-41a5b188d195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351873873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1351873873
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.284445967
Short name T487
Test name
Test status
Simulation time 34055257 ps
CPU time 0.83 seconds
Started Jun 25 05:23:40 PM PDT 24
Finished Jun 25 05:23:43 PM PDT 24
Peak memory 206048 kb
Host smart-2ef6cb3f-5e0b-47ff-9137-8efe58933ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284445967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.284445967
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3362026948
Short name T665
Test name
Test status
Simulation time 131389206 ps
CPU time 3.17 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 221580 kb
Host smart-14ce7eac-5f4b-4422-a082-6a4055bd5ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362026948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3362026948
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1927590302
Short name T845
Test name
Test status
Simulation time 43024880 ps
CPU time 2.25 seconds
Started Jun 25 05:23:37 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 209056 kb
Host smart-b272a110-6bd5-4908-b22a-488b0bb54397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927590302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1927590302
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2405605686
Short name T384
Test name
Test status
Simulation time 235839787 ps
CPU time 3.63 seconds
Started Jun 25 05:23:42 PM PDT 24
Finished Jun 25 05:23:47 PM PDT 24
Peak memory 209860 kb
Host smart-fbd89782-1d3a-4619-9f5e-aa5010f320cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405605686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2405605686
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2345701433
Short name T343
Test name
Test status
Simulation time 463377530 ps
CPU time 3.5 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 214488 kb
Host smart-c46943d9-26bf-4a2e-9e69-4a99bbacb888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345701433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2345701433
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1633345605
Short name T59
Test name
Test status
Simulation time 52809848 ps
CPU time 2.63 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:23:37 PM PDT 24
Peak memory 219760 kb
Host smart-a9b2f61b-f168-4d20-b691-566c525b3b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633345605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1633345605
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3185266403
Short name T544
Test name
Test status
Simulation time 57101427 ps
CPU time 3.44 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 207460 kb
Host smart-a29d84ec-3b60-4160-8c53-9d7affaae7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185266403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3185266403
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3603421940
Short name T906
Test name
Test status
Simulation time 418115889 ps
CPU time 2.64 seconds
Started Jun 25 05:23:41 PM PDT 24
Finished Jun 25 05:23:46 PM PDT 24
Peak memory 207152 kb
Host smart-a0b6bc25-7bb7-4c31-ae45-8f39603d83dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603421940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3603421940
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.676927253
Short name T849
Test name
Test status
Simulation time 507930522 ps
CPU time 13.34 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:49 PM PDT 24
Peak memory 208604 kb
Host smart-20634c19-d347-46a5-acf6-ccd6b4086a78
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676927253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.676927253
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1167882795
Short name T775
Test name
Test status
Simulation time 99730544 ps
CPU time 3.57 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 206800 kb
Host smart-12f8ff04-38da-409f-84ca-067f50c512c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167882795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1167882795
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2139506838
Short name T722
Test name
Test status
Simulation time 692526882 ps
CPU time 5.42 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:23:40 PM PDT 24
Peak memory 208720 kb
Host smart-1c5881c4-c965-4698-adad-b2d03d121cc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139506838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2139506838
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2698812178
Short name T347
Test name
Test status
Simulation time 2216985184 ps
CPU time 22.93 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:24:01 PM PDT 24
Peak memory 214340 kb
Host smart-8eb7a821-4b02-4890-9171-028a7fa5fb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698812178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2698812178
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.351008296
Short name T524
Test name
Test status
Simulation time 1756936700 ps
CPU time 12.14 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:51 PM PDT 24
Peak memory 207880 kb
Host smart-afb33428-c945-4ce0-9576-f6fb7a922af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351008296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.351008296
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3576975928
Short name T76
Test name
Test status
Simulation time 629404657 ps
CPU time 29.26 seconds
Started Jun 25 05:23:37 PM PDT 24
Finished Jun 25 05:24:09 PM PDT 24
Peak memory 221736 kb
Host smart-56cb1ea9-f974-42e3-9b8e-19bb82a40929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576975928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3576975928
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.794518900
Short name T360
Test name
Test status
Simulation time 285698075 ps
CPU time 17.94 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 222584 kb
Host smart-be05d20f-934e-407b-9cee-4917ccd14ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794518900 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.794518900
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.556485496
Short name T705
Test name
Test status
Simulation time 42685679 ps
CPU time 3.27 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 214232 kb
Host smart-76e4def4-3b19-4503-8f41-3d91c8942687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556485496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.556485496
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.542936448
Short name T387
Test name
Test status
Simulation time 72519398 ps
CPU time 2.86 seconds
Started Jun 25 05:23:33 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 210436 kb
Host smart-f019da46-8c87-4487-87e6-40d8cbc23ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542936448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.542936448
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2234856997
Short name T101
Test name
Test status
Simulation time 29775176 ps
CPU time 0.71 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 206052 kb
Host smart-67f86aed-0f47-439b-b30b-7c9c54fcb6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234856997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2234856997
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3445533630
Short name T382
Test name
Test status
Simulation time 48048409 ps
CPU time 3.52 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:39 PM PDT 24
Peak memory 214308 kb
Host smart-1a07c797-6ea4-4744-9084-50f72ffa12bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445533630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3445533630
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4007365868
Short name T304
Test name
Test status
Simulation time 57113116 ps
CPU time 2.19 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 221632 kb
Host smart-97955c5b-7cf7-4607-8767-408f74826788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007365868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4007365868
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4095023001
Short name T69
Test name
Test status
Simulation time 32684424 ps
CPU time 2.18 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 209860 kb
Host smart-1721da6e-9476-436e-9794-8ce1842fab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095023001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4095023001
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1689431682
Short name T299
Test name
Test status
Simulation time 97832802 ps
CPU time 3.91 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 215428 kb
Host smart-bfab84ad-d29a-482b-99a5-cc55d8a44c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689431682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1689431682
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2204315848
Short name T282
Test name
Test status
Simulation time 542637145 ps
CPU time 3.54 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 214344 kb
Host smart-9cf2823c-64c8-48ae-9879-4cb1cdedce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204315848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2204315848
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1608321017
Short name T859
Test name
Test status
Simulation time 116708977 ps
CPU time 2.48 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:39 PM PDT 24
Peak memory 209844 kb
Host smart-f84820b7-e88e-42e9-abca-81636a077e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608321017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1608321017
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2219681361
Short name T245
Test name
Test status
Simulation time 4763157797 ps
CPU time 44.3 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:24:21 PM PDT 24
Peak memory 208688 kb
Host smart-2a8f7fd8-94cf-4247-bb0e-9edf4bcd2450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219681361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2219681361
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2420933088
Short name T313
Test name
Test status
Simulation time 86590857 ps
CPU time 3.93 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 208596 kb
Host smart-68168960-3a5a-4950-ba15-ab54d04c134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420933088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2420933088
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3458583968
Short name T713
Test name
Test status
Simulation time 2112618943 ps
CPU time 8.85 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:46 PM PDT 24
Peak memory 208132 kb
Host smart-cd2c1de1-a919-4865-b008-eb02e76fbc8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458583968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3458583968
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.95064654
Short name T443
Test name
Test status
Simulation time 299785562 ps
CPU time 3.67 seconds
Started Jun 25 05:23:36 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 206920 kb
Host smart-a4bf20a5-96f3-4e75-a72a-cd37bba1c246
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95064654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.95064654
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.670987402
Short name T716
Test name
Test status
Simulation time 32980157 ps
CPU time 2.26 seconds
Started Jun 25 05:23:32 PM PDT 24
Finished Jun 25 05:23:36 PM PDT 24
Peak memory 206820 kb
Host smart-dd7a1570-3c96-4bd4-8bdb-907eec6e75f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670987402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.670987402
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2204965215
Short name T576
Test name
Test status
Simulation time 42425508 ps
CPU time 2.01 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 207268 kb
Host smart-053ace64-5e1e-48df-9796-f1f5b12847e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204965215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2204965215
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2181483253
Short name T446
Test name
Test status
Simulation time 69520886 ps
CPU time 2.31 seconds
Started Jun 25 05:23:34 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 206840 kb
Host smart-a7d8dc4e-03fd-4a5d-8b86-6731e7ba5c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181483253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2181483253
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.284570856
Short name T417
Test name
Test status
Simulation time 117782285 ps
CPU time 5.07 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:42 PM PDT 24
Peak memory 218580 kb
Host smart-67e96f0b-56ee-426a-bfe7-7bf3d90b8ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284570856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.284570856
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4142406285
Short name T17
Test name
Test status
Simulation time 879969726 ps
CPU time 4.17 seconds
Started Jun 25 05:23:35 PM PDT 24
Finished Jun 25 05:23:41 PM PDT 24
Peak memory 210904 kb
Host smart-e41a2de4-b116-473c-aba1-bad8ede436a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142406285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4142406285
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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