Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
1 |
4 |
80.00 |
Automatically Generated Bins for op_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OpDisable] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
50 |
1 |
|
|
T1 |
1 |
|
T18 |
1 |
|
T49 |
1 |
auto[OpGenId] |
9 |
1 |
|
|
T150 |
1 |
|
T54 |
1 |
|
T215 |
1 |
auto[OpGenSwOut] |
16 |
1 |
|
|
T78 |
1 |
|
T216 |
1 |
|
T62 |
1 |
auto[OpGenHwOut] |
24 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T9 |
1 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
1700 |
1 |
|
|
T27 |
3 |
|
T107 |
1 |
|
T7 |
2 |
auto[StInit] |
97 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T37 |
1 |
auto[StCreatorRootKey] |
53 |
1 |
|
|
T18 |
1 |
|
T57 |
1 |
|
T50 |
1 |
auto[StOwnerIntKey] |
51 |
1 |
|
|
T42 |
1 |
|
T60 |
1 |
|
T61 |
1 |
auto[StOwnerKey] |
32 |
1 |
|
|
T43 |
1 |
|
T65 |
1 |
|
T67 |
1 |
auto[StDisabled] |
451 |
1 |
|
|
T27 |
3 |
|
T107 |
1 |
|
T7 |
9 |
auto[StInvalid] |
50 |
1 |
|
|
T19 |
1 |
|
T52 |
1 |
|
T137 |
1 |
Summary for Variable wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wip_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3424 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
99 |
1 |
|
|
T1 |
1 |
|
T18 |
1 |
|
T7 |
1 |
Summary for Cross state_x_wip_cross
Samples crossed: state_cp wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
14 |
1 |
13 |
92.86 |
1 |
Automatically Generated Cross Bins for state_x_wip_cross
Uncovered bins
state_cp | wip_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
state_cp | wip_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[0] |
1694 |
1 |
|
|
T27 |
3 |
|
T107 |
1 |
|
T7 |
2 |
auto[StReset] |
auto[1] |
6 |
1 |
|
|
T53 |
1 |
|
T8 |
1 |
|
T54 |
1 |
auto[StInit] |
auto[0] |
47 |
1 |
|
|
T4 |
1 |
|
T37 |
1 |
|
T78 |
1 |
auto[StInit] |
auto[1] |
50 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T49 |
1 |
auto[StCreatorRootKey] |
auto[0] |
33 |
1 |
|
|
T57 |
1 |
|
T77 |
1 |
|
T58 |
1 |
auto[StCreatorRootKey] |
auto[1] |
20 |
1 |
|
|
T18 |
1 |
|
T50 |
1 |
|
T216 |
1 |
auto[StOwnerIntKey] |
auto[0] |
42 |
1 |
|
|
T42 |
1 |
|
T60 |
1 |
|
T61 |
1 |
auto[StOwnerIntKey] |
auto[1] |
9 |
1 |
|
|
T28 |
1 |
|
T72 |
1 |
|
T217 |
1 |
auto[StOwnerKey] |
auto[0] |
26 |
1 |
|
|
T43 |
1 |
|
T65 |
1 |
|
T67 |
1 |
auto[StOwnerKey] |
auto[1] |
6 |
1 |
|
|
T69 |
1 |
|
T70 |
1 |
|
T198 |
1 |
auto[StDisabled] |
auto[0] |
443 |
1 |
|
|
T27 |
3 |
|
T107 |
1 |
|
T7 |
9 |
auto[StDisabled] |
auto[1] |
8 |
1 |
|
|
T74 |
1 |
|
T54 |
1 |
|
T218 |
1 |
auto[StInvalid] |
auto[0] |
50 |
1 |
|
|
T19 |
1 |
|
T52 |
1 |
|
T137 |
1 |
Summary for Cross state_x_op_cross
Samples crossed: state_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
16 |
19 |
54.29 |
16 |
Automatically Generated Cross Bins for state_x_op_cross
Element holes
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
* |
-- |
-- |
5 |
|
Uncovered bins
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StReset]] |
[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
4 |
|
[auto[StInit] , auto[StCreatorRootKey]] |
[auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StOwnerIntKey]] |
[auto[OpGenId]] |
0 |
1 |
1 |
|
[auto[StOwnerIntKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerKey]] |
[auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StDisabled]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
Covered bins
state_cp | op_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[OpAdvance] |
6 |
1 |
|
|
T53 |
1 |
|
T8 |
1 |
|
T54 |
1 |
auto[StInit] |
auto[OpAdvance] |
27 |
1 |
|
|
T1 |
1 |
|
T49 |
1 |
|
T56 |
1 |
auto[StInit] |
auto[OpGenId] |
3 |
1 |
|
|
T150 |
1 |
|
T219 |
1 |
|
T220 |
1 |
auto[StInit] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T78 |
1 |
|
T221 |
1 |
|
T222 |
1 |
auto[StInit] |
auto[OpGenHwOut] |
14 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T223 |
1 |
auto[StCreatorRootKey] |
auto[OpAdvance] |
7 |
1 |
|
|
T18 |
1 |
|
T50 |
1 |
|
T224 |
1 |
auto[StCreatorRootKey] |
auto[OpGenId] |
3 |
1 |
|
|
T215 |
1 |
|
T225 |
1 |
|
T226 |
1 |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T216 |
1 |
|
T62 |
1 |
|
T29 |
1 |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
4 |
1 |
|
|
T9 |
1 |
|
T227 |
1 |
|
T228 |
1 |
auto[StOwnerIntKey] |
auto[OpAdvance] |
3 |
1 |
|
|
T217 |
1 |
|
T30 |
1 |
|
T222 |
1 |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T69 |
1 |
|
T229 |
1 |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
4 |
1 |
|
|
T28 |
1 |
|
T72 |
1 |
|
T230 |
1 |
auto[StOwnerKey] |
auto[OpAdvance] |
3 |
1 |
|
|
T69 |
1 |
|
T231 |
1 |
|
T232 |
1 |
auto[StOwnerKey] |
auto[OpGenId] |
2 |
1 |
|
|
T70 |
1 |
|
T233 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T198 |
1 |
|
- |
- |
|
- |
- |
auto[StDisabled] |
auto[OpAdvance] |
4 |
1 |
|
|
T74 |
1 |
|
T218 |
1 |
|
T234 |
1 |
auto[StDisabled] |
auto[OpGenId] |
1 |
1 |
|
|
T54 |
1 |
|
- |
- |
|
- |
- |
auto[StDisabled] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T232 |
1 |
|
- |
- |
|
- |
- |
auto[StDisabled] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T235 |
1 |
|
T236 |
1 |
|
- |
- |