Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4777

1

T1

2

T2

9

T3

8

auto[1]

522

1

T44

6

T47

4

T26

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4777

1

T1

2

T2

9

T3

8

auto[1]

522

1

T44

6

T47

4

T26

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4738

1

T1

2

T2

4

T3

8

auto[1]

561

1

T2

5

T5

1

T45

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4738

1

T1

2

T2

4

T3

8

auto[1]

561

1

T2

5

T5

1

T45

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	379	1			T1	1		T16	1		T17	4
auto[OpGenId]	1146	1			T16	1		T17	2		T18	1
auto[OpGenSwOut]	1113	1			T1	1		T16	2		T5	1
auto[OpGenHwOut]	2587	1			T2	9		T3	8		T16	3
auto[OpDisable]	74	1			T55	1		T59	1		T78	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	379	1			T1	1		T16	1		T17	4
auto[OpGenId]	1146	1			T16	1		T17	2		T18	1
auto[OpGenSwOut]	1113	1			T1	1		T16	2		T5	1
auto[OpGenHwOut]	2587	1			T2	9		T3	8		T16	3
auto[OpDisable]	74	1			T55	1		T59	1		T78	4

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4803

1

T1

2

T2

9

T3

5

auto[1]

496

1

T3

3

T45

1

T46

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4803

1

T1

2

T2

9

T3

5

auto[1]

496

1

T3

3

T45

1

T46

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5088

1

T1

2

T2

9

T3

8

auto[1]

211

1

T17

5

T119

9

T151

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1769	1			T1	2		T2	3		T3	3
auto[1]	724	1			T2	1		T17	3		T18	1
auto[2]	666	1			T2	1		T3	1		T16	1
auto[3]	721	1			T2	3		T3	2		T16	1
auto[4]	367	1			T2	1		T16	1		T17	1
auto[5]	344	1			T16	1		T51	1		T137	1
auto[6]	344	1			T3	1		T16	1		T17	5
auto[7]	364	1			T3	1		T17	1		T51	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1419	1			T2	1		T3	2		T16	3
clear_one[1]	724	1			T2	1		T17	3		T18	1
clear_one[2]	666	1			T2	1		T3	1		T16	1
clear_one[3]	721	1			T2	3		T3	2		T16	1
clear_none	1769	1			T1	2		T2	3		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1038	1			T1	1		T2	1		T16	2
auto[StInit]	603	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	580	1			T2	1		T3	1		T5	1
auto[StOwnerIntKey]	500	1			T2	1		T3	1		T44	1
auto[StOwnerKey]	464	1			T2	1		T3	1		T17	1
auto[StDisabled]	1845	1			T2	4		T3	4		T17	7
auto[StInvalid]	269	1			T16	5		T19	4		T51	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1038	1			T1	1		T2	1		T16	2
auto[StInit]	603	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	580	1			T2	1		T3	1		T5	1
auto[StOwnerIntKey]	500	1			T2	1		T3	1		T44	1
auto[StOwnerKey]	464	1			T2	1		T3	1		T17	1
auto[StDisabled]	1845	1			T2	4		T3	4		T17	7
auto[StInvalid]	269	1			T16	5		T19	4		T51	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2] - auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T138	1		T237	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T19	1		T57	1		T23	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	170	1			T1	1		T17	1		T18	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	253	1			T2	1		T16	1		T19	1
auto[0]	auto[StInit]	auto[OpAdvance]	35	1			T1	1		T23	1		T7	1
auto[0]	auto[StInit]	auto[OpGenId]	90	1			T7	1		T89	1		T56	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	76	1			T110	1		T59	1		T78	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	164	1			T3	1		T44	1		T199	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	26	1			T27	1		T138	1		T8	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	63	1			T23	1		T201	1		T7	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	55	1			T5	1		T45	1		T27	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	72	1			T2	1		T3	1		T27	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T78	1		T206	1		T141	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T204	1		T238	1		T239	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T138	2		T9	1		T92	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	56	1			T2	1		T44	1		T45	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T240	1		T218	1		T241	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T213	1		T138	1		T80	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T88	1		T134	1		T92	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T200	1		T7	1		T20	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T107	1		T207	1		T151	1
auto[0]	auto[StDisabled]	auto[OpGenId]	62	1			T46	1		T88	1		T89	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T17	1		T7	1		T77	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T3	1		T44	1		T199	2
auto[0]	auto[StDisabled]	auto[OpDisable]	27	1			T55	1		T78	2		T79	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T16	1		T87	1		T242	1
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T19	1		T52	1		T112	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T38	1		T39	1		T243	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T51	1		T137	1		T96	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T18	1		T7	1		T78	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	20	1			T8	1		T244	1		T245	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T26	1		T246	1		T78	2
auto[1]	auto[StInit]	auto[OpAdvance]	5	1			T247	1		T54	1		T33	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T78	1		T74	1		T244	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T248	2		T249	1		T250	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T212	1		T251	1		T252	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T17	2		T247	1		T140	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T7	2		T74	1		T80	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T8	1		T216	1		T128	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T135	1		T78	1		T253	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T131	1		T254	1		T255	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T80	2		T130	1		T34	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T256	1		T257	1		T54	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T199	1		T247	1		T258	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T259	1		T260	1		T261	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	10	1			T17	1		T74	1		T237	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T8	1		T93	1		T262	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T204	1		T199	1		T214	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T27	1		T119	3		T78	1
auto[1]	auto[StDisabled]	auto[OpGenId]	66	1			T7	2		T88	1		T89	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T27	1		T7	1		T208	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T2	1		T7	1		T263	2
auto[1]	auto[StDisabled]	auto[OpDisable]	4	1			T221	1		T264	1		T190	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	9	1			T87	1		T265	1		T266	2
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T19	1		T265	1		T267	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T96	1		T195	1		T268	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T39	1		T269	1		T97	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T270	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	17	1			T17	1		T38	1		T20	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T16	1		T269	1		T271	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	46	1			T272	1		T273	2		T274	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T144	1		T102	1		T198	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T275	1		T128	1		T102	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	4	1			T276	1		T221	1		T85	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	26	1			T200	1		T272	1		T273	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T57	1		T277	1		T278	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T279	1		T280	1		T54	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T77	1		T151	1		T131	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T47	1		T199	1		T212	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T246	1		T144	1		T281	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T74	1		T66	1		T9	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T7	1		T244	1		T75	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T3	1		T7	1		T214	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T140	1		T277	1		T69	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T282	1		T144	1		T136	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T276	1		T277	1		T130	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T44	1		T263	1		T283	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T284	1		T271	1		T80	1
auto[2]	auto[StDisabled]	auto[OpGenId]	54	1			T46	1		T78	1		T284	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T26	1		T213	1		T285	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T2	1		T44	1		T47	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T59	1		T197	1		T221	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T52	1		T106	1		T286	2
auto[2]	auto[StInvalid]	auto[OpGenId]	15	1			T287	1		T288	1		T289	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T38	1		T287	1		T265	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T39	1		T243	1		T105	1
auto[3]	auto[StReset]	auto[OpAdvance]	2	1			T290	1		T291	1		-	-
auto[3]	auto[StReset]	auto[OpGenId]	25	1			T57	1		T32	1		T271	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T144	1		T245	1		T257	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	53	1			T19	1		T283	1		T78	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T227	1		T292	1		T291	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T207	1		T144	1		T293	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T113	1		T294	2		T295	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T2	1		T47	1		T296	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T113	1		T229	1		T297	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T277	1		T84	2		T298	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T7	1		T299	1		T300	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T44	1		T7	1		T111	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T65	1		T245	1		T248	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T23	1		T301	1		T132	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T77	1		T8	1		T75	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T110	1		T263	1		T283	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T257	1		T302	1		T303	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T284	1		T8	1		T62	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T27	1		T78	2		T131	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T2	1		T47	1		T7	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	18	1			T304	1		T144	1		T305	1
auto[3]	auto[StDisabled]	auto[OpGenId]	56	1			T27	2		T7	1		T285	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T7	3		T77	1		T78	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T2	1		T3	2		T44	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T256	1		T306	1		T197	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T95	1		T307	1		T308	1
auto[3]	auto[StInvalid]	auto[OpGenId]	20	1			T19	1		T51	1		T52	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T137	1		T243	1		T309	2
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T16	1		T112	1		T96	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T136	1		T86	1		T229	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	6	1			T276	1		T84	1		T197	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	26	1			T57	1		T200	1		T53	2
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T17	1		T20	1		T310	1
auto[4]	auto[StInit]	auto[OpGenId]	1	1			T9	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	8	1			T304	2		T311	1		T312	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T313	1		T314	1		T315	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T316	1		T228	1		T292	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T244	1		T69	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T84	1		T318	1		T319	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T209	1		T258	1		T320	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T321	1		T322	1		T323	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T151	1		T284	1		T304	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T132	1		T324	1		T325	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T212	1		T326	1		T132	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T327	1		T305	2		T84	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	13	1			T77	1		T74	1		T251	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T80	1		T322	1		T328	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T253	1		T329	1		T304	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T20	1		T93	1		T142	2
auto[4]	auto[StDisabled]	auto[OpGenId]	31	1			T27	1		T209	1		T330	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T80	2		T128	1		T327	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T2	1		T47	1		T200	1
auto[4]	auto[StDisabled]	auto[OpDisable]	2	1			T331	1		T332	1		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T87	1		T333	1		T334	1
auto[4]	auto[StInvalid]	auto[OpGenId]	9	1			T137	1		T195	1		T309	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T335	1		T336	1		T337	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T16	1		T38	1		T338	1
auto[5]	auto[StReset]	auto[OpAdvance]	1	1			T339	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T331	1		T340	1		T341	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T331	1		T131	1		T54	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	30	1			T59	1		T326	1		T41	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T342	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T279	1		T343	1		T344	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T8	1		T345	1		T346	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T23	1		T92	1		T347	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T348	1		T54	1		T70	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T7	1		T349	1		T277	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T59	1		T347	1		T350	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T228	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T351	1		T249	1		T346	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T85	1		T352	1		T353	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T47	1		T78	1		T216	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T246	1		T354	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T89	1		T210	1		T228	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T356	1		T357	1		T358	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T273	1		T359	1		T360	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	6	1			T304	1		T340	1		T197	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T134	1		T78	1		T205	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T27	1		T107	1		T78	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T47	1		T199	1		T7	1
auto[5]	auto[StDisabled]	auto[OpDisable]	10	1			T78	2		T277	1		T256	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T242	1		T361	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T16	1		T243	1		T97	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T51	1		T96	1		T362	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T137	1		T105	1		T363	1
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T131	1		T309	1		T102	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T195	1		T364	1		T63	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T200	1		T20	1		T272	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T23	1		T189	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T57	1		T46	1		T365	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T133	1		T99	1		T366	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T18	1		T283	1		T367	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T368	1		T34	1		T156	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T369	1		T370	1		T317	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T78	1		T251	1		T327	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T274	1		T276	1		T371	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T93	1		T75	1		T372	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T84	1		T191	1		T233	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T27	1		T128	1		T343	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T200	1		T111	1		T135	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T75	1		T188	1		T373	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	2	1			T188	1		T374	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T216	1		T222	1		T188	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T3	1		T272	1		T66	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	9	1			T17	1		T280	1		T84	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T55	1		T78	2		T80	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T17	3		T8	1		T54	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T17	1		T44	1		T200	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T375	1		T352	1		T297	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T51	1		T265	1		T289	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T105	1		T309	1		T376	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T16	1		T19	1		T242	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T195	1		T377	1		T378	1
auto[7]	auto[StReset]	auto[OpGenId]	20	1			T113	1		T132	1		T364	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	14	1			T26	1		T23	1		T74	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	24	1			T283	2		T212	1		T272	2
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T77	1		T340	1		T317	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T228	1		T338	1		T99	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	10	1			T38	1		T7	1		T348	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T119	1		T246	1		T277	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T7	1		T62	1		T379	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T119	3		T246	1		T80	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T26	1		T200	1		T263	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T119	1		T282	1		T84	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T208	1		T80	1		T85	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T8	1		T140	1		T131	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	30	1			T213	1		T205	1		T113	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T380	1		T297	1		T379	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T7	1		T216	1		T324	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T301	1		T381	1		T382	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	6	1			T383	1		T384	1		T385	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T204	1		T246	1		T386	1
auto[7]	auto[StDisabled]	auto[OpGenId]	19	1			T216	1		T364	1		T387	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T46	1		T119	1		T207	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T3	1		T17	1		T272	1
auto[7]	auto[StDisabled]	auto[OpDisable]	8	1			T82	1		T136	1		T161	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T39	1		T265	1		T388	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T242	1		T389	1		T362	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T51	1		T307	1		T390	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T287	1		T333	1		T267	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1419

1

T2

1

T3

2

T16

3

clear_one[1]

auto[0]

auto[0]

auto[0]

430

1

T17

3

T18

1

T19

1

clear_one[1]

auto[0]

auto[0]

auto[1]

109

1

T214

2

T78

1

T212

3

clear_one[1]

auto[0]

auto[1]

auto[0]

134

1

T2

1

T204

1

T27

1

clear_one[1]

auto[0]

auto[1]

auto[1]

51

1

T7

2

T88

1

T207

1

clear_one[2]

auto[0]

auto[0]

auto[0]

402

1

T2

1

T16

1

T17

1

clear_one[2]

auto[0]

auto[0]

auto[1]

109

1

T3

1

T46

1

T214

3

clear_one[2]

auto[1]

auto[0]

auto[0]

123

1

T44

2

T47

2

T7

2

clear_one[2]

auto[1]

auto[0]

auto[1]

32

1

T247

1

T238

1

T277

1

clear_one[3]

auto[0]

auto[0]

auto[0]

438

1

T2

1

T3

2

T16

1

clear_one[3]

auto[0]

auto[1]

auto[0]

122

1

T2

2

T27

1

T199

1

clear_one[3]

auto[1]

auto[0]

auto[0]

131

1

T44

2

T47

2

T7

1

clear_one[3]

auto[1]

auto[1]

auto[0]

30

1

T26

1

T27

1

T23

1

clear_none

auto[0]

auto[0]

auto[0]

1287

1

T1

2

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

108

1

T3

2

T27

2

T7

1

clear_none

auto[0]

auto[1]

auto[0]

132

1

T2

2

T5

1

T45

1

clear_none

auto[0]

auto[1]

auto[1]

36

1

T45

1

T46

1

T205

1

clear_none

auto[1]

auto[0]

auto[0]

119

1

T44

2

T263

1

T78

1

clear_none

auto[1]

auto[0]

auto[1]

31

1

T138

3

T206

1

T8

1

clear_none

auto[1]

auto[1]

auto[0]

36

1

T23

1

T7

1

T20

2

clear_none

auto[1]

auto[1]

auto[1]

20

1

T7

1

T138

2

T365

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1343	1			T2	1		T3	2		T16	3
clear_all	auto[1]	76	1			T17	4		T119	5		T304	6
clear_one[1]	auto[0]	696	1			T2	1		T17	2		T18	1
clear_one[1]	auto[1]	28	1			T17	1		T119	4		T247	1
clear_one[2]	auto[0]	632	1			T2	1		T3	1		T16	1
clear_one[2]	auto[1]	34	1			T247	1		T370	1		T144	1
clear_one[3]	auto[0]	696	1			T2	3		T3	2		T16	1
clear_one[3]	auto[1]	25	1			T370	2		T248	7		T294	1
clear_none	auto[0]	1721	1			T1	2		T2	3		T3	3
clear_none	auto[1]	48	1			T151	3		T138	3		T140	5