Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10911

1

T1

2

T2

6

T3

5

auto[Attestation]

7723

1

T2

3

T3

3

T4

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2724	1			T4	2		T5	2		T6	2
auto[Aes]	3410	1			T4	2		T5	3		T6	1
auto[Kmac]	3419	1			T2	9		T4	1		T16	1
auto[Otbn]	3271	1			T1	1		T3	8		T4	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7661	1			T1	1		T2	8		T3	8
auto[OpGenId]	5810	1			T1	1		T4	3		T16	3
auto[OpGenSwOut]	5924	1			T1	1		T4	4		T16	2
auto[OpGenHwOut]	6900	1			T2	9		T3	8		T4	4
auto[OpDisable]	137	1			T45	1		T27	1		T7	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10578

1

T1

1

T2

8

T3

8

auto[OpDoneFail]

15854

1

T1

2

T2

9

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6496	1			T1	3		T2	2		T3	1
auto[StInit]	3648	1			T2	2		T3	2		T4	2
auto[StCreatorRootKey]	3184	1			T2	2		T3	2		T5	3
auto[StOwnerIntKey]	2695	1			T2	2		T3	2		T5	2
auto[StOwnerKey]	2490	1			T2	2		T3	2		T5	2
auto[StDisabled]	7919	1			T2	7		T3	7		T5	6

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	317	1			T4	1		T18	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T5	1		T18	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	90	1			T26	1		T27	1		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	78	1			T204	1		T119	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T17	1		T26	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	246	1			T17	1		T91	1		T204	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	300	1			T17	1		T19	5		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	91	1			T201	1		T78	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	71	1			T77	1		T119	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	63	1			T27	1		T7	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	57	1			T134	1		T151	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	234	1			T6	1		T17	3		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	335	1			T4	1		T17	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	97	1			T201	1		T20	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T91	1		T38	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T6	1		T46	1		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T7	1		T134	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	236	1			T6	1		T17	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	319	1			T1	1		T4	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	117	1			T19	1		T27	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	92	1			T45	1		T27	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	56	1			T27	1		T88	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T207	1		T208	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	240	1			T5	2		T6	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	83	1			T27	1		T107	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	95	1			T6	1		T37	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T5	1		T27	1		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T7	1		T110	2		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T6	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T17	1		T204	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	102	1			T27	1		T7	3		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	97	1			T50	1		T209	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T7	2		T50	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T77	1		T208	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T107	1		T88	1		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	211	1			T17	1		T91	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T27	1		T7	1		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T38	1		T201	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T38	1		T107	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T204	1		T88	1		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	61	1			T17	1		T27	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	251	1			T17	1		T46	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	86	1			T27	2		T7	3		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	92	1			T5	1		T204	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	66	1			T27	1		T88	2		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T204	1		T7	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T17	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	193	1			T27	2		T107	1		T7	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	261	1			T19	2		T57	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	92	1			T26	1		T107	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T42	1		T207	1		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T7	2		T20	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T7	3		T151	2		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	176	1			T17	1		T26	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	493	1			T4	1		T17	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	125	1			T4	1		T44	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T44	1		T23	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	87	1			T5	1		T110	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T5	1		T44	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	325	1			T5	1		T17	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	477	1			T2	1		T16	1		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	109	1			T5	1		T37	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T2	1		T45	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T2	1		T46	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	96	1			T2	1		T200	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T2	2		T17	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	425	1			T4	1		T19	2		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T18	1		T26	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T3	1		T46	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T3	1		T45	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T7	1		T111	1		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	257	1			T3	3		T204	1		T111	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T78	2		T74	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T4	1		T18	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T45	1		T26	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	50	1			T23	1		T7	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T204	1		T20	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	188	1			T45	1		T46	1		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T7	1		T78	7		T8	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T57	1		T46	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T47	1		T59	1		T78	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T44	1		T47	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	100	1			T47	1		T27	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	240	1			T17	1		T44	4		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T7	1		T78	2		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	102	1			T2	1		T199	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T5	1		T7	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T107	1		T7	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	95	1			T204	2		T199	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	271	1			T2	2		T27	3		T200	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T78	4		T74	1		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	107	1			T3	1		T57	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T27	1		T212	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T213	1		T212	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	94	1			T3	1		T27	1		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	279	1			T3	1		T46	1		T204	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T17	1		T26	2		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	683	1			T4	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	184	1			T27	1		T7	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	632	1			T6	1		T17	4		T19	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T6	1		T46	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	683	1			T4	1		T6	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	190	1			T45	1		T27	2		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	694	1			T1	1		T4	2		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	193	1			T5	1		T6	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	391	1			T6	1		T17	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	214	1			T107	1		T7	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	429	1			T17	1		T91	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	202	1			T17	1		T204	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	451	1			T17	1		T46	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T17	1		T204	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	389	1			T5	1		T26	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T7	5		T42	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	543	1			T17	1		T19	2		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	248	1			T5	1		T44	2		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	961	1			T4	2		T5	2		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T2	3		T45	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	873	1			T2	3		T16	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T3	2		T45	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	817	1			T3	3		T4	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	175	1			T45	1		T26	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	358	1			T4	1		T18	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	292	1			T44	1		T47	3		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	450	1			T17	1		T44	4		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	289	1			T5	1		T204	2		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	454	1			T2	3		T27	3		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T3	1		T27	2		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	467	1			T3	2		T57	1		T46	1