Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32410

1

T1

4

T2

21

T3

18

auto[1]

238

1

T17

9

T119

5

T151

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32416	1			T1	4		T2	21		T3	18
auto[134217728:268435455]	12	1			T248	3		T414	2		T415	2
auto[268435456:402653183]	10	1			T141	2		T370	1		T280	1
auto[402653184:536870911]	3	1			T370	1		T416	1		T291	1
auto[536870912:671088639]	13	1			T141	1		T304	1		T142	1
auto[671088640:805306367]	8	1			T280	1		T294	1		T417	2
auto[805306368:939524095]	8	1			T141	1		T294	1		T414	1
auto[939524096:1073741823]	7	1			T151	1		T138	1		T299	1
auto[1073741824:1207959551]	10	1			T17	1		T139	1		T304	1
auto[1207959552:1342177279]	2	1			T17	1		T414	1		-	-
auto[1342177280:1476395007]	8	1			T140	1		T141	1		T144	1
auto[1476395008:1610612735]	5	1			T17	1		T298	1		T418	1
auto[1610612736:1744830463]	5	1			T17	1		T248	1		T290	1
auto[1744830464:1879048191]	5	1			T119	1		T370	1		T248	1
auto[1879048192:2013265919]	5	1			T119	1		T304	1		T370	1
auto[2013265920:2147483647]	7	1			T140	1		T237	1		T345	1
auto[2147483648:2281701375]	8	1			T370	1		T248	1		T345	1
auto[2281701376:2415919103]	10	1			T119	1		T141	1		T142	1
auto[2415919104:2550136831]	4	1			T305	1		T294	1		T419	1
auto[2550136832:2684354559]	6	1			T141	1		T248	1		T291	1
auto[2684354560:2818572287]	6	1			T151	1		T144	1		T305	1
auto[2818572288:2952790015]	10	1			T247	1		T304	2		T305	1
auto[2952790016:3087007743]	5	1			T141	1		T299	1		T294	1
auto[3087007744:3221225471]	11	1			T141	1		T305	1		T298	1
auto[3221225472:3355443199]	12	1			T17	2		T399	1		T141	2
auto[3355443200:3489660927]	3	1			T142	1		T144	1		T420	1
auto[3489660928:3623878655]	12	1			T17	2		T304	1		T237	1
auto[3623878656:3758096383]	8	1			T119	1		T141	1		T142	1
auto[3758096384:3892314111]	6	1			T141	1		T304	1		T305	2
auto[3892314112:4026531839]	8	1			T17	1		T151	1		T141	2
auto[4026531840:4160749567]	8	1			T140	1		T141	1		T142	1
auto[4160749568:4294967295]	7	1			T119	1		T248	1		T294	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32410	1			T1	4		T2	21		T3	18
auto[0:134217727]	auto[1]	6	1			T141	1		T248	1		T322	1
auto[134217728:268435455]	auto[1]	12	1			T248	3		T414	2		T415	2
auto[268435456:402653183]	auto[1]	10	1			T141	2		T370	1		T280	1
auto[402653184:536870911]	auto[1]	3	1			T370	1		T416	1		T291	1
auto[536870912:671088639]	auto[1]	13	1			T141	1		T304	1		T142	1
auto[671088640:805306367]	auto[1]	8	1			T280	1		T294	1		T417	2
auto[805306368:939524095]	auto[1]	8	1			T141	1		T294	1		T414	1
auto[939524096:1073741823]	auto[1]	7	1			T151	1		T138	1		T299	1
auto[1073741824:1207959551]	auto[1]	10	1			T17	1		T139	1		T304	1
auto[1207959552:1342177279]	auto[1]	2	1			T17	1		T414	1		-	-
auto[1342177280:1476395007]	auto[1]	8	1			T140	1		T141	1		T144	1
auto[1476395008:1610612735]	auto[1]	5	1			T17	1		T298	1		T418	1
auto[1610612736:1744830463]	auto[1]	5	1			T17	1		T248	1		T290	1
auto[1744830464:1879048191]	auto[1]	5	1			T119	1		T370	1		T248	1
auto[1879048192:2013265919]	auto[1]	5	1			T119	1		T304	1		T370	1
auto[2013265920:2147483647]	auto[1]	7	1			T140	1		T237	1		T345	1
auto[2147483648:2281701375]	auto[1]	8	1			T370	1		T248	1		T345	1
auto[2281701376:2415919103]	auto[1]	10	1			T119	1		T141	1		T142	1
auto[2415919104:2550136831]	auto[1]	4	1			T305	1		T294	1		T419	1
auto[2550136832:2684354559]	auto[1]	6	1			T141	1		T248	1		T291	1
auto[2684354560:2818572287]	auto[1]	6	1			T151	1		T144	1		T305	1
auto[2818572288:2952790015]	auto[1]	10	1			T247	1		T304	2		T305	1
auto[2952790016:3087007743]	auto[1]	5	1			T141	1		T299	1		T294	1
auto[3087007744:3221225471]	auto[1]	11	1			T141	1		T305	1		T298	1
auto[3221225472:3355443199]	auto[1]	12	1			T17	2		T399	1		T141	2
auto[3355443200:3489660927]	auto[1]	3	1			T142	1		T144	1		T420	1
auto[3489660928:3623878655]	auto[1]	12	1			T17	2		T304	1		T237	1
auto[3623878656:3758096383]	auto[1]	8	1			T119	1		T141	1		T142	1
auto[3758096384:3892314111]	auto[1]	6	1			T141	1		T304	1		T305	2
auto[3892314112:4026531839]	auto[1]	8	1			T17	1		T151	1		T141	2
auto[4026531840:4160749567]	auto[1]	8	1			T140	1		T141	1		T142	1
auto[4160749568:4294967295]	auto[1]	7	1			T119	1		T248	1		T294	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2869

1

T1

2

T16

7

T5

2

auto[1]

182

1

T17

5

T119

8

T151

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T16	1		T39	1		T7	1
auto[134217728:268435455]	90	1			T46	1		T201	1		T110	1
auto[268435456:402653183]	109	1			T1	1		T16	1		T17	2
auto[402653184:536870911]	107	1			T19	1		T46	1		T119	1
auto[536870912:671088639]	87	1			T17	1		T51	1		T45	1
auto[671088640:805306367]	81	1			T110	1		T206	1		T269	1
auto[805306368:939524095]	108	1			T52	1		T137	1		T26	1
auto[939524096:1073741823]	80	1			T19	1		T27	1		T38	1
auto[1073741824:1207959551]	96	1			T52	2		T204	1		T27	1
auto[1207959552:1342177279]	97	1			T16	1		T19	1		T52	1
auto[1342177280:1476395007]	93	1			T16	1		T19	1		T46	1
auto[1476395008:1610612735]	99	1			T17	1		T19	3		T87	1
auto[1610612736:1744830463]	70	1			T16	1		T17	3		T137	1
auto[1744830464:1879048191]	87	1			T19	1		T51	1		T88	1
auto[1879048192:2013265919]	94	1			T5	1		T27	1		T7	1
auto[2013265920:2147483647]	91	1			T16	1		T38	2		T7	1
auto[2147483648:2281701375]	86	1			T17	1		T38	1		T7	1
auto[2281701376:2415919103]	103	1			T16	1		T5	1		T137	1
auto[2415919104:2550136831]	87	1			T39	1		T23	1		T49	1
auto[2550136832:2684354559]	106	1			T1	1		T17	1		T51	1
auto[2684354560:2818572287]	97	1			T27	1		T38	1		T23	1
auto[2818572288:2952790015]	90	1			T52	1		T27	1		T38	1
auto[2952790016:3087007743]	110	1			T26	1		T87	1		T89	1
auto[3087007744:3221225471]	110	1			T18	1		T45	1		T27	1
auto[3221225472:3355443199]	95	1			T52	1		T27	2		T119	2
auto[3355443200:3489660927]	92	1			T137	1		T27	1		T39	1
auto[3489660928:3623878655]	103	1			T26	1		T89	2		T119	1
auto[3623878656:3758096383]	103	1			T17	1		T19	1		T51	1
auto[3758096384:3892314111]	109	1			T45	1		T89	1		T112	1
auto[3892314112:4026531839]	91	1			T17	1		T19	1		T23	1
auto[4026531840:4160749567]	79	1			T51	1		T107	1		T7	1
auto[4160749568:4294967295]	100	1			T204	1		T38	1		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1879048192:2013265919]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	97	1			T16	1		T39	1		T7	1
auto[0:134217727]	auto[1]	4	1			T140	1		T421	1		T270	1
auto[134217728:268435455]	auto[0]	86	1			T46	1		T201	1		T110	1
auto[134217728:268435455]	auto[1]	4	1			T370	1		T294	1		T417	1
auto[268435456:402653183]	auto[0]	94	1			T1	1		T16	1		T19	1
auto[268435456:402653183]	auto[1]	15	1			T17	2		T138	1		T141	1
auto[402653184:536870911]	auto[0]	102	1			T19	1		T46	1		T119	1
auto[402653184:536870911]	auto[1]	5	1			T399	1		T294	1		T417	1
auto[536870912:671088639]	auto[0]	75	1			T51	1		T45	1		T204	2
auto[536870912:671088639]	auto[1]	12	1			T17	1		T139	1		T247	1
auto[671088640:805306367]	auto[0]	78	1			T110	1		T206	1		T269	1
auto[671088640:805306367]	auto[1]	3	1			T140	1		T370	1		T417	1
auto[805306368:939524095]	auto[0]	102	1			T52	1		T137	1		T26	1
auto[805306368:939524095]	auto[1]	6	1			T119	1		T151	1		T237	1
auto[939524096:1073741823]	auto[0]	77	1			T19	1		T27	1		T38	1
auto[939524096:1073741823]	auto[1]	3	1			T237	1		T414	1		T422	1
auto[1073741824:1207959551]	auto[0]	91	1			T52	2		T204	1		T27	1
auto[1073741824:1207959551]	auto[1]	5	1			T370	1		T144	1		T298	1
auto[1207959552:1342177279]	auto[0]	91	1			T16	1		T19	1		T52	1
auto[1207959552:1342177279]	auto[1]	6	1			T248	1		T345	1		T423	1
auto[1342177280:1476395007]	auto[0]	88	1			T16	1		T19	1		T46	1
auto[1342177280:1476395007]	auto[1]	5	1			T305	1		T237	1		T294	1
auto[1476395008:1610612735]	auto[0]	87	1			T19	3		T87	1		T77	1
auto[1476395008:1610612735]	auto[1]	12	1			T17	1		T119	1		T139	1
auto[1610612736:1744830463]	auto[0]	68	1			T16	1		T17	3		T137	1
auto[1610612736:1744830463]	auto[1]	2	1			T304	1		T305	1		-	-
auto[1744830464:1879048191]	auto[0]	83	1			T19	1		T51	1		T88	1
auto[1744830464:1879048191]	auto[1]	4	1			T247	1		T414	1		T418	1
auto[1879048192:2013265919]	auto[0]	94	1			T5	1		T27	1		T7	1
auto[2013265920:2147483647]	auto[0]	85	1			T16	1		T38	2		T7	1
auto[2013265920:2147483647]	auto[1]	6	1			T138	1		T247	1		T370	1
auto[2147483648:2281701375]	auto[0]	83	1			T17	1		T38	1		T7	1
auto[2147483648:2281701375]	auto[1]	3	1			T415	1		T420	1		T424	1
auto[2281701376:2415919103]	auto[0]	95	1			T16	1		T5	1		T137	1
auto[2281701376:2415919103]	auto[1]	8	1			T140	1		T370	1		T423	1
auto[2415919104:2550136831]	auto[0]	85	1			T39	1		T23	1		T49	1
auto[2415919104:2550136831]	auto[1]	2	1			T415	1		T420	1		-	-
auto[2550136832:2684354559]	auto[0]	99	1			T1	1		T17	1		T51	1
auto[2550136832:2684354559]	auto[1]	7	1			T119	1		T247	1		T304	1
auto[2684354560:2818572287]	auto[0]	96	1			T27	1		T38	1		T23	1
auto[2684354560:2818572287]	auto[1]	1	1			T416	1		-	-		-	-
auto[2818572288:2952790015]	auto[0]	82	1			T52	1		T27	1		T38	1
auto[2818572288:2952790015]	auto[1]	8	1			T140	1		T142	1		T298	1
auto[2952790016:3087007743]	auto[0]	104	1			T26	1		T87	1		T89	1
auto[2952790016:3087007743]	auto[1]	6	1			T304	1		T423	1		T298	2
auto[3087007744:3221225471]	auto[0]	103	1			T18	1		T45	1		T27	1
auto[3087007744:3221225471]	auto[1]	7	1			T151	1		T304	1		T237	1
auto[3221225472:3355443199]	auto[0]	89	1			T52	1		T27	2		T78	1
auto[3221225472:3355443199]	auto[1]	6	1			T119	2		T294	1		T423	1
auto[3355443200:3489660927]	auto[0]	85	1			T137	1		T27	1		T39	1
auto[3355443200:3489660927]	auto[1]	7	1			T138	1		T141	1		T305	1
auto[3489660928:3623878655]	auto[0]	100	1			T26	1		T89	2		T119	1
auto[3489660928:3623878655]	auto[1]	3	1			T305	1		T298	1		T415	1
auto[3623878656:3758096383]	auto[0]	97	1			T17	1		T19	1		T51	1
auto[3623878656:3758096383]	auto[1]	6	1			T399	1		T345	1		T294	1
auto[3758096384:3892314111]	auto[0]	104	1			T45	1		T89	1		T112	1
auto[3758096384:3892314111]	auto[1]	5	1			T119	1		T138	1		T305	1
auto[3892314112:4026531839]	auto[0]	81	1			T19	1		T23	1		T7	3
auto[3892314112:4026531839]	auto[1]	10	1			T17	1		T119	1		T151	1
auto[4026531840:4160749567]	auto[0]	72	1			T51	1		T107	1		T7	1
auto[4026531840:4160749567]	auto[1]	7	1			T119	1		T280	1		T290	1
auto[4160749568:4294967295]	auto[0]	96	1			T204	1		T38	1		T23	1
auto[4160749568:4294967295]	auto[1]	4	1			T304	1		T414	1		T420	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1569

1

T1

3

T16

6

T17

1

auto[1]

1723

1

T16

1

T5

2

T17

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T51	1		T57	1		T39	1
auto[134217728:268435455]	108	1			T17	1		T51	1		T52	1
auto[268435456:402653183]	105	1			T204	1		T23	1		T87	2
auto[402653184:536870911]	104	1			T16	1		T19	1		T204	1
auto[536870912:671088639]	104	1			T45	1		T7	1		T89	1
auto[671088640:805306367]	113	1			T19	1		T137	1		T57	2
auto[805306368:939524095]	121	1			T52	1		T23	2		T7	2
auto[939524096:1073741823]	103	1			T19	1		T137	1		T46	2
auto[1073741824:1207959551]	96	1			T5	1		T19	1		T38	1
auto[1207959552:1342177279]	103	1			T1	1		T52	1		T45	1
auto[1342177280:1476395007]	107	1			T137	1		T26	1		T119	1
auto[1476395008:1610612735]	82	1			T27	1		T201	1		T7	1
auto[1610612736:1744830463]	104	1			T57	1		T26	1		T39	2
auto[1744830464:1879048191]	101	1			T16	1		T38	1		T7	2
auto[1879048192:2013265919]	118	1			T16	1		T45	1		T27	3
auto[2013265920:2147483647]	99	1			T1	1		T16	1		T17	1
auto[2147483648:2281701375]	115	1			T51	1		T52	2		T137	1
auto[2281701376:2415919103]	88	1			T19	1		T57	1		T204	1
auto[2415919104:2550136831]	128	1			T57	1		T38	1		T89	2
auto[2550136832:2684354559]	111	1			T19	1		T38	1		T23	1
auto[2684354560:2818572287]	95	1			T17	1		T38	1		T87	1
auto[2818572288:2952790015]	100	1			T19	2		T137	1		T38	1
auto[2952790016:3087007743]	101	1			T16	1		T52	1		T7	2
auto[3087007744:3221225471]	101	1			T17	1		T19	1		T26	1
auto[3221225472:3355443199]	79	1			T18	1		T27	1		T56	1
auto[3355443200:3489660927]	80	1			T16	1		T19	1		T204	1
auto[3489660928:3623878655]	105	1			T23	1		T7	1		T49	1
auto[3623878656:3758096383]	109	1			T17	1		T18	1		T51	1
auto[3758096384:3892314111]	91	1			T19	1		T107	1		T7	2
auto[3892314112:4026531839]	113	1			T5	1		T51	1		T27	3
auto[4026531840:4160749567]	92	1			T1	1		T16	1		T17	1
auto[4160749568:4294967295]	103	1			T18	1		T46	1		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T51	1		T57	1		T39	1
auto[0:134217727]	auto[1]	54	1			T7	2		T246	1		T78	1
auto[134217728:268435455]	auto[0]	48	1			T51	1		T38	1		T7	1
auto[134217728:268435455]	auto[1]	60	1			T17	1		T52	1		T20	1
auto[268435456:402653183]	auto[0]	53	1			T204	1		T23	1		T87	1
auto[268435456:402653183]	auto[1]	52	1			T87	1		T20	1		T246	1
auto[402653184:536870911]	auto[0]	62	1			T16	1		T204	1		T23	2
auto[402653184:536870911]	auto[1]	42	1			T19	1		T27	1		T134	1
auto[536870912:671088639]	auto[0]	45	1			T55	1		T20	1		T195	1
auto[536870912:671088639]	auto[1]	59	1			T45	1		T7	1		T89	1
auto[671088640:805306367]	auto[0]	54	1			T137	1		T57	1		T96	1
auto[671088640:805306367]	auto[1]	59	1			T19	1		T57	1		T204	1
auto[805306368:939524095]	auto[0]	53	1			T23	2		T77	1		T207	1
auto[805306368:939524095]	auto[1]	68	1			T52	1		T7	2		T77	1
auto[939524096:1073741823]	auto[0]	53	1			T19	1		T137	1		T46	1
auto[939524096:1073741823]	auto[1]	50	1			T46	1		T107	1		T284	1
auto[1073741824:1207959551]	auto[0]	41	1			T19	1		T38	1		T7	1
auto[1073741824:1207959551]	auto[1]	55	1			T5	1		T77	1		T78	1
auto[1207959552:1342177279]	auto[0]	51	1			T1	1		T52	1		T7	2
auto[1207959552:1342177279]	auto[1]	52	1			T45	1		T46	1		T201	1
auto[1342177280:1476395007]	auto[0]	55	1			T137	1		T246	1		T78	1
auto[1342177280:1476395007]	auto[1]	52	1			T26	1		T119	1		T80	1
auto[1476395008:1610612735]	auto[0]	39	1			T7	1		T89	1		T77	1
auto[1476395008:1610612735]	auto[1]	43	1			T27	1		T201	1		T119	1
auto[1610612736:1744830463]	auto[0]	49	1			T39	2		T7	2		T112	1
auto[1610612736:1744830463]	auto[1]	55	1			T57	1		T26	1		T369	1
auto[1744830464:1879048191]	auto[0]	48	1			T16	1		T38	1		T49	1
auto[1744830464:1879048191]	auto[1]	53	1			T7	2		T284	1		T271	1
auto[1879048192:2013265919]	auto[0]	53	1			T16	1		T45	1		T7	1
auto[1879048192:2013265919]	auto[1]	65	1			T27	3		T59	1		T150	1
auto[2013265920:2147483647]	auto[0]	43	1			T1	1		T16	1		T17	1
auto[2013265920:2147483647]	auto[1]	56	1			T45	1		T26	1		T88	1
auto[2147483648:2281701375]	auto[0]	62	1			T52	2		T137	1		T7	1
auto[2147483648:2281701375]	auto[1]	53	1			T51	1		T39	1		T50	1
auto[2281701376:2415919103]	auto[0]	38	1			T19	1		T38	2		T211	1
auto[2281701376:2415919103]	auto[1]	50	1			T57	1		T204	1		T207	1
auto[2415919104:2550136831]	auto[0]	62	1			T38	1		T89	2		T78	2
auto[2415919104:2550136831]	auto[1]	66	1			T57	1		T110	1		T119	1
auto[2550136832:2684354559]	auto[0]	51	1			T38	1		T23	1		T150	1
auto[2550136832:2684354559]	auto[1]	60	1			T19	1		T20	1		T205	1
auto[2684354560:2818572287]	auto[0]	41	1			T38	1		T87	1		T78	1
auto[2684354560:2818572287]	auto[1]	54	1			T17	1		T59	1		T58	1
auto[2818572288:2952790015]	auto[0]	50	1			T19	1		T137	1		T56	1
auto[2818572288:2952790015]	auto[1]	50	1			T19	1		T38	1		T110	1
auto[2952790016:3087007743]	auto[0]	47	1			T16	1		T52	1		T7	1
auto[2952790016:3087007743]	auto[1]	54	1			T7	1		T88	2		T89	1
auto[3087007744:3221225471]	auto[0]	42	1			T26	1		T201	1		T20	1
auto[3087007744:3221225471]	auto[1]	59	1			T17	1		T19	1		T7	1
auto[3221225472:3355443199]	auto[0]	39	1			T18	1		T78	1		T58	1
auto[3221225472:3355443199]	auto[1]	40	1			T27	1		T56	1		T59	1
auto[3355443200:3489660927]	auto[0]	38	1			T19	1		T96	1		T287	1
auto[3355443200:3489660927]	auto[1]	42	1			T16	1		T204	1		T27	1
auto[3489660928:3623878655]	auto[0]	62	1			T49	1		T150	1		T78	2
auto[3489660928:3623878655]	auto[1]	43	1			T23	1		T7	1		T206	1
auto[3623878656:3758096383]	auto[0]	56	1			T18	1		T78	2		T105	1
auto[3623878656:3758096383]	auto[1]	53	1			T17	1		T51	1		T7	1
auto[3758096384:3892314111]	auto[0]	40	1			T19	1		T7	1		T207	1
auto[3758096384:3892314111]	auto[1]	51	1			T107	1		T7	1		T50	1
auto[3892314112:4026531839]	auto[0]	45	1			T27	1		T56	1		T78	3
auto[3892314112:4026531839]	auto[1]	68	1			T5	1		T51	1		T27	2
auto[4026531840:4160749567]	auto[0]	43	1			T1	1		T16	1		T23	1
auto[4026531840:4160749567]	auto[1]	49	1			T17	1		T7	1		T246	1
auto[4160749568:4294967295]	auto[0]	47	1			T18	1		T46	1		T26	1
auto[4160749568:4294967295]	auto[1]	56	1			T49	1		T78	1		T74	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T1

3

T16

6

T5

1

auto[1]

1689

1

T16

1

T5

1

T17

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T26	1		T7	2		T49	1
auto[134217728:268435455]	120	1			T19	1		T27	1		T89	1
auto[268435456:402653183]	103	1			T18	1		T52	1		T38	1
auto[402653184:536870911]	84	1			T57	1		T7	1		T88	1
auto[536870912:671088639]	97	1			T16	2		T51	1		T38	3
auto[671088640:805306367]	108	1			T17	1		T52	2		T7	1
auto[805306368:939524095]	103	1			T19	1		T52	1		T204	1
auto[939524096:1073741823]	103	1			T16	3		T19	1		T39	1
auto[1073741824:1207959551]	99	1			T18	1		T46	1		T204	1
auto[1207959552:1342177279]	98	1			T19	1		T45	1		T23	1
auto[1342177280:1476395007]	99	1			T17	2		T19	1		T39	2
auto[1476395008:1610612735]	92	1			T18	1		T246	1		T78	1
auto[1610612736:1744830463]	96	1			T5	1		T45	1		T201	1
auto[1744830464:1879048191]	117	1			T137	1		T57	2		T26	1
auto[1879048192:2013265919]	98	1			T51	1		T7	1		T49	1
auto[2013265920:2147483647]	104	1			T1	1		T19	1		T137	1
auto[2147483648:2281701375]	122	1			T51	1		T52	1		T46	1
auto[2281701376:2415919103]	80	1			T17	1		T23	1		T87	1
auto[2415919104:2550136831]	86	1			T52	1		T27	1		T38	1
auto[2550136832:2684354559]	101	1			T1	1		T45	1		T57	1
auto[2684354560:2818572287]	99	1			T45	1		T38	1		T23	1
auto[2818572288:2952790015]	108	1			T19	1		T57	1		T27	1
auto[2952790016:3087007743]	103	1			T17	1		T137	1		T204	1
auto[3087007744:3221225471]	113	1			T27	1		T23	1		T7	1
auto[3221225472:3355443199]	92	1			T5	1		T49	1		T134	2
auto[3355443200:3489660927]	107	1			T16	1		T17	1		T26	1
auto[3489660928:3623878655]	103	1			T51	1		T38	1		T7	2
auto[3623878656:3758096383]	120	1			T19	2		T137	1		T57	1
auto[3758096384:3892314111]	89	1			T137	1		T46	1		T23	1
auto[3892314112:4026531839]	109	1			T16	1		T38	1		T7	3
auto[4026531840:4160749567]	122	1			T1	1		T19	1		T27	1
auto[4160749568:4294967295]	113	1			T19	1		T51	1		T46	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T7	1		T49	1		T269	1
auto[0:134217727]	auto[1]	57	1			T26	1		T7	1		T207	1
auto[134217728:268435455]	auto[0]	54	1			T27	1		T89	1		T151	1
auto[134217728:268435455]	auto[1]	66	1			T19	1		T243	1		T195	1
auto[268435456:402653183]	auto[0]	52	1			T18	1		T52	1		T87	1
auto[268435456:402653183]	auto[1]	51	1			T38	1		T59	1		T192	1
auto[402653184:536870911]	auto[0]	43	1			T7	1		T150	1		T151	1
auto[402653184:536870911]	auto[1]	41	1			T57	1		T88	1		T96	1
auto[536870912:671088639]	auto[0]	48	1			T16	1		T38	3		T201	1
auto[536870912:671088639]	auto[1]	49	1			T16	1		T51	1		T7	2
auto[671088640:805306367]	auto[0]	49	1			T52	1		T53	1		T195	1
auto[671088640:805306367]	auto[1]	59	1			T17	1		T52	1		T7	1
auto[805306368:939524095]	auto[0]	59	1			T204	1		T38	1		T77	1
auto[805306368:939524095]	auto[1]	44	1			T19	1		T52	1		T27	1
auto[939524096:1073741823]	auto[0]	57	1			T16	3		T19	1		T78	1
auto[939524096:1073741823]	auto[1]	46	1			T39	1		T50	1		T78	1
auto[1073741824:1207959551]	auto[0]	47	1			T18	1		T7	1		T207	1
auto[1073741824:1207959551]	auto[1]	52	1			T46	1		T204	1		T7	1
auto[1207959552:1342177279]	auto[0]	47	1			T19	1		T23	1		T7	1
auto[1207959552:1342177279]	auto[1]	51	1			T45	1		T77	1		T119	1
auto[1342177280:1476395007]	auto[0]	49	1			T17	1		T19	1		T39	2
auto[1342177280:1476395007]	auto[1]	50	1			T17	1		T49	1		T208	1
auto[1476395008:1610612735]	auto[0]	48	1			T78	1		T105	1		T66	1
auto[1476395008:1610612735]	auto[1]	44	1			T18	1		T246	1		T368	1
auto[1610612736:1744830463]	auto[0]	49	1			T7	1		T88	1		T59	1
auto[1610612736:1744830463]	auto[1]	47	1			T5	1		T45	1		T201	1
auto[1744830464:1879048191]	auto[0]	57	1			T137	1		T57	1		T26	1
auto[1744830464:1879048191]	auto[1]	60	1			T57	1		T56	1		T216	2
auto[1879048192:2013265919]	auto[0]	49	1			T7	1		T49	1		T207	1
auto[1879048192:2013265919]	auto[1]	49	1			T51	1		T89	2		T20	2
auto[2013265920:2147483647]	auto[0]	45	1			T1	1		T137	1		T26	1
auto[2013265920:2147483647]	auto[1]	59	1			T19	1		T26	1		T27	1
auto[2147483648:2281701375]	auto[0]	54	1			T51	1		T52	1		T204	1
auto[2147483648:2281701375]	auto[1]	68	1			T46	1		T107	1		T201	1
auto[2281701376:2415919103]	auto[0]	34	1			T87	1		T78	1		T113	1
auto[2281701376:2415919103]	auto[1]	46	1			T17	1		T23	1		T78	2
auto[2415919104:2550136831]	auto[0]	41	1			T52	1		T27	1		T38	1
auto[2415919104:2550136831]	auto[1]	45	1			T7	1		T119	1		T243	1
auto[2550136832:2684354559]	auto[0]	48	1			T1	1		T45	1		T56	1
auto[2550136832:2684354559]	auto[1]	53	1			T57	1		T204	1		T27	2
auto[2684354560:2818572287]	auto[0]	52	1			T38	1		T23	1		T78	1
auto[2684354560:2818572287]	auto[1]	47	1			T45	1		T107	1		T78	1
auto[2818572288:2952790015]	auto[0]	50	1			T19	1		T49	1		T56	1
auto[2818572288:2952790015]	auto[1]	58	1			T57	1		T27	1		T78	1
auto[2952790016:3087007743]	auto[0]	55	1			T137	1		T204	1		T39	1
auto[2952790016:3087007743]	auto[1]	48	1			T17	1		T78	1		T247	1
auto[3087007744:3221225471]	auto[0]	60	1			T23	1		T7	1		T246	1
auto[3087007744:3221225471]	auto[1]	53	1			T27	1		T400	1		T80	1
auto[3221225472:3355443199]	auto[0]	50	1			T5	1		T96	1		T287	1
auto[3221225472:3355443199]	auto[1]	42	1			T49	1		T134	2		T138	1
auto[3355443200:3489660927]	auto[0]	51	1			T16	1		T26	1		T80	1
auto[3355443200:3489660927]	auto[1]	56	1			T17	1		T27	1		T78	1
auto[3489660928:3623878655]	auto[0]	48	1			T51	1		T38	1		T7	1
auto[3489660928:3623878655]	auto[1]	55	1			T7	1		T50	1		T20	1
auto[3623878656:3758096383]	auto[0]	61	1			T19	1		T137	1		T57	1
auto[3623878656:3758096383]	auto[1]	59	1			T19	1		T88	1		T20	1
auto[3758096384:3892314111]	auto[0]	38	1			T137	1		T23	1		T7	1
auto[3758096384:3892314111]	auto[1]	51	1			T46	1		T119	1		T152	1
auto[3892314112:4026531839]	auto[0]	56	1			T16	1		T38	1		T7	1
auto[3892314112:4026531839]	auto[1]	53	1			T7	2		T119	1		T59	2
auto[4026531840:4160749567]	auto[0]	54	1			T1	1		T19	1		T246	2
auto[4026531840:4160749567]	auto[1]	68	1			T27	1		T207	1		T151	1
auto[4160749568:4294967295]	auto[0]	51	1			T20	1		T78	2		T53	1
auto[4160749568:4294967295]	auto[1]	62	1			T19	1		T51	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1576

1

T1

3

T16

6

T17

2

auto[1]

1716

1

T16

1

T5

2

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	81	1			T27	2		T38	1		T112	1
auto[134217728:268435455]	102	1			T5	1		T17	1		T45	1
auto[268435456:402653183]	109	1			T27	2		T7	1		T119	1
auto[402653184:536870911]	101	1			T17	1		T19	2		T137	1
auto[536870912:671088639]	88	1			T16	1		T204	1		T23	1
auto[671088640:805306367]	117	1			T16	1		T27	1		T7	1
auto[805306368:939524095]	112	1			T1	1		T16	1		T18	1
auto[939524096:1073741823]	91	1			T19	1		T52	1		T7	1
auto[1073741824:1207959551]	117	1			T49	1		T110	1		T243	1
auto[1207959552:1342177279]	86	1			T5	1		T27	1		T7	2
auto[1342177280:1476395007]	98	1			T17	1		T52	1		T23	1
auto[1476395008:1610612735]	107	1			T16	1		T45	1		T137	1
auto[1610612736:1744830463]	122	1			T137	1		T57	1		T204	1
auto[1744830464:1879048191]	99	1			T19	1		T46	1		T38	1
auto[1879048192:2013265919]	112	1			T17	1		T19	1		T27	1
auto[2013265920:2147483647]	102	1			T7	2		T119	1		T59	1
auto[2147483648:2281701375]	106	1			T18	1		T45	1		T26	1
auto[2281701376:2415919103]	110	1			T16	1		T19	1		T57	1
auto[2415919104:2550136831]	96	1			T16	1		T51	2		T27	1
auto[2550136832:2684354559]	110	1			T18	1		T39	1		T50	1
auto[2684354560:2818572287]	101	1			T19	1		T51	1		T52	1
auto[2818572288:2952790015]	114	1			T19	1		T52	1		T45	1
auto[2952790016:3087007743]	97	1			T46	2		T89	1		T243	1
auto[3087007744:3221225471]	105	1			T19	1		T51	1		T57	1
auto[3221225472:3355443199]	112	1			T38	2		T23	1		T87	1
auto[3355443200:3489660927]	92	1			T17	1		T26	1		T201	1
auto[3489660928:3623878655]	94	1			T137	1		T38	1		T207	1
auto[3623878656:3758096383]	97	1			T1	1		T26	1		T23	1
auto[3758096384:3892314111]	108	1			T1	1		T57	1		T46	1
auto[3892314112:4026531839]	93	1			T16	1		T17	1		T19	1
auto[4026531840:4160749567]	105	1			T23	1		T201	1		T87	2
auto[4160749568:4294967295]	108	1			T52	2		T27	1		T38	2