Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1586

1

T1

3

T16

6

T5

1

auto[1]

1706

1

T16

1

T5

1

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T16	1		T17	1		T39	1
auto[134217728:268435455]	118	1			T16	1		T18	1		T51	1
auto[268435456:402653183]	105	1			T19	1		T51	1		T137	1
auto[402653184:536870911]	93	1			T19	2		T52	1		T23	2
auto[536870912:671088639]	76	1			T27	1		T243	1		T151	1
auto[671088640:805306367]	94	1			T19	1		T46	1		T7	1
auto[805306368:939524095]	89	1			T1	1		T46	1		T7	1
auto[939524096:1073741823]	105	1			T38	1		T7	1		T87	1
auto[1073741824:1207959551]	96	1			T17	1		T45	1		T204	1
auto[1207959552:1342177279]	101	1			T26	1		T23	2		T49	1
auto[1342177280:1476395007]	102	1			T45	1		T107	1		T89	1
auto[1476395008:1610612735]	101	1			T19	1		T45	1		T7	1
auto[1610612736:1744830463]	104	1			T57	1		T26	1		T23	1
auto[1744830464:1879048191]	106	1			T16	1		T17	1		T18	1
auto[1879048192:2013265919]	109	1			T51	1		T204	2		T38	1
auto[2013265920:2147483647]	106	1			T137	1		T57	1		T26	1
auto[2147483648:2281701375]	104	1			T27	1		T7	1		T20	1
auto[2281701376:2415919103]	98	1			T119	1		T59	1		T246	1
auto[2415919104:2550136831]	107	1			T137	1		T27	1		T23	1
auto[2550136832:2684354559]	127	1			T18	1		T52	1		T204	1
auto[2684354560:2818572287]	90	1			T5	2		T137	1		T46	1
auto[2818572288:2952790015]	101	1			T16	1		T52	1		T38	1
auto[2952790016:3087007743]	115	1			T1	1		T19	1		T27	1
auto[3087007744:3221225471]	114	1			T16	1		T19	1		T27	2
auto[3221225472:3355443199]	107	1			T52	1		T57	1		T7	1
auto[3355443200:3489660927]	102	1			T26	1		T38	1		T7	1
auto[3489660928:3623878655]	106	1			T16	1		T17	1		T19	1
auto[3623878656:3758096383]	102	1			T57	1		T204	1		T27	1
auto[3758096384:3892314111]	90	1			T16	1		T57	1		T59	1
auto[3892314112:4026531839]	109	1			T17	2		T19	1		T27	1
auto[4026531840:4160749567]	100	1			T52	1		T39	2		T7	3
auto[4160749568:4294967295]	110	1			T1	1		T19	2		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T16	1		T17	1		T39	1
auto[0:134217727]	auto[1]	56	1			T210	1		T97	1		T93	1
auto[134217728:268435455]	auto[0]	60	1			T16	1		T137	1		T38	2
auto[134217728:268435455]	auto[1]	58	1			T18	1		T51	1		T52	1
auto[268435456:402653183]	auto[0]	42	1			T19	1		T51	1		T137	1
auto[268435456:402653183]	auto[1]	63	1			T26	1		T79	1		T8	1
auto[402653184:536870911]	auto[0]	48	1			T19	1		T52	1		T23	1
auto[402653184:536870911]	auto[1]	45	1			T19	1		T23	1		T207	1
auto[536870912:671088639]	auto[0]	43	1			T151	1		T78	1		T369	1
auto[536870912:671088639]	auto[1]	33	1			T27	1		T243	1		T246	1
auto[671088640:805306367]	auto[0]	40	1			T19	1		T20	1		T78	1
auto[671088640:805306367]	auto[1]	54	1			T46	1		T7	1		T119	1
auto[805306368:939524095]	auto[0]	37	1			T1	1		T89	1		T56	1
auto[805306368:939524095]	auto[1]	52	1			T46	1		T7	1		T50	1
auto[939524096:1073741823]	auto[0]	66	1			T38	1		T7	1		T87	1
auto[939524096:1073741823]	auto[1]	39	1			T119	1		T151	1		T331	1
auto[1073741824:1207959551]	auto[0]	48	1			T7	1		T150	1		T78	1
auto[1073741824:1207959551]	auto[1]	48	1			T17	1		T45	1		T204	1
auto[1207959552:1342177279]	auto[0]	45	1			T26	1		T23	2		T49	1
auto[1207959552:1342177279]	auto[1]	56	1			T77	1		T78	1		T139	1
auto[1342177280:1476395007]	auto[0]	46	1			T58	1		T65	1		T80	1
auto[1342177280:1476395007]	auto[1]	56	1			T45	1		T107	1		T89	1
auto[1476395008:1610612735]	auto[0]	49	1			T19	1		T7	1		T78	2
auto[1476395008:1610612735]	auto[1]	52	1			T45	1		T195	1		T74	1
auto[1610612736:1744830463]	auto[0]	59	1			T26	1		T23	1		T49	1
auto[1610612736:1744830463]	auto[1]	45	1			T57	1		T107	1		T79	1
auto[1744830464:1879048191]	auto[0]	44	1			T16	1		T18	1		T7	2
auto[1744830464:1879048191]	auto[1]	62	1			T17	1		T38	1		T7	1
auto[1879048192:2013265919]	auto[0]	66	1			T51	1		T204	2		T38	1
auto[1879048192:2013265919]	auto[1]	43	1			T271	1		T80	1		T216	1
auto[2013265920:2147483647]	auto[0]	50	1			T137	1		T57	1		T26	1
auto[2013265920:2147483647]	auto[1]	56	1			T27	1		T7	1		T20	1
auto[2147483648:2281701375]	auto[0]	50	1			T20	1		T78	1		T53	1
auto[2147483648:2281701375]	auto[1]	54	1			T27	1		T7	1		T80	1
auto[2281701376:2415919103]	auto[0]	38	1			T78	2		T105	1		T269	1
auto[2281701376:2415919103]	auto[1]	60	1			T119	1		T59	1		T246	1
auto[2415919104:2550136831]	auto[0]	48	1			T137	1		T23	1		T201	1
auto[2415919104:2550136831]	auto[1]	59	1			T27	1		T119	1		T138	1
auto[2550136832:2684354559]	auto[0]	63	1			T7	1		T285	1		T96	1
auto[2550136832:2684354559]	auto[1]	64	1			T18	1		T52	1		T204	1
auto[2684354560:2818572287]	auto[0]	49	1			T5	1		T137	1		T77	1
auto[2684354560:2818572287]	auto[1]	41	1			T5	1		T46	1		T27	1
auto[2818572288:2952790015]	auto[0]	58	1			T16	1		T38	1		T23	1
auto[2818572288:2952790015]	auto[1]	43	1			T52	1		T59	1		T78	1
auto[2952790016:3087007743]	auto[0]	50	1			T1	1		T19	1		T7	1
auto[2952790016:3087007743]	auto[1]	65	1			T27	1		T7	2		T20	1
auto[3087007744:3221225471]	auto[0]	54	1			T16	1		T27	1		T38	1
auto[3087007744:3221225471]	auto[1]	60	1			T19	1		T27	1		T7	1
auto[3221225472:3355443199]	auto[0]	48	1			T52	1		T88	1		T243	1
auto[3221225472:3355443199]	auto[1]	59	1			T57	1		T7	1		T20	1
auto[3355443200:3489660927]	auto[0]	45	1			T38	1		T8	1		T304	1
auto[3355443200:3489660927]	auto[1]	57	1			T26	1		T7	1		T78	1
auto[3489660928:3623878655]	auto[0]	57	1			T16	1		T19	1		T51	1
auto[3489660928:3623878655]	auto[1]	49	1			T17	1		T45	1		T7	1
auto[3623878656:3758096383]	auto[0]	50	1			T27	1		T56	1		T246	2
auto[3623878656:3758096383]	auto[1]	52	1			T57	1		T204	1		T7	1
auto[3758096384:3892314111]	auto[0]	41	1			T207	1		T78	1		T74	1
auto[3758096384:3892314111]	auto[1]	49	1			T16	1		T57	1		T59	1
auto[3892314112:4026531839]	auto[0]	55	1			T17	1		T19	1		T38	1
auto[3892314112:4026531839]	auto[1]	54	1			T17	1		T27	1		T201	1
auto[4026531840:4160749567]	auto[0]	41	1			T52	1		T39	1		T7	2
auto[4026531840:4160749567]	auto[1]	59	1			T39	1		T7	1		T208	1
auto[4160749568:4294967295]	auto[0]	47	1			T1	1		T55	1		T77	1
auto[4160749568:4294967295]	auto[1]	63	1			T19	2		T51	1		T207	1