Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4432

1

T1

4

T16

12

T5

2

auto[1]

2154

1

T1

2

T16

2

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	170	1			T17	2		T26	2		T27	2
auto[134217728:268435455]	202	1			T5	2		T57	2		T204	2
auto[268435456:402653183]	164	1			T51	4		T137	2		T38	2
auto[402653184:536870911]	228	1			T16	2		T19	2		T7	2
auto[536870912:671088639]	208	1			T1	2		T16	2		T38	2
auto[671088640:805306367]	196	1			T19	2		T57	2		T26	2
auto[805306368:939524095]	222	1			T1	2		T16	2		T46	2
auto[939524096:1073741823]	208	1			T18	2		T45	2		T137	2
auto[1073741824:1207959551]	242	1			T17	4		T19	4		T137	2
auto[1207959552:1342177279]	218	1			T1	2		T16	2		T19	2
auto[1342177280:1476395007]	198	1			T52	2		T27	2		T38	2
auto[1476395008:1610612735]	190	1			T26	4		T38	2		T39	2
auto[1610612736:1744830463]	198	1			T19	2		T7	2		T77	2
auto[1744830464:1879048191]	196	1			T5	2		T46	2		T38	2
auto[1879048192:2013265919]	210	1			T52	2		T7	2		T89	2
auto[2013265920:2147483647]	234	1			T17	2		T57	2		T27	2
auto[2147483648:2281701375]	182	1			T27	4		T38	2		T88	2
auto[2281701376:2415919103]	220	1			T52	2		T46	2		T27	4
auto[2415919104:2550136831]	218	1			T17	2		T45	2		T57	2
auto[2550136832:2684354559]	210	1			T51	2		T110	2		T96	2
auto[2684354560:2818572287]	174	1			T16	2		T45	2		T38	4
auto[2818572288:2952790015]	254	1			T16	2		T19	2		T23	2
auto[2952790016:3087007743]	248	1			T19	2		T57	2		T112	2
auto[3087007744:3221225471]	218	1			T23	2		T78	4		T138	2
auto[3221225472:3355443199]	192	1			T16	2		T137	2		T87	2
auto[3355443200:3489660927]	150	1			T17	2		T18	2		T19	2
auto[3489660928:3623878655]	210	1			T19	2		T51	4		T27	4
auto[3623878656:3758096383]	196	1			T45	2		T38	2		T7	2
auto[3758096384:3892314111]	200	1			T18	2		T52	2		T57	2
auto[3892314112:4026531839]	232	1			T19	2		T137	2		T46	2
auto[4026531840:4160749567]	198	1			T52	2		T7	6		T49	2
auto[4160749568:4294967295]	200	1			T204	2		T201	4		T59	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	118	1			T17	2		T26	2		T27	2
auto[0:134217727]	auto[1]	52	1			T88	2		T223	2		T363	2
auto[134217728:268435455]	auto[0]	138	1			T5	2		T204	2		T23	2
auto[134217728:268435455]	auto[1]	64	1			T57	2		T56	2		T134	2
auto[268435456:402653183]	auto[0]	112	1			T51	4		T7	4		T59	2
auto[268435456:402653183]	auto[1]	52	1			T137	2		T38	2		T39	2
auto[402653184:536870911]	auto[0]	152	1			T16	2		T19	2		T7	2
auto[402653184:536870911]	auto[1]	76	1			T247	2		T130	2		T131	2
auto[536870912:671088639]	auto[0]	130	1			T16	2		T7	2		T207	2
auto[536870912:671088639]	auto[1]	78	1			T1	2		T38	2		T39	2
auto[671088640:805306367]	auto[0]	132	1			T19	2		T201	2		T7	2
auto[671088640:805306367]	auto[1]	64	1			T57	2		T26	2		T97	2
auto[805306368:939524095]	auto[0]	154	1			T1	2		T16	2		T23	2
auto[805306368:939524095]	auto[1]	68	1			T46	2		T7	4		T119	2
auto[939524096:1073741823]	auto[0]	136	1			T45	2		T137	2		T204	4
auto[939524096:1073741823]	auto[1]	72	1			T18	2		T107	2		T78	2
auto[1073741824:1207959551]	auto[0]	152	1			T17	2		T19	4		T246	2
auto[1073741824:1207959551]	auto[1]	90	1			T17	2		T137	2		T50	2
auto[1207959552:1342177279]	auto[0]	152	1			T1	2		T16	2		T19	2
auto[1207959552:1342177279]	auto[1]	66	1			T23	2		T7	2		T400	2
auto[1342177280:1476395007]	auto[0]	156	1			T52	2		T27	2		T107	2
auto[1342177280:1476395007]	auto[1]	42	1			T38	2		T7	2		T78	2
auto[1476395008:1610612735]	auto[0]	128	1			T26	4		T38	2		T39	2
auto[1476395008:1610612735]	auto[1]	62	1			T119	2		T150	2		T211	2
auto[1610612736:1744830463]	auto[0]	140	1			T19	2		T7	2		T78	4
auto[1610612736:1744830463]	auto[1]	58	1			T77	2		T8	2		T216	2
auto[1744830464:1879048191]	auto[0]	144	1			T7	2		T88	2		T59	2
auto[1744830464:1879048191]	auto[1]	52	1			T5	2		T46	2		T38	2
auto[1879048192:2013265919]	auto[0]	136	1			T52	2		T7	2		T246	2
auto[1879048192:2013265919]	auto[1]	74	1			T89	2		T78	2		T210	2
auto[2013265920:2147483647]	auto[0]	144	1			T17	2		T27	2		T38	2
auto[2013265920:2147483647]	auto[1]	90	1			T57	2		T119	2		T78	2
auto[2147483648:2281701375]	auto[0]	124	1			T27	4		T88	2		T59	2
auto[2147483648:2281701375]	auto[1]	58	1			T38	2		T89	2		T56	2
auto[2281701376:2415919103]	auto[0]	154	1			T52	2		T46	2		T27	4
auto[2281701376:2415919103]	auto[1]	66	1			T7	2		T119	2		T79	2
auto[2415919104:2550136831]	auto[0]	146	1			T17	2		T26	2		T204	2
auto[2415919104:2550136831]	auto[1]	72	1			T45	2		T57	2		T7	4
auto[2550136832:2684354559]	auto[0]	128	1			T51	2		T110	2		T65	2
auto[2550136832:2684354559]	auto[1]	82	1			T96	2		T93	2		T262	2
auto[2684354560:2818572287]	auto[0]	104	1			T16	2		T45	2		T87	2
auto[2684354560:2818572287]	auto[1]	70	1			T38	4		T400	2		T9	4
auto[2818572288:2952790015]	auto[0]	164	1			T16	2		T19	2		T23	2
auto[2818572288:2952790015]	auto[1]	90	1			T89	2		T56	2		T206	2
auto[2952790016:3087007743]	auto[0]	152	1			T19	2		T112	2		T20	2
auto[2952790016:3087007743]	auto[1]	96	1			T57	2		T53	2		T74	2
auto[3087007744:3221225471]	auto[0]	148	1			T23	2		T78	2		T138	2
auto[3087007744:3221225471]	auto[1]	70	1			T78	2		T331	2		T216	2
auto[3221225472:3355443199]	auto[0]	124	1			T87	2		T243	2		T208	2
auto[3221225472:3355443199]	auto[1]	68	1			T16	2		T137	2		T206	2
auto[3355443200:3489660927]	auto[0]	94	1			T17	2		T19	2		T201	2
auto[3355443200:3489660927]	auto[1]	56	1			T18	2		T39	2		T7	2
auto[3489660928:3623878655]	auto[0]	162	1			T19	2		T51	4		T27	2
auto[3489660928:3623878655]	auto[1]	48	1			T27	2		T78	2		T80	2
auto[3623878656:3758096383]	auto[0]	142	1			T45	2		T38	2		T49	2
auto[3623878656:3758096383]	auto[1]	54	1			T7	2		T105	2		T195	2
auto[3758096384:3892314111]	auto[0]	140	1			T52	2		T23	2		T7	2
auto[3758096384:3892314111]	auto[1]	60	1			T18	2		T57	2		T7	2
auto[3892314112:4026531839]	auto[0]	164	1			T19	2		T7	2		T87	2
auto[3892314112:4026531839]	auto[1]	68	1			T137	2		T46	2		T78	2
auto[4026531840:4160749567]	auto[0]	134	1			T52	2		T7	4		T50	2
auto[4026531840:4160749567]	auto[1]	64	1			T7	2		T49	2		T150	2
auto[4160749568:4294967295]	auto[0]	128	1			T201	2		T59	2		T78	4
auto[4160749568:4294967295]	auto[1]	72	1			T204	2		T201	2		T195	2