Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.11 98.37 100.00 99.02 98.41 91.17


Total test records in report: 1089
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1009 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1754660216 Jun 26 05:47:12 PM PDT 24 Jun 26 05:47:14 PM PDT 24 68090996 ps
T1010 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3803012253 Jun 26 05:47:49 PM PDT 24 Jun 26 05:47:51 PM PDT 24 24277534 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3118137187 Jun 26 05:47:37 PM PDT 24 Jun 26 05:47:43 PM PDT 24 295814545 ps
T124 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1722912334 Jun 26 05:47:45 PM PDT 24 Jun 26 05:47:53 PM PDT 24 196228005 ps
T1012 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1515647558 Jun 26 05:47:29 PM PDT 24 Jun 26 05:47:32 PM PDT 24 83185021 ps
T1013 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1272741532 Jun 26 05:47:43 PM PDT 24 Jun 26 05:47:45 PM PDT 24 49231160 ps
T184 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3483542077 Jun 26 05:47:11 PM PDT 24 Jun 26 05:47:21 PM PDT 24 1847758283 ps
T1014 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3212909953 Jun 26 05:47:48 PM PDT 24 Jun 26 05:47:50 PM PDT 24 8161707 ps
T1015 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.803710469 Jun 26 05:47:40 PM PDT 24 Jun 26 05:47:43 PM PDT 24 22388779 ps
T1016 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2326469316 Jun 26 05:47:36 PM PDT 24 Jun 26 05:47:41 PM PDT 24 187787023 ps
T1017 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2554229829 Jun 26 05:47:26 PM PDT 24 Jun 26 05:47:28 PM PDT 24 22754587 ps
T1018 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.369563642 Jun 26 05:47:37 PM PDT 24 Jun 26 05:47:44 PM PDT 24 164720883 ps
T1019 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1481157653 Jun 26 05:47:43 PM PDT 24 Jun 26 05:47:54 PM PDT 24 1419925636 ps
T1020 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2630130207 Jun 26 05:47:21 PM PDT 24 Jun 26 05:47:31 PM PDT 24 1345266511 ps
T1021 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1128384192 Jun 26 05:47:12 PM PDT 24 Jun 26 05:47:15 PM PDT 24 49866078 ps
T1022 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1531086139 Jun 26 05:47:34 PM PDT 24 Jun 26 05:47:37 PM PDT 24 62299096 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1041681279 Jun 26 05:47:13 PM PDT 24 Jun 26 05:47:17 PM PDT 24 63308861 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.42855673 Jun 26 05:47:15 PM PDT 24 Jun 26 05:47:17 PM PDT 24 55506898 ps
T1025 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3112137643 Jun 26 05:47:06 PM PDT 24 Jun 26 05:47:08 PM PDT 24 31089065 ps
T1026 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1686362640 Jun 26 05:47:31 PM PDT 24 Jun 26 05:47:35 PM PDT 24 230156800 ps
T1027 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.361867380 Jun 26 05:47:38 PM PDT 24 Jun 26 05:47:42 PM PDT 24 470621811 ps
T1028 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.483303416 Jun 26 05:47:44 PM PDT 24 Jun 26 05:47:49 PM PDT 24 176423200 ps
T1029 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.554212672 Jun 26 05:47:21 PM PDT 24 Jun 26 05:47:23 PM PDT 24 29891828 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2237484859 Jun 26 05:47:11 PM PDT 24 Jun 26 05:47:14 PM PDT 24 37186404 ps
T1031 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.115404636 Jun 26 05:47:43 PM PDT 24 Jun 26 05:47:48 PM PDT 24 168982855 ps
T1032 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2168288053 Jun 26 05:47:31 PM PDT 24 Jun 26 05:47:42 PM PDT 24 485350742 ps
T1033 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2715472361 Jun 26 05:47:45 PM PDT 24 Jun 26 05:47:48 PM PDT 24 9881360 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4151128580 Jun 26 05:47:13 PM PDT 24 Jun 26 05:47:22 PM PDT 24 138984911 ps
T1035 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4175041960 Jun 26 05:47:20 PM PDT 24 Jun 26 05:47:36 PM PDT 24 415060935 ps
T1036 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.822626214 Jun 26 05:46:58 PM PDT 24 Jun 26 05:47:05 PM PDT 24 606247667 ps
T1037 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2328870777 Jun 26 05:47:34 PM PDT 24 Jun 26 05:47:36 PM PDT 24 99864034 ps
T1038 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1451272019 Jun 26 05:47:22 PM PDT 24 Jun 26 05:47:24 PM PDT 24 44208656 ps
T1039 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2719134273 Jun 26 05:47:31 PM PDT 24 Jun 26 05:47:35 PM PDT 24 178061239 ps
T1040 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4106321295 Jun 26 05:47:46 PM PDT 24 Jun 26 05:47:49 PM PDT 24 12761324 ps
T1041 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3623952494 Jun 26 05:47:53 PM PDT 24 Jun 26 05:48:02 PM PDT 24 676478179 ps
T1042 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.513867367 Jun 26 05:47:21 PM PDT 24 Jun 26 05:47:25 PM PDT 24 337051732 ps
T1043 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3720690582 Jun 26 05:47:13 PM PDT 24 Jun 26 05:47:23 PM PDT 24 318243670 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2050746504 Jun 26 05:47:29 PM PDT 24 Jun 26 05:47:31 PM PDT 24 12224890 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.350696110 Jun 26 05:47:29 PM PDT 24 Jun 26 05:47:33 PM PDT 24 184012127 ps
T1046 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2383323572 Jun 26 05:47:19 PM PDT 24 Jun 26 05:47:22 PM PDT 24 188501346 ps
T1047 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2761176518 Jun 26 05:47:04 PM PDT 24 Jun 26 05:47:07 PM PDT 24 32046553 ps
T1048 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3890976216 Jun 26 05:47:41 PM PDT 24 Jun 26 05:47:54 PM PDT 24 373538745 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1470731181 Jun 26 05:47:04 PM PDT 24 Jun 26 05:47:12 PM PDT 24 1813717238 ps
T1050 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3708287322 Jun 26 05:47:18 PM PDT 24 Jun 26 05:47:19 PM PDT 24 41331416 ps
T1051 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3144278998 Jun 26 05:47:20 PM PDT 24 Jun 26 05:47:22 PM PDT 24 26892312 ps
T1052 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2651495341 Jun 26 05:47:31 PM PDT 24 Jun 26 05:47:37 PM PDT 24 97689967 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.646078485 Jun 26 05:47:03 PM PDT 24 Jun 26 05:47:05 PM PDT 24 66396760 ps
T1054 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.756565687 Jun 26 05:47:44 PM PDT 24 Jun 26 05:47:47 PM PDT 24 14296200 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.236038077 Jun 26 05:47:31 PM PDT 24 Jun 26 05:47:35 PM PDT 24 286679956 ps
T1056 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1037655718 Jun 26 05:47:29 PM PDT 24 Jun 26 05:47:33 PM PDT 24 75191359 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3039316503 Jun 26 05:47:40 PM PDT 24 Jun 26 05:47:44 PM PDT 24 184585932 ps
T172 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1796012116 Jun 26 05:47:35 PM PDT 24 Jun 26 05:47:42 PM PDT 24 229248825 ps
T1058 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4032045382 Jun 26 05:47:49 PM PDT 24 Jun 26 05:47:52 PM PDT 24 17822664 ps
T1059 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.467279476 Jun 26 05:47:03 PM PDT 24 Jun 26 05:47:11 PM PDT 24 135364305 ps
T1060 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2430833471 Jun 26 05:47:45 PM PDT 24 Jun 26 05:47:47 PM PDT 24 21373674 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3543238516 Jun 26 05:47:13 PM PDT 24 Jun 26 05:47:17 PM PDT 24 41245097 ps
T1062 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1637076093 Jun 26 05:47:39 PM PDT 24 Jun 26 05:47:44 PM PDT 24 662432854 ps
T1063 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3399067374 Jun 26 05:47:43 PM PDT 24 Jun 26 05:47:47 PM PDT 24 500023193 ps
T171 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3494413305 Jun 26 05:47:37 PM PDT 24 Jun 26 05:47:46 PM PDT 24 208963033 ps
T1064 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.964805616 Jun 26 05:47:44 PM PDT 24 Jun 26 05:47:48 PM PDT 24 81967063 ps
T1065 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.849965777 Jun 26 05:47:52 PM PDT 24 Jun 26 05:47:54 PM PDT 24 8336540 ps
T1066 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1309040555 Jun 26 05:47:35 PM PDT 24 Jun 26 05:47:38 PM PDT 24 17246674 ps
T1067 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1860964657 Jun 26 05:47:49 PM PDT 24 Jun 26 05:47:51 PM PDT 24 345245320 ps
T185 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1198616903 Jun 26 05:47:30 PM PDT 24 Jun 26 05:47:35 PM PDT 24 113252383 ps
T1068 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4282646546 Jun 26 05:47:45 PM PDT 24 Jun 26 05:47:48 PM PDT 24 13658107 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.251007417 Jun 26 05:47:12 PM PDT 24 Jun 26 05:47:15 PM PDT 24 57181225 ps
T1070 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1692809508 Jun 26 05:47:14 PM PDT 24 Jun 26 05:47:17 PM PDT 24 106553498 ps
T1071 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1619393811 Jun 26 05:47:28 PM PDT 24 Jun 26 05:47:30 PM PDT 24 13926654 ps
T182 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1488315895 Jun 26 05:47:46 PM PDT 24 Jun 26 05:47:52 PM PDT 24 407157487 ps
T1072 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3355451772 Jun 26 05:47:44 PM PDT 24 Jun 26 05:47:46 PM PDT 24 36104316 ps
T1073 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2578249968 Jun 26 05:47:42 PM PDT 24 Jun 26 05:47:45 PM PDT 24 79161944 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1397662828 Jun 26 05:47:36 PM PDT 24 Jun 26 05:47:47 PM PDT 24 332848941 ps
T1075 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1085030522 Jun 26 05:47:30 PM PDT 24 Jun 26 05:47:35 PM PDT 24 96809776 ps
T1076 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.691333273 Jun 26 05:47:37 PM PDT 24 Jun 26 05:47:43 PM PDT 24 396075922 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.165627566 Jun 26 05:47:11 PM PDT 24 Jun 26 05:47:44 PM PDT 24 5586619350 ps
T1078 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1883241481 Jun 26 05:47:36 PM PDT 24 Jun 26 05:47:40 PM PDT 24 35285343 ps
T1079 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2507813996 Jun 26 05:47:36 PM PDT 24 Jun 26 05:47:39 PM PDT 24 50429587 ps
T1080 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1349663740 Jun 26 05:47:14 PM PDT 24 Jun 26 05:47:20 PM PDT 24 167988417 ps
T160 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.829039351 Jun 26 05:47:11 PM PDT 24 Jun 26 05:47:16 PM PDT 24 436358706 ps
T166 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.106216468 Jun 26 05:47:16 PM PDT 24 Jun 26 05:47:22 PM PDT 24 383250837 ps
T1081 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.905441343 Jun 26 05:47:45 PM PDT 24 Jun 26 05:47:50 PM PDT 24 53641649 ps
T1082 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2356499622 Jun 26 05:47:22 PM PDT 24 Jun 26 05:47:25 PM PDT 24 27656606 ps
T1083 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2993405080 Jun 26 05:47:29 PM PDT 24 Jun 26 05:47:33 PM PDT 24 181725947 ps
T1084 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1467993736 Jun 26 05:47:49 PM PDT 24 Jun 26 05:47:51 PM PDT 24 35855343 ps
T1085 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2238989020 Jun 26 05:47:48 PM PDT 24 Jun 26 05:47:53 PM PDT 24 374423401 ps
T1086 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3271777404 Jun 26 05:47:21 PM PDT 24 Jun 26 05:47:31 PM PDT 24 210289516 ps
T1087 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.511926069 Jun 26 05:47:51 PM PDT 24 Jun 26 05:47:54 PM PDT 24 60990768 ps
T1088 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2438473661 Jun 26 05:47:49 PM PDT 24 Jun 26 05:47:51 PM PDT 24 25092513 ps
T1089 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1546546777 Jun 26 05:47:13 PM PDT 24 Jun 26 05:47:20 PM PDT 24 404499142 ps

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.938560278
Short name T17
Test name
Test status
Simulation time 130184292 ps
CPU time 5.16 seconds
Started Jun 26 05:54:51 PM PDT 24
Finished Jun 26 05:54:59 PM PDT 24
Peak memory 215544 kb
Host smart-079f8f9d-a2ac-42a9-a7d8-48eeddd7c9b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938560278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.938560278
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1916342195
Short name T78
Test name
Test status
Simulation time 11169768064 ps
CPU time 57.53 seconds
Started Jun 26 05:54:07 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 216452 kb
Host smart-7486f393-3f72-4530-b50c-64f085a32ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916342195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1916342195
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.929757837
Short name T137
Test name
Test status
Simulation time 361446665 ps
CPU time 3.42 seconds
Started Jun 26 05:54:06 PM PDT 24
Finished Jun 26 05:54:10 PM PDT 24
Peak memory 214228 kb
Host smart-66c3716a-428b-4a20-aeea-9b5fe52a7c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929757837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.929757837
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1483397996
Short name T9
Test name
Test status
Simulation time 615173008 ps
CPU time 22.39 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:53 PM PDT 24
Peak memory 222540 kb
Host smart-f9ac1260-17e5-44f5-a7bd-e43afbfa50b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483397996 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1483397996
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1469957833
Short name T13
Test name
Test status
Simulation time 837395971 ps
CPU time 17.17 seconds
Started Jun 26 05:54:12 PM PDT 24
Finished Jun 26 05:54:30 PM PDT 24
Peak memory 237588 kb
Host smart-610ead6b-91eb-4113-92d2-713ce50147de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469957833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1469957833
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1443957727
Short name T7
Test name
Test status
Simulation time 3585598689 ps
CPU time 45.41 seconds
Started Jun 26 05:56:48 PM PDT 24
Finished Jun 26 05:57:39 PM PDT 24
Peak memory 220664 kb
Host smart-3210af39-39da-47de-8626-a3a990c94329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443957727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1443957727
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2140875410
Short name T10
Test name
Test status
Simulation time 198770267 ps
CPU time 3.98 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 214884 kb
Host smart-31650111-da7f-4ca2-8bcc-445226ca0e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140875410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2140875410
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.819274680
Short name T19
Test name
Test status
Simulation time 633635845 ps
CPU time 6.21 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 222344 kb
Host smart-6628a6da-31cc-46eb-9b45-a3c3dd00d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819274680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.819274680
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.887579766
Short name T116
Test name
Test status
Simulation time 337164616 ps
CPU time 8.76 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 213936 kb
Host smart-b4cd51a0-6a54-49fa-afe8-50f0b47c288d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887579766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.887579766
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3364591149
Short name T62
Test name
Test status
Simulation time 230032609 ps
CPU time 6.74 seconds
Started Jun 26 05:56:37 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 222612 kb
Host smart-ba9c3905-c436-4d61-b12a-f60756f70018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364591149 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3364591149
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3392126771
Short name T65
Test name
Test status
Simulation time 79263879 ps
CPU time 2.49 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 218636 kb
Host smart-da7e7c9c-3e87-4420-bd99-1f50eadaa7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392126771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3392126771
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1813802610
Short name T141
Test name
Test status
Simulation time 196423577 ps
CPU time 8.95 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:03 PM PDT 24
Peak memory 214372 kb
Host smart-3fbe4fc3-2f65-4fc5-b48f-199ea6ee2582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813802610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1813802610
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.430295846
Short name T23
Test name
Test status
Simulation time 177150091 ps
CPU time 3.88 seconds
Started Jun 26 05:56:25 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 214348 kb
Host smart-62d18024-f833-4a83-8224-f9c6ecc60617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430295846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.430295846
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2309879044
Short name T8
Test name
Test status
Simulation time 86351431187 ps
CPU time 244.25 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:59:28 PM PDT 24
Peak memory 217024 kb
Host smart-fade915e-c742-4aad-8a85-1346d79a79ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309879044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2309879044
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1197853537
Short name T119
Test name
Test status
Simulation time 652481463 ps
CPU time 9.36 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:12 PM PDT 24
Peak memory 214984 kb
Host smart-7da5f942-90ad-4249-94a5-8348027921bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197853537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1197853537
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3265492145
Short name T305
Test name
Test status
Simulation time 7488583812 ps
CPU time 115.21 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:57:34 PM PDT 24
Peak memory 222500 kb
Host smart-dc395308-36b5-47c0-852d-1b8627277016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265492145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3265492145
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3293868309
Short name T75
Test name
Test status
Simulation time 19822442508 ps
CPU time 164.57 seconds
Started Jun 26 05:54:51 PM PDT 24
Finished Jun 26 05:57:38 PM PDT 24
Peak memory 218712 kb
Host smart-6c68a122-3834-4b62-8dc5-d304541383e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293868309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3293868309
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2754787784
Short name T37
Test name
Test status
Simulation time 201038866 ps
CPU time 1.48 seconds
Started Jun 26 05:54:35 PM PDT 24
Finished Jun 26 05:54:37 PM PDT 24
Peak memory 207500 kb
Host smart-fa7813b3-92f1-487f-bd0b-df6d2a8329a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754787784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2754787784
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3684919941
Short name T20
Test name
Test status
Simulation time 500824288 ps
CPU time 5.97 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:54:55 PM PDT 24
Peak memory 214360 kb
Host smart-21a2e3d0-240f-44c1-a8b1-91f5ecfe731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684919941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3684919941
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3575362169
Short name T294
Test name
Test status
Simulation time 724472654 ps
CPU time 10.61 seconds
Started Jun 26 05:54:23 PM PDT 24
Finished Jun 26 05:54:35 PM PDT 24
Peak memory 215136 kb
Host smart-e0e131b8-c2e6-47f9-a139-32afd67de2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575362169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3575362169
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3057311696
Short name T80
Test name
Test status
Simulation time 7857079938 ps
CPU time 175.13 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:58:10 PM PDT 24
Peak memory 222592 kb
Host smart-3c0cff44-8fe3-45bc-b7fb-c7ebc169c5df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057311696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3057311696
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3956287674
Short name T77
Test name
Test status
Simulation time 182939632 ps
CPU time 10.09 seconds
Started Jun 26 05:55:12 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 222540 kb
Host smart-fc95cf9a-6201-4ecc-901b-81576e52092d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956287674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3956287674
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.981413890
Short name T270
Test name
Test status
Simulation time 235122834 ps
CPU time 13.17 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:55:01 PM PDT 24
Peak memory 215540 kb
Host smart-53247ed1-5428-4595-b866-128ae67ac205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981413890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.981413890
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1469797212
Short name T303
Test name
Test status
Simulation time 716769059 ps
CPU time 18.78 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:35 PM PDT 24
Peak memory 222644 kb
Host smart-c6facb28-fabb-46ae-bb03-914114b7d385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469797212 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1469797212
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.308388773
Short name T22
Test name
Test status
Simulation time 42077491 ps
CPU time 1.85 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:06 PM PDT 24
Peak memory 221680 kb
Host smart-cbb104f2-134e-42a6-98fa-41b4255f97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308388773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.308388773
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.361979717
Short name T58
Test name
Test status
Simulation time 178713931 ps
CPU time 6.67 seconds
Started Jun 26 05:55:25 PM PDT 24
Finished Jun 26 05:55:35 PM PDT 24
Peak memory 218156 kb
Host smart-d24769a9-9650-4e04-b5b7-815bd9359218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361979717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.361979717
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.937970520
Short name T298
Test name
Test status
Simulation time 114555462 ps
CPU time 6.95 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:07 PM PDT 24
Peak memory 215784 kb
Host smart-52358e44-8b02-4615-9319-0b5a4df3cf95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937970520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.937970520
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2917855176
Short name T1001
Test name
Test status
Simulation time 312755714 ps
CPU time 2.83 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:15 PM PDT 24
Peak memory 214072 kb
Host smart-76d564e7-4a66-48e7-8cc9-4dd307b2b99c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917855176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2917855176
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4285549072
Short name T1
Test name
Test status
Simulation time 53407262 ps
CPU time 2.71 seconds
Started Jun 26 05:55:23 PM PDT 24
Finished Jun 26 05:55:30 PM PDT 24
Peak memory 218408 kb
Host smart-102b9b21-7ac4-4968-89f9-bb232a1e26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285549072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4285549072
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1613546622
Short name T248
Test name
Test status
Simulation time 195306438 ps
CPU time 5.71 seconds
Started Jun 26 05:55:00 PM PDT 24
Finished Jun 26 05:55:08 PM PDT 24
Peak memory 222716 kb
Host smart-2762b88f-03c0-44cf-82d9-d37d4308938e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613546622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1613546622
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2562036220
Short name T99
Test name
Test status
Simulation time 279111670 ps
CPU time 8.12 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:10 PM PDT 24
Peak memory 214320 kb
Host smart-460fdf2a-2ae2-4cfe-881b-5187c9fe5757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562036220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2562036220
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3103116573
Short name T16
Test name
Test status
Simulation time 116785626 ps
CPU time 2.62 seconds
Started Jun 26 05:55:07 PM PDT 24
Finished Jun 26 05:55:12 PM PDT 24
Peak memory 221160 kb
Host smart-ee286e3c-e3f8-40b5-9480-4a4d812b314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103116573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3103116573
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3312218479
Short name T54
Test name
Test status
Simulation time 21009897138 ps
CPU time 92.73 seconds
Started Jun 26 05:56:19 PM PDT 24
Finished Jun 26 05:58:06 PM PDT 24
Peak memory 222468 kb
Host smart-5e309e8c-5177-4e63-9b63-5b18aa5a71dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312218479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3312218479
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.4197202011
Short name T42
Test name
Test status
Simulation time 137476624 ps
CPU time 2.91 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:17 PM PDT 24
Peak memory 210856 kb
Host smart-95a3135c-bd8c-4664-99ed-1c30196e87e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197202011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4197202011
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.293940913
Short name T277
Test name
Test status
Simulation time 554940596 ps
CPU time 22.9 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:19 PM PDT 24
Peak memory 216224 kb
Host smart-a8c288d0-5ca7-4faa-bc8a-9f90212de2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293940913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.293940913
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1907907713
Short name T84
Test name
Test status
Simulation time 783446960 ps
CPU time 39.78 seconds
Started Jun 26 05:54:51 PM PDT 24
Finished Jun 26 05:55:33 PM PDT 24
Peak memory 222588 kb
Host smart-2a513d3c-09ac-44c8-9b95-dfa05725ab2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907907713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1907907713
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.387992533
Short name T435
Test name
Test status
Simulation time 51817979 ps
CPU time 0.8 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:32 PM PDT 24
Peak memory 206072 kb
Host smart-6f656436-78c7-43fa-8232-6d216ca8b69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387992533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.387992533
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4093780096
Short name T69
Test name
Test status
Simulation time 3379338681 ps
CPU time 32.57 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 222516 kb
Host smart-8bdd503a-ab95-433a-968d-e8aeb6f96b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093780096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4093780096
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.642464976
Short name T144
Test name
Test status
Simulation time 292586746 ps
CPU time 4.08 seconds
Started Jun 26 05:54:07 PM PDT 24
Finished Jun 26 05:54:12 PM PDT 24
Peak memory 215380 kb
Host smart-15b7472c-d477-449a-b5f1-e4f6351a88b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642464976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.642464976
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3571826713
Short name T151
Test name
Test status
Simulation time 62179212 ps
CPU time 3.18 seconds
Started Jun 26 05:54:28 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 215160 kb
Host smart-d3363b46-2e2e-43de-8771-6d8f79f5ee2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3571826713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3571826713
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3971169358
Short name T176
Test name
Test status
Simulation time 608245939 ps
CPU time 6.87 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 213644 kb
Host smart-6465c681-c719-4363-b389-66eec37918c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971169358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3971169358
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.276296691
Short name T92
Test name
Test status
Simulation time 540346298 ps
CPU time 6.09 seconds
Started Jun 26 05:56:58 PM PDT 24
Finished Jun 26 05:57:05 PM PDT 24
Peak memory 213976 kb
Host smart-89a75de1-9493-471e-b40f-63378b08f28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276296691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.276296691
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3934341937
Short name T419
Test name
Test status
Simulation time 214441977 ps
CPU time 6.15 seconds
Started Jun 26 05:54:32 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 215256 kb
Host smart-9e7a84b5-3d14-44db-bfe3-9668f2c73353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3934341937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3934341937
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.106216468
Short name T166
Test name
Test status
Simulation time 383250837 ps
CPU time 4.56 seconds
Started Jun 26 05:47:16 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 213756 kb
Host smart-cbd7f184-c08e-4e94-8045-8db5b6f2b5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106216468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
106216468
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.970331085
Short name T74
Test name
Test status
Simulation time 260763838 ps
CPU time 13.66 seconds
Started Jun 26 05:54:37 PM PDT 24
Finished Jun 26 05:54:52 PM PDT 24
Peak memory 215580 kb
Host smart-7f9bd2cf-36d7-4dcc-a653-46933cf5c5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970331085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.970331085
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.549252208
Short name T39
Test name
Test status
Simulation time 66735311 ps
CPU time 3.54 seconds
Started Jun 26 05:54:55 PM PDT 24
Finished Jun 26 05:55:00 PM PDT 24
Peak memory 220192 kb
Host smart-97462820-accf-48e2-86aa-3c72340acc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549252208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.549252208
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3512992835
Short name T297
Test name
Test status
Simulation time 3091746625 ps
CPU time 41.52 seconds
Started Jun 26 05:55:53 PM PDT 24
Finished Jun 26 05:56:46 PM PDT 24
Peak memory 216224 kb
Host smart-0bc184cb-3b2a-4a56-898e-fbf67fd07154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512992835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3512992835
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.885330552
Short name T197
Test name
Test status
Simulation time 3061136691 ps
CPU time 70.34 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:57:23 PM PDT 24
Peak memory 222556 kb
Host smart-acc9803c-c206-49e1-9514-16cb378810b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885330552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.885330552
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1796012116
Short name T172
Test name
Test status
Simulation time 229248825 ps
CPU time 5.71 seconds
Started Jun 26 05:47:35 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 213784 kb
Host smart-9a8f2417-918a-4123-bafd-c28b1efcccbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796012116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1796012116
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.969515065
Short name T156
Test name
Test status
Simulation time 92181032 ps
CPU time 3.03 seconds
Started Jun 26 05:54:23 PM PDT 24
Finished Jun 26 05:54:27 PM PDT 24
Peak memory 218188 kb
Host smart-52f0f776-0fb9-4185-81c5-3aeb5fcdfcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969515065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.969515065
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1591208487
Short name T51
Test name
Test status
Simulation time 81173137 ps
CPU time 2.8 seconds
Started Jun 26 05:56:52 PM PDT 24
Finished Jun 26 05:56:58 PM PDT 24
Peak memory 214428 kb
Host smart-9b44c34a-4c38-4cff-bf71-f2a10aad8cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591208487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1591208487
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3657961776
Short name T339
Test name
Test status
Simulation time 232803244 ps
CPU time 12.87 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:57 PM PDT 24
Peak memory 215592 kb
Host smart-ee79705b-98b0-4f57-a2f0-970a093b3cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657961776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3657961776
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3226548943
Short name T212
Test name
Test status
Simulation time 53686583 ps
CPU time 2.88 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 208500 kb
Host smart-1d3aba44-5b53-411a-a165-79302da86788
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226548943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3226548943
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1296258878
Short name T291
Test name
Test status
Simulation time 96227942 ps
CPU time 5.7 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 215232 kb
Host smart-ca0265a0-07af-4e72-b860-c74e2e1dde30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296258878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1296258878
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4019840921
Short name T179
Test name
Test status
Simulation time 184813033 ps
CPU time 4.29 seconds
Started Jun 26 05:47:08 PM PDT 24
Finished Jun 26 05:47:13 PM PDT 24
Peak memory 205540 kb
Host smart-320a7f9a-9be8-4ab9-bf8b-1445b951088f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019840921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4019840921
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2138451
Short name T159
Test name
Test status
Simulation time 505340336 ps
CPU time 9.83 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 213728 kb
Host smart-d428fae1-4039-4ea8-b435-340753fce5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.2138451
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.970801274
Short name T287
Test name
Test status
Simulation time 56766461 ps
CPU time 2.32 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:49 PM PDT 24
Peak memory 214264 kb
Host smart-76509dd4-8cff-4ce6-b0c3-3f0167f121ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970801274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.970801274
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3446564122
Short name T131
Test name
Test status
Simulation time 1441786146 ps
CPU time 12.67 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:19 PM PDT 24
Peak memory 222392 kb
Host smart-743986dc-ec41-49b7-bdea-7fc30e72bc09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446564122 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3446564122
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3119385231
Short name T136
Test name
Test status
Simulation time 520171100 ps
CPU time 20.95 seconds
Started Jun 26 05:55:45 PM PDT 24
Finished Jun 26 05:56:12 PM PDT 24
Peak memory 221180 kb
Host smart-9b3e2bdb-15c2-4c03-86a5-7e2cf875ec2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119385231 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3119385231
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3379891472
Short name T140
Test name
Test status
Simulation time 529882535 ps
CPU time 5.38 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 214176 kb
Host smart-aa7aee08-863c-4109-a08a-fd6e8a3c0021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3379891472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3379891472
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4198211639
Short name T67
Test name
Test status
Simulation time 52940786 ps
CPU time 2.75 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 210192 kb
Host smart-02073923-5b48-48fb-9165-be56b7d2f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198211639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4198211639
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.150495853
Short name T390
Test name
Test status
Simulation time 39051457 ps
CPU time 2.53 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 222444 kb
Host smart-bf5b553c-34cc-407d-b930-774831dcfe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150495853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.150495853
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3970930530
Short name T228
Test name
Test status
Simulation time 8637322631 ps
CPU time 48.93 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:56:04 PM PDT 24
Peak memory 216280 kb
Host smart-b6e01b45-11b8-4fbd-825d-d1f021e9e6f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970930530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3970930530
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1238785238
Short name T376
Test name
Test status
Simulation time 62377508 ps
CPU time 2.06 seconds
Started Jun 26 05:55:36 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 214348 kb
Host smart-23a20c2e-0706-4d34-af3b-f634d3309e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238785238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1238785238
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.785678684
Short name T424
Test name
Test status
Simulation time 373695748 ps
CPU time 3.44 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:17 PM PDT 24
Peak memory 214320 kb
Host smart-a862d084-671e-41d2-8056-ec8a0dae548c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785678684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.785678684
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3521136271
Short name T152
Test name
Test status
Simulation time 81032107 ps
CPU time 2.52 seconds
Started Jun 26 05:54:54 PM PDT 24
Finished Jun 26 05:54:58 PM PDT 24
Peak memory 217140 kb
Host smart-3890f9d1-0fed-4c0f-83a5-d5ca7f0e7aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521136271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3521136271
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.161239673
Short name T154
Test name
Test status
Simulation time 421632951 ps
CPU time 4.43 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 218280 kb
Host smart-8eef8813-025d-4f76-8b4f-e2455d8d40fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161239673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.161239673
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3607329455
Short name T155
Test name
Test status
Simulation time 48889308 ps
CPU time 2.01 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:03 PM PDT 24
Peak memory 216952 kb
Host smart-c4a91482-a0ed-4016-b461-c4f7e4973a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607329455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3607329455
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2579823440
Short name T345
Test name
Test status
Simulation time 2251652316 ps
CPU time 25.73 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:55:12 PM PDT 24
Peak memory 215972 kb
Host smart-42b73c28-9fa8-42ec-a819-fcce47295d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579823440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2579823440
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_random.1001739556
Short name T321
Test name
Test status
Simulation time 31490244 ps
CPU time 2.69 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 208352 kb
Host smart-fbd77498-8b73-4ffc-bd16-03e5e69b4f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001739556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1001739556
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2824205370
Short name T230
Test name
Test status
Simulation time 685278306 ps
CPU time 12.14 seconds
Started Jun 26 05:55:00 PM PDT 24
Finished Jun 26 05:55:14 PM PDT 24
Peak memory 215252 kb
Host smart-a3aff11c-ef21-42e8-b0ac-8954fb48f838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824205370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2824205370
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3947767936
Short name T242
Test name
Test status
Simulation time 75396027 ps
CPU time 2.72 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 214264 kb
Host smart-73fcce95-392d-4691-b460-0343c88e79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947767936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3947767936
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3503339075
Short name T221
Test name
Test status
Simulation time 2072932942 ps
CPU time 46.58 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:57:06 PM PDT 24
Peak memory 222420 kb
Host smart-3d057010-1237-4e4b-8042-684b1ea58d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503339075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3503339075
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.894931277
Short name T237
Test name
Test status
Simulation time 38905697 ps
CPU time 2.98 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 214428 kb
Host smart-d0438bff-a8b6-4fd4-829b-293267112228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894931277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.894931277
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2476503936
Short name T355
Test name
Test status
Simulation time 1891912869 ps
CPU time 50.56 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:54 PM PDT 24
Peak memory 215520 kb
Host smart-d0a3d391-1873-44f5-ba94-e0df7b1b62ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476503936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2476503936
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3713001565
Short name T222
Test name
Test status
Simulation time 3930179748 ps
CPU time 37.79 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:55:01 PM PDT 24
Peak memory 215120 kb
Host smart-86b4f991-1512-45f7-880c-d115bf91b889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713001565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3713001565
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2665321143
Short name T178
Test name
Test status
Simulation time 778174599 ps
CPU time 8.47 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 215140 kb
Host smart-319d05dc-ecaa-415e-be16-3c3bf571f953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665321143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2665321143
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3247034868
Short name T183
Test name
Test status
Simulation time 70577899 ps
CPU time 3.11 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:41 PM PDT 24
Peak memory 215028 kb
Host smart-1ab54d65-45bd-4a2f-83c8-974fc21c1abd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247034868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3247034868
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3494413305
Short name T171
Test name
Test status
Simulation time 208963033 ps
CPU time 7.05 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 205544 kb
Host smart-19af5779-9f71-4975-8965-43fdf3858159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494413305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3494413305
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3376667643
Short name T167
Test name
Test status
Simulation time 399252012 ps
CPU time 5.91 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 213616 kb
Host smart-796d2918-95bb-4150-abc8-860f8b0c2e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376667643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3376667643
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3956871935
Short name T48
Test name
Test status
Simulation time 226830525 ps
CPU time 4.97 seconds
Started Jun 26 05:53:51 PM PDT 24
Finished Jun 26 05:53:56 PM PDT 24
Peak memory 237132 kb
Host smart-bb940b23-8b8a-43c7-95ff-e62165ea0395
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956871935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3956871935
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2919153408
Short name T36
Test name
Test status
Simulation time 60779969 ps
CPU time 3.01 seconds
Started Jun 26 05:54:55 PM PDT 24
Finished Jun 26 05:54:59 PM PDT 24
Peak memory 221892 kb
Host smart-9eb4b22d-bcf3-484c-87ed-8c6832084f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919153408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2919153408
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3485379022
Short name T181
Test name
Test status
Simulation time 614404510 ps
CPU time 9.71 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:38 PM PDT 24
Peak memory 210708 kb
Host smart-961e918c-457d-4c33-b09f-11c3d509be06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485379022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3485379022
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.550713843
Short name T158
Test name
Test status
Simulation time 80282037 ps
CPU time 4.35 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 217900 kb
Host smart-8f0a2601-342c-4832-8415-3917cd2b58b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550713843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.550713843
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3315459261
Short name T157
Test name
Test status
Simulation time 187264015 ps
CPU time 2.94 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:56:58 PM PDT 24
Peak memory 217788 kb
Host smart-5c9222c5-51ed-4f63-ae2b-6bd4028a557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315459261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3315459261
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3135162516
Short name T153
Test name
Test status
Simulation time 252616666 ps
CPU time 4.18 seconds
Started Jun 26 05:54:09 PM PDT 24
Finished Jun 26 05:54:15 PM PDT 24
Peak memory 215332 kb
Host smart-efec84bd-0a53-4dda-91db-97ab982265f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135162516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3135162516
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3107621733
Short name T392
Test name
Test status
Simulation time 132230550 ps
CPU time 4.36 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:53:59 PM PDT 24
Peak memory 221492 kb
Host smart-a677e8d0-e4aa-4723-ad89-f8da76607026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107621733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3107621733
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1322497124
Short name T793
Test name
Test status
Simulation time 88620166 ps
CPU time 3.69 seconds
Started Jun 26 05:54:33 PM PDT 24
Finished Jun 26 05:54:38 PM PDT 24
Peak memory 206980 kb
Host smart-b041b421-612b-4ff0-8d6e-868fd10f43d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322497124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1322497124
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2520739398
Short name T489
Test name
Test status
Simulation time 299604318 ps
CPU time 3.48 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:34 PM PDT 24
Peak memory 208920 kb
Host smart-04d8cfc5-9a96-4776-925c-97dbed230d7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520739398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2520739398
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.96969020
Short name T170
Test name
Test status
Simulation time 182038821 ps
CPU time 2.15 seconds
Started Jun 26 05:54:38 PM PDT 24
Finished Jun 26 05:54:41 PM PDT 24
Peak memory 210376 kb
Host smart-d6e7281e-c8ad-4f60-a62d-e180e2b2183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96969020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.96969020
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3041593971
Short name T235
Test name
Test status
Simulation time 58360816 ps
CPU time 4.1 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 208224 kb
Host smart-74c3619b-95e7-4105-8459-fd6252f0d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041593971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3041593971
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.775268700
Short name T233
Test name
Test status
Simulation time 854128730 ps
CPU time 27.85 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:55:14 PM PDT 24
Peak memory 222960 kb
Host smart-c9d70353-92c2-4fe9-9bb4-2ea8b081b2c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775268700 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.775268700
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2928930508
Short name T220
Test name
Test status
Simulation time 176242485 ps
CPU time 1.74 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:54:56 PM PDT 24
Peak memory 222768 kb
Host smart-b6873fcd-3521-4ebe-ae9e-fb88ca3db931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928930508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2928930508
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2088151217
Short name T746
Test name
Test status
Simulation time 104448508 ps
CPU time 2.08 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 207180 kb
Host smart-874a165d-b589-4414-9f7b-c31f87730bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088151217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2088151217
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1942664953
Short name T331
Test name
Test status
Simulation time 130095681 ps
CPU time 2.66 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 214228 kb
Host smart-310794a7-908b-47ff-904b-ac4e4f423e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942664953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1942664953
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2923340863
Short name T47
Test name
Test status
Simulation time 683826506 ps
CPU time 11.44 seconds
Started Jun 26 05:54:54 PM PDT 24
Finished Jun 26 05:55:07 PM PDT 24
Peak memory 208888 kb
Host smart-787c0419-372b-4f78-ad7d-a72c9003780e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923340863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2923340863
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2346650580
Short name T884
Test name
Test status
Simulation time 326579390 ps
CPU time 3.02 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:09 PM PDT 24
Peak memory 214180 kb
Host smart-81afb475-9886-4d87-b171-859133f4364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346650580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2346650580
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3459304840
Short name T87
Test name
Test status
Simulation time 38176006 ps
CPU time 1.62 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 214236 kb
Host smart-966ae732-bbae-4489-8ec2-9bcd64a231cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459304840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3459304840
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1106721649
Short name T93
Test name
Test status
Simulation time 2650398040 ps
CPU time 35.49 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:56:19 PM PDT 24
Peak memory 214404 kb
Host smart-670e467f-32a8-4e04-a5c2-c24489ac3249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106721649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1106721649
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1565637405
Short name T416
Test name
Test status
Simulation time 131382837 ps
CPU time 2.07 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:34 PM PDT 24
Peak memory 214324 kb
Host smart-e677ba98-feff-43de-abf8-ea2eb03cee63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565637405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1565637405
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1258662718
Short name T415
Test name
Test status
Simulation time 1198997857 ps
CPU time 61.14 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 215248 kb
Host smart-ab6cd7b2-7de3-4be7-b424-b64faab5d998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258662718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1258662718
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1567121883
Short name T215
Test name
Test status
Simulation time 339058401 ps
CPU time 3.11 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 214284 kb
Host smart-dde75093-ef34-4f32-a80b-fbc095eeb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567121883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1567121883
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3866489203
Short name T52
Test name
Test status
Simulation time 81318940 ps
CPU time 1.73 seconds
Started Jun 26 05:55:41 PM PDT 24
Finished Jun 26 05:55:49 PM PDT 24
Peak memory 214188 kb
Host smart-77f93960-1387-42f2-8dc2-ed98c6559e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866489203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3866489203
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3290445152
Short name T229
Test name
Test status
Simulation time 286851862 ps
CPU time 15.77 seconds
Started Jun 26 05:55:46 PM PDT 24
Finished Jun 26 05:56:09 PM PDT 24
Peak memory 215712 kb
Host smart-e2aa0068-579f-4032-8434-aeddc90aaf1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290445152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3290445152
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3811303542
Short name T374
Test name
Test status
Simulation time 49224545518 ps
CPU time 333.26 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 06:01:59 PM PDT 24
Peak memory 219000 kb
Host smart-78009117-d42d-483a-bc27-783be1edfd20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811303542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3811303542
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.160333243
Short name T417
Test name
Test status
Simulation time 314029065 ps
CPU time 4.64 seconds
Started Jun 26 05:56:21 PM PDT 24
Finished Jun 26 05:56:42 PM PDT 24
Peak memory 214348 kb
Host smart-af4aba8f-be94-41fc-9d53-9660caf1eb7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160333243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.160333243
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.43968804
Short name T232
Test name
Test status
Simulation time 510858904 ps
CPU time 22.35 seconds
Started Jun 26 05:56:38 PM PDT 24
Finished Jun 26 05:57:11 PM PDT 24
Peak memory 217124 kb
Host smart-26d84772-73e7-4f5e-876b-67da6d94dc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43968804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.43968804
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3474919173
Short name T342
Test name
Test status
Simulation time 1528568457 ps
CPU time 5.3 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 208632 kb
Host smart-d21d6c56-b223-4489-8088-ae43ebce42e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474919173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3474919173
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2664295776
Short name T198
Test name
Test status
Simulation time 5941486474 ps
CPU time 33.31 seconds
Started Jun 26 05:56:59 PM PDT 24
Finished Jun 26 05:57:33 PM PDT 24
Peak memory 222560 kb
Host smart-d84f34c2-36b5-4fbf-9a2f-5b652d878a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664295776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2664295776
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2120553612
Short name T145
Test name
Test status
Simulation time 1021713057 ps
CPU time 17.32 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 205528 kb
Host smart-58cac18d-aec5-4dd5-8878-87f7a93bfe33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120553612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
120553612
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1470731181
Short name T1049
Test name
Test status
Simulation time 1813717238 ps
CPU time 7.52 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:12 PM PDT 24
Peak memory 205428 kb
Host smart-8558c74f-78c1-4744-8aa7-12b74c9d9ea1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470731181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
470731181
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3112137643
Short name T1025
Test name
Test status
Simulation time 31089065 ps
CPU time 1.14 seconds
Started Jun 26 05:47:06 PM PDT 24
Finished Jun 26 05:47:08 PM PDT 24
Peak memory 205480 kb
Host smart-1ba04913-904f-4ef5-8db4-9bca0fd1441b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112137643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
112137643
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2761176518
Short name T1047
Test name
Test status
Simulation time 32046553 ps
CPU time 1.09 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:07 PM PDT 24
Peak memory 205500 kb
Host smart-53183d51-2d4b-4cbc-8fe4-73bf475635d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761176518 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2761176518
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1540197185
Short name T990
Test name
Test status
Simulation time 24501924 ps
CPU time 1.53 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:06 PM PDT 24
Peak memory 205416 kb
Host smart-99b2948b-3b10-44ce-91c3-8198dfdde4b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540197185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1540197185
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2378621874
Short name T973
Test name
Test status
Simulation time 32014489 ps
CPU time 0.71 seconds
Started Jun 26 05:47:06 PM PDT 24
Finished Jun 26 05:47:08 PM PDT 24
Peak memory 205384 kb
Host smart-aca55be1-ac0d-4949-8e1b-765d654923b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378621874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2378621874
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.275529776
Short name T148
Test name
Test status
Simulation time 92375173 ps
CPU time 1.79 seconds
Started Jun 26 05:47:07 PM PDT 24
Finished Jun 26 05:47:10 PM PDT 24
Peak memory 205548 kb
Host smart-d4803137-4c46-4618-afc5-bc6cacb7ff5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275529776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.275529776
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.822626214
Short name T1036
Test name
Test status
Simulation time 606247667 ps
CPU time 4.84 seconds
Started Jun 26 05:46:58 PM PDT 24
Finished Jun 26 05:47:05 PM PDT 24
Peak memory 222148 kb
Host smart-c66ae5b7-b4a3-4675-aa42-9a89e7e859bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822626214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.822626214
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.499498845
Short name T989
Test name
Test status
Simulation time 105626432 ps
CPU time 3.59 seconds
Started Jun 26 05:46:55 PM PDT 24
Finished Jun 26 05:47:00 PM PDT 24
Peak memory 213964 kb
Host smart-a8174b5f-4111-43be-a16d-3b760bb57b84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499498845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.499498845
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2547468204
Short name T977
Test name
Test status
Simulation time 75286948 ps
CPU time 2.9 seconds
Started Jun 26 05:47:05 PM PDT 24
Finished Jun 26 05:47:09 PM PDT 24
Peak memory 213700 kb
Host smart-785ade9a-9bee-4153-a585-3bcbc42b6b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547468204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2547468204
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2170998147
Short name T956
Test name
Test status
Simulation time 1484218941 ps
CPU time 8.99 seconds
Started Jun 26 05:47:06 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 205592 kb
Host smart-24ff10e4-ad7e-4048-8bec-7d9542b17074
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170998147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
170998147
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.467279476
Short name T1059
Test name
Test status
Simulation time 135364305 ps
CPU time 7.78 seconds
Started Jun 26 05:47:03 PM PDT 24
Finished Jun 26 05:47:11 PM PDT 24
Peak memory 205536 kb
Host smart-68fbc0bf-1e1a-4d76-b6d7-a8f57e3c25db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467279476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.467279476
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2237484859
Short name T1030
Test name
Test status
Simulation time 37186404 ps
CPU time 1.36 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:14 PM PDT 24
Peak memory 205464 kb
Host smart-6a521351-2237-44d0-aa33-51cf1e1df4c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237484859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
237484859
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.416927687
Short name T966
Test name
Test status
Simulation time 43544264 ps
CPU time 1.68 seconds
Started Jun 26 05:47:03 PM PDT 24
Finished Jun 26 05:47:05 PM PDT 24
Peak memory 213628 kb
Host smart-3870a042-5bf6-401d-bcd2-dd1943ccb86d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416927687 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.416927687
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1987575922
Short name T993
Test name
Test status
Simulation time 73295762 ps
CPU time 1.28 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:06 PM PDT 24
Peak memory 205384 kb
Host smart-98cfbc09-c59b-4a83-be44-a440370551d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987575922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1987575922
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1833031415
Short name T1003
Test name
Test status
Simulation time 50189018 ps
CPU time 0.84 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:14 PM PDT 24
Peak memory 205352 kb
Host smart-49dc1d86-998b-493a-a2e2-51d9bb4b2855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833031415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1833031415
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3635862585
Short name T146
Test name
Test status
Simulation time 239255128 ps
CPU time 2.4 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:07 PM PDT 24
Peak memory 205520 kb
Host smart-d97a7de1-557f-499d-a562-66134191f1bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635862585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3635862585
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.645909334
Short name T120
Test name
Test status
Simulation time 444623927 ps
CPU time 5.33 seconds
Started Jun 26 05:47:06 PM PDT 24
Finished Jun 26 05:47:12 PM PDT 24
Peak memory 220132 kb
Host smart-da92b801-6b47-444f-a854-1312647b2e0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645909334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.645909334
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1101548569
Short name T957
Test name
Test status
Simulation time 75689478 ps
CPU time 2.58 seconds
Started Jun 26 05:47:04 PM PDT 24
Finished Jun 26 05:47:08 PM PDT 24
Peak memory 213660 kb
Host smart-29a26fc3-ab86-4430-9ee2-a777a3bb251c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101548569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1101548569
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1709256230
Short name T175
Test name
Test status
Simulation time 75948869 ps
CPU time 2.8 seconds
Started Jun 26 05:47:06 PM PDT 24
Finished Jun 26 05:47:10 PM PDT 24
Peak memory 213696 kb
Host smart-b7058c6d-5302-4b4a-b3ac-7f526c51f70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709256230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1709256230
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1883241481
Short name T1078
Test name
Test status
Simulation time 35285343 ps
CPU time 1.47 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 218768 kb
Host smart-64f6b37a-c436-4729-b86b-4fe198d1a05d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883241481 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1883241481
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1619393811
Short name T1071
Test name
Test status
Simulation time 13926654 ps
CPU time 1.27 seconds
Started Jun 26 05:47:28 PM PDT 24
Finished Jun 26 05:47:30 PM PDT 24
Peak memory 205600 kb
Host smart-ff839ba1-fa3f-4fdf-81a0-cbacd6c22797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619393811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1619393811
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2554229829
Short name T1017
Test name
Test status
Simulation time 22754587 ps
CPU time 0.76 seconds
Started Jun 26 05:47:26 PM PDT 24
Finished Jun 26 05:47:28 PM PDT 24
Peak memory 205376 kb
Host smart-9f2d171b-b14d-486a-a63f-66f5fe2af397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554229829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2554229829
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2326469316
Short name T1016
Test name
Test status
Simulation time 187787023 ps
CPU time 3.8 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:41 PM PDT 24
Peak memory 205412 kb
Host smart-240e7b43-0821-4dcf-bdf0-f15d59a2bc2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326469316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2326469316
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2719134273
Short name T1039
Test name
Test status
Simulation time 178061239 ps
CPU time 1.55 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 214104 kb
Host smart-08815ff1-20d2-4219-ad31-d52698a2cbd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719134273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2719134273
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3828764915
Short name T1002
Test name
Test status
Simulation time 257875212 ps
CPU time 6.64 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 214092 kb
Host smart-b78c4897-41de-4d6b-91f4-aab5a6cddda9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828764915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3828764915
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2993405080
Short name T1083
Test name
Test status
Simulation time 181725947 ps
CPU time 3.09 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:33 PM PDT 24
Peak memory 213684 kb
Host smart-5eeed742-618c-4d31-ab3b-625a139c6018
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993405080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2993405080
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.970063644
Short name T174
Test name
Test status
Simulation time 341194216 ps
CPU time 5.04 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 213584 kb
Host smart-82747aa8-d04c-4853-92bd-c4e2cd48df3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970063644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.970063644
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2005547930
Short name T997
Test name
Test status
Simulation time 50684236 ps
CPU time 2.23 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 213704 kb
Host smart-6bbd89a5-b380-417b-bc53-bcf05d529f08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005547930 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2005547930
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2543871632
Short name T398
Test name
Test status
Simulation time 75868472 ps
CPU time 0.93 seconds
Started Jun 26 05:47:38 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 205392 kb
Host smart-09f9b6f2-265e-4302-b932-49a28f547058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543871632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2543871632
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2686757647
Short name T938
Test name
Test status
Simulation time 9396743 ps
CPU time 0.82 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 205244 kb
Host smart-d221cd7e-0125-42b9-a138-01a83a5f9fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686757647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2686757647
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.803710469
Short name T1015
Test name
Test status
Simulation time 22388779 ps
CPU time 1.69 seconds
Started Jun 26 05:47:40 PM PDT 24
Finished Jun 26 05:47:43 PM PDT 24
Peak memory 205516 kb
Host smart-d8cbce52-1aec-4b4f-94a6-4e8ea6e41a84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803710469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.803710469
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2328870777
Short name T1037
Test name
Test status
Simulation time 99864034 ps
CPU time 1.11 seconds
Started Jun 26 05:47:34 PM PDT 24
Finished Jun 26 05:47:36 PM PDT 24
Peak memory 214004 kb
Host smart-84c25579-9b01-4db0-929a-f37ac053382a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328870777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2328870777
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.369563642
Short name T1018
Test name
Test status
Simulation time 164720883 ps
CPU time 4.93 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 214012 kb
Host smart-9ae12539-91b2-40b1-b84a-8ecccb010252
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369563642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.369563642
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1732012201
Short name T934
Test name
Test status
Simulation time 126762139 ps
CPU time 3.53 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:41 PM PDT 24
Peak memory 213796 kb
Host smart-be236a24-694c-4089-aabe-eab2dfa72c39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732012201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1732012201
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.836977360
Short name T947
Test name
Test status
Simulation time 259158880 ps
CPU time 1.65 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 213792 kb
Host smart-254332d0-c0e0-4b25-bd1f-96f9ced5f34b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836977360 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.836977360
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.294933414
Short name T968
Test name
Test status
Simulation time 16991815 ps
CPU time 1.11 seconds
Started Jun 26 05:47:38 PM PDT 24
Finished Jun 26 05:47:41 PM PDT 24
Peak memory 205540 kb
Host smart-cc3d1a0d-15b2-4022-854c-ea8b8c3e33dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294933414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.294933414
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3832412517
Short name T931
Test name
Test status
Simulation time 27145454 ps
CPU time 0.75 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 205380 kb
Host smart-45a35566-2e26-401f-b451-7c85afa65be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832412517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3832412517
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4090446925
Short name T975
Test name
Test status
Simulation time 368778622 ps
CPU time 2.54 seconds
Started Jun 26 05:47:38 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 205456 kb
Host smart-23f89265-6521-46e0-83e2-363b128da2e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090446925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4090446925
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.435881790
Short name T121
Test name
Test status
Simulation time 159032386 ps
CPU time 4.44 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 218504 kb
Host smart-1dbb2e2c-43b1-44be-9b85-4c651dca75c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435881790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.435881790
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.286791551
Short name T991
Test name
Test status
Simulation time 238793561 ps
CPU time 8.84 seconds
Started Jun 26 05:47:40 PM PDT 24
Finished Jun 26 05:47:50 PM PDT 24
Peak memory 213940 kb
Host smart-3854b26d-7c89-4fc6-91ce-f20dc252af9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286791551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.286791551
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1909868529
Short name T952
Test name
Test status
Simulation time 218971294 ps
CPU time 2.49 seconds
Started Jun 26 05:47:34 PM PDT 24
Finished Jun 26 05:47:38 PM PDT 24
Peak memory 213640 kb
Host smart-1ac239b7-f993-4577-b268-134292cd82b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909868529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1909868529
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1531086139
Short name T1022
Test name
Test status
Simulation time 62299096 ps
CPU time 1.14 seconds
Started Jun 26 05:47:34 PM PDT 24
Finished Jun 26 05:47:37 PM PDT 24
Peak memory 205592 kb
Host smart-6deca898-a7b9-43c0-8c9c-5fe299ee6af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531086139 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1531086139
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1086702926
Short name T147
Test name
Test status
Simulation time 15321219 ps
CPU time 1.26 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 205508 kb
Host smart-1b82bfe8-b939-4295-b627-216f7a416b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086702926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1086702926
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1721363402
Short name T951
Test name
Test status
Simulation time 26875964 ps
CPU time 0.82 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 205388 kb
Host smart-53aae224-5061-4aac-ab6e-c800cd404a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721363402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1721363402
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1291697260
Short name T964
Test name
Test status
Simulation time 85192574 ps
CPU time 1.83 seconds
Started Jun 26 05:47:38 PM PDT 24
Finished Jun 26 05:47:41 PM PDT 24
Peak memory 205500 kb
Host smart-fb6e8c6d-5542-49ef-851f-c70af26ac4e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291697260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1291697260
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.361867380
Short name T1027
Test name
Test status
Simulation time 470621811 ps
CPU time 2.67 seconds
Started Jun 26 05:47:38 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 213944 kb
Host smart-f6ad2382-573d-4504-91ab-06a9f3d611bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361867380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.361867380
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1397662828
Short name T1074
Test name
Test status
Simulation time 332848941 ps
CPU time 8.83 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 213936 kb
Host smart-d4f0cf1e-884f-411a-85ff-eeee50ab039f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397662828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1397662828
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3039316503
Short name T1057
Test name
Test status
Simulation time 184585932 ps
CPU time 2.16 seconds
Started Jun 26 05:47:40 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 213736 kb
Host smart-46cae406-95dc-40a2-8cd8-113ead717ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039316503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3039316503
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2507813996
Short name T1079
Test name
Test status
Simulation time 50429587 ps
CPU time 1.62 seconds
Started Jun 26 05:47:36 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 213852 kb
Host smart-d92753c3-2980-4011-a46e-e8b65719a127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507813996 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2507813996
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1309040555
Short name T1066
Test name
Test status
Simulation time 17246674 ps
CPU time 1.2 seconds
Started Jun 26 05:47:35 PM PDT 24
Finished Jun 26 05:47:38 PM PDT 24
Peak memory 205448 kb
Host smart-3cf9b1ea-d81e-462f-8937-ab515f687d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309040555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1309040555
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1981894156
Short name T981
Test name
Test status
Simulation time 21508437 ps
CPU time 0.72 seconds
Started Jun 26 05:47:35 PM PDT 24
Finished Jun 26 05:47:37 PM PDT 24
Peak memory 205424 kb
Host smart-a8fc505c-d878-4539-97d1-1765ca6a17e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981894156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1981894156
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3904637365
Short name T1000
Test name
Test status
Simulation time 21876811 ps
CPU time 1.85 seconds
Started Jun 26 05:47:38 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 205564 kb
Host smart-173a8023-adc7-41d6-b794-60ba2dc837c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904637365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3904637365
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1637076093
Short name T1062
Test name
Test status
Simulation time 662432854 ps
CPU time 3.66 seconds
Started Jun 26 05:47:39 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 214012 kb
Host smart-8ba6c4e4-0f6e-4a63-a6a7-a8f6eeb69cc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637076093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1637076093
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1184453877
Short name T125
Test name
Test status
Simulation time 1497583773 ps
CPU time 12.2 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 214036 kb
Host smart-f9e0a9e8-82a2-459c-8bf5-5310f3af5663
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184453877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1184453877
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1158078244
Short name T922
Test name
Test status
Simulation time 42204929 ps
CPU time 1.7 seconds
Started Jun 26 05:47:40 PM PDT 24
Finished Jun 26 05:47:43 PM PDT 24
Peak memory 213812 kb
Host smart-d84a19ec-1455-484f-b081-a000f1d02015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158078244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1158078244
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1833384358
Short name T941
Test name
Test status
Simulation time 57182291 ps
CPU time 2.35 seconds
Started Jun 26 05:47:46 PM PDT 24
Finished Jun 26 05:47:50 PM PDT 24
Peak memory 213800 kb
Host smart-527fc95e-1ab7-436f-9fec-d37120bd387e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833384358 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1833384358
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2716185089
Short name T397
Test name
Test status
Simulation time 28781270 ps
CPU time 1.24 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 205512 kb
Host smart-e3cdbd8f-40b6-41ab-ae56-b2ea31638648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716185089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2716185089
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.646646328
Short name T936
Test name
Test status
Simulation time 9984752 ps
CPU time 0.83 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205324 kb
Host smart-6d43a5b2-5d52-457b-bde7-5cc512cd1f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646646328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.646646328
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3399067374
Short name T1063
Test name
Test status
Simulation time 500023193 ps
CPU time 2.48 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 205564 kb
Host smart-19552445-13d3-4716-9c2f-1008692b9520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399067374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3399067374
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1879708258
Short name T976
Test name
Test status
Simulation time 135488275 ps
CPU time 3.52 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 213964 kb
Host smart-aaead86e-5a27-4553-82bc-40071797850d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879708258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1879708258
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3118137187
Short name T1011
Test name
Test status
Simulation time 295814545 ps
CPU time 3.68 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:43 PM PDT 24
Peak memory 219860 kb
Host smart-e2607605-05e7-4a39-a82a-2e6943ffae4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118137187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3118137187
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.691333273
Short name T1076
Test name
Test status
Simulation time 396075922 ps
CPU time 4.66 seconds
Started Jun 26 05:47:37 PM PDT 24
Finished Jun 26 05:47:43 PM PDT 24
Peak memory 216948 kb
Host smart-c61ab422-7b0e-4c22-81d6-dcf5cdd752e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691333273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.691333273
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3273897884
Short name T992
Test name
Test status
Simulation time 164840430 ps
CPU time 1.55 seconds
Started Jun 26 05:47:42 PM PDT 24
Finished Jun 26 05:47:45 PM PDT 24
Peak memory 213564 kb
Host smart-f28a1223-f552-4e0c-9d06-b660d9257f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273897884 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3273897884
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1823714704
Short name T969
Test name
Test status
Simulation time 42645311 ps
CPU time 0.98 seconds
Started Jun 26 05:47:42 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 205456 kb
Host smart-ee36f656-dca8-4829-b208-b84cf825ffa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823714704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1823714704
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3355451772
Short name T1072
Test name
Test status
Simulation time 36104316 ps
CPU time 0.79 seconds
Started Jun 26 05:47:44 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 205268 kb
Host smart-af0fe943-8d73-430e-8fa7-4afa8cf0582c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355451772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3355451772
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.964805616
Short name T1064
Test name
Test status
Simulation time 81967063 ps
CPU time 1.92 seconds
Started Jun 26 05:47:44 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 205436 kb
Host smart-3b039a7a-bcaf-438f-808a-321fde18de39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964805616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.964805616
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.115404636
Short name T1031
Test name
Test status
Simulation time 168982855 ps
CPU time 4.15 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 213964 kb
Host smart-0f022205-44fd-4816-860c-f417491b443f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115404636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.115404636
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3890976216
Short name T1048
Test name
Test status
Simulation time 373538745 ps
CPU time 11.22 seconds
Started Jun 26 05:47:41 PM PDT 24
Finished Jun 26 05:47:54 PM PDT 24
Peak memory 214064 kb
Host smart-6e282777-8626-49cf-b2ce-229fab7a1fdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890976216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3890976216
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.288747338
Short name T929
Test name
Test status
Simulation time 151845307 ps
CPU time 1.36 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 205636 kb
Host smart-37e265c9-e8dd-44b3-b9be-1bf50c18a499
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288747338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.288747338
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2262807698
Short name T165
Test name
Test status
Simulation time 185142578 ps
CPU time 3.02 seconds
Started Jun 26 05:47:42 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 213788 kb
Host smart-562b35be-25fb-4af1-9c2c-e976e891ba86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262807698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2262807698
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1224749109
Short name T998
Test name
Test status
Simulation time 170969371 ps
CPU time 1.16 seconds
Started Jun 26 05:47:41 PM PDT 24
Finished Jun 26 05:47:43 PM PDT 24
Peak memory 213708 kb
Host smart-bc7a135c-ab8e-470d-aceb-848dcbb1138a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224749109 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1224749109
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1395904258
Short name T960
Test name
Test status
Simulation time 34259275 ps
CPU time 0.96 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 205468 kb
Host smart-8ac70073-7517-4101-9589-f65f3b836252
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395904258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1395904258
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.476512925
Short name T1008
Test name
Test status
Simulation time 37962493 ps
CPU time 0.75 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 205348 kb
Host smart-e19659d3-e1bd-4a6e-92fb-2a05f447aace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476512925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.476512925
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2333630036
Short name T958
Test name
Test status
Simulation time 24482061 ps
CPU time 1.73 seconds
Started Jun 26 05:47:42 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 205496 kb
Host smart-ebae45f3-6255-454a-af36-b886cf785098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333630036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2333630036
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1722912334
Short name T124
Test name
Test status
Simulation time 196228005 ps
CPU time 5.66 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:53 PM PDT 24
Peak memory 213984 kb
Host smart-d9e06e40-0b86-4023-9ed8-1053f0b07e84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722912334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1722912334
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1333567468
Short name T114
Test name
Test status
Simulation time 854090578 ps
CPU time 5.43 seconds
Started Jun 26 05:47:48 PM PDT 24
Finished Jun 26 05:47:55 PM PDT 24
Peak memory 219864 kb
Host smart-974edf47-14fe-4a18-a1eb-a060aeacedc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333567468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1333567468
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.905441343
Short name T1081
Test name
Test status
Simulation time 53641649 ps
CPU time 3.12 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:50 PM PDT 24
Peak memory 213744 kb
Host smart-c004098e-c983-4b07-8024-01c2ca917e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905441343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.905441343
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1860964657
Short name T1067
Test name
Test status
Simulation time 345245320 ps
CPU time 1.39 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 213660 kb
Host smart-741c0b46-0f13-4f04-9e97-13f46c947630
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860964657 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1860964657
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2438473661
Short name T1088
Test name
Test status
Simulation time 25092513 ps
CPU time 1.03 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205372 kb
Host smart-be2d5ed3-c050-41c6-b70a-e7cd3092bbde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438473661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2438473661
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.756565687
Short name T1054
Test name
Test status
Simulation time 14296200 ps
CPU time 0.84 seconds
Started Jun 26 05:47:44 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 205396 kb
Host smart-38c90e7d-61e3-4c54-92cc-b57998fa3ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756565687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.756565687
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3513147418
Short name T996
Test name
Test status
Simulation time 187879990 ps
CPU time 1.84 seconds
Started Jun 26 05:47:42 PM PDT 24
Finished Jun 26 05:47:45 PM PDT 24
Peak memory 205472 kb
Host smart-e5cec59a-2352-4002-a6e5-82096e5350ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513147418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3513147418
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.483303416
Short name T1028
Test name
Test status
Simulation time 176423200 ps
CPU time 3.23 seconds
Started Jun 26 05:47:44 PM PDT 24
Finished Jun 26 05:47:49 PM PDT 24
Peak memory 214064 kb
Host smart-9d55e321-dd89-4cde-8a69-8329e4b51239
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483303416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.483303416
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3623952494
Short name T1041
Test name
Test status
Simulation time 676478179 ps
CPU time 6.41 seconds
Started Jun 26 05:47:53 PM PDT 24
Finished Jun 26 05:48:02 PM PDT 24
Peak memory 220068 kb
Host smart-a96ab558-e42c-4d24-8af8-0dc6647cef3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623952494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3623952494
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3133501023
Short name T937
Test name
Test status
Simulation time 234556030 ps
CPU time 2.01 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:49 PM PDT 24
Peak memory 213640 kb
Host smart-c2dac83d-0bf5-4520-9dd3-954f5523b97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133501023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3133501023
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3046700329
Short name T942
Test name
Test status
Simulation time 270621460 ps
CPU time 6.89 seconds
Started Jun 26 05:47:46 PM PDT 24
Finished Jun 26 05:47:55 PM PDT 24
Peak memory 205924 kb
Host smart-efd05523-4bfd-4679-9f2e-06e2fb9ba4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046700329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3046700329
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1824925451
Short name T961
Test name
Test status
Simulation time 48100743 ps
CPU time 1.69 seconds
Started Jun 26 05:47:44 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 213604 kb
Host smart-eb08d673-3130-4f03-85a2-2fa9c420bdaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824925451 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1824925451
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4285689371
Short name T985
Test name
Test status
Simulation time 36081404 ps
CPU time 0.92 seconds
Started Jun 26 05:47:53 PM PDT 24
Finished Jun 26 05:47:57 PM PDT 24
Peak memory 205360 kb
Host smart-bf9d406d-fa84-4ca3-a6ea-b33f3d8aa6c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285689371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4285689371
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2563291064
Short name T950
Test name
Test status
Simulation time 42463862 ps
CPU time 0.7 seconds
Started Jun 26 05:47:44 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 205232 kb
Host smart-9fb7e3cb-16e9-4f4d-b22e-9ebd2d9b2ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563291064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2563291064
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4217252834
Short name T983
Test name
Test status
Simulation time 56944494 ps
CPU time 2.35 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 205472 kb
Host smart-51708297-f41f-4c1d-9d45-9ca6da565a90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217252834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4217252834
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1139280999
Short name T117
Test name
Test status
Simulation time 232066123 ps
CPU time 2.64 seconds
Started Jun 26 05:47:41 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 213972 kb
Host smart-974631eb-d3ef-46dc-9c6a-cfbddd4094bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139280999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1139280999
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1481157653
Short name T1019
Test name
Test status
Simulation time 1419925636 ps
CPU time 8.9 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:54 PM PDT 24
Peak memory 214200 kb
Host smart-3d494c8b-bf37-44db-8e23-b59c96a0ebee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481157653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1481157653
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2238989020
Short name T1085
Test name
Test status
Simulation time 374423401 ps
CPU time 3.2 seconds
Started Jun 26 05:47:48 PM PDT 24
Finished Jun 26 05:47:53 PM PDT 24
Peak memory 213588 kb
Host smart-6894db2d-a164-4316-aeb7-164b0d0e9107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238989020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2238989020
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1488315895
Short name T182
Test name
Test status
Simulation time 407157487 ps
CPU time 3.4 seconds
Started Jun 26 05:47:46 PM PDT 24
Finished Jun 26 05:47:52 PM PDT 24
Peak memory 205644 kb
Host smart-fcdcc5c0-1f40-4763-af87-ca6f05ad0e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488315895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1488315895
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1039876958
Short name T1004
Test name
Test status
Simulation time 111450145 ps
CPU time 4.25 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:19 PM PDT 24
Peak memory 205512 kb
Host smart-533fd9aa-0b03-45cc-a2c8-4e1eff47a095
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039876958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
039876958
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.165627566
Short name T1077
Test name
Test status
Simulation time 5586619350 ps
CPU time 31.8 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 205568 kb
Host smart-44d2515e-c6b8-463a-8710-e60302b79de1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165627566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.165627566
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.646078485
Short name T1053
Test name
Test status
Simulation time 66396760 ps
CPU time 1.2 seconds
Started Jun 26 05:47:03 PM PDT 24
Finished Jun 26 05:47:05 PM PDT 24
Peak memory 205444 kb
Host smart-11fb04d4-2c4f-43ed-97c8-064332a67724
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646078485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.646078485
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.251007417
Short name T1069
Test name
Test status
Simulation time 57181225 ps
CPU time 1.58 seconds
Started Jun 26 05:47:12 PM PDT 24
Finished Jun 26 05:47:15 PM PDT 24
Peak memory 213732 kb
Host smart-fe8d3f20-8330-4c3c-96b5-774eb360e973
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251007417 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.251007417
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.21001654
Short name T945
Test name
Test status
Simulation time 22002867 ps
CPU time 1.28 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 205504 kb
Host smart-c29d4180-12c8-478b-9359-a38e3f288288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21001654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.21001654
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2202491883
Short name T972
Test name
Test status
Simulation time 35228462 ps
CPU time 0.74 seconds
Started Jun 26 05:47:03 PM PDT 24
Finished Jun 26 05:47:04 PM PDT 24
Peak memory 205304 kb
Host smart-74616ff4-394f-4fdb-9249-37158666ce7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202491883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2202491883
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1041681279
Short name T1023
Test name
Test status
Simulation time 63308861 ps
CPU time 1.79 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 205524 kb
Host smart-48e25095-248a-4977-8ea6-66eb02e0b84c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041681279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1041681279
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.104329842
Short name T118
Test name
Test status
Simulation time 373607188 ps
CPU time 2.67 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:14 PM PDT 24
Peak memory 213972 kb
Host smart-77554d15-3e23-44b3-8f3d-2739c360c70a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104329842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.104329842
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4132836846
Short name T123
Test name
Test status
Simulation time 325524562 ps
CPU time 4.56 seconds
Started Jun 26 05:47:08 PM PDT 24
Finished Jun 26 05:47:14 PM PDT 24
Peak memory 213992 kb
Host smart-77262664-b6d9-4d0e-b034-bb58f73a662f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132836846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4132836846
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.732248111
Short name T948
Test name
Test status
Simulation time 620923356 ps
CPU time 2.95 seconds
Started Jun 26 05:47:07 PM PDT 24
Finished Jun 26 05:47:11 PM PDT 24
Peak memory 216932 kb
Host smart-419690e1-7204-489d-9f16-5a2946403ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732248111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.732248111
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3483542077
Short name T184
Test name
Test status
Simulation time 1847758283 ps
CPU time 8.1 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:21 PM PDT 24
Peak memory 216032 kb
Host smart-e552a893-c5bf-49fa-bc01-5539cf4ebaad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483542077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3483542077
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2715472361
Short name T1033
Test name
Test status
Simulation time 9881360 ps
CPU time 0.8 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 205140 kb
Host smart-868608ac-7356-4c30-ad1f-9b0800bd45d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715472361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2715472361
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2578249968
Short name T1073
Test name
Test status
Simulation time 79161944 ps
CPU time 0.81 seconds
Started Jun 26 05:47:42 PM PDT 24
Finished Jun 26 05:47:45 PM PDT 24
Peak memory 205340 kb
Host smart-ac6971e1-3b5b-446a-81e1-3d647ed7ebe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578249968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2578249968
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.173295268
Short name T928
Test name
Test status
Simulation time 22272108 ps
CPU time 0.74 seconds
Started Jun 26 05:47:53 PM PDT 24
Finished Jun 26 05:47:56 PM PDT 24
Peak memory 205376 kb
Host smart-6540e0cd-40c9-4d7f-8569-5783ea0adca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173295268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.173295268
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1272741532
Short name T1013
Test name
Test status
Simulation time 49231160 ps
CPU time 0.81 seconds
Started Jun 26 05:47:43 PM PDT 24
Finished Jun 26 05:47:45 PM PDT 24
Peak memory 205372 kb
Host smart-0d2b4aee-9e91-477b-885a-a53bf25d721a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272741532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1272741532
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2550022018
Short name T927
Test name
Test status
Simulation time 50738144 ps
CPU time 0.82 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 205348 kb
Host smart-1f968bb2-9c56-414e-a508-45a78fcea860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550022018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2550022018
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.975528999
Short name T988
Test name
Test status
Simulation time 20645747 ps
CPU time 0.87 seconds
Started Jun 26 05:47:53 PM PDT 24
Finished Jun 26 05:47:57 PM PDT 24
Peak memory 205300 kb
Host smart-ba5096ee-92b3-4b75-9791-5227ab31fab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975528999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.975528999
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2569970839
Short name T940
Test name
Test status
Simulation time 12737955 ps
CPU time 0.75 seconds
Started Jun 26 05:47:53 PM PDT 24
Finished Jun 26 05:47:56 PM PDT 24
Peak memory 205312 kb
Host smart-1256fa5b-0aa4-4da6-9448-8a42963e8d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569970839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2569970839
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3368518443
Short name T939
Test name
Test status
Simulation time 29515358 ps
CPU time 0.73 seconds
Started Jun 26 05:47:46 PM PDT 24
Finished Jun 26 05:47:49 PM PDT 24
Peak memory 205356 kb
Host smart-54393cd1-deed-4062-bc87-1294f8cddd9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368518443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3368518443
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4106321295
Short name T1040
Test name
Test status
Simulation time 12761324 ps
CPU time 0.9 seconds
Started Jun 26 05:47:46 PM PDT 24
Finished Jun 26 05:47:49 PM PDT 24
Peak memory 205416 kb
Host smart-057fbf37-7180-445a-b499-754a39562f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106321295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4106321295
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2430833471
Short name T1060
Test name
Test status
Simulation time 21373674 ps
CPU time 0.71 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:47 PM PDT 24
Peak memory 205320 kb
Host smart-893836f6-a7fb-45e1-8bce-f3ca5a197dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430833471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2430833471
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4151128580
Short name T1034
Test name
Test status
Simulation time 138984911 ps
CPU time 7.55 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 205500 kb
Host smart-7036f80c-f6d4-4746-a933-c88b6b91ca7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151128580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
151128580
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2492466548
Short name T163
Test name
Test status
Simulation time 3378254339 ps
CPU time 9.87 seconds
Started Jun 26 05:47:15 PM PDT 24
Finished Jun 26 05:47:26 PM PDT 24
Peak memory 205588 kb
Host smart-e0ccc1af-6c0a-4718-9d40-14455313dfbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492466548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
492466548
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.42855673
Short name T1024
Test name
Test status
Simulation time 55506898 ps
CPU time 1.02 seconds
Started Jun 26 05:47:15 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 205456 kb
Host smart-cc8d295f-cdd7-4df4-8744-1cec01cc808b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42855673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.42855673
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1128384192
Short name T1021
Test name
Test status
Simulation time 49866078 ps
CPU time 1.67 seconds
Started Jun 26 05:47:12 PM PDT 24
Finished Jun 26 05:47:15 PM PDT 24
Peak memory 213788 kb
Host smart-4b0d5f05-7d45-4bfb-90cf-fcfd52ba982a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128384192 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1128384192
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1692809508
Short name T1070
Test name
Test status
Simulation time 106553498 ps
CPU time 1.42 seconds
Started Jun 26 05:47:14 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 205684 kb
Host smart-13a3fc12-318a-40e3-a4d3-f24967779b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692809508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1692809508
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2501997540
Short name T924
Test name
Test status
Simulation time 25068561 ps
CPU time 0.83 seconds
Started Jun 26 05:47:14 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 205280 kb
Host smart-1b65c673-d854-4863-9170-c7cbefa12398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501997540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2501997540
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3543238516
Short name T1061
Test name
Test status
Simulation time 41245097 ps
CPU time 2.07 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 205596 kb
Host smart-523c3ab9-ad55-4cb0-88ae-96c02be4d52e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543238516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3543238516
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1349663740
Short name T1080
Test name
Test status
Simulation time 167988417 ps
CPU time 4.38 seconds
Started Jun 26 05:47:14 PM PDT 24
Finished Jun 26 05:47:20 PM PDT 24
Peak memory 213960 kb
Host smart-2f050524-d4fd-4fca-a5a3-7a6c4f1e7997
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349663740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1349663740
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3720690582
Short name T1043
Test name
Test status
Simulation time 318243670 ps
CPU time 8.27 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:23 PM PDT 24
Peak memory 214100 kb
Host smart-6cef437e-99c9-43a4-83af-5c437b9cd7f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720690582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3720690582
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2936931850
Short name T962
Test name
Test status
Simulation time 135637090 ps
CPU time 2.12 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 213672 kb
Host smart-62c4b358-56f6-4625-a8f2-bbe60e5e73dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936931850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2936931850
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.829039351
Short name T160
Test name
Test status
Simulation time 436358706 ps
CPU time 3.49 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 213692 kb
Host smart-573daf56-9b47-48cb-bae8-5a07144ea9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829039351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
829039351
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4149576043
Short name T935
Test name
Test status
Simulation time 35167290 ps
CPU time 0.83 seconds
Started Jun 26 05:47:53 PM PDT 24
Finished Jun 26 05:47:56 PM PDT 24
Peak memory 205372 kb
Host smart-c7fab45c-68be-4fa5-bf5d-82b6d8580eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149576043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4149576043
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4282646546
Short name T1068
Test name
Test status
Simulation time 13658107 ps
CPU time 0.84 seconds
Started Jun 26 05:47:45 PM PDT 24
Finished Jun 26 05:47:48 PM PDT 24
Peak memory 205136 kb
Host smart-f001256a-c72f-43f4-b3a4-bccbfad4bd21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282646546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4282646546
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3570521055
Short name T925
Test name
Test status
Simulation time 44063402 ps
CPU time 0.72 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205412 kb
Host smart-fa29d5b2-b3f1-4b85-b318-41f289793d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570521055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3570521055
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2777557888
Short name T943
Test name
Test status
Simulation time 11309715 ps
CPU time 0.73 seconds
Started Jun 26 05:47:50 PM PDT 24
Finished Jun 26 05:47:52 PM PDT 24
Peak memory 205428 kb
Host smart-0b40bb1e-c3cc-41b5-b306-5d1e67b5bbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777557888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2777557888
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2221835651
Short name T949
Test name
Test status
Simulation time 9589431 ps
CPU time 0.9 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:52 PM PDT 24
Peak memory 205360 kb
Host smart-41d00580-3c34-4b94-b922-b8c2e1dcffe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221835651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2221835651
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.90138058
Short name T930
Test name
Test status
Simulation time 13838599 ps
CPU time 0.91 seconds
Started Jun 26 05:47:51 PM PDT 24
Finished Jun 26 05:47:53 PM PDT 24
Peak memory 205364 kb
Host smart-b1a5fd8f-9909-45ce-896b-a2fef537076c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90138058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.90138058
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.945470729
Short name T1005
Test name
Test status
Simulation time 25752135 ps
CPU time 0.86 seconds
Started Jun 26 05:47:51 PM PDT 24
Finished Jun 26 05:47:53 PM PDT 24
Peak memory 205336 kb
Host smart-32729b1f-511f-4050-8a32-1cafe8b2cd8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945470729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.945470729
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4032045382
Short name T1058
Test name
Test status
Simulation time 17822664 ps
CPU time 0.83 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:52 PM PDT 24
Peak memory 205264 kb
Host smart-91892a51-9734-4c0c-ab4c-87ee164a2ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032045382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4032045382
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.650229158
Short name T953
Test name
Test status
Simulation time 44693364 ps
CPU time 0.71 seconds
Started Jun 26 05:47:51 PM PDT 24
Finished Jun 26 05:47:53 PM PDT 24
Peak memory 205412 kb
Host smart-73866b40-20c6-4780-a930-e994b7e66782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650229158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.650229158
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.849965777
Short name T1065
Test name
Test status
Simulation time 8336540 ps
CPU time 0.82 seconds
Started Jun 26 05:47:52 PM PDT 24
Finished Jun 26 05:47:54 PM PDT 24
Peak memory 205324 kb
Host smart-4e74d140-3cf3-420f-998a-8a2d5618d95a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849965777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.849965777
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1238037417
Short name T955
Test name
Test status
Simulation time 370042904 ps
CPU time 9.49 seconds
Started Jun 26 05:47:24 PM PDT 24
Finished Jun 26 05:47:34 PM PDT 24
Peak memory 205820 kb
Host smart-98920824-64a7-4dfa-9676-37d6e88242a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238037417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
238037417
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1546546777
Short name T1089
Test name
Test status
Simulation time 404499142 ps
CPU time 6.53 seconds
Started Jun 26 05:47:13 PM PDT 24
Finished Jun 26 05:47:20 PM PDT 24
Peak memory 205348 kb
Host smart-b0b65dda-80d0-417f-9353-46ab5b9d033b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546546777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
546546777
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1754660216
Short name T1009
Test name
Test status
Simulation time 68090996 ps
CPU time 0.94 seconds
Started Jun 26 05:47:12 PM PDT 24
Finished Jun 26 05:47:14 PM PDT 24
Peak memory 205432 kb
Host smart-feb0a2a5-dddc-4ffe-8234-35205865c039
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754660216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
754660216
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.472762116
Short name T984
Test name
Test status
Simulation time 76866573 ps
CPU time 2.24 seconds
Started Jun 26 05:47:24 PM PDT 24
Finished Jun 26 05:47:27 PM PDT 24
Peak memory 213796 kb
Host smart-b21b6d05-4ff3-4c29-a1e1-d94c8ce1cca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472762116 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.472762116
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4236437481
Short name T978
Test name
Test status
Simulation time 39764379 ps
CPU time 1.17 seconds
Started Jun 26 05:47:14 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 205512 kb
Host smart-3229ae1e-5ce8-423e-a471-7c80d4b7037c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236437481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4236437481
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3928632991
Short name T963
Test name
Test status
Simulation time 15371780 ps
CPU time 0.73 seconds
Started Jun 26 05:47:14 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 205356 kb
Host smart-5992e9d1-5f47-43d9-843b-8cbab210df78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928632991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3928632991
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2383323572
Short name T1046
Test name
Test status
Simulation time 188501346 ps
CPU time 2.13 seconds
Started Jun 26 05:47:19 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 205576 kb
Host smart-e748945d-6510-44ea-802c-df86d93139dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383323572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2383323572
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.243952477
Short name T127
Test name
Test status
Simulation time 325879170 ps
CPU time 3.22 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:16 PM PDT 24
Peak memory 213952 kb
Host smart-07f601ee-c098-4267-919d-160c76258d9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243952477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.243952477
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.99591689
Short name T126
Test name
Test status
Simulation time 801166245 ps
CPU time 8.29 seconds
Started Jun 26 05:47:11 PM PDT 24
Finished Jun 26 05:47:20 PM PDT 24
Peak memory 213956 kb
Host smart-c2f1af2f-81f1-4cb0-898f-353c7b239e76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99591689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ke
ymgr_shadow_reg_errors_with_csr_rw.99591689
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2916000980
Short name T954
Test name
Test status
Simulation time 243582189 ps
CPU time 2.52 seconds
Started Jun 26 05:47:14 PM PDT 24
Finished Jun 26 05:47:18 PM PDT 24
Peak memory 215780 kb
Host smart-390037af-a0d1-4f85-bd46-a778be646ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916000980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2916000980
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3116462248
Short name T982
Test name
Test status
Simulation time 24157558 ps
CPU time 0.75 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205416 kb
Host smart-5295d581-8bbf-4d3c-9f3f-abf5772869e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116462248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3116462248
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.94780343
Short name T987
Test name
Test status
Simulation time 156542020 ps
CPU time 0.81 seconds
Started Jun 26 05:47:47 PM PDT 24
Finished Jun 26 05:47:49 PM PDT 24
Peak memory 205396 kb
Host smart-04e877b9-0373-4c8c-aa2f-a13919f494dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94780343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.94780343
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.511926069
Short name T1087
Test name
Test status
Simulation time 60990768 ps
CPU time 0.84 seconds
Started Jun 26 05:47:51 PM PDT 24
Finished Jun 26 05:47:54 PM PDT 24
Peak memory 205412 kb
Host smart-07cc2c2c-20e7-46a1-b5d5-30a5f73b6fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511926069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.511926069
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1149899075
Short name T923
Test name
Test status
Simulation time 53709083 ps
CPU time 0.75 seconds
Started Jun 26 05:47:51 PM PDT 24
Finished Jun 26 05:47:54 PM PDT 24
Peak memory 205280 kb
Host smart-d82ae131-e96d-4311-8bdd-c19222336e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149899075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1149899075
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3803012253
Short name T1010
Test name
Test status
Simulation time 24277534 ps
CPU time 0.73 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205388 kb
Host smart-aedf94a8-a849-409e-bb6b-1bb8dc756b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803012253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3803012253
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2559092861
Short name T986
Test name
Test status
Simulation time 14885406 ps
CPU time 0.9 seconds
Started Jun 26 05:47:52 PM PDT 24
Finished Jun 26 05:47:54 PM PDT 24
Peak memory 205328 kb
Host smart-35dd9cce-b6d0-48e3-861c-0dfdf3cfe881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559092861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2559092861
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3329324071
Short name T933
Test name
Test status
Simulation time 41525237 ps
CPU time 0.83 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205388 kb
Host smart-4495e89a-fcc8-4682-94d4-14e8b58614d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329324071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3329324071
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1467993736
Short name T1084
Test name
Test status
Simulation time 35855343 ps
CPU time 0.75 seconds
Started Jun 26 05:47:49 PM PDT 24
Finished Jun 26 05:47:51 PM PDT 24
Peak memory 205396 kb
Host smart-fe89672d-18aa-423b-a8fe-e9a668fddc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467993736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1467993736
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3212909953
Short name T1014
Test name
Test status
Simulation time 8161707 ps
CPU time 0.75 seconds
Started Jun 26 05:47:48 PM PDT 24
Finished Jun 26 05:47:50 PM PDT 24
Peak memory 205260 kb
Host smart-fcaa1967-afa9-449e-a897-9ae65a211fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212909953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3212909953
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.998996767
Short name T1006
Test name
Test status
Simulation time 9451332 ps
CPU time 0.84 seconds
Started Jun 26 05:47:50 PM PDT 24
Finished Jun 26 05:47:52 PM PDT 24
Peak memory 205388 kb
Host smart-dd5513a6-fd0c-4193-97ff-18f0c4893da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998996767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.998996767
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1451272019
Short name T1038
Test name
Test status
Simulation time 44208656 ps
CPU time 1.22 seconds
Started Jun 26 05:47:22 PM PDT 24
Finished Jun 26 05:47:24 PM PDT 24
Peak memory 205848 kb
Host smart-043ec849-1c49-4789-8dfe-ec5d7107f81a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451272019 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1451272019
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3144278998
Short name T1051
Test name
Test status
Simulation time 26892312 ps
CPU time 1.24 seconds
Started Jun 26 05:47:20 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 205560 kb
Host smart-f7b9679a-768c-4975-8cae-bffe5dab8095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144278998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3144278998
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.554212672
Short name T1029
Test name
Test status
Simulation time 29891828 ps
CPU time 0.7 seconds
Started Jun 26 05:47:21 PM PDT 24
Finished Jun 26 05:47:23 PM PDT 24
Peak memory 205276 kb
Host smart-f7101ca0-dd9e-4207-91a4-59c300c6d2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554212672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.554212672
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3320688889
Short name T149
Test name
Test status
Simulation time 63134585 ps
CPU time 2.72 seconds
Started Jun 26 05:47:20 PM PDT 24
Finished Jun 26 05:47:24 PM PDT 24
Peak memory 205452 kb
Host smart-d0dd0202-13f7-40ae-8cdd-5d702f27fb6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320688889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3320688889
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3940712938
Short name T115
Test name
Test status
Simulation time 934994230 ps
CPU time 1.95 seconds
Started Jun 26 05:47:19 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 214256 kb
Host smart-c4a9a8c9-5bce-438b-a78e-a12bee0ed401
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940712938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3940712938
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4175041960
Short name T1035
Test name
Test status
Simulation time 415060935 ps
CPU time 15.08 seconds
Started Jun 26 05:47:20 PM PDT 24
Finished Jun 26 05:47:36 PM PDT 24
Peak memory 214016 kb
Host smart-0de3d902-b905-496f-afe9-e6c286f31015
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175041960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4175041960
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.216822985
Short name T959
Test name
Test status
Simulation time 43473496 ps
CPU time 2.6 seconds
Started Jun 26 05:47:19 PM PDT 24
Finished Jun 26 05:47:23 PM PDT 24
Peak memory 213764 kb
Host smart-cbef03e4-9b4a-432d-9e4d-29f46f5d9535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216822985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.216822985
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3271777404
Short name T1086
Test name
Test status
Simulation time 210289516 ps
CPU time 8.98 seconds
Started Jun 26 05:47:21 PM PDT 24
Finished Jun 26 05:47:31 PM PDT 24
Peak memory 213708 kb
Host smart-c04e4200-babd-4366-a624-d73620e0d1a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271777404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3271777404
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3270084739
Short name T967
Test name
Test status
Simulation time 41750499 ps
CPU time 1.46 seconds
Started Jun 26 05:47:20 PM PDT 24
Finished Jun 26 05:47:23 PM PDT 24
Peak memory 213748 kb
Host smart-2dcae1d4-1bfb-40b3-8943-fc75ab76bb35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270084739 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3270084739
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3249742948
Short name T1007
Test name
Test status
Simulation time 21076595 ps
CPU time 0.9 seconds
Started Jun 26 05:47:22 PM PDT 24
Finished Jun 26 05:47:24 PM PDT 24
Peak memory 205404 kb
Host smart-dc9cb675-95c3-4f9f-a1aa-0b704cc96890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249742948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3249742948
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3708287322
Short name T1050
Test name
Test status
Simulation time 41331416 ps
CPU time 0.74 seconds
Started Jun 26 05:47:18 PM PDT 24
Finished Jun 26 05:47:19 PM PDT 24
Peak memory 205328 kb
Host smart-bcb30cdf-4e96-473b-b980-c9d25e5208d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708287322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3708287322
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2547727825
Short name T974
Test name
Test status
Simulation time 118449433 ps
CPU time 1.75 seconds
Started Jun 26 05:47:19 PM PDT 24
Finished Jun 26 05:47:22 PM PDT 24
Peak memory 205400 kb
Host smart-0c7ae8d2-aef4-44b1-86c4-1cd0590ad520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547727825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2547727825
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.513867367
Short name T1042
Test name
Test status
Simulation time 337051732 ps
CPU time 2.57 seconds
Started Jun 26 05:47:21 PM PDT 24
Finished Jun 26 05:47:25 PM PDT 24
Peak memory 213996 kb
Host smart-c5117eac-dc46-4fe3-a3ae-8ade29a022c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513867367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.513867367
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2630130207
Short name T1020
Test name
Test status
Simulation time 1345266511 ps
CPU time 8.55 seconds
Started Jun 26 05:47:21 PM PDT 24
Finished Jun 26 05:47:31 PM PDT 24
Peak memory 214016 kb
Host smart-df0503be-731f-4f35-8b7b-c68071d2c936
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630130207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2630130207
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2356499622
Short name T1082
Test name
Test status
Simulation time 27656606 ps
CPU time 1.75 seconds
Started Jun 26 05:47:22 PM PDT 24
Finished Jun 26 05:47:25 PM PDT 24
Peak memory 213740 kb
Host smart-78cf320b-1587-4b5f-8246-3f92d3ce3453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356499622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2356499622
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2753442147
Short name T980
Test name
Test status
Simulation time 107762302 ps
CPU time 5.32 seconds
Started Jun 26 05:47:21 PM PDT 24
Finished Jun 26 05:47:28 PM PDT 24
Peak memory 213708 kb
Host smart-427e7a3a-2577-4cbb-b26b-b55c41da3f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753442147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2753442147
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.867899338
Short name T926
Test name
Test status
Simulation time 32322494 ps
CPU time 1.23 seconds
Started Jun 26 05:47:27 PM PDT 24
Finished Jun 26 05:47:29 PM PDT 24
Peak memory 213768 kb
Host smart-f62f12cf-9cc1-41d6-9587-9a2c29d61c4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867899338 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.867899338
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3566130882
Short name T979
Test name
Test status
Simulation time 19502027 ps
CPU time 1.33 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:32 PM PDT 24
Peak memory 205376 kb
Host smart-a7a7bd4f-be6b-4467-85d5-92e0bee0b8fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566130882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3566130882
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2050746504
Short name T1044
Test name
Test status
Simulation time 12224890 ps
CPU time 0.79 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:31 PM PDT 24
Peak memory 205240 kb
Host smart-e0fb8117-f49d-46f9-be2d-530c1938581b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050746504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2050746504
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1085030522
Short name T1075
Test name
Test status
Simulation time 96809776 ps
CPU time 3.52 seconds
Started Jun 26 05:47:30 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 205540 kb
Host smart-24a040f5-8193-4307-b9cf-3171c3389c45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085030522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1085030522
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3169862943
Short name T971
Test name
Test status
Simulation time 244334765 ps
CPU time 2.43 seconds
Started Jun 26 05:47:19 PM PDT 24
Finished Jun 26 05:47:23 PM PDT 24
Peak memory 214088 kb
Host smart-029be1a3-1ec7-4e11-83c5-ae3119a9d9d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169862943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3169862943
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1037655718
Short name T1056
Test name
Test status
Simulation time 75191359 ps
CPU time 2.41 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:33 PM PDT 24
Peak memory 215584 kb
Host smart-42333efd-2b5e-4b25-97be-d089c42eeed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037655718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1037655718
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1198616903
Short name T185
Test name
Test status
Simulation time 113252383 ps
CPU time 3.51 seconds
Started Jun 26 05:47:30 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 213724 kb
Host smart-17e8430d-d034-4f7f-b01d-f97f66498ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198616903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1198616903
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.236038077
Short name T1055
Test name
Test status
Simulation time 286679956 ps
CPU time 2.39 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 213840 kb
Host smart-142974a9-8d93-41c3-9fa8-9411927016ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236038077 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.236038077
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1920172162
Short name T946
Test name
Test status
Simulation time 17043456 ps
CPU time 1.11 seconds
Started Jun 26 05:47:28 PM PDT 24
Finished Jun 26 05:47:30 PM PDT 24
Peak memory 205436 kb
Host smart-beb60ba6-b343-4305-8a45-79c5d3b112de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920172162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1920172162
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2172309651
Short name T994
Test name
Test status
Simulation time 41587975 ps
CPU time 0.74 seconds
Started Jun 26 05:47:32 PM PDT 24
Finished Jun 26 05:47:34 PM PDT 24
Peak memory 205296 kb
Host smart-c1917c9a-7d6e-4c30-8dcd-69480e8eade4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172309651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2172309651
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2087032606
Short name T965
Test name
Test status
Simulation time 630803442 ps
CPU time 2.35 seconds
Started Jun 26 05:47:30 PM PDT 24
Finished Jun 26 05:47:34 PM PDT 24
Peak memory 205528 kb
Host smart-7e5d30ce-a79d-450b-849b-e753e07801c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087032606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2087032606
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2910706085
Short name T970
Test name
Test status
Simulation time 235083300 ps
CPU time 2.17 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 213948 kb
Host smart-8a38c14e-2cc3-475b-9b51-bb0ace5abe53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910706085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2910706085
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2168288053
Short name T1032
Test name
Test status
Simulation time 485350742 ps
CPU time 9.66 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:42 PM PDT 24
Peak memory 214120 kb
Host smart-96210ab4-047c-4850-ba75-a21894866477
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168288053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2168288053
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2651495341
Short name T1052
Test name
Test status
Simulation time 97689967 ps
CPU time 3.65 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:37 PM PDT 24
Peak memory 213732 kb
Host smart-9148436e-c9d5-4ea6-9cb8-8a32cced5e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651495341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2651495341
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1515647558
Short name T1012
Test name
Test status
Simulation time 83185021 ps
CPU time 2.74 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:32 PM PDT 24
Peak memory 214984 kb
Host smart-7ebc29ab-6c97-4f9b-8f55-72d63f0a957b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515647558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1515647558
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1528076049
Short name T999
Test name
Test status
Simulation time 45952235 ps
CPU time 2.02 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:32 PM PDT 24
Peak memory 213764 kb
Host smart-ce43fe88-24a7-4a3f-9ae9-f6dc1c92b563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528076049 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1528076049
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2766707874
Short name T995
Test name
Test status
Simulation time 125843796 ps
CPU time 0.93 seconds
Started Jun 26 05:47:30 PM PDT 24
Finished Jun 26 05:47:32 PM PDT 24
Peak memory 205400 kb
Host smart-02c867f7-3db0-49d5-a854-1e5adc191053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766707874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2766707874
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4119764137
Short name T932
Test name
Test status
Simulation time 14274856 ps
CPU time 0.96 seconds
Started Jun 26 05:47:32 PM PDT 24
Finished Jun 26 05:47:34 PM PDT 24
Peak memory 205300 kb
Host smart-15f6e278-790a-45de-95c1-e823cfcef471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119764137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4119764137
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1686362640
Short name T1026
Test name
Test status
Simulation time 230156800 ps
CPU time 2.53 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 205492 kb
Host smart-12540946-1d4a-4384-a8ff-e45cdbcdbd54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686362640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1686362640
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.350696110
Short name T1045
Test name
Test status
Simulation time 184012127 ps
CPU time 1.84 seconds
Started Jun 26 05:47:29 PM PDT 24
Finished Jun 26 05:47:33 PM PDT 24
Peak memory 214108 kb
Host smart-f7290192-e86d-4430-9d28-8c27aa0b7b82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350696110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.350696110
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3990326385
Short name T122
Test name
Test status
Simulation time 203090919 ps
CPU time 4.89 seconds
Started Jun 26 05:47:31 PM PDT 24
Finished Jun 26 05:47:38 PM PDT 24
Peak memory 220052 kb
Host smart-3aac72f4-c52f-4e86-b051-a345cc74ec86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990326385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3990326385
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3977576305
Short name T944
Test name
Test status
Simulation time 147955671 ps
CPU time 4.18 seconds
Started Jun 26 05:47:34 PM PDT 24
Finished Jun 26 05:47:39 PM PDT 24
Peak memory 213764 kb
Host smart-de48a8e2-0c76-4962-987a-2b849d5b0ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977576305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3977576305
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1829883661
Short name T678
Test name
Test status
Simulation time 35103686 ps
CPU time 0.9 seconds
Started Jun 26 05:53:54 PM PDT 24
Finished Jun 26 05:53:56 PM PDT 24
Peak memory 205992 kb
Host smart-85b7ff72-27bd-40aa-bbe9-b74bfeb68a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829883661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1829883661
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1319685883
Short name T808
Test name
Test status
Simulation time 257027572 ps
CPU time 4.86 seconds
Started Jun 26 05:53:54 PM PDT 24
Finished Jun 26 05:54:00 PM PDT 24
Peak memory 209956 kb
Host smart-273f1710-19cf-41e4-99e1-d97c7baea7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319685883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1319685883
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1538113525
Short name T59
Test name
Test status
Simulation time 320768578 ps
CPU time 5.32 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 214320 kb
Host smart-746b6769-f835-4adb-a594-c54ada408b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538113525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1538113525
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3019550796
Short name T349
Test name
Test status
Simulation time 1425343518 ps
CPU time 19.29 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 209160 kb
Host smart-233a5997-a95c-4515-bf67-1b7a31ae37cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019550796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3019550796
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3338569762
Short name T770
Test name
Test status
Simulation time 191433659 ps
CPU time 2.92 seconds
Started Jun 26 05:53:56 PM PDT 24
Finished Jun 26 05:54:00 PM PDT 24
Peak memory 206396 kb
Host smart-0e29a397-7b01-4e54-a185-bfc7358e3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338569762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3338569762
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4213936445
Short name T278
Test name
Test status
Simulation time 148623295 ps
CPU time 2.61 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:50 PM PDT 24
Peak memory 220196 kb
Host smart-74429b61-f261-4571-9eb7-48fd3128b410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213936445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4213936445
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2739351812
Short name T869
Test name
Test status
Simulation time 3534228199 ps
CPU time 35.88 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:54:21 PM PDT 24
Peak memory 218212 kb
Host smart-fba3a75b-8f95-42d8-b17b-80162cf07adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739351812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2739351812
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2559417419
Short name T461
Test name
Test status
Simulation time 131428170 ps
CPU time 4.1 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:51 PM PDT 24
Peak memory 208572 kb
Host smart-f3dae912-b7c5-4387-b8b5-93e9bb0c24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559417419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2559417419
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3017736041
Short name T486
Test name
Test status
Simulation time 346554125 ps
CPU time 3.81 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:50 PM PDT 24
Peak memory 206804 kb
Host smart-c530e218-1f54-4245-9ef7-bd8f5cb94cad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017736041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3017736041
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3985971198
Short name T809
Test name
Test status
Simulation time 1414412807 ps
CPU time 18.48 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 208884 kb
Host smart-27381228-1c28-432c-8049-7c3e8db53d9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985971198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3985971198
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3769931493
Short name T611
Test name
Test status
Simulation time 63183378 ps
CPU time 3.08 seconds
Started Jun 26 05:53:42 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 208120 kb
Host smart-1d5a1774-4d19-497f-9a6f-b625550f7a55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769931493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3769931493
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1153183275
Short name T295
Test name
Test status
Simulation time 75533116 ps
CPU time 3.61 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:53:57 PM PDT 24
Peak memory 210232 kb
Host smart-ec05e757-d9f3-49b5-beed-1549e75bfaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153183275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1153183275
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.385382903
Short name T745
Test name
Test status
Simulation time 269956737 ps
CPU time 5.32 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:52 PM PDT 24
Peak memory 207316 kb
Host smart-abb38674-6b52-4b66-b2c0-c4769725b89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385382903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.385382903
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2996465260
Short name T260
Test name
Test status
Simulation time 609215897 ps
CPU time 20.36 seconds
Started Jun 26 05:53:52 PM PDT 24
Finished Jun 26 05:54:13 PM PDT 24
Peak memory 216904 kb
Host smart-589d3106-b4d7-472b-ab99-45dccb0722bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996465260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2996465260
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3437091632
Short name T189
Test name
Test status
Simulation time 269005821 ps
CPU time 5.36 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:00 PM PDT 24
Peak memory 222528 kb
Host smart-af9acc4c-3b6d-449e-80d3-e51ac809f330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437091632 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3437091632
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.24259084
Short name T863
Test name
Test status
Simulation time 116655398 ps
CPU time 5.09 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:53 PM PDT 24
Peak memory 209244 kb
Host smart-dd52ca55-a2cd-4dbb-8a9a-ee2ca4b0b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24259084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.24259084
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1748116262
Short name T393
Test name
Test status
Simulation time 2793538968 ps
CPU time 19.75 seconds
Started Jun 26 05:53:52 PM PDT 24
Finished Jun 26 05:54:12 PM PDT 24
Peak memory 211340 kb
Host smart-d19cda25-0832-464f-926d-60313e241966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748116262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1748116262
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2453378856
Short name T625
Test name
Test status
Simulation time 21766720 ps
CPU time 0.75 seconds
Started Jun 26 05:53:54 PM PDT 24
Finished Jun 26 05:53:56 PM PDT 24
Peak memory 206016 kb
Host smart-5c9c0a87-a065-4b82-aaee-eca90f4e367a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453378856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2453378856
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3666595284
Short name T496
Test name
Test status
Simulation time 80080628 ps
CPU time 3.47 seconds
Started Jun 26 05:53:54 PM PDT 24
Finished Jun 26 05:53:58 PM PDT 24
Peak memory 222784 kb
Host smart-8f8ce19d-0215-4952-909b-46f6b6e330c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666595284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3666595284
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1410938269
Short name T708
Test name
Test status
Simulation time 224287107 ps
CPU time 3.03 seconds
Started Jun 26 05:53:55 PM PDT 24
Finished Jun 26 05:53:59 PM PDT 24
Peak memory 207728 kb
Host smart-196bc490-9d59-4383-9794-593b352d50fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410938269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1410938269
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1744385648
Short name T729
Test name
Test status
Simulation time 195827372 ps
CPU time 5.1 seconds
Started Jun 26 05:53:56 PM PDT 24
Finished Jun 26 05:54:02 PM PDT 24
Peak memory 208968 kb
Host smart-0ca0f2c2-2639-4f0b-aae5-27bf5ba3dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744385648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1744385648
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3676323528
Short name T475
Test name
Test status
Simulation time 143662648 ps
CPU time 3.15 seconds
Started Jun 26 05:53:51 PM PDT 24
Finished Jun 26 05:53:55 PM PDT 24
Peak memory 209032 kb
Host smart-eaa06376-00f6-42e0-ac96-d9f839b3f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676323528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3676323528
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3863932214
Short name T807
Test name
Test status
Simulation time 81329673 ps
CPU time 4.12 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:53:59 PM PDT 24
Peak memory 209624 kb
Host smart-68abf5c7-3fd2-494d-9878-9a9e617569d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863932214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3863932214
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.397330574
Short name T14
Test name
Test status
Simulation time 623845603 ps
CPU time 12.78 seconds
Started Jun 26 05:53:54 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 230676 kb
Host smart-2ca5b5c3-1561-451d-b282-baa11fb98fb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397330574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.397330574
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3689585280
Short name T749
Test name
Test status
Simulation time 759375925 ps
CPU time 8.83 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:03 PM PDT 24
Peak memory 206904 kb
Host smart-1725916c-273b-44aa-b48a-a2e95c3edef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689585280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3689585280
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3626818745
Short name T866
Test name
Test status
Simulation time 669521387 ps
CPU time 18.31 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:13 PM PDT 24
Peak memory 208012 kb
Host smart-f47a0a59-9591-470c-8978-51283b953e8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626818745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3626818745
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2225168784
Short name T511
Test name
Test status
Simulation time 1966977085 ps
CPU time 33.84 seconds
Started Jun 26 05:53:55 PM PDT 24
Finished Jun 26 05:54:29 PM PDT 24
Peak memory 209124 kb
Host smart-84037783-5d55-4e1a-a09e-d183aca97e98
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225168784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2225168784
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1959024955
Short name T559
Test name
Test status
Simulation time 376666191 ps
CPU time 7.11 seconds
Started Jun 26 05:53:56 PM PDT 24
Finished Jun 26 05:54:04 PM PDT 24
Peak memory 207968 kb
Host smart-b8e27d51-24b9-4607-bb9f-9f0d505c41d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959024955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1959024955
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.394023181
Short name T508
Test name
Test status
Simulation time 103008788 ps
CPU time 1.9 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:53:56 PM PDT 24
Peak memory 207520 kb
Host smart-2c7eab61-da6f-418e-a0c7-8941b0a96d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394023181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.394023181
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.504889383
Short name T452
Test name
Test status
Simulation time 1382798006 ps
CPU time 24.68 seconds
Started Jun 26 05:53:52 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 208464 kb
Host smart-d8be29a1-b6df-4f93-be89-36466d97c1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504889383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.504889383
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2546646865
Short name T565
Test name
Test status
Simulation time 900844478 ps
CPU time 34.03 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:29 PM PDT 24
Peak memory 216324 kb
Host smart-89004403-b141-458b-bd74-225d8441ebf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546646865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2546646865
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3081405457
Short name T206
Test name
Test status
Simulation time 1697323037 ps
CPU time 28.52 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:23 PM PDT 24
Peak memory 209848 kb
Host smart-8dda2d11-8716-471a-837d-8ee8ef2c7390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081405457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3081405457
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1012828923
Short name T186
Test name
Test status
Simulation time 130423605 ps
CPU time 2.06 seconds
Started Jun 26 05:53:55 PM PDT 24
Finished Jun 26 05:53:58 PM PDT 24
Peak memory 209984 kb
Host smart-69c468f4-a5e1-456e-931e-f5cdd29fbd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012828923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1012828923
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3971021543
Short name T619
Test name
Test status
Simulation time 235950330 ps
CPU time 2.92 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 220204 kb
Host smart-c19f9641-82c5-4b2d-bc49-54924234949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971021543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3971021543
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.163788145
Short name T800
Test name
Test status
Simulation time 27882074 ps
CPU time 1.96 seconds
Started Jun 26 05:54:31 PM PDT 24
Finished Jun 26 05:54:35 PM PDT 24
Peak memory 209464 kb
Host smart-4ecc99f1-4341-4331-aaac-8be781e309f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163788145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.163788145
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.483711361
Short name T780
Test name
Test status
Simulation time 7563623407 ps
CPU time 19.39 seconds
Started Jun 26 05:54:28 PM PDT 24
Finished Jun 26 05:54:49 PM PDT 24
Peak memory 214384 kb
Host smart-863fca82-ed0b-47af-93cb-105dbe48efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483711361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.483711361
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4289818229
Short name T647
Test name
Test status
Simulation time 244551962 ps
CPU time 3.21 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:34 PM PDT 24
Peak memory 214360 kb
Host smart-08e6dda1-d817-4255-a4d7-2d6ed53e0480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289818229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4289818229
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1369960432
Short name T217
Test name
Test status
Simulation time 618352091 ps
CPU time 3.51 seconds
Started Jun 26 05:54:33 PM PDT 24
Finished Jun 26 05:54:38 PM PDT 24
Peak memory 214312 kb
Host smart-2a6a2765-dbcd-4af2-8b40-78145ce2cc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369960432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1369960432
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.532378372
Short name T554
Test name
Test status
Simulation time 76391808 ps
CPU time 3.41 seconds
Started Jun 26 05:54:31 PM PDT 24
Finished Jun 26 05:54:36 PM PDT 24
Peak memory 209540 kb
Host smart-a0decf8e-606d-4865-a62c-5c440963f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532378372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.532378372
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.997781808
Short name T727
Test name
Test status
Simulation time 870932355 ps
CPU time 7.15 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:37 PM PDT 24
Peak memory 208548 kb
Host smart-1073cdee-3c16-4920-82a0-3c74f6eb9f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997781808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.997781808
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3225400716
Short name T359
Test name
Test status
Simulation time 53922606 ps
CPU time 2.92 seconds
Started Jun 26 05:54:28 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 206968 kb
Host smart-9730a8be-6a16-4633-9190-33e539ebb4ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225400716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3225400716
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.544483500
Short name T360
Test name
Test status
Simulation time 45308820 ps
CPU time 2.81 seconds
Started Jun 26 05:54:31 PM PDT 24
Finished Jun 26 05:54:35 PM PDT 24
Peak memory 208896 kb
Host smart-db251a40-3780-411e-b405-8577c39d4f08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544483500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.544483500
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3809521546
Short name T575
Test name
Test status
Simulation time 285123155 ps
CPU time 2.75 seconds
Started Jun 26 05:54:32 PM PDT 24
Finished Jun 26 05:54:36 PM PDT 24
Peak memory 214288 kb
Host smart-c573fe00-9d7c-4437-ad12-c91547f50c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809521546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3809521546
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1457135697
Short name T821
Test name
Test status
Simulation time 675198978 ps
CPU time 14.66 seconds
Started Jun 26 05:54:30 PM PDT 24
Finished Jun 26 05:54:46 PM PDT 24
Peak memory 208596 kb
Host smart-566811e7-f670-4ac1-a1a5-6aa81ae5a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457135697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1457135697
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2107552735
Short name T900
Test name
Test status
Simulation time 2324925205 ps
CPU time 72.08 seconds
Started Jun 26 05:54:30 PM PDT 24
Finished Jun 26 05:55:44 PM PDT 24
Peak memory 217300 kb
Host smart-3fa3df03-ba07-4e54-9278-c335e7996ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107552735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2107552735
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.59537598
Short name T768
Test name
Test status
Simulation time 460063676 ps
CPU time 5.5 seconds
Started Jun 26 05:54:30 PM PDT 24
Finished Jun 26 05:54:37 PM PDT 24
Peak memory 209244 kb
Host smart-2ab888b2-c56b-4bce-b85f-bc68250aa295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59537598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.59537598
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.895346031
Short name T741
Test name
Test status
Simulation time 99220572 ps
CPU time 2.37 seconds
Started Jun 26 05:54:30 PM PDT 24
Finished Jun 26 05:54:34 PM PDT 24
Peak memory 209944 kb
Host smart-b753ce8f-35a9-4e02-8740-38df8f6c892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895346031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.895346031
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3272515001
Short name T194
Test name
Test status
Simulation time 17373109 ps
CPU time 0.99 seconds
Started Jun 26 05:54:38 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 206024 kb
Host smart-e5dc840b-0f63-4e11-a1f8-ffa9ddb54037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272515001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3272515001
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1849356352
Short name T514
Test name
Test status
Simulation time 324538076 ps
CPU time 2.41 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 207712 kb
Host smart-4346757d-5e0f-4922-9d10-4b42fa59aba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849356352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1849356352
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1139438610
Short name T601
Test name
Test status
Simulation time 57905816 ps
CPU time 3.22 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 222448 kb
Host smart-fc7d0660-1192-49c3-a500-7f7f25cf178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139438610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1139438610
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1799723692
Short name T38
Test name
Test status
Simulation time 166607634 ps
CPU time 3.72 seconds
Started Jun 26 05:54:35 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 222412 kb
Host smart-938fd129-bfef-483f-bc7d-b029fe31c053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799723692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1799723692
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3986235975
Short name T819
Test name
Test status
Simulation time 78073067 ps
CPU time 3.8 seconds
Started Jun 26 05:54:33 PM PDT 24
Finished Jun 26 05:54:38 PM PDT 24
Peak memory 207108 kb
Host smart-c1634ec7-5010-41ff-9db6-aa86537b7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986235975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3986235975
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4147965095
Short name T353
Test name
Test status
Simulation time 88991208 ps
CPU time 4.01 seconds
Started Jun 26 05:54:29 PM PDT 24
Finished Jun 26 05:54:35 PM PDT 24
Peak memory 206996 kb
Host smart-5a1efca0-bff8-4eff-8f86-3a79f5022530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147965095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4147965095
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1405101848
Short name T358
Test name
Test status
Simulation time 481619471 ps
CPU time 6.81 seconds
Started Jun 26 05:54:30 PM PDT 24
Finished Jun 26 05:54:38 PM PDT 24
Peak memory 208536 kb
Host smart-ba58c23b-f87c-4a0e-ba25-5022f25c01ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405101848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1405101848
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3572744558
Short name T890
Test name
Test status
Simulation time 169334743 ps
CPU time 1.87 seconds
Started Jun 26 05:54:28 PM PDT 24
Finished Jun 26 05:54:31 PM PDT 24
Peak memory 206972 kb
Host smart-b3e15b98-cade-4e7b-a628-67a81881ee9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572744558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3572744558
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3369989226
Short name T524
Test name
Test status
Simulation time 8479631460 ps
CPU time 44.74 seconds
Started Jun 26 05:54:32 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 209052 kb
Host smart-6cbf5261-edb2-47b5-a1e3-8bc534a82218
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369989226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3369989226
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1294695280
Short name T679
Test name
Test status
Simulation time 252774765 ps
CPU time 3.46 seconds
Started Jun 26 05:54:38 PM PDT 24
Finished Jun 26 05:54:43 PM PDT 24
Peak memory 208132 kb
Host smart-fbd0d30c-7606-4eb7-9d10-7e1a689dcc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294695280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1294695280
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3489660702
Short name T834
Test name
Test status
Simulation time 78776381 ps
CPU time 1.79 seconds
Started Jun 26 05:54:32 PM PDT 24
Finished Jun 26 05:54:35 PM PDT 24
Peak memory 207208 kb
Host smart-108d5868-d8c7-474f-8f06-b9bbc8f981b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489660702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3489660702
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1085711994
Short name T379
Test name
Test status
Simulation time 377642553 ps
CPU time 15.41 seconds
Started Jun 26 05:54:36 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 219628 kb
Host smart-fbaf8ee6-4e2d-4bd1-b8b3-cb4c7be2fd7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085711994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1085711994
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3552843015
Short name T516
Test name
Test status
Simulation time 495511669 ps
CPU time 4.34 seconds
Started Jun 26 05:54:27 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 208724 kb
Host smart-d91bd00b-7804-417e-9555-e19b330403cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552843015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3552843015
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3594738925
Short name T763
Test name
Test status
Simulation time 31948417 ps
CPU time 0.71 seconds
Started Jun 26 05:54:35 PM PDT 24
Finished Jun 26 05:54:37 PM PDT 24
Peak memory 206064 kb
Host smart-d1c46bf5-dc20-4186-a94a-b56b3c4f23a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594738925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3594738925
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.403786690
Short name T299
Test name
Test status
Simulation time 38372691 ps
CPU time 2.98 seconds
Started Jun 26 05:54:34 PM PDT 24
Finished Jun 26 05:54:39 PM PDT 24
Peak memory 215420 kb
Host smart-f39c838b-0ce6-44bf-868e-72f78c101472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403786690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.403786690
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.455541560
Short name T846
Test name
Test status
Simulation time 79897411 ps
CPU time 2.24 seconds
Started Jun 26 05:54:36 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 208516 kb
Host smart-39e6680f-eac2-4435-82b5-42a6aaed79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455541560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.455541560
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3106271396
Short name T752
Test name
Test status
Simulation time 252018155 ps
CPU time 2.13 seconds
Started Jun 26 05:54:36 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 209372 kb
Host smart-46208d7f-dbdf-4dbc-a06e-98d596b83281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106271396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3106271396
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2971499717
Short name T389
Test name
Test status
Simulation time 132294395 ps
CPU time 1.95 seconds
Started Jun 26 05:54:39 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 214348 kb
Host smart-184f1870-f0d2-4259-86f6-1ab3a667e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971499717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2971499717
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.518874874
Short name T269
Test name
Test status
Simulation time 411898964 ps
CPU time 3.42 seconds
Started Jun 26 05:54:35 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 214736 kb
Host smart-2bf6f29e-70ab-4f65-9e4c-c2b06e308021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518874874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.518874874
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1666128569
Short name T227
Test name
Test status
Simulation time 227144173 ps
CPU time 3.09 seconds
Started Jun 26 05:54:39 PM PDT 24
Finished Jun 26 05:54:43 PM PDT 24
Peak memory 209400 kb
Host smart-238a6e59-3c28-4d5c-910a-076ef6a3ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666128569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1666128569
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2632144332
Short name T301
Test name
Test status
Simulation time 874333596 ps
CPU time 9.96 seconds
Started Jun 26 05:54:37 PM PDT 24
Finished Jun 26 05:54:48 PM PDT 24
Peak memory 218376 kb
Host smart-58af1e6a-a7c3-4297-bed5-03e72c4a7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632144332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2632144332
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.4214787706
Short name T690
Test name
Test status
Simulation time 529570779 ps
CPU time 4.86 seconds
Started Jun 26 05:54:36 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 206828 kb
Host smart-75c2cd31-3880-456d-9518-ff449887694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214787706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4214787706
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.226541723
Short name T474
Test name
Test status
Simulation time 80224746 ps
CPU time 3.88 seconds
Started Jun 26 05:54:37 PM PDT 24
Finished Jun 26 05:54:43 PM PDT 24
Peak memory 208812 kb
Host smart-56e49a43-a546-4722-886e-ccb5e079039d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226541723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.226541723
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3869607657
Short name T634
Test name
Test status
Simulation time 904912215 ps
CPU time 7.6 seconds
Started Jun 26 05:54:37 PM PDT 24
Finished Jun 26 05:54:46 PM PDT 24
Peak memory 209228 kb
Host smart-c795af76-fd94-4120-8320-614e422cadb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869607657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3869607657
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4270746164
Short name T258
Test name
Test status
Simulation time 48854441 ps
CPU time 2.76 seconds
Started Jun 26 05:54:39 PM PDT 24
Finished Jun 26 05:54:43 PM PDT 24
Peak memory 207056 kb
Host smart-9a7b943b-eed1-48c7-9cd9-b24b713afbe2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270746164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4270746164
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2627934152
Short name T405
Test name
Test status
Simulation time 248781184 ps
CPU time 1.81 seconds
Started Jun 26 05:54:36 PM PDT 24
Finished Jun 26 05:54:40 PM PDT 24
Peak memory 207644 kb
Host smart-4584c2f1-a05e-4dae-839e-0e07e9d1f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627934152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2627934152
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2773994367
Short name T895
Test name
Test status
Simulation time 102290601 ps
CPU time 3.65 seconds
Started Jun 26 05:54:39 PM PDT 24
Finished Jun 26 05:54:44 PM PDT 24
Peak memory 208480 kb
Host smart-b95136fe-a0e9-4c6e-a1db-1b240d45ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773994367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2773994367
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.589800860
Short name T527
Test name
Test status
Simulation time 1759584435 ps
CPU time 7.51 seconds
Started Jun 26 05:54:41 PM PDT 24
Finished Jun 26 05:54:49 PM PDT 24
Peak memory 208028 kb
Host smart-0c6f6aea-c9b8-4c50-a20d-a3d73087ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589800860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.589800860
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2928461415
Short name T766
Test name
Test status
Simulation time 132230709 ps
CPU time 3.43 seconds
Started Jun 26 05:54:39 PM PDT 24
Finished Jun 26 05:54:44 PM PDT 24
Peak memory 210340 kb
Host smart-2e4730ed-e653-462f-bb46-590717ca2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928461415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2928461415
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1395352967
Short name T814
Test name
Test status
Simulation time 47628750 ps
CPU time 0.95 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:54:49 PM PDT 24
Peak memory 206044 kb
Host smart-22732473-4363-48f8-b1da-3c5c833a556a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395352967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1395352967
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.818311573
Short name T399
Test name
Test status
Simulation time 122631748 ps
CPU time 2.75 seconds
Started Jun 26 05:54:38 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 214332 kb
Host smart-1fa931ec-5362-4e40-8914-9f5f21045993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818311573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.818311573
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3341440145
Short name T772
Test name
Test status
Simulation time 137948320 ps
CPU time 4.59 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:52 PM PDT 24
Peak memory 214436 kb
Host smart-9fe89200-d3bf-46bf-baa8-89864be7355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341440145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3341440145
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3296131136
Short name T813
Test name
Test status
Simulation time 69129662 ps
CPU time 2.94 seconds
Started Jun 26 05:54:40 PM PDT 24
Finished Jun 26 05:54:44 PM PDT 24
Peak memory 214368 kb
Host smart-9fd12a4c-0a38-47cb-a178-eebd073ecd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296131136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3296131136
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1750397664
Short name T266
Test name
Test status
Simulation time 340946986 ps
CPU time 2.98 seconds
Started Jun 26 05:54:47 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 214252 kb
Host smart-5a320e9c-07fa-41df-a9a3-9b5d9611643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750397664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1750397664
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.2506704339
Short name T548
Test name
Test status
Simulation time 102541960 ps
CPU time 3.93 seconds
Started Jun 26 05:54:36 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 207728 kb
Host smart-824b3f69-4e95-4587-93f6-91101474981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506704339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2506704339
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2988242545
Short name T276
Test name
Test status
Simulation time 380142249 ps
CPU time 4.26 seconds
Started Jun 26 05:54:35 PM PDT 24
Finished Jun 26 05:54:41 PM PDT 24
Peak memory 208832 kb
Host smart-0a5e33f9-63a4-4135-89e5-36a5d739758c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988242545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2988242545
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2056718341
Short name T569
Test name
Test status
Simulation time 219591404 ps
CPU time 3.03 seconds
Started Jun 26 05:54:37 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 208904 kb
Host smart-21d58fe7-cd51-4f86-abc6-52ee01c46c0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056718341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2056718341
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2748677537
Short name T350
Test name
Test status
Simulation time 361304070 ps
CPU time 10.39 seconds
Started Jun 26 05:54:41 PM PDT 24
Finished Jun 26 05:54:52 PM PDT 24
Peak memory 208032 kb
Host smart-11de3ac7-9afa-4ac9-97c2-422bc1074b46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748677537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2748677537
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2901822394
Short name T537
Test name
Test status
Simulation time 61986484 ps
CPU time 3.14 seconds
Started Jun 26 05:54:37 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 207004 kb
Host smart-48787a24-7175-4282-96d1-2f697e7aa901
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901822394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2901822394
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2023893883
Short name T192
Test name
Test status
Simulation time 82568635 ps
CPU time 2.14 seconds
Started Jun 26 05:54:47 PM PDT 24
Finished Jun 26 05:54:52 PM PDT 24
Peak memory 214308 kb
Host smart-e72d0150-121b-45d4-aa61-a9f9631418f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023893883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2023893883
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2018169572
Short name T457
Test name
Test status
Simulation time 120013328 ps
CPU time 2.73 seconds
Started Jun 26 05:54:38 PM PDT 24
Finished Jun 26 05:54:42 PM PDT 24
Peak memory 206900 kb
Host smart-92526631-3118-4356-bdfa-88913d5bca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018169572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2018169572
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1312154602
Short name T853
Test name
Test status
Simulation time 3789204623 ps
CPU time 23.85 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:55:13 PM PDT 24
Peak memory 217456 kb
Host smart-989c2288-fa80-40fc-85e6-0aec13822b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312154602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1312154602
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2207714953
Short name T356
Test name
Test status
Simulation time 268002872 ps
CPU time 3.02 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:51 PM PDT 24
Peak memory 208408 kb
Host smart-c3219396-b924-417f-bc16-e3168991d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207714953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2207714953
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3732108086
Short name T782
Test name
Test status
Simulation time 36462227 ps
CPU time 2.39 seconds
Started Jun 26 05:54:47 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 210368 kb
Host smart-b3512632-0012-46ac-9d87-823900eaf89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732108086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3732108086
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2293456707
Short name T521
Test name
Test status
Simulation time 46710417 ps
CPU time 0.73 seconds
Started Jun 26 05:54:42 PM PDT 24
Finished Jun 26 05:54:44 PM PDT 24
Peak memory 206024 kb
Host smart-05fd019a-82bf-4afb-ae6e-0e7defa45265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293456707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2293456707
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4096482079
Short name T25
Test name
Test status
Simulation time 1301731071 ps
CPU time 12.08 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 222860 kb
Host smart-f83dba82-0359-4496-b8a2-5b950939e19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096482079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4096482079
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3334501650
Short name T735
Test name
Test status
Simulation time 212873067 ps
CPU time 2.66 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:48 PM PDT 24
Peak memory 210408 kb
Host smart-76a9a43e-27af-49dc-bb41-23962b0700e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334501650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3334501650
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.829395904
Short name T801
Test name
Test status
Simulation time 286110581 ps
CPU time 3.85 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:49 PM PDT 24
Peak memory 214240 kb
Host smart-d201c601-17d9-40b7-bbed-200cd5039d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829395904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.829395904
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.156166199
Short name T105
Test name
Test status
Simulation time 57616093 ps
CPU time 2.51 seconds
Started Jun 26 05:54:43 PM PDT 24
Finished Jun 26 05:54:47 PM PDT 24
Peak memory 220224 kb
Host smart-3966fc27-d229-4be1-a966-93e3e0dd73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156166199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.156166199
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3173216631
Short name T412
Test name
Test status
Simulation time 137671440 ps
CPU time 3.49 seconds
Started Jun 26 05:54:47 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 209872 kb
Host smart-d9aeea08-dce9-4d18-8a51-e549eeb2e32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173216631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3173216631
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3193921313
Short name T686
Test name
Test status
Simulation time 41579314 ps
CPU time 2.6 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:51 PM PDT 24
Peak memory 208244 kb
Host smart-68307d5a-cf6f-474d-bd5a-d0e10143621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193921313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3193921313
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3910558154
Short name T606
Test name
Test status
Simulation time 138376031 ps
CPU time 3.43 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 208544 kb
Host smart-b17be7ac-b1a4-429b-8083-c992b4896281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910558154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3910558154
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3491220943
Short name T715
Test name
Test status
Simulation time 37396959 ps
CPU time 2.27 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:49 PM PDT 24
Peak memory 206976 kb
Host smart-8e8638bc-c2a1-4f69-bd36-422d36498bf4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491220943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3491220943
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2659117045
Short name T483
Test name
Test status
Simulation time 53314951 ps
CPU time 2.81 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 208116 kb
Host smart-5346cc69-2929-4bf8-9633-61ab5ead1e87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659117045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2659117045
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3201780645
Short name T657
Test name
Test status
Simulation time 532821629 ps
CPU time 14.52 seconds
Started Jun 26 05:54:48 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 207964 kb
Host smart-e5cf8ce0-3a80-4094-8e67-e8b8b5016d8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201780645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3201780645
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2876656425
Short name T755
Test name
Test status
Simulation time 1237899799 ps
CPU time 12.44 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:58 PM PDT 24
Peak memory 214404 kb
Host smart-a4cd7da7-9e1f-4f58-88ca-52d82d78540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876656425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2876656425
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1076135226
Short name T406
Test name
Test status
Simulation time 496751336 ps
CPU time 14.11 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:55:02 PM PDT 24
Peak memory 208376 kb
Host smart-ff8a601f-185e-4e0a-bb1c-58ada626beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076135226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1076135226
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.992656553
Short name T470
Test name
Test status
Simulation time 34469858 ps
CPU time 0.82 seconds
Started Jun 26 05:54:50 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 206024 kb
Host smart-24c928a4-ccfe-44b6-a290-1e601fcd11da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992656553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.992656553
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.576813203
Short name T251
Test name
Test status
Simulation time 679742300 ps
CPU time 7.64 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 214332 kb
Host smart-365716a3-9c60-419e-9017-c4223a4af00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576813203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.576813203
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3723827219
Short name T852
Test name
Test status
Simulation time 125798814 ps
CPU time 1.89 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 210828 kb
Host smart-edd8a3fe-22d1-48a1-8e90-c107c9542531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723827219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3723827219
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.62889717
Short name T439
Test name
Test status
Simulation time 11780342 ps
CPU time 0.84 seconds
Started Jun 26 05:54:56 PM PDT 24
Finished Jun 26 05:54:58 PM PDT 24
Peak memory 206052 kb
Host smart-6cbb3d5e-a5d2-4ee9-8ab3-0e1bee50c7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62889717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.62889717
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2695963132
Short name T101
Test name
Test status
Simulation time 183699378 ps
CPU time 4.68 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 222516 kb
Host smart-d8840fea-7ceb-4329-b9c7-3c485c146850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695963132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2695963132
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3410345497
Short name T833
Test name
Test status
Simulation time 66095940 ps
CPU time 2.54 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:54:51 PM PDT 24
Peak memory 214548 kb
Host smart-c4003bce-7ed4-4eb7-8159-793a8165590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410345497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3410345497
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4085231794
Short name T572
Test name
Test status
Simulation time 368615767 ps
CPU time 5.57 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:50 PM PDT 24
Peak memory 208700 kb
Host smart-ff7ba3c2-eb33-4e67-8119-8c3b9c53f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085231794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4085231794
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2100117183
Short name T624
Test name
Test status
Simulation time 53150227 ps
CPU time 2.72 seconds
Started Jun 26 05:54:47 PM PDT 24
Finished Jun 26 05:54:52 PM PDT 24
Peak memory 206848 kb
Host smart-ee397f84-85ad-49ef-9a2b-b8fab7e10b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100117183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2100117183
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2915243267
Short name T916
Test name
Test status
Simulation time 431911415 ps
CPU time 10.72 seconds
Started Jun 26 05:54:45 PM PDT 24
Finished Jun 26 05:54:58 PM PDT 24
Peak memory 208120 kb
Host smart-5a3209dc-240b-4f09-8e30-4dff0957b8ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915243267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2915243267
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2873430570
Short name T518
Test name
Test status
Simulation time 20723234 ps
CPU time 1.76 seconds
Started Jun 26 05:54:47 PM PDT 24
Finished Jun 26 05:54:51 PM PDT 24
Peak memory 207100 kb
Host smart-6e20b506-f467-445c-984f-535dbb597e2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873430570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2873430570
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3573503569
Short name T658
Test name
Test status
Simulation time 291920015 ps
CPU time 3.67 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 208756 kb
Host smart-8933742a-0fb0-4506-8e19-5099ea16110f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573503569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3573503569
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3152082951
Short name T633
Test name
Test status
Simulation time 54520740 ps
CPU time 2.84 seconds
Started Jun 26 05:54:55 PM PDT 24
Finished Jun 26 05:54:59 PM PDT 24
Peak memory 209456 kb
Host smart-bc57c5dd-fe8a-4f23-bab8-bd3258f5127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152082951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3152082951
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2245695163
Short name T721
Test name
Test status
Simulation time 441806671 ps
CPU time 3.83 seconds
Started Jun 26 05:54:46 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 207128 kb
Host smart-64043b6c-74c9-487f-a3f9-450eebd8be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245695163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2245695163
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1561243326
Short name T134
Test name
Test status
Simulation time 875553161 ps
CPU time 5.84 seconds
Started Jun 26 05:54:44 PM PDT 24
Finished Jun 26 05:54:51 PM PDT 24
Peak memory 208704 kb
Host smart-0782383e-08b8-4759-9a9c-11f139763076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561243326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1561243326
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3580920676
Short name T394
Test name
Test status
Simulation time 84806527 ps
CPU time 2 seconds
Started Jun 26 05:54:59 PM PDT 24
Finished Jun 26 05:55:02 PM PDT 24
Peak memory 210012 kb
Host smart-847e5c8f-8370-49eb-9f50-dd4080e88461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580920676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3580920676
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1106774776
Short name T476
Test name
Test status
Simulation time 46662692 ps
CPU time 0.89 seconds
Started Jun 26 05:54:55 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 206048 kb
Host smart-75daefd4-dfc9-4572-ba5c-183e5280ac9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106774776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1106774776
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1310913061
Short name T733
Test name
Test status
Simulation time 145365430 ps
CPU time 3.11 seconds
Started Jun 26 05:54:51 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 214348 kb
Host smart-e8ef71f2-76e5-4bd7-9ace-60f79a3b0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310913061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1310913061
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4196762164
Short name T899
Test name
Test status
Simulation time 308350817 ps
CPU time 3.37 seconds
Started Jun 26 05:54:50 PM PDT 24
Finished Jun 26 05:54:56 PM PDT 24
Peak memory 217672 kb
Host smart-d6c5c1cb-8b23-47ee-86ac-b77664fcfa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196762164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4196762164
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1262607307
Short name T835
Test name
Test status
Simulation time 4547353168 ps
CPU time 50.23 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 208588 kb
Host smart-e6077262-9cae-4bc1-b8ff-6dbb4791b376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262607307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1262607307
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.595362167
Short name T564
Test name
Test status
Simulation time 183740437 ps
CPU time 2.65 seconds
Started Jun 26 05:54:54 PM PDT 24
Finished Jun 26 05:54:58 PM PDT 24
Peak memory 206412 kb
Host smart-88d7f063-30d9-4281-9534-f420f8eb83e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595362167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.595362167
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2605807289
Short name T347
Test name
Test status
Simulation time 77349514 ps
CPU time 3.68 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:54:59 PM PDT 24
Peak memory 208408 kb
Host smart-890b52e4-ad6f-4bcc-a808-a9ba8afd8f16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605807289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2605807289
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2014559698
Short name T862
Test name
Test status
Simulation time 271643933 ps
CPU time 2.79 seconds
Started Jun 26 05:54:54 PM PDT 24
Finished Jun 26 05:54:58 PM PDT 24
Peak memory 217848 kb
Host smart-5afb512a-78b7-4009-869c-1321cbc818d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014559698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2014559698
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.114074935
Short name T582
Test name
Test status
Simulation time 2254310161 ps
CPU time 24.91 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:55:19 PM PDT 24
Peak memory 209056 kb
Host smart-4f8c4fdf-7298-4cbc-96ff-d0b7e8aa0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114074935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.114074935
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3193893643
Short name T613
Test name
Test status
Simulation time 424287413 ps
CPU time 4.5 seconds
Started Jun 26 05:54:56 PM PDT 24
Finished Jun 26 05:55:01 PM PDT 24
Peak memory 209420 kb
Host smart-916984f9-43ef-4189-a761-0e22eaefa496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193893643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3193893643
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.694527844
Short name T689
Test name
Test status
Simulation time 115645598 ps
CPU time 2.15 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 210384 kb
Host smart-9876b33c-0fc2-4e00-8bf3-0188004411a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694527844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.694527844
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2987980454
Short name T574
Test name
Test status
Simulation time 57098211 ps
CPU time 0.82 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:08 PM PDT 24
Peak memory 206052 kb
Host smart-cfab9973-f482-4511-a59f-cd2d4d9ca8a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987980454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2987980454
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1180751594
Short name T421
Test name
Test status
Simulation time 194276744 ps
CPU time 10.92 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:55:06 PM PDT 24
Peak memory 215836 kb
Host smart-9795dc9e-88ab-4c1d-bb26-892738ac4979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180751594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1180751594
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2310888512
Short name T562
Test name
Test status
Simulation time 94013770 ps
CPU time 2.31 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:54:56 PM PDT 24
Peak memory 218432 kb
Host smart-4890694e-c338-487a-893d-8fde5e12b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310888512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2310888512
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2513328731
Short name T817
Test name
Test status
Simulation time 57394658 ps
CPU time 2.46 seconds
Started Jun 26 05:54:56 PM PDT 24
Finished Jun 26 05:55:00 PM PDT 24
Peak memory 214352 kb
Host smart-370887fe-01f9-47a6-a7f5-9fe91238cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513328731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2513328731
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1164896899
Short name T309
Test name
Test status
Simulation time 1388024124 ps
CPU time 5.85 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:55:01 PM PDT 24
Peak memory 214296 kb
Host smart-f4add6e3-decf-4671-9b27-bc4aa48169f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164896899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1164896899
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4221304207
Short name T224
Test name
Test status
Simulation time 165541729 ps
CPU time 2.47 seconds
Started Jun 26 05:54:55 PM PDT 24
Finished Jun 26 05:54:59 PM PDT 24
Peak memory 208468 kb
Host smart-0554465d-8336-4893-9cf3-f38971a88438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221304207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4221304207
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.213292111
Short name T387
Test name
Test status
Simulation time 4656491007 ps
CPU time 34.25 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:55:29 PM PDT 24
Peak memory 214344 kb
Host smart-7236c0e1-930b-4189-a968-db2c9f83b94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213292111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.213292111
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1275848050
Short name T694
Test name
Test status
Simulation time 54400376 ps
CPU time 2.68 seconds
Started Jun 26 05:54:52 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 206148 kb
Host smart-22bfcb15-9ef9-4516-88c7-795fa2f42254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275848050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1275848050
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.4051456691
Short name T538
Test name
Test status
Simulation time 319252404 ps
CPU time 4.16 seconds
Started Jun 26 05:54:57 PM PDT 24
Finished Jun 26 05:55:02 PM PDT 24
Peak memory 208856 kb
Host smart-cc07cb3b-3660-43a8-a5f8-e74a18821dd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051456691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.4051456691
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3909428757
Short name T385
Test name
Test status
Simulation time 45821011 ps
CPU time 1.85 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:54:57 PM PDT 24
Peak memory 206968 kb
Host smart-5e6e3b25-6ad2-40dc-b70b-af20fedb2bb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909428757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3909428757
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1856978470
Short name T587
Test name
Test status
Simulation time 186232173 ps
CPU time 6.96 seconds
Started Jun 26 05:54:54 PM PDT 24
Finished Jun 26 05:55:03 PM PDT 24
Peak memory 207188 kb
Host smart-b235556e-caca-4274-840f-37528bc4f86d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856978470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1856978470
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2001513343
Short name T912
Test name
Test status
Simulation time 68684739 ps
CPU time 3.02 seconds
Started Jun 26 05:54:59 PM PDT 24
Finished Jun 26 05:55:04 PM PDT 24
Peak memory 210144 kb
Host smart-35941e96-70c2-4aab-b99a-3059ad1ce7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001513343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2001513343
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4153132578
Short name T709
Test name
Test status
Simulation time 408627421 ps
CPU time 3.12 seconds
Started Jun 26 05:54:51 PM PDT 24
Finished Jun 26 05:54:56 PM PDT 24
Peak memory 208500 kb
Host smart-eb1c2a35-17b4-464a-9b7f-e1c34502e5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153132578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4153132578
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.4219835864
Short name T671
Test name
Test status
Simulation time 282326744 ps
CPU time 16.22 seconds
Started Jun 26 05:55:05 PM PDT 24
Finished Jun 26 05:55:25 PM PDT 24
Peak memory 222628 kb
Host smart-e8b3f99e-59a6-4cae-a698-f759cd0a24ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219835864 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.4219835864
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1897819114
Short name T201
Test name
Test status
Simulation time 279344539 ps
CPU time 7.51 seconds
Started Jun 26 05:54:53 PM PDT 24
Finished Jun 26 05:55:03 PM PDT 24
Peak memory 208160 kb
Host smart-88b195da-66a6-4492-84a3-96dffe91659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897819114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1897819114
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1814841900
Short name T168
Test name
Test status
Simulation time 776239886 ps
CPU time 2.09 seconds
Started Jun 26 05:54:51 PM PDT 24
Finished Jun 26 05:54:56 PM PDT 24
Peak memory 209920 kb
Host smart-aa960ab2-e3b9-4494-8bc3-45718bc6530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814841900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1814841900
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3968133794
Short name T883
Test name
Test status
Simulation time 23510120 ps
CPU time 0.76 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:07 PM PDT 24
Peak memory 206032 kb
Host smart-c530a244-1e59-4cf1-a378-1d3e0f6e1054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968133794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3968133794
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1455711225
Short name T139
Test name
Test status
Simulation time 150356637 ps
CPU time 2.57 seconds
Started Jun 26 05:55:07 PM PDT 24
Finished Jun 26 05:55:12 PM PDT 24
Peak memory 214984 kb
Host smart-d917cf70-b958-4165-89ac-fada00301251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455711225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1455711225
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1927688903
Short name T30
Test name
Test status
Simulation time 187869183 ps
CPU time 2.97 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:10 PM PDT 24
Peak memory 214716 kb
Host smart-097a9c3f-aae0-45f2-8c7c-4b942fcb83b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927688903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1927688903
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.362465340
Short name T885
Test name
Test status
Simulation time 2087665786 ps
CPU time 11.49 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 208920 kb
Host smart-92ace370-d0d7-44e8-9677-40e80c4932f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362465340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.362465340
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3422117112
Short name T655
Test name
Test status
Simulation time 152872365 ps
CPU time 5.29 seconds
Started Jun 26 05:55:07 PM PDT 24
Finished Jun 26 05:55:15 PM PDT 24
Peak memory 220308 kb
Host smart-17afc6f0-2a68-4510-8121-66c84ecc6d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422117112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3422117112
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3767674650
Short name T341
Test name
Test status
Simulation time 923024056 ps
CPU time 9.64 seconds
Started Jun 26 05:55:02 PM PDT 24
Finished Jun 26 05:55:15 PM PDT 24
Peak memory 210336 kb
Host smart-0ccc4684-fa91-43b6-81ab-da7beff94e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767674650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3767674650
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.24725565
Short name T786
Test name
Test status
Simulation time 525217249 ps
CPU time 4.33 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:07 PM PDT 24
Peak memory 206900 kb
Host smart-afdf2d9f-a0f2-49bb-995c-b93119638bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24725565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.24725565
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2618061494
Short name T911
Test name
Test status
Simulation time 749227276 ps
CPU time 3.5 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:09 PM PDT 24
Peak memory 206996 kb
Host smart-0decfde7-1655-4519-91b6-bcd2dc78681f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618061494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2618061494
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3740785622
Short name T463
Test name
Test status
Simulation time 151994308 ps
CPU time 2.78 seconds
Started Jun 26 05:55:00 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 208648 kb
Host smart-4a64a05f-8cb3-445a-9997-9687b1d3ca76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740785622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3740785622
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2022732035
Short name T620
Test name
Test status
Simulation time 3478858196 ps
CPU time 25.19 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:31 PM PDT 24
Peak memory 208496 kb
Host smart-1b108882-0389-4f1f-a8e8-47700b089d15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022732035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2022732035
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1220289870
Short name T259
Test name
Test status
Simulation time 366418675 ps
CPU time 12.79 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:15 PM PDT 24
Peak memory 220580 kb
Host smart-ddaeb138-95be-4a6b-b9d1-dd0fd100f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220289870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1220289870
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2958673381
Short name T865
Test name
Test status
Simulation time 85214126 ps
CPU time 1.77 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:08 PM PDT 24
Peak memory 207180 kb
Host smart-3aa39e50-68e1-488f-81ce-0880ec255c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958673381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2958673381
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4191689463
Short name T317
Test name
Test status
Simulation time 2285067197 ps
CPU time 54.45 seconds
Started Jun 26 05:55:02 PM PDT 24
Finished Jun 26 05:55:59 PM PDT 24
Peak memory 215032 kb
Host smart-878d511b-dd21-47cd-9e2d-bef98b545dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191689463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4191689463
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1107052624
Short name T702
Test name
Test status
Simulation time 106969958 ps
CPU time 3.98 seconds
Started Jun 26 05:55:02 PM PDT 24
Finished Jun 26 05:55:08 PM PDT 24
Peak memory 214440 kb
Host smart-edd0b2e8-455c-423d-a349-e64dc5e6330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107052624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1107052624
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4159490635
Short name T68
Test name
Test status
Simulation time 587866554 ps
CPU time 2.71 seconds
Started Jun 26 05:55:05 PM PDT 24
Finished Jun 26 05:55:11 PM PDT 24
Peak memory 210460 kb
Host smart-0795c839-2ca4-4e8b-bb5d-82bc43396e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159490635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4159490635
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3148215299
Short name T437
Test name
Test status
Simulation time 28681222 ps
CPU time 0.98 seconds
Started Jun 26 05:55:02 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 206184 kb
Host smart-4a49d8a1-a59a-49fe-a675-6fa84a40566e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148215299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3148215299
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2527164380
Short name T615
Test name
Test status
Simulation time 790520725 ps
CPU time 7.74 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:13 PM PDT 24
Peak memory 217476 kb
Host smart-9fd24db2-4ba1-42e2-84ba-4688b3aa2fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527164380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2527164380
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1650876778
Short name T799
Test name
Test status
Simulation time 57107849 ps
CPU time 2.99 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:06 PM PDT 24
Peak memory 214320 kb
Host smart-1c1727b4-c880-4fe2-8d82-8d732706fb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650876778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1650876778
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2798473862
Short name T5
Test name
Test status
Simulation time 383470388 ps
CPU time 5.66 seconds
Started Jun 26 05:55:05 PM PDT 24
Finished Jun 26 05:55:14 PM PDT 24
Peak memory 208652 kb
Host smart-647d5882-c9c1-4a23-95fa-7bfe0509cd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798473862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2798473862
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2415659447
Short name T792
Test name
Test status
Simulation time 469291428 ps
CPU time 4.57 seconds
Started Jun 26 05:55:02 PM PDT 24
Finished Jun 26 05:55:09 PM PDT 24
Peak memory 209528 kb
Host smart-8e11d469-db77-4b75-9aae-9fc2709833df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415659447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2415659447
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3775096597
Short name T257
Test name
Test status
Simulation time 2078791171 ps
CPU time 20.49 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:23 PM PDT 24
Peak memory 222396 kb
Host smart-1f9973fd-ac75-4a20-8354-72470574f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775096597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3775096597
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1842460404
Short name T713
Test name
Test status
Simulation time 237327477 ps
CPU time 3.18 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:07 PM PDT 24
Peak memory 206884 kb
Host smart-fe4a25de-4b56-45e6-a379-dfa4e09ca63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842460404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1842460404
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1049358196
Short name T383
Test name
Test status
Simulation time 1014434091 ps
CPU time 8.75 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:14 PM PDT 24
Peak memory 208856 kb
Host smart-651124c1-b121-433f-8605-af1998c2a301
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049358196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1049358196
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4060434470
Short name T472
Test name
Test status
Simulation time 5539394859 ps
CPU time 13.46 seconds
Started Jun 26 05:55:00 PM PDT 24
Finished Jun 26 05:55:15 PM PDT 24
Peak memory 208944 kb
Host smart-c08a2dad-03ad-4afe-b380-3e88821e98f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060434470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4060434470
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3778195352
Short name T764
Test name
Test status
Simulation time 676764846 ps
CPU time 8.31 seconds
Started Jun 26 05:55:07 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 208132 kb
Host smart-608f3dd6-0975-4618-837a-71a443db6aac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778195352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3778195352
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.534720868
Short name T354
Test name
Test status
Simulation time 37288880 ps
CPU time 2.72 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:10 PM PDT 24
Peak memory 209756 kb
Host smart-c7615e6f-80e1-4466-8b77-80b1ed671fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534720868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.534720868
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4187184816
Short name T604
Test name
Test status
Simulation time 23500483 ps
CPU time 1.79 seconds
Started Jun 26 05:55:01 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 206748 kb
Host smart-c36eb72b-1909-4f10-975b-b6b510270313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187184816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4187184816
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2883388654
Short name T600
Test name
Test status
Simulation time 144100004 ps
CPU time 4.68 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:12 PM PDT 24
Peak memory 207324 kb
Host smart-8f01770c-287f-40f7-8bbd-c8866c372abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883388654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2883388654
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2396866114
Short name T870
Test name
Test status
Simulation time 58811291 ps
CPU time 1.77 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:10 PM PDT 24
Peak memory 210040 kb
Host smart-9cecaa05-14aa-4abf-9e1b-921cb108c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396866114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2396866114
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3215567325
Short name T842
Test name
Test status
Simulation time 12880052 ps
CPU time 0.75 seconds
Started Jun 26 05:54:04 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 206032 kb
Host smart-fa8fb08c-aee1-411a-8bcd-0b84b8ca5bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215567325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3215567325
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3228345078
Short name T21
Test name
Test status
Simulation time 63790918 ps
CPU time 1.54 seconds
Started Jun 26 05:53:58 PM PDT 24
Finished Jun 26 05:54:01 PM PDT 24
Peak memory 215636 kb
Host smart-b9e4e448-d9a3-4bb8-837f-8b65f33e82ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228345078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3228345078
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.4064751026
Short name T710
Test name
Test status
Simulation time 1173803785 ps
CPU time 27.41 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:29 PM PDT 24
Peak memory 222472 kb
Host smart-9aa0cebf-6035-47d4-bce3-2c17630bf390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064751026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4064751026
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3692904200
Short name T391
Test name
Test status
Simulation time 5539779029 ps
CPU time 57.84 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:55:01 PM PDT 24
Peak memory 215276 kb
Host smart-135ca3e2-0fc7-4130-b537-8a98611faf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692904200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3692904200
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4077096546
Short name T288
Test name
Test status
Simulation time 365292970 ps
CPU time 4.51 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 222744 kb
Host smart-caceaa27-0157-426f-bbac-6e4b139d754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077096546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4077096546
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1244581928
Short name T311
Test name
Test status
Simulation time 382745763 ps
CPU time 3.74 seconds
Started Jun 26 05:54:03 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 222452 kb
Host smart-13e86a0e-eb69-4ad3-adf3-8ae0ce363de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244581928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1244581928
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.805714053
Short name T699
Test name
Test status
Simulation time 1349360940 ps
CPU time 6.39 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:00 PM PDT 24
Peak memory 209500 kb
Host smart-0ed35fd5-a794-4d44-8906-00befab219d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805714053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.805714053
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4259118290
Short name T108
Test name
Test status
Simulation time 232597663 ps
CPU time 7.36 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 230636 kb
Host smart-0f8c6548-aa10-4ae1-a2aa-1b496feee33d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259118290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4259118290
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3331943907
Short name T583
Test name
Test status
Simulation time 3520785336 ps
CPU time 35.57 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:54:30 PM PDT 24
Peak memory 208448 kb
Host smart-3dc19d32-1a35-48e8-a188-850000b7e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331943907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3331943907
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.868674992
Short name T535
Test name
Test status
Simulation time 80316950 ps
CPU time 1.86 seconds
Started Jun 26 05:53:52 PM PDT 24
Finished Jun 26 05:53:55 PM PDT 24
Peak memory 206868 kb
Host smart-07eda6d6-3532-48c9-aab0-af71487546b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868674992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.868674992
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2116395911
Short name T605
Test name
Test status
Simulation time 83559326 ps
CPU time 2.5 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:53:56 PM PDT 24
Peak memory 207384 kb
Host smart-79788a63-dcef-462e-a769-8059ce48f84d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116395911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2116395911
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4189888117
Short name T759
Test name
Test status
Simulation time 248107499 ps
CPU time 3.07 seconds
Started Jun 26 05:53:55 PM PDT 24
Finished Jun 26 05:53:59 PM PDT 24
Peak memory 207020 kb
Host smart-15bbf7cf-e038-4263-8721-0d423b310036
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189888117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4189888117
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3714015318
Short name T279
Test name
Test status
Simulation time 147011979 ps
CPU time 5.81 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 218060 kb
Host smart-60005293-92a5-4b7c-91d3-c6c2f4bb4606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714015318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3714015318
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4237963604
Short name T493
Test name
Test status
Simulation time 178503337 ps
CPU time 2.49 seconds
Started Jun 26 05:53:53 PM PDT 24
Finished Jun 26 05:53:57 PM PDT 24
Peak memory 208512 kb
Host smart-cd39bdc1-6c86-47d0-a452-9b5252b6c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237963604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4237963604
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1000587669
Short name T827
Test name
Test status
Simulation time 876295571 ps
CPU time 28.87 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:30 PM PDT 24
Peak memory 215944 kb
Host smart-043ab399-a79b-45ac-8b63-af9dfcd3caab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000587669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1000587669
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1480569685
Short name T784
Test name
Test status
Simulation time 314702753 ps
CPU time 5.09 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 210508 kb
Host smart-7c0f212b-553c-4269-b095-8128bd8b9096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480569685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1480569685
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3563193876
Short name T826
Test name
Test status
Simulation time 46120378 ps
CPU time 2.09 seconds
Started Jun 26 05:53:59 PM PDT 24
Finished Jun 26 05:54:02 PM PDT 24
Peak memory 210084 kb
Host smart-4181ea0c-8ec7-4fb7-9073-ac05281470ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563193876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3563193876
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3696584319
Short name T478
Test name
Test status
Simulation time 30354495 ps
CPU time 1.04 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:24 PM PDT 24
Peak memory 206120 kb
Host smart-4b35a312-728b-4c0b-992b-032fae0e43ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696584319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3696584319
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2697344744
Short name T820
Test name
Test status
Simulation time 44268072 ps
CPU time 3.35 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:10 PM PDT 24
Peak memory 214356 kb
Host smart-31987efc-3619-4b1a-af14-0503d5745aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697344744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2697344744
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4052355810
Short name T325
Test name
Test status
Simulation time 883739181 ps
CPU time 25.36 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 214168 kb
Host smart-8982f009-c766-4900-998f-2dd9e7d9ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052355810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4052355810
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3438662239
Short name T268
Test name
Test status
Simulation time 55324158 ps
CPU time 3.05 seconds
Started Jun 26 05:55:08 PM PDT 24
Finished Jun 26 05:55:14 PM PDT 24
Peak memory 222440 kb
Host smart-33edfb87-956b-4e9c-ae8f-3fd863c9f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438662239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3438662239
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4136141272
Short name T53
Test name
Test status
Simulation time 90208430 ps
CPU time 2.88 seconds
Started Jun 26 05:55:12 PM PDT 24
Finished Jun 26 05:55:19 PM PDT 24
Peak memory 206100 kb
Host smart-9e897325-0062-46d4-8bb1-7c87e50883d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136141272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4136141272
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3802671634
Short name T723
Test name
Test status
Simulation time 214464654 ps
CPU time 3.67 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:09 PM PDT 24
Peak memory 218340 kb
Host smart-23286c09-8239-4d66-aa1e-2fea9cde8ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802671634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3802671634
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2068383948
Short name T330
Test name
Test status
Simulation time 271883824 ps
CPU time 3.57 seconds
Started Jun 26 05:55:00 PM PDT 24
Finished Jun 26 05:55:05 PM PDT 24
Peak memory 206732 kb
Host smart-18f01078-d171-4a01-b5b5-21be20000389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068383948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2068383948
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4205447622
Short name T641
Test name
Test status
Simulation time 2424856472 ps
CPU time 7.08 seconds
Started Jun 26 05:55:04 PM PDT 24
Finished Jun 26 05:55:14 PM PDT 24
Peak memory 208844 kb
Host smart-c68a2a1e-51f4-45e5-8ebc-a44d37684094
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205447622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4205447622
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2755111165
Short name T371
Test name
Test status
Simulation time 2506571473 ps
CPU time 4.9 seconds
Started Jun 26 05:55:05 PM PDT 24
Finished Jun 26 05:55:13 PM PDT 24
Peak memory 209036 kb
Host smart-7e40bdf7-e05e-4a9e-8b7c-f5fe9711f313
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755111165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2755111165
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3573994707
Short name T888
Test name
Test status
Simulation time 179254555 ps
CPU time 2.77 seconds
Started Jun 26 05:55:05 PM PDT 24
Finished Jun 26 05:55:11 PM PDT 24
Peak memory 207000 kb
Host smart-fe85b2d4-3fb2-492a-81e7-2b08d0c8ed64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573994707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3573994707
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2925936990
Short name T211
Test name
Test status
Simulation time 178883062 ps
CPU time 4.99 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:30 PM PDT 24
Peak memory 216000 kb
Host smart-58821979-f847-4457-aded-bd3bd763969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925936990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2925936990
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3933550794
Short name T460
Test name
Test status
Simulation time 434076364 ps
CPU time 3.07 seconds
Started Jun 26 05:55:03 PM PDT 24
Finished Jun 26 05:55:08 PM PDT 24
Peak memory 208572 kb
Host smart-b893af9c-7783-479f-a4d7-206f427f3c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933550794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3933550794
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3114481474
Short name T736
Test name
Test status
Simulation time 1116305449 ps
CPU time 12.56 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:25 PM PDT 24
Peak memory 222648 kb
Host smart-b9f18bcd-5d73-4260-a5a7-cf5884aa1b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114481474 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3114481474
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4209844673
Short name T357
Test name
Test status
Simulation time 344054915 ps
CPU time 3.88 seconds
Started Jun 26 05:55:08 PM PDT 24
Finished Jun 26 05:55:16 PM PDT 24
Peak memory 209392 kb
Host smart-9ac42250-3956-40b5-be88-db6184900df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209844673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4209844673
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2570495188
Short name T802
Test name
Test status
Simulation time 469312295 ps
CPU time 3.35 seconds
Started Jun 26 05:55:10 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 211032 kb
Host smart-63dcf87e-71c2-4062-9eac-d8fca14bd06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570495188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2570495188
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1240371113
Short name T681
Test name
Test status
Simulation time 16821056 ps
CPU time 0.77 seconds
Started Jun 26 05:55:10 PM PDT 24
Finished Jun 26 05:55:15 PM PDT 24
Peak memory 205960 kb
Host smart-86884643-a5b0-4fc6-b37d-ce36690b61d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240371113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1240371113
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.735179478
Short name T370
Test name
Test status
Simulation time 56017028 ps
CPU time 3.73 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:55:19 PM PDT 24
Peak memory 215380 kb
Host smart-3428840e-f632-4354-806f-3a150bcf62c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735179478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.735179478
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2072251863
Short name T12
Test name
Test status
Simulation time 551030616 ps
CPU time 4.45 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:55:20 PM PDT 24
Peak memory 222708 kb
Host smart-5f0f7292-7bce-40a2-85d4-57aa6b487ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072251863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2072251863
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.957648918
Short name T730
Test name
Test status
Simulation time 327072247 ps
CPU time 2.34 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:15 PM PDT 24
Peak memory 209356 kb
Host smart-4fe1342e-0c4b-4fe0-9668-3a26df8b6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957648918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.957648918
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2286236735
Short name T380
Test name
Test status
Simulation time 69137711 ps
CPU time 3.58 seconds
Started Jun 26 05:55:10 PM PDT 24
Finished Jun 26 05:55:17 PM PDT 24
Peak memory 208304 kb
Host smart-e763e2e4-727a-4848-bd25-6e3b07c8691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286236735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2286236735
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2141636405
Short name T706
Test name
Test status
Simulation time 75082363 ps
CPU time 2.94 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 220580 kb
Host smart-a1c816a2-cf90-4caa-bfed-e91bc250933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141636405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2141636405
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3675825707
Short name T318
Test name
Test status
Simulation time 104684894 ps
CPU time 4.04 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 209320 kb
Host smart-92a9e874-5916-490a-87d4-7b9ad5bad0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675825707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3675825707
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3665044207
Short name T282
Test name
Test status
Simulation time 187403014 ps
CPU time 3.92 seconds
Started Jun 26 05:55:10 PM PDT 24
Finished Jun 26 05:55:18 PM PDT 24
Peak memory 208304 kb
Host smart-fec2f796-132b-4e09-b785-8ee8fea79f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665044207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3665044207
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.223775219
Short name T510
Test name
Test status
Simulation time 1545713146 ps
CPU time 4.61 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:30 PM PDT 24
Peak memory 208060 kb
Host smart-26e795dd-9904-4346-ab84-008ffc028a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223775219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.223775219
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3535873287
Short name T676
Test name
Test status
Simulation time 5298152526 ps
CPU time 30.67 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 209248 kb
Host smart-82641f80-4640-4cd0-be54-97cfaf5c3910
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535873287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3535873287
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3923306307
Short name T519
Test name
Test status
Simulation time 431679754 ps
CPU time 2.95 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 207112 kb
Host smart-3fe5b6e6-49bd-4310-9352-75a0c89697b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923306307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3923306307
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.620347944
Short name T509
Test name
Test status
Simulation time 69839362 ps
CPU time 3.13 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 208072 kb
Host smart-f2fc652d-0768-4c7c-b592-994880e98285
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620347944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.620347944
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1563904377
Short name T840
Test name
Test status
Simulation time 222436337 ps
CPU time 2.79 seconds
Started Jun 26 05:55:10 PM PDT 24
Finished Jun 26 05:55:17 PM PDT 24
Peak memory 214332 kb
Host smart-e7d0dc56-8896-4d7b-8ec8-376c0bc4e318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563904377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1563904377
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3740665704
Short name T598
Test name
Test status
Simulation time 75488574 ps
CPU time 2.5 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:16 PM PDT 24
Peak memory 208696 kb
Host smart-b36ec642-1545-4e39-955e-aad501f12036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740665704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3740665704
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2693510644
Short name T531
Test name
Test status
Simulation time 389604197 ps
CPU time 6.28 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:19 PM PDT 24
Peak memory 207824 kb
Host smart-bcb1ae16-2f11-4857-bfb5-5bb21636bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693510644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2693510644
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2312322637
Short name T771
Test name
Test status
Simulation time 586954144 ps
CPU time 4.22 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:30 PM PDT 24
Peak memory 210488 kb
Host smart-b47a58a4-4a71-400d-b3f9-0f97c0a06532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312322637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2312322637
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2087435550
Short name T492
Test name
Test status
Simulation time 188310269 ps
CPU time 0.92 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 206064 kb
Host smart-1e5c4021-442d-4f1b-80ad-5fe1bebaa650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087435550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2087435550
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1097326677
Short name T142
Test name
Test status
Simulation time 219119469 ps
CPU time 3.78 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 215448 kb
Host smart-a3456b10-01ac-4341-8aa5-9c59aef45a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097326677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1097326677
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3282798342
Short name T732
Test name
Test status
Simulation time 397143073 ps
CPU time 2.12 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 216928 kb
Host smart-3855bc13-325c-4fbe-b843-f5f4ee7b4ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282798342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3282798342
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3068864703
Short name T882
Test name
Test status
Simulation time 110572277 ps
CPU time 2.78 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 207340 kb
Host smart-f387fd2f-39f3-4d8b-99e2-af7bdcada54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068864703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3068864703
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2575925079
Short name T46
Test name
Test status
Simulation time 65000294 ps
CPU time 2.72 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 209888 kb
Host smart-86255a2e-6f4a-4efb-a3e0-8326ae84e1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575925079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2575925079
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.179197
Short name T836
Test name
Test status
Simulation time 105430927 ps
CPU time 2.6 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:24 PM PDT 24
Peak memory 214284 kb
Host smart-2f46934a-1f8b-4f71-9123-15569b5e3d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.179197
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2947842773
Short name T56
Test name
Test status
Simulation time 222708896 ps
CPU time 2.69 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 219784 kb
Host smart-f7b543dc-8f5e-42da-8969-bfa23e7e5e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947842773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2947842773
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1136539200
Short name T520
Test name
Test status
Simulation time 148606117 ps
CPU time 6.09 seconds
Started Jun 26 05:55:11 PM PDT 24
Finished Jun 26 05:55:21 PM PDT 24
Peak memory 208784 kb
Host smart-ce5c09d2-ddd5-453b-9483-95745262e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136539200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1136539200
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1977332547
Short name T239
Test name
Test status
Simulation time 69198393 ps
CPU time 3.3 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 208612 kb
Host smart-b3d1ded4-74cb-407f-aab8-beb5ecf12823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977332547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1977332547
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3529357701
Short name T859
Test name
Test status
Simulation time 707984269 ps
CPU time 5.5 seconds
Started Jun 26 05:55:09 PM PDT 24
Finished Jun 26 05:55:19 PM PDT 24
Peak memory 207928 kb
Host smart-4a4b567d-e87e-4e34-b43e-8501067bc65e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529357701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3529357701
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.730033856
Short name T602
Test name
Test status
Simulation time 303202180 ps
CPU time 4.7 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:31 PM PDT 24
Peak memory 208544 kb
Host smart-bf9d9703-a22a-4639-bbe8-b9937feb3180
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730033856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.730033856
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.64164444
Short name T214
Test name
Test status
Simulation time 64547364 ps
CPU time 3.46 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 206900 kb
Host smart-36a2f4f7-a53f-4919-b674-16659888f345
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64164444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.64164444
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.643063717
Short name T300
Test name
Test status
Simulation time 93069317 ps
CPU time 4.31 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 208632 kb
Host smart-667e2779-95b5-45fc-a996-3d69fe757105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643063717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.643063717
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.900358293
Short name T903
Test name
Test status
Simulation time 139444383 ps
CPU time 2.83 seconds
Started Jun 26 05:55:10 PM PDT 24
Finished Jun 26 05:55:17 PM PDT 24
Peak memory 207156 kb
Host smart-8550ac61-3312-4548-a38d-71f96e58faf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900358293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.900358293
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.851984543
Short name T614
Test name
Test status
Simulation time 4926297462 ps
CPU time 22.32 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 216268 kb
Host smart-20b694b3-2c8f-4b60-b065-2d13e136ee4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851984543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.851984543
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.456644879
Short name T343
Test name
Test status
Simulation time 2157643599 ps
CPU time 21.65 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:44 PM PDT 24
Peak memory 222400 kb
Host smart-7029e2fd-663d-4e85-9ffc-236bcc8bceae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456644879 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.456644879
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1786135685
Short name T413
Test name
Test status
Simulation time 192711841 ps
CPU time 5.84 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 208836 kb
Host smart-74fa5a69-7083-496b-9da8-9031d036c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786135685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1786135685
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3992542565
Short name T777
Test name
Test status
Simulation time 91463350 ps
CPU time 2.17 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 209808 kb
Host smart-96b37524-52a2-4ba0-8fe2-653c84a8aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992542565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3992542565
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1507327798
Short name T465
Test name
Test status
Simulation time 23714707 ps
CPU time 0.85 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:24 PM PDT 24
Peak memory 206064 kb
Host smart-bdb08bbd-d4f1-4cd7-9adb-4954cc0e5913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507327798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1507327798
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2638373929
Short name T414
Test name
Test status
Simulation time 656988580 ps
CPU time 8.82 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:33 PM PDT 24
Peak memory 214580 kb
Host smart-6e542874-2bab-4649-be0d-c7443dd8af8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638373929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2638373929
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2754315074
Short name T72
Test name
Test status
Simulation time 149183508 ps
CPU time 6.8 seconds
Started Jun 26 05:55:22 PM PDT 24
Finished Jun 26 05:55:33 PM PDT 24
Peak memory 210684 kb
Host smart-4346a5e2-acdb-4003-af61-8bf1bfe6605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754315074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2754315074
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2894614731
Short name T81
Test name
Test status
Simulation time 341102186 ps
CPU time 2.65 seconds
Started Jun 26 05:55:22 PM PDT 24
Finished Jun 26 05:55:29 PM PDT 24
Peak memory 209052 kb
Host smart-40774a3c-7993-44dd-90c1-8d298890d9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894614731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2894614731
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3586184996
Short name T843
Test name
Test status
Simulation time 780811604 ps
CPU time 3.82 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 214312 kb
Host smart-c00de575-3198-448e-b8bf-0076abd578d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586184996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3586184996
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3845860002
Short name T195
Test name
Test status
Simulation time 142534981 ps
CPU time 6.29 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 222348 kb
Host smart-8cc5afb6-35cc-4863-ba74-57b96480e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845860002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3845860002
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3764871499
Short name T481
Test name
Test status
Simulation time 290926064 ps
CPU time 3.35 seconds
Started Jun 26 05:55:23 PM PDT 24
Finished Jun 26 05:55:31 PM PDT 24
Peak memory 219740 kb
Host smart-293f5335-680d-4bec-a2e6-7bef8ba4a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764871499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3764871499
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.218600213
Short name T302
Test name
Test status
Simulation time 4738577766 ps
CPU time 37.51 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:56:02 PM PDT 24
Peak memory 214476 kb
Host smart-0d9f19e9-b10b-4dd3-a294-b26a1701ad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218600213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.218600213
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1562536140
Short name T364
Test name
Test status
Simulation time 118207038 ps
CPU time 3.4 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:26 PM PDT 24
Peak memory 208564 kb
Host smart-d4db1cac-e142-4482-baad-3436986f220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562536140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1562536140
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.688584260
Short name T464
Test name
Test status
Simulation time 194654295 ps
CPU time 2.41 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:25 PM PDT 24
Peak memory 206984 kb
Host smart-6e0ed8f3-0d9d-491b-b30f-2a18febeeae4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688584260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.688584260
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1495951751
Short name T728
Test name
Test status
Simulation time 2094926617 ps
CPU time 47.75 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:56:10 PM PDT 24
Peak memory 208248 kb
Host smart-b21a20a5-26d9-47ae-ae25-a8a90726a0aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495951751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1495951751
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.785996251
Short name T494
Test name
Test status
Simulation time 121073998 ps
CPU time 2.9 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 209900 kb
Host smart-80b8ea1c-9a73-4bf4-8b4d-1a94cf6a314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785996251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.785996251
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2907782237
Short name T550
Test name
Test status
Simulation time 416783325 ps
CPU time 3.09 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 208700 kb
Host smart-51c5faba-9b02-4ffe-ab82-d2e6a0d8b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907782237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2907782237
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2206993754
Short name T162
Test name
Test status
Simulation time 6214174916 ps
CPU time 22.93 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:49 PM PDT 24
Peak memory 222896 kb
Host smart-ea0eb400-2096-43a6-bab9-dd89600879d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206993754 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2206993754
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.227165456
Short name T849
Test name
Test status
Simulation time 480170152 ps
CPU time 7.21 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 209792 kb
Host smart-c87f15f0-198f-466a-809e-1d809c560000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227165456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.227165456
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.720606391
Short name T526
Test name
Test status
Simulation time 44912809 ps
CPU time 0.92 seconds
Started Jun 26 05:55:31 PM PDT 24
Finished Jun 26 05:55:36 PM PDT 24
Peak memory 206028 kb
Host smart-c4c4908f-19d5-4139-b87d-305519785f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720606391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.720606391
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.942149690
Short name T138
Test name
Test status
Simulation time 126090900 ps
CPU time 2.65 seconds
Started Jun 26 05:55:17 PM PDT 24
Finished Jun 26 05:55:23 PM PDT 24
Peak memory 215508 kb
Host smart-62e5f2c1-0c23-4918-b80f-e7a2006358ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942149690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.942149690
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3081257685
Short name T71
Test name
Test status
Simulation time 47141582 ps
CPU time 2.06 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 207444 kb
Host smart-bf02b1e8-1670-4e93-9bd8-5d21ef614e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081257685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3081257685
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4245114298
Short name T97
Test name
Test status
Simulation time 53195813 ps
CPU time 2.81 seconds
Started Jun 26 05:55:20 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 220944 kb
Host smart-287b9558-2153-4d74-aac2-c6567425311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245114298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4245114298
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1322113763
Short name T607
Test name
Test status
Simulation time 200003456 ps
CPU time 2.89 seconds
Started Jun 26 05:55:22 PM PDT 24
Finished Jun 26 05:55:29 PM PDT 24
Peak memory 214316 kb
Host smart-d603c959-266d-4966-8045-b7cffa3c6b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322113763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1322113763
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2553698021
Short name T920
Test name
Test status
Simulation time 2460758839 ps
CPU time 36.72 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:56:01 PM PDT 24
Peak memory 208708 kb
Host smart-4fbb6dab-81ba-40b6-9913-95d5681c061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553698021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2553698021
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2752214044
Short name T541
Test name
Test status
Simulation time 440486637 ps
CPU time 4.46 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 208736 kb
Host smart-049e71dc-2400-4b16-9ca9-9028fbaa2e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752214044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2752214044
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2750026010
Short name T756
Test name
Test status
Simulation time 282815468 ps
CPU time 2.91 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 208584 kb
Host smart-50f09cb6-2408-4905-8053-d1108a51b233
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750026010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2750026010
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2939937658
Short name T739
Test name
Test status
Simulation time 304065767 ps
CPU time 4.03 seconds
Started Jun 26 05:55:21 PM PDT 24
Finished Jun 26 05:55:29 PM PDT 24
Peak memory 208704 kb
Host smart-77492875-4cfd-4555-b855-a256632a7bfc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939937658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2939937658
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2446311943
Short name T616
Test name
Test status
Simulation time 104111680 ps
CPU time 2.91 seconds
Started Jun 26 05:55:24 PM PDT 24
Finished Jun 26 05:55:30 PM PDT 24
Peak memory 206956 kb
Host smart-91b03aff-e45c-49fa-ab84-6b71ba49ea9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446311943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2446311943
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.683694471
Short name T738
Test name
Test status
Simulation time 39692055 ps
CPU time 2.45 seconds
Started Jun 26 05:55:25 PM PDT 24
Finished Jun 26 05:55:31 PM PDT 24
Peak memory 209584 kb
Host smart-79947098-f1f2-43ec-9e74-9f8d0b142324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683694471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.683694471
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3415314261
Short name T407
Test name
Test status
Simulation time 363996351 ps
CPU time 2.92 seconds
Started Jun 26 05:55:19 PM PDT 24
Finished Jun 26 05:55:27 PM PDT 24
Peak memory 207040 kb
Host smart-36dbba09-5d72-4966-9771-f02579edb160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415314261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3415314261
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.400019270
Short name T622
Test name
Test status
Simulation time 133533236 ps
CPU time 6.02 seconds
Started Jun 26 05:55:27 PM PDT 24
Finished Jun 26 05:55:37 PM PDT 24
Peak memory 215600 kb
Host smart-fa7e0110-c7fc-490d-9088-4e7829fff92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400019270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.400019270
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.4087444187
Short name T161
Test name
Test status
Simulation time 216743446 ps
CPU time 13.16 seconds
Started Jun 26 05:55:29 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 222236 kb
Host smart-e2670545-76a4-459a-94af-e4d1e8576588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087444187 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.4087444187
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1016512859
Short name T245
Test name
Test status
Simulation time 581216090 ps
CPU time 5.67 seconds
Started Jun 26 05:55:18 PM PDT 24
Finished Jun 26 05:55:28 PM PDT 24
Peak memory 210504 kb
Host smart-b66c4ea6-7cc9-4752-9a06-224639849712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016512859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1016512859
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3462286908
Short name T177
Test name
Test status
Simulation time 2524566122 ps
CPU time 14.06 seconds
Started Jun 26 05:55:31 PM PDT 24
Finished Jun 26 05:55:49 PM PDT 24
Peak memory 210296 kb
Host smart-dbec1853-04ea-46f7-ad9a-ed562f9f0575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462286908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3462286908
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1124054872
Short name T459
Test name
Test status
Simulation time 40975805 ps
CPU time 0.8 seconds
Started Jun 26 05:55:25 PM PDT 24
Finished Jun 26 05:55:29 PM PDT 24
Peak memory 206064 kb
Host smart-a3f48c32-723e-4034-a7a3-faa065bf2e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124054872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1124054872
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3276794182
Short name T432
Test name
Test status
Simulation time 143840514 ps
CPU time 2.92 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 215152 kb
Host smart-00908626-e12d-4811-b864-f463153cdf89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276794182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3276794182
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3852868773
Short name T700
Test name
Test status
Simulation time 60113485 ps
CPU time 2.73 seconds
Started Jun 26 05:55:27 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 208088 kb
Host smart-543b9dff-a8a7-42b8-b089-696eb908f59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852868773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3852868773
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2162917827
Short name T307
Test name
Test status
Simulation time 44420152 ps
CPU time 2.29 seconds
Started Jun 26 05:55:25 PM PDT 24
Finished Jun 26 05:55:31 PM PDT 24
Peak memory 211720 kb
Host smart-9927dff1-edf5-461e-b808-aa77b13bbfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162917827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2162917827
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4196941987
Short name T894
Test name
Test status
Simulation time 647819852 ps
CPU time 3.61 seconds
Started Jun 26 05:55:25 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 206152 kb
Host smart-681c91ae-707d-48b1-8e6f-903eee30a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196941987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4196941987
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3483074666
Short name T365
Test name
Test status
Simulation time 201243291 ps
CPU time 5.22 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:36 PM PDT 24
Peak memory 209804 kb
Host smart-6f47150e-7c0f-4911-8ed3-f98195a50686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483074666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3483074666
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2097542667
Short name T446
Test name
Test status
Simulation time 199761961 ps
CPU time 3.88 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:47 PM PDT 24
Peak memory 208604 kb
Host smart-508ddaa5-afd0-4e46-95b7-c0c18206efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097542667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2097542667
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.818737636
Short name T906
Test name
Test status
Simulation time 134391867 ps
CPU time 2.63 seconds
Started Jun 26 05:55:27 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 208672 kb
Host smart-ebad7641-775a-4e18-b0b8-0bafd2d415bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818737636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.818737636
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2047364382
Short name T448
Test name
Test status
Simulation time 1383810397 ps
CPU time 5.58 seconds
Started Jun 26 05:55:24 PM PDT 24
Finished Jun 26 05:55:33 PM PDT 24
Peak memory 206952 kb
Host smart-29346ca8-4fa1-49ac-a835-3d0c4255b16c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047364382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2047364382
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1795484988
Short name T111
Test name
Test status
Simulation time 51937087 ps
CPU time 2.84 seconds
Started Jun 26 05:55:29 PM PDT 24
Finished Jun 26 05:55:36 PM PDT 24
Peak memory 208212 kb
Host smart-fb3c658f-c54f-42e5-9826-dd57cbc1c78d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795484988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1795484988
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1485224285
Short name T400
Test name
Test status
Simulation time 43276126 ps
CPU time 2.06 seconds
Started Jun 26 05:55:27 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 209872 kb
Host smart-4fe28838-bbc3-4bf8-81cd-8825f89f5827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485224285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1485224285
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4116302186
Short name T451
Test name
Test status
Simulation time 422658590 ps
CPU time 4.84 seconds
Started Jun 26 05:55:26 PM PDT 24
Finished Jun 26 05:55:34 PM PDT 24
Peak memory 206724 kb
Host smart-4cc138ad-46df-4879-bc68-9a23a6241236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116302186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4116302186
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2369319888
Short name T27
Test name
Test status
Simulation time 3449699193 ps
CPU time 16 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:59 PM PDT 24
Peak memory 217244 kb
Host smart-805b6470-80a2-4372-85b0-87c0ca6d020e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369319888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2369319888
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1817304847
Short name T737
Test name
Test status
Simulation time 378687930 ps
CPU time 4.49 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:35 PM PDT 24
Peak memory 214348 kb
Host smart-68282303-7930-454b-8980-b5cf9b53b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817304847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1817304847
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4228440915
Short name T788
Test name
Test status
Simulation time 109251453 ps
CPU time 2.77 seconds
Started Jun 26 05:55:31 PM PDT 24
Finished Jun 26 05:55:38 PM PDT 24
Peak memory 210212 kb
Host smart-4d2ff0c1-4b9d-4261-a20c-7c69ba217a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228440915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4228440915
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1787894831
Short name T579
Test name
Test status
Simulation time 260380746 ps
CPU time 0.79 seconds
Started Jun 26 05:55:37 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 206068 kb
Host smart-f1142f43-3bcb-4605-968c-11e9b41e9456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787894831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1787894831
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3776351696
Short name T32
Test name
Test status
Simulation time 111000661 ps
CPU time 3.33 seconds
Started Jun 26 05:55:31 PM PDT 24
Finished Jun 26 05:55:38 PM PDT 24
Peak memory 214228 kb
Host smart-84d3904e-f671-49cb-89fd-3fe7ce3d9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776351696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3776351696
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.838192799
Short name T55
Test name
Test status
Simulation time 81849894 ps
CPU time 1.67 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:33 PM PDT 24
Peak memory 207496 kb
Host smart-7271b52b-0c24-4905-89c1-d91bec5ebac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838192799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.838192799
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1963538886
Short name T838
Test name
Test status
Simulation time 1100288695 ps
CPU time 11.14 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 214300 kb
Host smart-2b941b7d-9a34-44ec-a306-981b26f8ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963538886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1963538886
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3028812746
Short name T724
Test name
Test status
Simulation time 244639791 ps
CPU time 2.5 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 214292 kb
Host smart-8ad9f6b0-7add-4a5e-b484-376ff96ab043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028812746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3028812746
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3000815207
Short name T219
Test name
Test status
Simulation time 50818169 ps
CPU time 2.88 seconds
Started Jun 26 05:55:26 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 210036 kb
Host smart-5b420eab-44e0-493d-abbb-55aa7fbedacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000815207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3000815207
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.965492556
Short name T204
Test name
Test status
Simulation time 1013840601 ps
CPU time 7.07 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:50 PM PDT 24
Peak memory 209128 kb
Host smart-5ec6735f-b833-4da5-9b7e-6cf80beb575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965492556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.965492556
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2972525237
Short name T469
Test name
Test status
Simulation time 63628527 ps
CPU time 3.02 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:35 PM PDT 24
Peak memory 208116 kb
Host smart-75aad73a-e7fc-4125-b9e7-4e8ff939152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972525237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2972525237
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1867108561
Short name T329
Test name
Test status
Simulation time 197699860 ps
CPU time 3.58 seconds
Started Jun 26 05:55:26 PM PDT 24
Finished Jun 26 05:55:33 PM PDT 24
Peak memory 207152 kb
Host smart-c1886cf4-bf71-4fff-ad85-672ea8cb1391
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867108561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1867108561
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4288710807
Short name T546
Test name
Test status
Simulation time 1102115134 ps
CPU time 3.98 seconds
Started Jun 26 05:55:25 PM PDT 24
Finished Jun 26 05:55:32 PM PDT 24
Peak memory 208620 kb
Host smart-e01bbe80-4a74-47b3-a53d-efd9ef2eec6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288710807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4288710807
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.366292448
Short name T313
Test name
Test status
Simulation time 1465692159 ps
CPU time 19.68 seconds
Started Jun 26 05:55:28 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 208556 kb
Host smart-7aa786c3-df23-4eb5-ac12-23078cf7cc3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366292448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.366292448
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2006048492
Short name T642
Test name
Test status
Simulation time 135349160 ps
CPU time 3.26 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:49 PM PDT 24
Peak memory 214320 kb
Host smart-7baa282e-480f-47c1-8a65-95d84133966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006048492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2006048492
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.132101062
Short name T592
Test name
Test status
Simulation time 1333472319 ps
CPU time 4.04 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:47 PM PDT 24
Peak memory 208432 kb
Host smart-29289374-4fa6-44f5-9d49-e88a9286d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132101062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.132101062
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1407408685
Short name T292
Test name
Test status
Simulation time 1157568514 ps
CPU time 38.9 seconds
Started Jun 26 05:55:36 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 215812 kb
Host smart-351fb35d-7eb1-4e5e-909a-d732a5e38dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407408685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1407408685
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.4148218774
Short name T644
Test name
Test status
Simulation time 123471400 ps
CPU time 5.44 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:43 PM PDT 24
Peak memory 220000 kb
Host smart-941961a1-d1c2-4d6b-8699-c034436224b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148218774 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.4148218774
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.117498843
Short name T271
Test name
Test status
Simulation time 303265657 ps
CPU time 5.49 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 218312 kb
Host smart-3faa1e63-7cad-4902-9bb5-286012024bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117498843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.117498843
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1962847345
Short name T897
Test name
Test status
Simulation time 67696521 ps
CPU time 2.21 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 210532 kb
Host smart-c2f36eac-8a0b-4d55-bf42-1d98b413ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962847345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1962847345
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3481683809
Short name T480
Test name
Test status
Simulation time 12063263 ps
CPU time 0.76 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:40 PM PDT 24
Peak memory 206056 kb
Host smart-7b4f3c9b-2825-484d-86da-ee5475d07db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481683809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3481683809
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2126911274
Short name T35
Test name
Test status
Simulation time 78358658 ps
CPU time 3.49 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:44 PM PDT 24
Peak memory 210216 kb
Host smart-17beefd4-e102-4ffc-b305-090b38bddc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126911274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2126911274
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.120710125
Short name T264
Test name
Test status
Simulation time 136693850 ps
CPU time 1.78 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:43 PM PDT 24
Peak memory 207416 kb
Host smart-8f6a30b8-ab6b-415b-b1f8-58f057463409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120710125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.120710125
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1953520508
Short name T661
Test name
Test status
Simulation time 1135701785 ps
CPU time 8.11 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 209632 kb
Host smart-760f6b72-f8c1-433a-89c0-795324b42080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953520508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1953520508
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1640650027
Short name T64
Test name
Test status
Simulation time 338773762 ps
CPU time 2.99 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 220520 kb
Host smart-ea904232-3569-4bff-9d72-947f002e86f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640650027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1640650027
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.590231008
Short name T695
Test name
Test status
Simulation time 1149405769 ps
CPU time 8.88 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 218236 kb
Host smart-aed9c077-0b61-462b-870c-9a3a2393f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590231008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.590231008
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3757084112
Short name T473
Test name
Test status
Simulation time 496085530 ps
CPU time 4.02 seconds
Started Jun 26 05:55:36 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 208448 kb
Host smart-aba83aa2-bcdf-4969-b6ea-4f265e65133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757084112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3757084112
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.668115075
Short name T488
Test name
Test status
Simulation time 54914108 ps
CPU time 2.91 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:49 PM PDT 24
Peak memory 208812 kb
Host smart-774971ac-0211-4d79-8a2b-8ccaf5003784
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668115075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.668115075
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3624581341
Short name T272
Test name
Test status
Simulation time 153775228 ps
CPU time 2.34 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:43 PM PDT 24
Peak memory 208880 kb
Host smart-f1fd6d17-175c-413b-95c4-f8df66d3beaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624581341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3624581341
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2136651970
Short name T636
Test name
Test status
Simulation time 264076058 ps
CPU time 3.81 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 206980 kb
Host smart-69090a21-c1ee-4019-a708-56dee2bb5079
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136651970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2136651970
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2817668712
Short name T653
Test name
Test status
Simulation time 78575880 ps
CPU time 1.74 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 218484 kb
Host smart-9e6f5e4c-50fb-42c2-b6c6-4742a50f0a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817668712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2817668712
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.393430697
Short name T910
Test name
Test status
Simulation time 540323595 ps
CPU time 5.96 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 208108 kb
Host smart-be7e5eb8-5765-4078-9392-f9326b87fb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393430697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.393430697
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2874982535
Short name T879
Test name
Test status
Simulation time 410461276 ps
CPU time 16.07 seconds
Started Jun 26 05:55:32 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 215788 kb
Host smart-484df28d-170c-4bc8-830d-ff6f9b5ff195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874982535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2874982535
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1749679468
Short name T889
Test name
Test status
Simulation time 563526176 ps
CPU time 24.27 seconds
Started Jun 26 05:55:40 PM PDT 24
Finished Jun 26 05:56:11 PM PDT 24
Peak memory 222620 kb
Host smart-1cd280b1-fed9-4e64-830b-4c96502ed43f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749679468 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1749679468
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2570726348
Short name T386
Test name
Test status
Simulation time 221881870 ps
CPU time 5.59 seconds
Started Jun 26 05:55:37 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 218312 kb
Host smart-e5300fd3-7dd7-435c-8bb9-84cd359a38d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570726348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2570726348
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2573274474
Short name T540
Test name
Test status
Simulation time 335493684 ps
CPU time 2.29 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:43 PM PDT 24
Peak memory 210424 kb
Host smart-09248d72-ca37-4a2f-bda4-566025cd25ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573274474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2573274474
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1572340374
Short name T445
Test name
Test status
Simulation time 14568765 ps
CPU time 0.95 seconds
Started Jun 26 05:55:37 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 206088 kb
Host smart-d0979e4f-db7d-4157-931e-5753e0f04bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572340374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1572340374
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3696245799
Short name T635
Test name
Test status
Simulation time 76836211 ps
CPU time 2.53 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 209052 kb
Host smart-c94aaab7-2226-47db-9461-91f19dcef63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696245799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3696245799
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.332664308
Short name T82
Test name
Test status
Simulation time 20469089 ps
CPU time 1.79 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:50 PM PDT 24
Peak memory 207528 kb
Host smart-e49c5867-fd75-4e96-976b-4fbd59c90092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332664308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.332664308
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1318908314
Short name T839
Test name
Test status
Simulation time 2789293249 ps
CPU time 16.7 seconds
Started Jun 26 05:55:47 PM PDT 24
Finished Jun 26 05:56:12 PM PDT 24
Peak memory 220884 kb
Host smart-ade6c5b1-3421-4187-ab56-32c51e73916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318908314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1318908314
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2067804586
Short name T388
Test name
Test status
Simulation time 834498594 ps
CPU time 8.11 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 214296 kb
Host smart-8ab86903-f048-454a-be7b-5a848e1e5212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067804586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2067804586
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.1928783545
Short name T804
Test name
Test status
Simulation time 343704817 ps
CPU time 7.83 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:53 PM PDT 24
Peak memory 218188 kb
Host smart-497d43fe-f485-4fda-ab27-78375851bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928783545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1928783545
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3898200321
Short name T213
Test name
Test status
Simulation time 70168381 ps
CPU time 3.55 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:44 PM PDT 24
Peak memory 208592 kb
Host smart-60bda4a4-c2a2-4b04-993b-8be4918543fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898200321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3898200321
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1361950743
Short name T263
Test name
Test status
Simulation time 124945647 ps
CPU time 2.51 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 206992 kb
Host smart-16c73e9a-59e9-48dd-ab11-4b375870c22b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361950743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1361950743
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.699152792
Short name T471
Test name
Test status
Simulation time 1708957917 ps
CPU time 9.77 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:58 PM PDT 24
Peak memory 207776 kb
Host smart-da504d19-1c0e-427a-aab6-d9863887ca8a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699152792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.699152792
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1306591480
Short name T595
Test name
Test status
Simulation time 113507175 ps
CPU time 4.69 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 207184 kb
Host smart-98ac2dee-121f-4f2d-bd0d-0ec375e297f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306591480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1306591480
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.471499684
Short name T667
Test name
Test status
Simulation time 715619311 ps
CPU time 3.5 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:43 PM PDT 24
Peak memory 209156 kb
Host smart-c0a2ade6-a167-43d3-a2bf-ca7d25ae24b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471499684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.471499684
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3999223209
Short name T443
Test name
Test status
Simulation time 14092224412 ps
CPU time 50.45 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:56:28 PM PDT 24
Peak memory 208280 kb
Host smart-47d21bd4-0aa7-4320-a2a9-533bb893186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999223209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3999223209
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.821118035
Short name T256
Test name
Test status
Simulation time 3886965644 ps
CPU time 37.09 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 216720 kb
Host smart-4089023d-2eeb-423e-81f1-9bb249426b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821118035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.821118035
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.443008102
Short name T662
Test name
Test status
Simulation time 587486202 ps
CPU time 5.26 seconds
Started Jun 26 05:55:38 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 214300 kb
Host smart-5e0bb9eb-73e9-4ad9-acf0-fdbe068404dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443008102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.443008102
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1330154436
Short name T4
Test name
Test status
Simulation time 110795561 ps
CPU time 1.82 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 209840 kb
Host smart-a3de94c9-9e0e-427c-8a13-16e1b125b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330154436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1330154436
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1947758161
Short name T590
Test name
Test status
Simulation time 120199825 ps
CPU time 0.82 seconds
Started Jun 26 05:55:40 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 206032 kb
Host smart-07798cb5-3d75-4cea-94a2-f7008294bdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947758161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1947758161
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1736469011
Short name T914
Test name
Test status
Simulation time 33737976 ps
CPU time 2.74 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 214312 kb
Host smart-1fa09aa8-209a-4391-9650-e311f89e0736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736469011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1736469011
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.199661784
Short name T28
Test name
Test status
Simulation time 183498696 ps
CPU time 3.21 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 219004 kb
Host smart-e5fc07a2-4246-45ae-b0f5-931aaef6f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199661784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.199661784
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1312829485
Short name T556
Test name
Test status
Simulation time 236771606 ps
CPU time 3.09 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 210072 kb
Host smart-f1401bb8-5af4-446a-8ec9-fc1bf2aad1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312829485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1312829485
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.299034055
Short name T887
Test name
Test status
Simulation time 329891290 ps
CPU time 3.92 seconds
Started Jun 26 05:55:46 PM PDT 24
Finished Jun 26 05:55:58 PM PDT 24
Peak memory 208724 kb
Host smart-7e34afdd-ba86-4e2a-9bb1-1d70c68ddbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299034055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.299034055
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.688726283
Short name T18
Test name
Test status
Simulation time 203278873 ps
CPU time 2.9 seconds
Started Jun 26 05:55:45 PM PDT 24
Finished Jun 26 05:55:55 PM PDT 24
Peak memory 220440 kb
Host smart-ec58638b-d82b-4906-b05e-bf0628332eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688726283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.688726283
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1017150201
Short name T262
Test name
Test status
Simulation time 254097090 ps
CPU time 6.34 seconds
Started Jun 26 05:55:45 PM PDT 24
Finished Jun 26 05:56:00 PM PDT 24
Peak memory 208828 kb
Host smart-94d67992-d372-45a6-a3e7-6b12b0fbdd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017150201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1017150201
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1456446056
Short name T588
Test name
Test status
Simulation time 513493606 ps
CPU time 3.01 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:45 PM PDT 24
Peak memory 207012 kb
Host smart-3062b621-2fed-49af-89eb-c09ab47fa180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456446056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1456446056
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1089121503
Short name T629
Test name
Test status
Simulation time 162756550 ps
CPU time 4.83 seconds
Started Jun 26 05:55:33 PM PDT 24
Finished Jun 26 05:55:43 PM PDT 24
Peak memory 207832 kb
Host smart-3b391c49-e2d9-468c-abea-91ad5f263060
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089121503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1089121503
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2220526778
Short name T703
Test name
Test status
Simulation time 137459093 ps
CPU time 3.39 seconds
Started Jun 26 05:55:37 PM PDT 24
Finished Jun 26 05:55:48 PM PDT 24
Peak memory 208660 kb
Host smart-75ea5454-69f5-4396-b943-db5f06d1fc73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220526778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2220526778
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1764648788
Short name T868
Test name
Test status
Simulation time 345836543 ps
CPU time 2.94 seconds
Started Jun 26 05:55:34 PM PDT 24
Finished Jun 26 05:55:44 PM PDT 24
Peak memory 207068 kb
Host smart-b77b0a50-bfd4-4bc6-b2c5-380ecf3cbcac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764648788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1764648788
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1895717190
Short name T369
Test name
Test status
Simulation time 149343920 ps
CPU time 2.73 seconds
Started Jun 26 05:55:41 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 218428 kb
Host smart-a19f1c72-3bb1-4f2e-ab2e-c91ff6f9629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895717190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1895717190
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2493602858
Short name T561
Test name
Test status
Simulation time 68139784 ps
CPU time 2.98 seconds
Started Jun 26 05:55:35 PM PDT 24
Finished Jun 26 05:55:46 PM PDT 24
Peak memory 208296 kb
Host smart-3a187a81-9da9-4566-846b-6868a7fd5ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493602858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2493602858
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2743495991
Short name T344
Test name
Test status
Simulation time 973063873 ps
CPU time 20.68 seconds
Started Jun 26 05:55:41 PM PDT 24
Finished Jun 26 05:56:09 PM PDT 24
Peak memory 216200 kb
Host smart-029ac8a8-6ee6-4973-8447-5a6f7960597c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743495991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2743495991
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1632719355
Short name T173
Test name
Test status
Simulation time 188525955 ps
CPU time 10.34 seconds
Started Jun 26 05:55:41 PM PDT 24
Finished Jun 26 05:55:58 PM PDT 24
Peak memory 219856 kb
Host smart-a02b9bc2-5a58-4ee5-88df-d92c90639147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632719355 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1632719355
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1541527811
Short name T714
Test name
Test status
Simulation time 883897368 ps
CPU time 19.72 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:56:10 PM PDT 24
Peak memory 208888 kb
Host smart-0f081605-b6b1-4429-8f66-1055db5236c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541527811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1541527811
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3461011010
Short name T495
Test name
Test status
Simulation time 382445867 ps
CPU time 4.04 seconds
Started Jun 26 05:55:45 PM PDT 24
Finished Jun 26 05:55:56 PM PDT 24
Peak memory 210428 kb
Host smart-e41194f5-702e-4933-bb6e-5bca756d505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461011010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3461011010
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.347262944
Short name T876
Test name
Test status
Simulation time 14084132 ps
CPU time 0.92 seconds
Started Jun 26 05:54:02 PM PDT 24
Finished Jun 26 05:54:05 PM PDT 24
Peak memory 205968 kb
Host smart-3bec3793-71b2-4dbe-9742-a0660f474d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347262944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.347262944
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.59267728
Short name T290
Test name
Test status
Simulation time 69438670 ps
CPU time 4.8 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 222540 kb
Host smart-3fcba020-6fdc-4514-8712-3ac15a63bf57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59267728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.59267728
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.315770349
Short name T11
Test name
Test status
Simulation time 33986540 ps
CPU time 1.86 seconds
Started Jun 26 05:54:03 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 222840 kb
Host smart-47c1f5b6-9368-4ab1-a571-a7c56a8f06f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315770349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.315770349
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2708999172
Short name T66
Test name
Test status
Simulation time 643614794 ps
CPU time 4.64 seconds
Started Jun 26 05:53:59 PM PDT 24
Finished Jun 26 05:54:04 PM PDT 24
Peak memory 210280 kb
Host smart-13999fcb-09ba-4527-85a7-e15d7d8c7cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708999172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2708999172
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1849986454
Short name T106
Test name
Test status
Simulation time 1057112823 ps
CPU time 2.75 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 220192 kb
Host smart-95e499e3-f5d6-4e5b-a1fb-e189649ee17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849986454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1849986454
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2746980036
Short name T560
Test name
Test status
Simulation time 101324097 ps
CPU time 2.06 seconds
Started Jun 26 05:54:04 PM PDT 24
Finished Jun 26 05:54:07 PM PDT 24
Peak memory 208748 kb
Host smart-0816299e-6e01-46d4-826e-d58a4d2c97e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746980036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2746980036
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3528291402
Short name T368
Test name
Test status
Simulation time 193300164 ps
CPU time 4.38 seconds
Started Jun 26 05:54:04 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 208924 kb
Host smart-18c040af-cf77-4fc7-bb4b-470cffe0f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528291402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3528291402
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4185980958
Short name T15
Test name
Test status
Simulation time 418994348 ps
CPU time 5.35 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 233236 kb
Host smart-39cd4ed5-8096-4809-b734-ef4b14f0b58e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185980958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4185980958
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1850136529
Short name T209
Test name
Test status
Simulation time 845403917 ps
CPU time 8.45 seconds
Started Jun 26 05:54:02 PM PDT 24
Finished Jun 26 05:54:12 PM PDT 24
Peak memory 208368 kb
Host smart-3923ff30-f344-421d-88dc-3f1e78babd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850136529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1850136529
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2569291263
Short name T502
Test name
Test status
Simulation time 463681224 ps
CPU time 4.19 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:07 PM PDT 24
Peak memory 206772 kb
Host smart-303069d8-b098-47cd-be3e-87137bbd501f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569291263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2569291263
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4167850992
Short name T532
Test name
Test status
Simulation time 67417546 ps
CPU time 2.88 seconds
Started Jun 26 05:53:59 PM PDT 24
Finished Jun 26 05:54:02 PM PDT 24
Peak memory 206788 kb
Host smart-e53cf42d-8c67-48bd-a086-a3d37d94204d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167850992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4167850992
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2183983140
Short name T409
Test name
Test status
Simulation time 2662235114 ps
CPU time 9.26 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:10 PM PDT 24
Peak memory 208744 kb
Host smart-cfe2d532-ffbf-41a2-941c-753303dd89e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183983140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2183983140
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.47933770
Short name T720
Test name
Test status
Simulation time 85691456 ps
CPU time 2.44 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:04 PM PDT 24
Peak memory 215648 kb
Host smart-76142acc-c703-4183-91f9-a4cc5269dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47933770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.47933770
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2641280512
Short name T447
Test name
Test status
Simulation time 1773198179 ps
CPU time 17.3 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:21 PM PDT 24
Peak memory 207952 kb
Host smart-87a08aed-083e-478b-ac3f-4cdcefcf8720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641280512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2641280512
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.168076028
Short name T558
Test name
Test status
Simulation time 181556475 ps
CPU time 11.13 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:14 PM PDT 24
Peak memory 222616 kb
Host smart-8c0d3774-0619-424b-99fe-0d5f961e616c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168076028 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.168076028
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2325021570
Short name T348
Test name
Test status
Simulation time 67469320 ps
CPU time 4.18 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 214244 kb
Host smart-412e4c4d-e773-4374-9cb3-16a29c4becee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325021570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2325021570
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3651602306
Short name T740
Test name
Test status
Simulation time 55549956 ps
CPU time 1.94 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:03 PM PDT 24
Peak memory 209940 kb
Host smart-d52182a4-a6bb-4172-bec6-7917aa63db0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651602306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3651602306
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1553246125
Short name T748
Test name
Test status
Simulation time 24919414 ps
CPU time 0.77 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 206272 kb
Host smart-0856798e-60d0-44e4-b3fe-67b38ed01a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553246125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1553246125
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2400850357
Short name T854
Test name
Test status
Simulation time 216470107 ps
CPU time 4.2 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:53 PM PDT 24
Peak memory 222576 kb
Host smart-1a8ecb1e-2681-4f9a-baeb-97ffadbed2c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400850357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2400850357
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2864054764
Short name T648
Test name
Test status
Simulation time 40952883 ps
CPU time 1.84 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 214832 kb
Host smart-966fc2e6-f3fb-4d8a-8890-5d4988e78e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864054764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2864054764
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4148895148
Short name T751
Test name
Test status
Simulation time 45670355 ps
CPU time 1.55 seconds
Started Jun 26 05:55:46 PM PDT 24
Finished Jun 26 05:55:55 PM PDT 24
Peak memory 207864 kb
Host smart-13b3ae4f-ea3c-4651-9f14-178e0d14fffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148895148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4148895148
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4106687818
Short name T918
Test name
Test status
Simulation time 75860651 ps
CPU time 3.42 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 209548 kb
Host smart-12c4f47b-0da4-4c37-8e1a-e9108d7674e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106687818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4106687818
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.523006354
Short name T596
Test name
Test status
Simulation time 185545613 ps
CPU time 3.97 seconds
Started Jun 26 05:55:41 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 222436 kb
Host smart-d5fa43b9-e3b3-4280-9c3d-3f6a0d5a4f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523006354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.523006354
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2029758461
Short name T704
Test name
Test status
Simulation time 1032828812 ps
CPU time 4.87 seconds
Started Jun 26 05:55:43 PM PDT 24
Finished Jun 26 05:55:54 PM PDT 24
Peak memory 208880 kb
Host smart-ab6cf168-4136-4443-b549-bf7c594ff95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029758461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2029758461
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3408100001
Short name T547
Test name
Test status
Simulation time 3676201298 ps
CPU time 73.88 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:57:04 PM PDT 24
Peak memory 210004 kb
Host smart-ae733ef7-ac08-4743-85b4-e88e67422e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408100001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3408100001
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.311388337
Short name T717
Test name
Test status
Simulation time 4477392848 ps
CPU time 16.39 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:56:07 PM PDT 24
Peak memory 208496 kb
Host smart-7951e913-f16d-4f6e-ac56-b45e1477376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311388337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.311388337
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2463120533
Short name T529
Test name
Test status
Simulation time 174857271 ps
CPU time 4.94 seconds
Started Jun 26 05:55:41 PM PDT 24
Finished Jun 26 05:55:53 PM PDT 24
Peak memory 208404 kb
Host smart-33e5c12f-dd8c-410d-8fcd-f77c095d2bb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463120533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2463120533
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.453851994
Short name T544
Test name
Test status
Simulation time 50840648 ps
CPU time 2.76 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:53 PM PDT 24
Peak memory 207008 kb
Host smart-309b0874-879d-43a7-bb72-e65575680b96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453851994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.453851994
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3767531611
Short name T3
Test name
Test status
Simulation time 124200470 ps
CPU time 2.45 seconds
Started Jun 26 05:55:45 PM PDT 24
Finished Jun 26 05:55:54 PM PDT 24
Peak memory 207036 kb
Host smart-20d93ea9-aca6-4422-af97-10a5530e7ab5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767531611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3767531611
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4015215099
Short name T411
Test name
Test status
Simulation time 218860299 ps
CPU time 2.3 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:54 PM PDT 24
Peak memory 208624 kb
Host smart-2d88d2e7-129f-442b-afaa-f59b6804eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015215099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4015215099
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.488566134
Short name T719
Test name
Test status
Simulation time 1272632079 ps
CPU time 3.78 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:54 PM PDT 24
Peak memory 208352 kb
Host smart-f657c755-f0eb-4662-8598-e247d2fa24de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488566134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.488566134
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2552687378
Short name T778
Test name
Test status
Simulation time 125164887 ps
CPU time 5.25 seconds
Started Jun 26 05:55:46 PM PDT 24
Finished Jun 26 05:56:00 PM PDT 24
Peak memory 209168 kb
Host smart-1c29542d-67fe-4e88-9243-db3f2d203228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552687378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2552687378
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3598164865
Short name T630
Test name
Test status
Simulation time 100151557 ps
CPU time 3.7 seconds
Started Jun 26 05:55:45 PM PDT 24
Finished Jun 26 05:55:56 PM PDT 24
Peak memory 210196 kb
Host smart-4a087a0b-1d93-4c97-a162-4f70ea874780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598164865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3598164865
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2520816127
Short name T750
Test name
Test status
Simulation time 43919190 ps
CPU time 0.76 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:03 PM PDT 24
Peak memory 206076 kb
Host smart-46355263-1806-49cf-93ca-8f26673b156f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520816127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2520816127
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3823759002
Short name T247
Test name
Test status
Simulation time 44091031 ps
CPU time 3.24 seconds
Started Jun 26 05:55:46 PM PDT 24
Finished Jun 26 05:55:58 PM PDT 24
Peak memory 214972 kb
Host smart-34a7d0fe-dedd-4f0c-b607-ef98b923970c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823759002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3823759002
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.690758472
Short name T324
Test name
Test status
Simulation time 41848966 ps
CPU time 2.38 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:51 PM PDT 24
Peak memory 207408 kb
Host smart-1e7fccb5-50bf-4054-98c4-97d3786b2b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690758472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.690758472
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.758855877
Short name T100
Test name
Test status
Simulation time 111850867 ps
CPU time 4.19 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:03 PM PDT 24
Peak memory 209508 kb
Host smart-e9e01f42-6916-480e-ade1-50271d992c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758855877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.758855877
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3168441677
Short name T880
Test name
Test status
Simulation time 258039121 ps
CPU time 2.56 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:04 PM PDT 24
Peak memory 214284 kb
Host smart-2cca7af5-5187-406d-bd04-0c99cfbbe77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168441677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3168441677
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1026392615
Short name T234
Test name
Test status
Simulation time 55661316 ps
CPU time 3.69 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:04 PM PDT 24
Peak memory 208284 kb
Host smart-e416b3fb-ccf8-4dd6-bea6-5db9c198082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026392615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1026392615
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1386942884
Short name T776
Test name
Test status
Simulation time 156423467 ps
CPU time 3.68 seconds
Started Jun 26 05:55:42 PM PDT 24
Finished Jun 26 05:55:53 PM PDT 24
Peak memory 207492 kb
Host smart-3fc6105d-5a2c-48ee-90ec-5037bdb9b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386942884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1386942884
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.364130778
Short name T696
Test name
Test status
Simulation time 1603998378 ps
CPU time 43.64 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 208388 kb
Host smart-a950568a-afae-4fda-be33-579b1f2911f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364130778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.364130778
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2917815221
Short name T553
Test name
Test status
Simulation time 88084042 ps
CPU time 1.78 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:52 PM PDT 24
Peak memory 207112 kb
Host smart-b1b26e14-aa9e-4e3f-bcad-4bbc541cac59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917815221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2917815221
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4039862440
Short name T742
Test name
Test status
Simulation time 246962897 ps
CPU time 6.55 seconds
Started Jun 26 05:55:44 PM PDT 24
Finished Jun 26 05:55:57 PM PDT 24
Peak memory 208552 kb
Host smart-76a916c0-73ae-44a8-abd2-5539e0d753e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039862440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4039862440
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1592388578
Short name T830
Test name
Test status
Simulation time 10770800164 ps
CPU time 47.04 seconds
Started Jun 26 05:55:43 PM PDT 24
Finished Jun 26 05:56:36 PM PDT 24
Peak memory 209332 kb
Host smart-289f9545-0db3-438e-a593-78bc8b2541d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592388578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1592388578
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3358965007
Short name T666
Test name
Test status
Simulation time 227446819 ps
CPU time 3.95 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:08 PM PDT 24
Peak memory 209832 kb
Host smart-0d59018f-8684-4e1a-b5b9-b26e590e5604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358965007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3358965007
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.203413072
Short name T640
Test name
Test status
Simulation time 121107988 ps
CPU time 4.26 seconds
Started Jun 26 05:55:46 PM PDT 24
Finished Jun 26 05:55:58 PM PDT 24
Peak memory 208716 kb
Host smart-28522807-36be-4056-a84b-ebf047ce60b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203413072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.203413072
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2116159059
Short name T250
Test name
Test status
Simulation time 306079728 ps
CPU time 12.31 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:15 PM PDT 24
Peak memory 222608 kb
Host smart-1e24f6a6-f9ed-446d-9780-a40d2d017496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116159059 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2116159059
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.268755863
Short name T675
Test name
Test status
Simulation time 100787123 ps
CPU time 2.94 seconds
Started Jun 26 05:55:55 PM PDT 24
Finished Jun 26 05:56:10 PM PDT 24
Peak memory 210340 kb
Host smart-8f758cf8-65ec-498c-93d6-d54d11a6462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268755863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.268755863
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3920903449
Short name T396
Test name
Test status
Simulation time 1159431184 ps
CPU time 5.34 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:07 PM PDT 24
Peak memory 210340 kb
Host smart-b6a5f03e-ac61-4584-b4f9-e620293e3c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920903449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3920903449
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3227200289
Short name T593
Test name
Test status
Simulation time 42568698 ps
CPU time 0.73 seconds
Started Jun 26 05:55:55 PM PDT 24
Finished Jun 26 05:56:08 PM PDT 24
Peak memory 206016 kb
Host smart-f29c818e-d1a2-4cb2-a304-929b9a72fa13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227200289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3227200289
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3118687679
Short name T418
Test name
Test status
Simulation time 548102630 ps
CPU time 7.95 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:09 PM PDT 24
Peak memory 222416 kb
Host smart-4a8e2c69-9e84-4a9d-8763-86e926719dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3118687679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3118687679
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.700843921
Short name T691
Test name
Test status
Simulation time 2661137832 ps
CPU time 12.39 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:13 PM PDT 24
Peak memory 209540 kb
Host smart-f508220f-a4a5-4564-881f-b19b1a4a0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700843921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.700843921
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.277628654
Short name T705
Test name
Test status
Simulation time 80706686 ps
CPU time 4.05 seconds
Started Jun 26 05:55:54 PM PDT 24
Finished Jun 26 05:56:10 PM PDT 24
Peak memory 214172 kb
Host smart-c4f24310-3838-4989-b5c1-fb33ae908841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277628654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.277628654
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.633264385
Short name T293
Test name
Test status
Simulation time 55411918 ps
CPU time 2.78 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:06 PM PDT 24
Peak memory 209808 kb
Host smart-392936f7-6ee2-45a1-b3f7-71fc4c36db84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633264385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.633264385
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1079328500
Short name T244
Test name
Test status
Simulation time 81641239 ps
CPU time 3.07 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:04 PM PDT 24
Peak memory 210356 kb
Host smart-0d561d4e-d595-4670-9a82-940e0bc3dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079328500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1079328500
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1652360283
Short name T312
Test name
Test status
Simulation time 83682018 ps
CPU time 3.39 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:06 PM PDT 24
Peak memory 208464 kb
Host smart-2842bdad-8bb3-42c6-bec5-6d851b7af736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652360283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1652360283
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1481193695
Short name T580
Test name
Test status
Simulation time 198870546 ps
CPU time 3.5 seconds
Started Jun 26 05:55:55 PM PDT 24
Finished Jun 26 05:56:10 PM PDT 24
Peak memory 208844 kb
Host smart-6c851f28-f137-4f9e-b2ee-ed2ffcc7c18b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481193695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1481193695
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3280919146
Short name T668
Test name
Test status
Simulation time 970493151 ps
CPU time 16.05 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:18 PM PDT 24
Peak memory 208804 kb
Host smart-af6d5be0-4ce7-4ec1-ba5f-cc9e741410a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280919146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3280919146
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3745939701
Short name T787
Test name
Test status
Simulation time 136540994 ps
CPU time 4.79 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:08 PM PDT 24
Peak memory 208972 kb
Host smart-ad77f9fc-9479-4675-8a8c-1b6fe1c49fa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745939701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3745939701
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.626471641
Short name T805
Test name
Test status
Simulation time 1025653405 ps
CPU time 24.86 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:26 PM PDT 24
Peak memory 209648 kb
Host smart-fc225e72-b56c-476d-99dd-01b6f39b7684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626471641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.626471641
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3749753303
Short name T91
Test name
Test status
Simulation time 1549427685 ps
CPU time 31.42 seconds
Started Jun 26 05:55:48 PM PDT 24
Finished Jun 26 05:56:30 PM PDT 24
Peak memory 208816 kb
Host smart-9c9c1dfc-c2c6-49be-92ad-5ef817f8f1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749753303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3749753303
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3290787172
Short name T761
Test name
Test status
Simulation time 739216105 ps
CPU time 4.04 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:08 PM PDT 24
Peak memory 208496 kb
Host smart-005fcd32-c06e-4aa0-b62f-96726c91200b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290787172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3290787172
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1927371075
Short name T202
Test name
Test status
Simulation time 452859780 ps
CPU time 10.12 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:11 PM PDT 24
Peak memory 222600 kb
Host smart-de801612-0c58-4021-be26-0cede05ec2fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927371075 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1927371075
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3214656526
Short name T552
Test name
Test status
Simulation time 50778387 ps
CPU time 2.82 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:06 PM PDT 24
Peak memory 209944 kb
Host smart-fab8cbc7-e3ed-43a5-bfeb-764a47fa94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214656526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3214656526
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2380178244
Short name T656
Test name
Test status
Simulation time 1160821111 ps
CPU time 3.19 seconds
Started Jun 26 05:55:52 PM PDT 24
Finished Jun 26 05:56:07 PM PDT 24
Peak memory 209860 kb
Host smart-58982e98-dfd1-4eb0-a4f9-eacc62b4255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380178244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2380178244
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.767195314
Short name T872
Test name
Test status
Simulation time 39480757 ps
CPU time 0.9 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:15 PM PDT 24
Peak memory 206028 kb
Host smart-f2f5d688-e421-40b6-be04-18063a456b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767195314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.767195314
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2409886246
Short name T225
Test name
Test status
Simulation time 108161795 ps
CPU time 3.53 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:16 PM PDT 24
Peak memory 214604 kb
Host smart-626a972c-b910-4f01-9fa8-c5403e522a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409886246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2409886246
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3496122437
Short name T79
Test name
Test status
Simulation time 368721809 ps
CPU time 3.56 seconds
Started Jun 26 05:55:52 PM PDT 24
Finished Jun 26 05:56:08 PM PDT 24
Peak memory 209532 kb
Host smart-082659a6-ca10-47e5-a603-17f72db25e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496122437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3496122437
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3054829263
Short name T289
Test name
Test status
Simulation time 133202494 ps
CPU time 4.59 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:17 PM PDT 24
Peak memory 215524 kb
Host smart-5aa48569-8628-4ca8-bbaf-cce25a8d86f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054829263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3054829263
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3341381987
Short name T112
Test name
Test status
Simulation time 89015648 ps
CPU time 1.79 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:14 PM PDT 24
Peak memory 214352 kb
Host smart-18476bbb-119f-4a4f-b17a-be5e80055fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341381987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3341381987
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.505802630
Short name T466
Test name
Test status
Simulation time 170968573 ps
CPU time 3.16 seconds
Started Jun 26 05:55:48 PM PDT 24
Finished Jun 26 05:56:01 PM PDT 24
Peak memory 210148 kb
Host smart-2368e4c5-c4b9-4559-8021-f330b6cd43d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505802630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.505802630
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2385069948
Short name T726
Test name
Test status
Simulation time 174620377 ps
CPU time 4.15 seconds
Started Jun 26 05:55:55 PM PDT 24
Finished Jun 26 05:56:11 PM PDT 24
Peak memory 209632 kb
Host smart-cbe1623b-1ebf-439f-859c-84d1a25ba657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385069948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2385069948
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1262654098
Short name T454
Test name
Test status
Simulation time 280739884 ps
CPU time 1.89 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:05 PM PDT 24
Peak memory 206816 kb
Host smart-4f3e708d-ae20-4873-9c14-f61c72d349ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262654098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1262654098
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1627068892
Short name T274
Test name
Test status
Simulation time 38997298 ps
CPU time 2.6 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:05 PM PDT 24
Peak memory 208656 kb
Host smart-530a31db-4dbd-4dd4-aec8-76e86e00e9e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627068892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1627068892
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.54560050
Short name T199
Test name
Test status
Simulation time 2208708769 ps
CPU time 22.98 seconds
Started Jun 26 05:55:49 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 208568 kb
Host smart-044a6687-cc40-4029-b841-078883180959
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54560050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.54560050
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2000785965
Short name T823
Test name
Test status
Simulation time 57353619 ps
CPU time 2.23 seconds
Started Jun 26 05:55:51 PM PDT 24
Finished Jun 26 05:56:06 PM PDT 24
Peak memory 206872 kb
Host smart-0212fa72-96ed-4daf-83c4-595302fad515
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000785965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2000785965
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4165367092
Short name T753
Test name
Test status
Simulation time 356529376 ps
CPU time 4.05 seconds
Started Jun 26 05:56:01 PM PDT 24
Finished Jun 26 05:56:19 PM PDT 24
Peak memory 214264 kb
Host smart-175a850d-f26e-4013-a205-7de968606f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165367092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4165367092
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3931189227
Short name T441
Test name
Test status
Simulation time 372944198 ps
CPU time 3.14 seconds
Started Jun 26 05:55:50 PM PDT 24
Finished Jun 26 05:56:04 PM PDT 24
Peak memory 208356 kb
Host smart-9f4ecf8b-50bf-4fd6-a03d-52511b91a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931189227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3931189227
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1189069329
Short name T773
Test name
Test status
Simulation time 3345497773 ps
CPU time 72.7 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:57:29 PM PDT 24
Peak memory 217692 kb
Host smart-e2e7a5f3-da4b-4800-9509-f8bad1012393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189069329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1189069329
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.407305179
Short name T851
Test name
Test status
Simulation time 1777099492 ps
CPU time 14.84 seconds
Started Jun 26 05:56:03 PM PDT 24
Finished Jun 26 05:56:31 PM PDT 24
Peak memory 222772 kb
Host smart-88508ddf-f7b0-4afa-ab2c-2bf45ee91682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407305179 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.407305179
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3495918344
Short name T847
Test name
Test status
Simulation time 160393530 ps
CPU time 4.19 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:18 PM PDT 24
Peak memory 207628 kb
Host smart-bc18b59b-772e-4b9d-aed8-d16eb5802682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495918344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3495918344
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.324184054
Short name T758
Test name
Test status
Simulation time 46374336 ps
CPU time 2.1 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:16 PM PDT 24
Peak memory 210012 kb
Host smart-9fce70cf-73a9-423c-949e-61e86605590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324184054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.324184054
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3142479079
Short name T534
Test name
Test status
Simulation time 37436309 ps
CPU time 0.76 seconds
Started Jun 26 05:56:01 PM PDT 24
Finished Jun 26 05:56:16 PM PDT 24
Peak memory 206068 kb
Host smart-a7ed14c1-911a-4056-b050-d139f33ef4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142479079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3142479079
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.174471071
Short name T423
Test name
Test status
Simulation time 52818314 ps
CPU time 3.69 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:17 PM PDT 24
Peak memory 215860 kb
Host smart-137f254e-457d-4ca3-a508-157c96223c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174471071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.174471071
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2985143127
Short name T226
Test name
Test status
Simulation time 231317544 ps
CPU time 4.42 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:17 PM PDT 24
Peak memory 214608 kb
Host smart-eadadb9c-3698-4aa4-a333-1fac0075154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985143127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2985143127
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.927946979
Short name T919
Test name
Test status
Simulation time 2077496766 ps
CPU time 18.72 seconds
Started Jun 26 05:56:01 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 209232 kb
Host smart-e4327967-954c-4f3c-b793-bdf966fca087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927946979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.927946979
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3081083466
Short name T95
Test name
Test status
Simulation time 51581031 ps
CPU time 1.98 seconds
Started Jun 26 05:55:58 PM PDT 24
Finished Jun 26 05:56:13 PM PDT 24
Peak memory 214508 kb
Host smart-e707cbd6-ce48-4a98-bd32-2f0f96aeb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081083466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3081083466
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.260115393
Short name T632
Test name
Test status
Simulation time 283416854 ps
CPU time 3.34 seconds
Started Jun 26 05:55:58 PM PDT 24
Finished Jun 26 05:56:15 PM PDT 24
Peak memory 209016 kb
Host smart-3db2917c-9c7d-44a8-ba39-4c228ec51499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260115393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.260115393
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2032661852
Short name T522
Test name
Test status
Simulation time 5042028396 ps
CPU time 51.02 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:57:05 PM PDT 24
Peak memory 209572 kb
Host smart-96038ba1-3163-4e0d-bf68-b033b0728cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032661852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2032661852
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2534677985
Short name T589
Test name
Test status
Simulation time 341198925 ps
CPU time 4.47 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:17 PM PDT 24
Peak memory 208452 kb
Host smart-fd1e028c-ca73-47d7-9adc-b8428255f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534677985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2534677985
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3130666408
Short name T855
Test name
Test status
Simulation time 327617831 ps
CPU time 10.86 seconds
Started Jun 26 05:56:01 PM PDT 24
Finished Jun 26 05:56:26 PM PDT 24
Peak memory 208004 kb
Host smart-89260876-2aaf-4ae3-a752-ce0c59fdb2f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130666408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3130666408
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4208923591
Short name T844
Test name
Test status
Simulation time 37461111 ps
CPU time 2.34 seconds
Started Jun 26 05:55:58 PM PDT 24
Finished Jun 26 05:56:14 PM PDT 24
Peak memory 208468 kb
Host smart-498c8d93-a55f-4c87-b64b-b431658fd70f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208923591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4208923591
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3835966290
Short name T769
Test name
Test status
Simulation time 53369673 ps
CPU time 2.25 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:15 PM PDT 24
Peak memory 208864 kb
Host smart-22467834-794d-4ff8-a998-05929234b879
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835966290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3835966290
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3419523590
Short name T241
Test name
Test status
Simulation time 200415350 ps
CPU time 2.87 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:16 PM PDT 24
Peak memory 209260 kb
Host smart-faaa508f-cc05-4ba4-8e46-ad05d0447311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419523590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3419523590
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3350929647
Short name T468
Test name
Test status
Simulation time 519229479 ps
CPU time 9.44 seconds
Started Jun 26 05:55:58 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 208360 kb
Host smart-a41fc6d8-aeaf-4d9b-839c-05d9abce9a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350929647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3350929647
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.342973854
Short name T113
Test name
Test status
Simulation time 726866687 ps
CPU time 8.2 seconds
Started Jun 26 05:56:02 PM PDT 24
Finished Jun 26 05:56:24 PM PDT 24
Peak memory 222644 kb
Host smart-871afceb-775f-4f01-b83b-b487911ddf06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342973854 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.342973854
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3061681779
Short name T340
Test name
Test status
Simulation time 501871030 ps
CPU time 4.27 seconds
Started Jun 26 05:55:57 PM PDT 24
Finished Jun 26 05:56:15 PM PDT 24
Peak memory 210584 kb
Host smart-fdc1de74-dbfa-4ab1-a969-628e18091276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061681779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3061681779
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1949228176
Short name T169
Test name
Test status
Simulation time 29475496 ps
CPU time 1.83 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:16 PM PDT 24
Peak memory 208836 kb
Host smart-4838e1b3-8a5f-4f5d-99f3-b3cda33b980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949228176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1949228176
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2958693126
Short name T449
Test name
Test status
Simulation time 39016271 ps
CPU time 0.93 seconds
Started Jun 26 05:56:07 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 206064 kb
Host smart-c0345c28-dae5-417d-af18-f05b2a074f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958693126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2958693126
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1155165807
Short name T281
Test name
Test status
Simulation time 535276336 ps
CPU time 8.36 seconds
Started Jun 26 05:56:02 PM PDT 24
Finished Jun 26 05:56:24 PM PDT 24
Peak memory 214356 kb
Host smart-a4eef161-f61b-42c9-bcc1-3ee584ed2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155165807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1155165807
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1113826771
Short name T375
Test name
Test status
Simulation time 434650019 ps
CPU time 5.88 seconds
Started Jun 26 05:56:01 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 209416 kb
Host smart-8efc7f9a-735c-4155-994a-2204b439fcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113826771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1113826771
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2620359263
Short name T781
Test name
Test status
Simulation time 27919631 ps
CPU time 2.18 seconds
Started Jun 26 05:56:03 PM PDT 24
Finished Jun 26 05:56:18 PM PDT 24
Peak memory 222092 kb
Host smart-e6796843-0f32-4be8-b08c-6d2005a630b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620359263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2620359263
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.4042192127
Short name T361
Test name
Test status
Simulation time 536572243 ps
CPU time 4.61 seconds
Started Jun 26 05:56:03 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 222452 kb
Host smart-32dd40da-2937-47c4-aae3-a99449c21f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042192127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4042192127
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2810888356
Short name T150
Test name
Test status
Simulation time 245791084 ps
CPU time 2.55 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:15 PM PDT 24
Peak memory 208676 kb
Host smart-a63f5192-87a4-4253-a55e-0a454268b1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810888356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2810888356
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1184675673
Short name T208
Test name
Test status
Simulation time 736435321 ps
CPU time 6.78 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 208520 kb
Host smart-be95d37e-b94f-48b2-8433-6bac38817e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184675673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1184675673
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3041985794
Short name T573
Test name
Test status
Simulation time 1333203195 ps
CPU time 25.29 seconds
Started Jun 26 05:56:00 PM PDT 24
Finished Jun 26 05:56:39 PM PDT 24
Peak memory 207864 kb
Host smart-f123d8c6-9c43-4577-83fc-bcf36dd4f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041985794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3041985794
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.205660500
Short name T810
Test name
Test status
Simulation time 674476577 ps
CPU time 22.18 seconds
Started Jun 26 05:55:58 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 209160 kb
Host smart-5be86976-2380-4382-baec-63709cdc6e4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205660500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.205660500
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3444863467
Short name T612
Test name
Test status
Simulation time 86962436 ps
CPU time 3.83 seconds
Started Jun 26 05:56:02 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 208692 kb
Host smart-90cb2476-c60b-407c-99d7-52ea1618a2a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444863467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3444863467
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2408530332
Short name T585
Test name
Test status
Simulation time 192651341 ps
CPU time 7.12 seconds
Started Jun 26 05:56:01 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 207924 kb
Host smart-93b03aac-f6cf-4762-bbaf-14dbebc039a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408530332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2408530332
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1201051971
Short name T372
Test name
Test status
Simulation time 709439963 ps
CPU time 19.96 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 214292 kb
Host smart-fa0bfa8c-8bd7-404f-81e2-b52e49282874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201051971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1201051971
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4256117574
Short name T790
Test name
Test status
Simulation time 4230039798 ps
CPU time 20.87 seconds
Started Jun 26 05:56:03 PM PDT 24
Finished Jun 26 05:56:37 PM PDT 24
Peak memory 208196 kb
Host smart-f7dec07f-1d68-49ff-9b00-eff261c9799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256117574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4256117574
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1419232455
Short name T191
Test name
Test status
Simulation time 288980347 ps
CPU time 10.74 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:30 PM PDT 24
Peak memory 217496 kb
Host smart-29c27a15-b648-4081-9f83-257c6fea7a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419232455 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1419232455
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4157198953
Short name T577
Test name
Test status
Simulation time 115336882 ps
CPU time 5.28 seconds
Started Jun 26 05:55:59 PM PDT 24
Finished Jun 26 05:56:18 PM PDT 24
Peak memory 208848 kb
Host smart-8461e5fd-0870-4a2c-8c26-c6dadc31741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157198953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4157198953
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.860826659
Short name T692
Test name
Test status
Simulation time 39358110 ps
CPU time 0.78 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:18 PM PDT 24
Peak memory 206032 kb
Host smart-0bc0d8e3-ebe2-456e-8d47-15a9ec8455b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860826659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.860826659
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.864367839
Short name T829
Test name
Test status
Simulation time 127935031 ps
CPU time 2.56 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 214344 kb
Host smart-3f8aab9b-1ec7-4f79-a3be-2cd3c4c5f792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864367839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.864367839
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2588390114
Short name T530
Test name
Test status
Simulation time 342785592 ps
CPU time 2.15 seconds
Started Jun 26 05:56:08 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 214320 kb
Host smart-3e5455da-4df6-4b41-b2f6-996f47734236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588390114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2588390114
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2548750665
Short name T306
Test name
Test status
Simulation time 24768773 ps
CPU time 1.59 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 208988 kb
Host smart-2f08372d-dd18-444a-b6c3-796b05516582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548750665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2548750665
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3417188212
Short name T310
Test name
Test status
Simulation time 6028332416 ps
CPU time 34.56 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:53 PM PDT 24
Peak memory 219148 kb
Host smart-9b1d902a-b023-4d26-8823-905228eeb239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417188212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3417188212
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4254132839
Short name T627
Test name
Test status
Simulation time 257434346 ps
CPU time 2.76 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 214284 kb
Host smart-63be7fe2-191f-434e-9e9d-14b1fe593525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254132839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4254132839
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3094702017
Short name T649
Test name
Test status
Simulation time 272871218 ps
CPU time 3.28 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 208704 kb
Host smart-3ccf2f84-792b-450c-a046-7fe3bac4fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094702017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3094702017
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.101300373
Short name T238
Test name
Test status
Simulation time 677304683 ps
CPU time 4.73 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 207976 kb
Host smart-db9ba2bb-e5f3-49fb-8156-453446786fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101300373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.101300373
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.715489968
Short name T682
Test name
Test status
Simulation time 269946236 ps
CPU time 7.86 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:27 PM PDT 24
Peak memory 208016 kb
Host smart-24e59132-6c23-4360-b6a0-3270d6ed5add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715489968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.715489968
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.302547691
Short name T314
Test name
Test status
Simulation time 218430945 ps
CPU time 3.02 seconds
Started Jun 26 05:56:10 PM PDT 24
Finished Jun 26 05:56:25 PM PDT 24
Peak memory 209152 kb
Host smart-0e44cbf7-1ce7-41b5-9301-a510a9c35a5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302547691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.302547691
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2084119042
Short name T512
Test name
Test status
Simulation time 58869055 ps
CPU time 3.14 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 208252 kb
Host smart-fa3ec641-9303-4c5b-8fe5-6d46911a7d96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084119042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2084119042
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3186832444
Short name T403
Test name
Test status
Simulation time 164596062 ps
CPU time 5.19 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 208228 kb
Host smart-16237cb1-014f-451b-a58e-f3c847ccfe49
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186832444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3186832444
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2320084884
Short name T873
Test name
Test status
Simulation time 578231179 ps
CPU time 3.16 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 209812 kb
Host smart-49c1cd58-622f-48b5-9885-d99adb6888af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320084884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2320084884
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3120534101
Short name T791
Test name
Test status
Simulation time 63390085 ps
CPU time 2.8 seconds
Started Jun 26 05:56:03 PM PDT 24
Finished Jun 26 05:56:19 PM PDT 24
Peak memory 206876 kb
Host smart-5734ce70-431c-490e-9fab-c1776641184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120534101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3120534101
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2620277492
Short name T249
Test name
Test status
Simulation time 22742046540 ps
CPU time 207.35 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:59:47 PM PDT 24
Peak memory 222604 kb
Host smart-05fc96ab-df5a-43d5-b390-6e463f1a70af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620277492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2620277492
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3794391346
Short name T187
Test name
Test status
Simulation time 219172333 ps
CPU time 7.64 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:26 PM PDT 24
Peak memory 222580 kb
Host smart-a4fef57b-9ed4-4546-9d74-b06a4dd264f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794391346 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3794391346
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4221597866
Short name T628
Test name
Test status
Simulation time 467429651 ps
CPU time 5.67 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:25 PM PDT 24
Peak memory 219528 kb
Host smart-0b549c5e-80f5-4193-b351-6f014ff66377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221597866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4221597866
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2489953362
Short name T609
Test name
Test status
Simulation time 115833654 ps
CPU time 2.7 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 210360 kb
Host smart-7b6abf3c-a515-4a9f-b805-91a20494cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489953362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2489953362
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3742787863
Short name T687
Test name
Test status
Simulation time 14033720 ps
CPU time 0.81 seconds
Started Jun 26 05:56:17 PM PDT 24
Finished Jun 26 05:56:31 PM PDT 24
Peak memory 206076 kb
Host smart-809d17a4-5795-408a-8c46-dd9cd31b2d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742787863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3742787863
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.633062706
Short name T76
Test name
Test status
Simulation time 199085005 ps
CPU time 2.79 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:19 PM PDT 24
Peak memory 208004 kb
Host smart-ffef2e01-2351-4e64-8eb3-98146dc97a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633062706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.633062706
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4274458271
Short name T497
Test name
Test status
Simulation time 1398416232 ps
CPU time 10.67 seconds
Started Jun 26 05:56:04 PM PDT 24
Finished Jun 26 05:56:27 PM PDT 24
Peak memory 208472 kb
Host smart-ce746c6c-4692-4241-89d6-019b98d68b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274458271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4274458271
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2347095528
Short name T94
Test name
Test status
Simulation time 39645629 ps
CPU time 2.22 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 215248 kb
Host smart-8c98babb-380a-4ffc-b716-2c320fe7b101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347095528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2347095528
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2761053784
Short name T333
Test name
Test status
Simulation time 43358479 ps
CPU time 2.11 seconds
Started Jun 26 05:56:08 PM PDT 24
Finished Jun 26 05:56:24 PM PDT 24
Peak memory 214260 kb
Host smart-7458740b-7b26-4fc7-8fd5-820b0ec93ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761053784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2761053784
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2093959445
Short name T410
Test name
Test status
Simulation time 313794997 ps
CPU time 3.89 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 209588 kb
Host smart-3d7f2158-f7f2-4175-a196-033dafa85245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093959445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2093959445
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3586249186
Short name T246
Test name
Test status
Simulation time 125946350 ps
CPU time 5.08 seconds
Started Jun 26 05:56:08 PM PDT 24
Finished Jun 26 05:56:26 PM PDT 24
Peak memory 214400 kb
Host smart-c90faa85-af00-4172-b85a-813a4a3786fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586249186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3586249186
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1395602849
Short name T479
Test name
Test status
Simulation time 31911624 ps
CPU time 2.19 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:21 PM PDT 24
Peak memory 208860 kb
Host smart-2aad095e-be84-4e71-ac41-83776eb3bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395602849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1395602849
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1688735972
Short name T320
Test name
Test status
Simulation time 66281301 ps
CPU time 1.89 seconds
Started Jun 26 05:56:07 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 206896 kb
Host smart-446aa057-44b5-4251-8ad9-7d8ad91b7c0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688735972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1688735972
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.375834678
Short name T878
Test name
Test status
Simulation time 298806821 ps
CPU time 2.86 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:22 PM PDT 24
Peak memory 206808 kb
Host smart-423c0655-d876-44df-91f0-d0bc9c337abc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375834678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.375834678
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3211378254
Short name T637
Test name
Test status
Simulation time 250422343 ps
CPU time 3.23 seconds
Started Jun 26 05:56:06 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 208820 kb
Host smart-67eec4e8-2369-4b45-b067-7a32d5832a57
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211378254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3211378254
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3479781946
Short name T507
Test name
Test status
Simulation time 95752188 ps
CPU time 2.92 seconds
Started Jun 26 05:56:14 PM PDT 24
Finished Jun 26 05:56:31 PM PDT 24
Peak memory 215852 kb
Host smart-f7712a7b-44a9-4a42-9dbe-7ceff64d222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479781946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3479781946
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3386111350
Short name T857
Test name
Test status
Simulation time 71507255 ps
CPU time 2.32 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:20 PM PDT 24
Peak memory 208656 kb
Host smart-2154d13c-f91f-4d8c-b24d-a49386283e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386111350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3386111350
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3375302387
Short name T216
Test name
Test status
Simulation time 506682197 ps
CPU time 17.18 seconds
Started Jun 26 05:56:18 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 216396 kb
Host smart-e8330f61-8ee6-42cb-9db6-dc91536f810a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375302387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3375302387
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2611363089
Short name T698
Test name
Test status
Simulation time 773956072 ps
CPU time 19.74 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 219884 kb
Host smart-bd6c08f4-3955-4269-9e5a-e9511df4a0ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611363089 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2611363089
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2007663096
Short name T373
Test name
Test status
Simulation time 142802392 ps
CPU time 4.65 seconds
Started Jun 26 05:56:05 PM PDT 24
Finished Jun 26 05:56:23 PM PDT 24
Peak memory 209196 kb
Host smart-5ae51924-c03b-4b77-89e6-ec0e510b4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007663096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2007663096
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2254026291
Short name T626
Test name
Test status
Simulation time 104583461 ps
CPU time 3.85 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 210460 kb
Host smart-d300ec60-36db-48ee-8654-5f284aab6fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254026291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2254026291
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2571577201
Short name T806
Test name
Test status
Simulation time 13496942 ps
CPU time 0.76 seconds
Started Jun 26 05:56:14 PM PDT 24
Finished Jun 26 05:56:28 PM PDT 24
Peak memory 206076 kb
Host smart-1beffbb8-f256-4f7c-ab02-ee8815dba51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571577201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2571577201
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4203801897
Short name T280
Test name
Test status
Simulation time 176270134 ps
CPU time 4.33 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 05:56:30 PM PDT 24
Peak memory 214488 kb
Host smart-82730524-5efb-4ecc-bfd5-0a97fe6919fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203801897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4203801897
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.347802738
Short name T352
Test name
Test status
Simulation time 188323122 ps
CPU time 5.72 seconds
Started Jun 26 05:56:14 PM PDT 24
Finished Jun 26 05:56:33 PM PDT 24
Peak memory 222504 kb
Host smart-6fbcf926-bd8c-4f0f-80f9-8f3ed045a8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347802738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.347802738
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.552924515
Short name T334
Test name
Test status
Simulation time 95294469 ps
CPU time 3.13 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 214348 kb
Host smart-279a4f06-473f-42b7-a74d-b7168db41e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552924515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.552924515
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2388956284
Short name T775
Test name
Test status
Simulation time 2277285120 ps
CPU time 19.29 seconds
Started Jun 26 05:56:19 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 214348 kb
Host smart-396bff51-c44c-4925-949c-9fc26e47c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388956284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2388956284
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.241806347
Short name T631
Test name
Test status
Simulation time 157851259 ps
CPU time 4.77 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:33 PM PDT 24
Peak memory 219724 kb
Host smart-bbc09480-f498-4261-a0d9-9d44744dc81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241806347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.241806347
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3037840105
Short name T284
Test name
Test status
Simulation time 4365825126 ps
CPU time 7.63 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 209572 kb
Host smart-bf73091a-b89c-475f-a382-e96a9a11fb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037840105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3037840105
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2864962109
Short name T351
Test name
Test status
Simulation time 1362006178 ps
CPU time 26.73 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 208012 kb
Host smart-d298480a-f29f-4744-836c-9d598fe76feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864962109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2864962109
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4234000564
Short name T523
Test name
Test status
Simulation time 183190394 ps
CPU time 6.61 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:35 PM PDT 24
Peak memory 208728 kb
Host smart-2e32efd6-a4d2-4851-8de6-f37bb89b38f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234000564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4234000564
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3532901124
Short name T326
Test name
Test status
Simulation time 2666402140 ps
CPU time 33.64 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 208676 kb
Host smart-393b1bf3-cca4-4200-b320-397dbc0af404
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532901124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3532901124
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4178695207
Short name T712
Test name
Test status
Simulation time 20358393 ps
CPU time 1.79 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 05:56:28 PM PDT 24
Peak memory 206976 kb
Host smart-b9c7df0c-4a21-4661-b1b4-8fb662084009
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178695207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4178695207
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3228936783
Short name T825
Test name
Test status
Simulation time 304676014 ps
CPU time 2.44 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 05:56:28 PM PDT 24
Peak memory 208720 kb
Host smart-3366927b-8a7f-4e8d-ba5a-311a7733fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228936783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3228936783
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.588748482
Short name T6
Test name
Test status
Simulation time 27133848 ps
CPU time 1.83 seconds
Started Jun 26 05:56:17 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 208572 kb
Host smart-b8faa227-855c-4627-a0ae-8c48dfc466f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588748482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.588748482
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1798644986
Short name T130
Test name
Test status
Simulation time 251187294 ps
CPU time 10.61 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:39 PM PDT 24
Peak memory 222600 kb
Host smart-f7c2c8cd-95a5-4a07-8919-560991939cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798644986 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1798644986
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.868512935
Short name T892
Test name
Test status
Simulation time 508055498 ps
CPU time 7.23 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:36 PM PDT 24
Peak memory 214428 kb
Host smart-3270dae9-db4e-44a1-9834-0bedb551ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868512935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.868512935
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1613067104
Short name T822
Test name
Test status
Simulation time 1421766563 ps
CPU time 13.33 seconds
Started Jun 26 05:56:18 PM PDT 24
Finished Jun 26 05:56:45 PM PDT 24
Peak memory 211140 kb
Host smart-be26b185-3b09-4d0d-bd7a-5d5eb16db1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613067104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1613067104
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3602540883
Short name T498
Test name
Test status
Simulation time 8988896 ps
CPU time 0.8 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:29 PM PDT 24
Peak memory 206040 kb
Host smart-6acbca84-c5b6-46ca-8b84-59457e2f587a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602540883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3602540883
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4195552906
Short name T429
Test name
Test status
Simulation time 53929169 ps
CPU time 3.88 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 214364 kb
Host smart-e1d56bb7-ff0e-4b43-94b8-70fc05e126d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195552906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4195552906
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1283944529
Short name T41
Test name
Test status
Simulation time 136731254 ps
CPU time 2.55 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 219812 kb
Host smart-2b63a736-650f-47c4-aafc-276759dce839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283944529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1283944529
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3432067449
Short name T664
Test name
Test status
Simulation time 117397726 ps
CPU time 2.73 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:30 PM PDT 24
Peak memory 208224 kb
Host smart-e5461195-5069-4671-85ef-6a7613a61695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432067449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3432067449
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.699967708
Short name T243
Test name
Test status
Simulation time 97226647 ps
CPU time 1.98 seconds
Started Jun 26 05:56:18 PM PDT 24
Finished Jun 26 05:56:33 PM PDT 24
Peak memory 214236 kb
Host smart-4076f3af-29a8-4f82-aa5e-735c58738ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699967708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.699967708
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.580229793
Short name T871
Test name
Test status
Simulation time 176452090 ps
CPU time 2.96 seconds
Started Jun 26 05:56:19 PM PDT 24
Finished Jun 26 05:56:36 PM PDT 24
Peak memory 214272 kb
Host smart-48c3c12c-bdc7-44a1-88e0-598f982f51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580229793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.580229793
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_random.406698807
Short name T898
Test name
Test status
Simulation time 412811863 ps
CPU time 5.82 seconds
Started Jun 26 05:56:14 PM PDT 24
Finished Jun 26 05:56:33 PM PDT 24
Peak memory 214412 kb
Host smart-52837291-73a9-40aa-83b3-b557226a55ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406698807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.406698807
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3889600161
Short name T551
Test name
Test status
Simulation time 285259364 ps
CPU time 4.27 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:33 PM PDT 24
Peak memory 208408 kb
Host smart-11e17e2d-3be1-494e-a985-706411848941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889600161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3889600161
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3831806462
Short name T908
Test name
Test status
Simulation time 41487088 ps
CPU time 2.39 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 206912 kb
Host smart-3c29fc0d-8293-4b0d-8e44-d162e8041fe7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831806462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3831806462
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1483659013
Short name T253
Test name
Test status
Simulation time 414299266 ps
CPU time 4.96 seconds
Started Jun 26 05:56:14 PM PDT 24
Finished Jun 26 05:56:33 PM PDT 24
Peak memory 207124 kb
Host smart-5a52559c-a7d3-4ae6-8a18-5017ae9fd845
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483659013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1483659013
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2292438100
Short name T315
Test name
Test status
Simulation time 90937281 ps
CPU time 4.01 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 208872 kb
Host smart-c8990d76-4ef9-41a5-ae9d-e317bc21c286
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292438100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2292438100
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2695812266
Short name T617
Test name
Test status
Simulation time 201203173 ps
CPU time 1.76 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:30 PM PDT 24
Peak memory 209184 kb
Host smart-79ac475f-5106-4c19-a274-1adc749d7a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695812266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2695812266
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.454963234
Short name T760
Test name
Test status
Simulation time 145735618 ps
CPU time 4.56 seconds
Started Jun 26 05:56:13 PM PDT 24
Finished Jun 26 05:56:31 PM PDT 24
Peak memory 208576 kb
Host smart-124bedc8-5ec7-48df-a9d9-a2ea284dafa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454963234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.454963234
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1071783663
Short name T901
Test name
Test status
Simulation time 1847239135 ps
CPU time 17.44 seconds
Started Jun 26 05:56:18 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 220088 kb
Host smart-f6b443ee-1713-40e8-9657-b284b807e45e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071783663 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1071783663
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1345852225
Short name T210
Test name
Test status
Simulation time 435941117 ps
CPU time 6.26 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:35 PM PDT 24
Peak memory 208532 kb
Host smart-997fcaaf-cd20-4924-8b0b-79b17c56ca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345852225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1345852225
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4055263013
Short name T193
Test name
Test status
Simulation time 46864051 ps
CPU time 0.82 seconds
Started Jun 26 05:54:06 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 206008 kb
Host smart-a166e4f0-7241-431c-a196-7524a2b32fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055263013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4055263013
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.157207146
Short name T33
Test name
Test status
Simulation time 455196156 ps
CPU time 3.38 seconds
Started Jun 26 05:54:03 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 220368 kb
Host smart-ed4347a5-f72e-4c86-af62-a1f5ca2258a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157207146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.157207146
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2989102368
Short name T815
Test name
Test status
Simulation time 98741095 ps
CPU time 3.34 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 214512 kb
Host smart-22814a50-04c7-41c8-9f40-636c58e12c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989102368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2989102368
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2242583107
Short name T286
Test name
Test status
Simulation time 41361587 ps
CPU time 1.88 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:05 PM PDT 24
Peak memory 214320 kb
Host smart-94c16c7d-32be-4418-a123-9271d60d53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242583107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2242583107
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.222395033
Short name T639
Test name
Test status
Simulation time 47193479 ps
CPU time 2.48 seconds
Started Jun 26 05:54:02 PM PDT 24
Finished Jun 26 05:54:06 PM PDT 24
Peak memory 222396 kb
Host smart-3faaccc7-d0fe-4a59-9917-e3a91441b688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222395033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.222395033
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2157490545
Short name T646
Test name
Test status
Simulation time 732883367 ps
CPU time 7.68 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:11 PM PDT 24
Peak memory 210092 kb
Host smart-8191d516-b40c-40aa-96a2-7a3e6698f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157490545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2157490545
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.538085054
Short name T597
Test name
Test status
Simulation time 2944761287 ps
CPU time 4.42 seconds
Started Jun 26 05:54:02 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 208832 kb
Host smart-315bf35c-6de4-43cc-be47-96c9dc6e12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538085054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.538085054
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.815923779
Short name T491
Test name
Test status
Simulation time 133385078 ps
CPU time 3.33 seconds
Started Jun 26 05:54:02 PM PDT 24
Finished Jun 26 05:54:08 PM PDT 24
Peak memory 206744 kb
Host smart-c54870ff-ad77-4c01-9c3b-01da51337e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815923779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.815923779
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.737580598
Short name T795
Test name
Test status
Simulation time 67871444 ps
CPU time 3.43 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:07 PM PDT 24
Peak memory 209012 kb
Host smart-105addb7-c81a-4ebe-a54f-8f36f65e98ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737580598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.737580598
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2375199496
Short name T200
Test name
Test status
Simulation time 10970237171 ps
CPU time 24.86 seconds
Started Jun 26 05:54:04 PM PDT 24
Finished Jun 26 05:54:30 PM PDT 24
Peak memory 208588 kb
Host smart-a7d0247e-fe4b-4d05-adc6-d38b54566fe2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375199496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2375199496
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2167745079
Short name T621
Test name
Test status
Simulation time 252668451 ps
CPU time 3.45 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:07 PM PDT 24
Peak memory 208360 kb
Host smart-46946745-6cf8-4049-aa3c-f3be3ee020a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167745079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2167745079
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2527172990
Short name T645
Test name
Test status
Simulation time 65252938 ps
CPU time 1.99 seconds
Started Jun 26 05:54:08 PM PDT 24
Finished Jun 26 05:54:11 PM PDT 24
Peak memory 207988 kb
Host smart-3af774b5-93d7-4f40-91f0-fa7eccbc8c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527172990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2527172990
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2787252452
Short name T402
Test name
Test status
Simulation time 526333907 ps
CPU time 3.26 seconds
Started Jun 26 05:54:00 PM PDT 24
Finished Jun 26 05:54:05 PM PDT 24
Peak memory 207376 kb
Host smart-ba7678f9-e8c9-4856-8278-7bf5a0679d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787252452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2787252452
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1787031433
Short name T107
Test name
Test status
Simulation time 551953690 ps
CPU time 5.53 seconds
Started Jun 26 05:54:08 PM PDT 24
Finished Jun 26 05:54:14 PM PDT 24
Peak memory 216064 kb
Host smart-b0edb3ba-fc57-4e12-bc68-faca475f9347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787031433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1787031433
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1839774344
Short name T132
Test name
Test status
Simulation time 4549337544 ps
CPU time 11.01 seconds
Started Jun 26 05:54:05 PM PDT 24
Finished Jun 26 05:54:17 PM PDT 24
Peak memory 222632 kb
Host smart-e6325eb7-13f9-449a-a85e-0eabfd7c0c81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839774344 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1839774344
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1158955906
Short name T261
Test name
Test status
Simulation time 242263366 ps
CPU time 5.24 seconds
Started Jun 26 05:54:01 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 210068 kb
Host smart-b0706ba0-10e2-4478-b1b0-f243622c7d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158955906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1158955906
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3786075161
Short name T180
Test name
Test status
Simulation time 63439591 ps
CPU time 2.04 seconds
Started Jun 26 05:54:10 PM PDT 24
Finished Jun 26 05:54:13 PM PDT 24
Peak memory 210284 kb
Host smart-9edab072-9fa3-4962-bff3-765377509059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786075161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3786075161
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2804755336
Short name T104
Test name
Test status
Simulation time 31819759 ps
CPU time 0.89 seconds
Started Jun 26 05:56:26 PM PDT 24
Finished Jun 26 05:56:42 PM PDT 24
Peak memory 206184 kb
Host smart-f2a42b95-f4d9-43c9-8d9b-3dc5bc3890b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804755336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2804755336
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1959454585
Short name T427
Test name
Test status
Simulation time 140212592 ps
CPU time 3.29 seconds
Started Jun 26 05:56:16 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 214284 kb
Host smart-2b01abde-466c-448a-bee8-6533ae559922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959454585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1959454585
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3311878784
Short name T231
Test name
Test status
Simulation time 97836909 ps
CPU time 4.07 seconds
Started Jun 26 05:56:20 PM PDT 24
Finished Jun 26 05:56:39 PM PDT 24
Peak memory 208516 kb
Host smart-b1d70ea4-c97e-4000-be6d-6a0d2dccc648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311878784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3311878784
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.856697463
Short name T543
Test name
Test status
Simulation time 45819264 ps
CPU time 2.05 seconds
Started Jun 26 05:56:23 PM PDT 24
Finished Jun 26 05:56:40 PM PDT 24
Peak memory 207892 kb
Host smart-2f9dc124-b906-4750-ba46-b2b1c99cd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856697463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.856697463
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2666845480
Short name T672
Test name
Test status
Simulation time 350245274 ps
CPU time 2.66 seconds
Started Jun 26 05:56:25 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 214368 kb
Host smart-8e09b75c-d537-4801-a17c-d985b6925ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666845480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2666845480
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2627170314
Short name T677
Test name
Test status
Simulation time 149741179 ps
CPU time 5.04 seconds
Started Jun 26 05:56:22 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 222056 kb
Host smart-095abdb1-b76f-408b-bb50-3b875bff12c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627170314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2627170314
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3592412304
Short name T143
Test name
Test status
Simulation time 52797813 ps
CPU time 2.95 seconds
Started Jun 26 05:56:24 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 214568 kb
Host smart-4be1b10b-0abf-41ab-a3f5-9a4204c6374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592412304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3592412304
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.135189450
Short name T902
Test name
Test status
Simulation time 469335658 ps
CPU time 3.88 seconds
Started Jun 26 05:56:18 PM PDT 24
Finished Jun 26 05:56:35 PM PDT 24
Peak memory 207548 kb
Host smart-b2d1f0f2-f3b3-4105-ba41-4a6b7ecda8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135189450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.135189450
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1943481967
Short name T381
Test name
Test status
Simulation time 20734403 ps
CPU time 1.88 seconds
Started Jun 26 05:56:15 PM PDT 24
Finished Jun 26 05:56:30 PM PDT 24
Peak memory 206884 kb
Host smart-e89b4107-cd83-4d14-bdea-322098ecd8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943481967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1943481967
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2547515262
Short name T796
Test name
Test status
Simulation time 133222852 ps
CPU time 4.07 seconds
Started Jun 26 05:56:14 PM PDT 24
Finished Jun 26 05:56:32 PM PDT 24
Peak memory 208556 kb
Host smart-deaa1981-11c0-458e-8cb9-a86c11f86521
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547515262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2547515262
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.198138202
Short name T707
Test name
Test status
Simulation time 217500312 ps
CPU time 6.77 seconds
Started Jun 26 05:56:22 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 208316 kb
Host smart-75556e88-6e24-4678-a4da-45c71c7fdecb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198138202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.198138202
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1843458373
Short name T734
Test name
Test status
Simulation time 118580167 ps
CPU time 2.26 seconds
Started Jun 26 05:56:19 PM PDT 24
Finished Jun 26 05:56:35 PM PDT 24
Peak memory 207448 kb
Host smart-66c26500-bbea-42d9-b72f-a4736979a6ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843458373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1843458373
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1824183250
Short name T425
Test name
Test status
Simulation time 107921217 ps
CPU time 2.75 seconds
Started Jun 26 05:56:20 PM PDT 24
Finished Jun 26 05:56:37 PM PDT 24
Peak memory 207848 kb
Host smart-3017b2d1-195d-40eb-8e28-f72eb5d2ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824183250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1824183250
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1317725201
Short name T896
Test name
Test status
Simulation time 43774346 ps
CPU time 2.09 seconds
Started Jun 26 05:57:17 PM PDT 24
Finished Jun 26 05:57:20 PM PDT 24
Peak memory 206684 kb
Host smart-20b396d3-2b43-4d2d-a48b-8b5e683dfdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317725201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1317725201
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3489778452
Short name T86
Test name
Test status
Simulation time 4701640411 ps
CPU time 34.59 seconds
Started Jun 26 05:56:23 PM PDT 24
Finished Jun 26 05:57:13 PM PDT 24
Peak memory 221672 kb
Host smart-e5c2636f-1b3f-4249-af73-10d047cb643b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489778452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3489778452
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1959325124
Short name T477
Test name
Test status
Simulation time 96433050 ps
CPU time 4.18 seconds
Started Jun 26 05:56:21 PM PDT 24
Finished Jun 26 05:56:40 PM PDT 24
Peak memory 209432 kb
Host smart-5ccf8bf9-d954-46e6-90d2-68180236dc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959325124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1959325124
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3574862741
Short name T618
Test name
Test status
Simulation time 327467097 ps
CPU time 3.66 seconds
Started Jun 26 05:56:25 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 210732 kb
Host smart-f8de9051-a4d2-4677-b594-029edbd19acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574862741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3574862741
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1255857279
Short name T462
Test name
Test status
Simulation time 42974156 ps
CPU time 0.73 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 206056 kb
Host smart-8800099e-e8ac-4d52-937e-2892892c1ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255857279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1255857279
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.183800949
Short name T744
Test name
Test status
Simulation time 114589261 ps
CPU time 2.65 seconds
Started Jun 26 05:56:34 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 221616 kb
Host smart-a91a3281-8628-4d14-bff8-bd5e65796ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183800949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.183800949
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4277194623
Short name T757
Test name
Test status
Simulation time 43755928 ps
CPU time 2.7 seconds
Started Jun 26 05:56:24 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 218480 kb
Host smart-ebc3bc15-bd63-4e87-ac45-cb5e02401417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277194623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4277194623
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2889626575
Short name T338
Test name
Test status
Simulation time 684583652 ps
CPU time 7.61 seconds
Started Jun 26 05:56:21 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 222376 kb
Host smart-4bd3a627-630a-422e-afac-86bd6e9c8d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889626575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2889626575
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3314391574
Short name T659
Test name
Test status
Simulation time 100041078 ps
CPU time 2.6 seconds
Started Jun 26 05:56:19 PM PDT 24
Finished Jun 26 05:56:35 PM PDT 24
Peak memory 222480 kb
Host smart-1e696e73-05a6-4263-ac48-3daf01d042fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314391574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3314391574
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1758864198
Short name T490
Test name
Test status
Simulation time 188169848 ps
CPU time 4.9 seconds
Started Jun 26 05:56:26 PM PDT 24
Finished Jun 26 05:56:46 PM PDT 24
Peak memory 214424 kb
Host smart-faf4e3d4-9c1a-4e17-b35c-ba9f7ac75741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758864198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1758864198
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2631867040
Short name T275
Test name
Test status
Simulation time 434592810 ps
CPU time 3.78 seconds
Started Jun 26 05:56:21 PM PDT 24
Finished Jun 26 05:56:40 PM PDT 24
Peak memory 208472 kb
Host smart-4f373d2d-fdbe-49aa-9418-8e8464be5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631867040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2631867040
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1589356155
Short name T673
Test name
Test status
Simulation time 96194806 ps
CPU time 2.1 seconds
Started Jun 26 05:56:20 PM PDT 24
Finished Jun 26 05:56:37 PM PDT 24
Peak memory 208932 kb
Host smart-15beb84f-894a-409f-8299-b267936e5506
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589356155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1589356155
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.779006566
Short name T586
Test name
Test status
Simulation time 762211972 ps
CPU time 7.08 seconds
Started Jun 26 05:56:21 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 208684 kb
Host smart-ae6bc3d5-bb11-46db-845d-1159c865a336
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779006566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.779006566
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.903940103
Short name T506
Test name
Test status
Simulation time 6684940860 ps
CPU time 63.97 seconds
Started Jun 26 05:56:22 PM PDT 24
Finished Jun 26 05:57:41 PM PDT 24
Peak memory 209280 kb
Host smart-135f1df9-8cfc-41a6-93aa-0aca80452355
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903940103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.903940103
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2454403207
Short name T816
Test name
Test status
Simulation time 245810250 ps
CPU time 2.93 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 209892 kb
Host smart-91feae20-3f7c-42ac-aca8-86fef96a0c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454403207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2454403207
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2110880696
Short name T785
Test name
Test status
Simulation time 53470177 ps
CPU time 2.2 seconds
Started Jun 26 05:56:24 PM PDT 24
Finished Jun 26 05:56:41 PM PDT 24
Peak memory 206832 kb
Host smart-580c5ca0-a57d-4d2c-9389-c4f890992b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110880696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2110880696
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2925800906
Short name T850
Test name
Test status
Simulation time 576074188 ps
CPU time 7.15 seconds
Started Jun 26 05:56:28 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 214312 kb
Host smart-5f62ce77-5404-4b84-b78e-1daa27e2df98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925800906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2925800906
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2101589707
Short name T133
Test name
Test status
Simulation time 2223955382 ps
CPU time 8.73 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 222916 kb
Host smart-84aef3e8-387b-4a0f-aa97-3265d35797bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101589707 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2101589707
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2049155354
Short name T549
Test name
Test status
Simulation time 465184939 ps
CPU time 5.66 seconds
Started Jun 26 05:56:21 PM PDT 24
Finished Jun 26 05:56:42 PM PDT 24
Peak memory 209588 kb
Host smart-7053c7db-b610-4dd4-b39b-aee49ade5ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049155354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2049155354
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.608432991
Short name T576
Test name
Test status
Simulation time 209251848 ps
CPU time 2.05 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:46 PM PDT 24
Peak memory 210072 kb
Host smart-6adf3aa0-9531-49c2-be43-fc3548918015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608432991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.608432991
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.749931694
Short name T467
Test name
Test status
Simulation time 97604587 ps
CPU time 0.79 seconds
Started Jun 26 05:56:28 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 206068 kb
Host smart-a60e42f0-0e9d-443e-b9e8-36fb96448ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749931694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.749931694
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3451248769
Short name T34
Test name
Test status
Simulation time 285096108 ps
CPU time 2.79 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 221912 kb
Host smart-0d13dff1-da68-4722-80d8-6c8181be8c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451248769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3451248769
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.268278381
Short name T346
Test name
Test status
Simulation time 970659714 ps
CPU time 23.6 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:57:07 PM PDT 24
Peak memory 209728 kb
Host smart-9295c1b9-75f6-447c-b2a7-7ecae13937cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268278381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.268278381
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4177580103
Short name T610
Test name
Test status
Simulation time 751859350 ps
CPU time 6.58 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 209320 kb
Host smart-81404784-3e72-43f1-b80f-02625efda391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177580103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4177580103
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4045903413
Short name T363
Test name
Test status
Simulation time 122300225 ps
CPU time 5.53 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 222460 kb
Host smart-33522d31-ea5b-48d2-848f-f3294123e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045903413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4045903413
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.16656339
Short name T779
Test name
Test status
Simulation time 553305756 ps
CPU time 4.59 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 209720 kb
Host smart-f18424a9-bc06-4436-9907-bf8b7e3774d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16656339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.16656339
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1294240487
Short name T327
Test name
Test status
Simulation time 351865522 ps
CPU time 3.76 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 207700 kb
Host smart-d53114f7-a838-43a7-be44-d2cd02a19d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294240487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1294240487
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2849673295
Short name T874
Test name
Test status
Simulation time 53523242 ps
CPU time 2.58 seconds
Started Jun 26 05:56:31 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 208004 kb
Host smart-98f58e2d-0c63-4109-9e68-83b5749ec6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849673295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2849673295
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1973062063
Short name T283
Test name
Test status
Simulation time 237663857 ps
CPU time 7.07 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 208772 kb
Host smart-57e53b16-ada0-4d23-952d-e8dbdaa4e6a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973062063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1973062063
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.420484668
Short name T913
Test name
Test status
Simulation time 234685826 ps
CPU time 3.85 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 206932 kb
Host smart-7257aebb-8598-4664-92eb-becd89a7814b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420484668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.420484668
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3461188150
Short name T545
Test name
Test status
Simulation time 6552959394 ps
CPU time 46.08 seconds
Started Jun 26 05:56:34 PM PDT 24
Finished Jun 26 05:57:33 PM PDT 24
Peak memory 208512 kb
Host smart-9f1e6061-4151-4664-b137-94bd25b2f95a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461188150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3461188150
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.424426490
Short name T501
Test name
Test status
Simulation time 320249505 ps
CPU time 4.05 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 215824 kb
Host smart-2d5f8be9-f526-4daf-aedb-ba4d786dbcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424426490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.424426490
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3171379892
Short name T907
Test name
Test status
Simulation time 663052814 ps
CPU time 6.07 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 208872 kb
Host smart-6657e358-c9a6-433d-85cc-9756083d6bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171379892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3171379892
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1611887303
Short name T382
Test name
Test status
Simulation time 6489457631 ps
CPU time 130.54 seconds
Started Jun 26 05:56:28 PM PDT 24
Finished Jun 26 05:58:53 PM PDT 24
Peak memory 216844 kb
Host smart-8b09833b-1ff5-46de-9e48-7ade2d46233a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611887303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1611887303
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.755586043
Short name T828
Test name
Test status
Simulation time 429735597 ps
CPU time 10.97 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:57 PM PDT 24
Peak memory 209300 kb
Host smart-810ba503-d6a3-4a66-83b4-f9feddd5a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755586043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.755586043
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2606051425
Short name T164
Test name
Test status
Simulation time 290898513 ps
CPU time 3.23 seconds
Started Jun 26 05:56:31 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 210608 kb
Host smart-aa47b3c9-0684-4730-a82f-dca18db1c366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606051425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2606051425
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4151763766
Short name T701
Test name
Test status
Simulation time 45457521 ps
CPU time 0.92 seconds
Started Jun 26 05:56:28 PM PDT 24
Finished Jun 26 05:56:44 PM PDT 24
Peak memory 206076 kb
Host smart-80c13dc6-05ac-4877-93c5-a281ff1a1979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151763766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4151763766
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2382214916
Short name T891
Test name
Test status
Simulation time 289412290 ps
CPU time 3.54 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 221368 kb
Host smart-56afdee8-f364-4570-9985-b4655191c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382214916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2382214916
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1542473784
Short name T905
Test name
Test status
Simulation time 108996882 ps
CPU time 1.68 seconds
Started Jun 26 05:56:35 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 207392 kb
Host smart-0d09e48f-6c0f-4dd5-84cc-2c32859d81b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542473784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1542473784
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2807888253
Short name T831
Test name
Test status
Simulation time 1080713738 ps
CPU time 25.42 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:57:09 PM PDT 24
Peak memory 214316 kb
Host smart-235d5149-0ea8-4dc8-b700-9d149100b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807888253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2807888253
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2419589224
Short name T362
Test name
Test status
Simulation time 515210658 ps
CPU time 3.77 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 221156 kb
Host smart-cfa06cea-e554-4273-9d96-b46aa97061f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419589224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2419589224
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3988666047
Short name T578
Test name
Test status
Simulation time 65899447 ps
CPU time 2.25 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 214316 kb
Host smart-f739fb67-95a3-49d9-9e22-1ed993998043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988666047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3988666047
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2174150939
Short name T711
Test name
Test status
Simulation time 257466824 ps
CPU time 2.11 seconds
Started Jun 26 05:56:26 PM PDT 24
Finished Jun 26 05:56:43 PM PDT 24
Peak memory 208120 kb
Host smart-c42d6d26-4709-4354-90a2-4358f313b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174150939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2174150939
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.854822945
Short name T716
Test name
Test status
Simulation time 29023205 ps
CPU time 2.14 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 208620 kb
Host smart-15f45ca5-1486-4c3e-9c97-d7f1f5ebd496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854822945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.854822945
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4049163607
Short name T499
Test name
Test status
Simulation time 55297340 ps
CPU time 2.77 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 207944 kb
Host smart-b0fc9121-3db2-46f3-a195-b6cb4c18c75b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049163607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4049163607
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.958192292
Short name T743
Test name
Test status
Simulation time 170079914 ps
CPU time 3.28 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 207340 kb
Host smart-ae15a6b9-e41e-4188-b8bb-a6c4332bd73e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958192292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.958192292
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2986670839
Short name T453
Test name
Test status
Simulation time 155054383 ps
CPU time 4.21 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 208460 kb
Host smart-46cd2e8b-fe85-4d2b-9ced-35065331f569
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986670839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2986670839
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1163976364
Short name T570
Test name
Test status
Simulation time 124111209 ps
CPU time 3.01 seconds
Started Jun 26 05:56:34 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 216000 kb
Host smart-2dc537d9-d056-426d-a165-95ec08f978fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163976364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1163976364
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2584051466
Short name T803
Test name
Test status
Simulation time 126782624 ps
CPU time 2.84 seconds
Started Jun 26 05:56:35 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 208164 kb
Host smart-e23ee7bc-a45e-4cb5-a307-2fe26b9e335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584051466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2584051466
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2274227930
Short name T893
Test name
Test status
Simulation time 271435789 ps
CPU time 3.21 seconds
Started Jun 26 05:56:27 PM PDT 24
Finished Jun 26 05:56:45 PM PDT 24
Peak memory 219728 kb
Host smart-c6de862c-4e26-4b28-85ea-c1a45e07b577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274227930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2274227930
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.472040245
Short name T568
Test name
Test status
Simulation time 394196530 ps
CPU time 5.96 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 218456 kb
Host smart-5ef88486-d5c5-46e8-9094-ead2cf92827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472040245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.472040245
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.956421844
Short name T638
Test name
Test status
Simulation time 162675021 ps
CPU time 2.16 seconds
Started Jun 26 05:56:28 PM PDT 24
Finished Jun 26 05:56:45 PM PDT 24
Peak memory 210016 kb
Host smart-9b7d5818-8990-4c78-9db8-93212d32cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956421844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.956421844
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.930635340
Short name T513
Test name
Test status
Simulation time 56921088 ps
CPU time 0.86 seconds
Started Jun 26 05:56:38 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 206056 kb
Host smart-3c73a6b5-c8cb-4e6d-9b03-49cdf8771acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930635340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.930635340
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.293394686
Short name T433
Test name
Test status
Simulation time 307626391 ps
CPU time 4.12 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 214340 kb
Host smart-e3e1eee6-f3e3-4d3c-98ef-eb3020cfe05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293394686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.293394686
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1040892370
Short name T858
Test name
Test status
Simulation time 407631054 ps
CPU time 4.63 seconds
Started Jun 26 05:56:34 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 214360 kb
Host smart-81b2cc3f-5c25-42c1-bc82-df41574a578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040892370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1040892370
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1113397582
Short name T652
Test name
Test status
Simulation time 1157043449 ps
CPU time 4.69 seconds
Started Jun 26 05:56:28 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 208480 kb
Host smart-1ef23fa9-7851-4c2a-b230-fcaead659c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113397582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1113397582
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2501263857
Short name T812
Test name
Test status
Simulation time 813142461 ps
CPU time 6.09 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 214140 kb
Host smart-abbd5e31-c4f9-4e3b-9b18-ea707ba7486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501263857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2501263857
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2491908524
Short name T557
Test name
Test status
Simulation time 226882452 ps
CPU time 3.39 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:56:47 PM PDT 24
Peak memory 209020 kb
Host smart-d12cea54-28c2-4dfd-a0be-461be445444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491908524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2491908524
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1366568924
Short name T774
Test name
Test status
Simulation time 1865312302 ps
CPU time 6.61 seconds
Started Jun 26 05:56:35 PM PDT 24
Finished Jun 26 05:56:53 PM PDT 24
Peak memory 219588 kb
Host smart-12a83dbb-5cc5-4470-9a80-2f9450e87ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366568924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1366568924
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1117353445
Short name T875
Test name
Test status
Simulation time 133595965 ps
CPU time 4.71 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 208508 kb
Host smart-017dd4a8-05b3-46aa-8215-306488e39819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117353445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1117353445
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3386833277
Short name T484
Test name
Test status
Simulation time 288048843 ps
CPU time 3.05 seconds
Started Jun 26 05:56:29 PM PDT 24
Finished Jun 26 05:56:46 PM PDT 24
Peak memory 208880 kb
Host smart-07b7372b-e1df-429b-b798-21348c17a353
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386833277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3386833277
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.328173021
Short name T867
Test name
Test status
Simulation time 41783441 ps
CPU time 2.44 seconds
Started Jun 26 05:56:35 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 207028 kb
Host smart-d0b9605b-437a-4676-8a38-6237b778bc19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328173021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.328173021
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3147991515
Short name T444
Test name
Test status
Simulation time 119184408 ps
CPU time 3.27 seconds
Started Jun 26 05:56:33 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 208212 kb
Host smart-d61d2580-e885-45db-b09d-2c10138949ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147991515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3147991515
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1597486461
Short name T487
Test name
Test status
Simulation time 26540211 ps
CPU time 2.17 seconds
Started Jun 26 05:56:30 PM PDT 24
Finished Jun 26 05:56:46 PM PDT 24
Peak memory 214348 kb
Host smart-7b651d86-7903-4339-9e52-d5254064a374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597486461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1597486461
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2253940129
Short name T762
Test name
Test status
Simulation time 155348343 ps
CPU time 2.67 seconds
Started Jun 26 05:56:32 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 208544 kb
Host smart-5544ea08-fe8c-481d-93dd-8fc292183fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253940129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2253940129
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3229679363
Short name T683
Test name
Test status
Simulation time 64535849 ps
CPU time 2.88 seconds
Started Jun 26 05:56:35 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 206840 kb
Host smart-143c71a1-7453-45ef-9488-fcc14bf74ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229679363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3229679363
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.315329446
Short name T504
Test name
Test status
Simulation time 66183129 ps
CPU time 4.29 seconds
Started Jun 26 05:56:31 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 214316 kb
Host smart-57dc0c81-d99a-4b7d-8a0d-d380d66e25cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315329446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.315329446
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3857497158
Short name T203
Test name
Test status
Simulation time 756080807 ps
CPU time 12.66 seconds
Started Jun 26 05:56:39 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 210968 kb
Host smart-0199db7c-7909-43b1-bfdf-65cd188ea58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857497158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3857497158
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1032796433
Short name T103
Test name
Test status
Simulation time 25584555 ps
CPU time 0.83 seconds
Started Jun 26 05:56:36 PM PDT 24
Finished Jun 26 05:56:48 PM PDT 24
Peak memory 206024 kb
Host smart-cb0b0b1f-e3ff-4db6-90ec-ea675594550d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032796433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1032796433
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2784480638
Short name T420
Test name
Test status
Simulation time 144987001 ps
CPU time 7.74 seconds
Started Jun 26 05:56:38 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 222516 kb
Host smart-fc11749a-a814-4551-87aa-9244800a88d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784480638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2784480638
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4275791009
Short name T29
Test name
Test status
Simulation time 447867687 ps
CPU time 19.88 seconds
Started Jun 26 05:56:38 PM PDT 24
Finished Jun 26 05:57:08 PM PDT 24
Peak memory 214660 kb
Host smart-1bd966c1-fc2b-446b-bec5-e5efda478d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275791009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4275791009
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3665201377
Short name T205
Test name
Test status
Simulation time 974675549 ps
CPU time 4.58 seconds
Started Jun 26 05:56:36 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 209196 kb
Host smart-d438ab20-84a3-45cd-90d7-0008bb2975a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665201377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3665201377
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1884146115
Short name T335
Test name
Test status
Simulation time 23254805 ps
CPU time 1.97 seconds
Started Jun 26 05:56:40 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 214332 kb
Host smart-90b09469-24d7-4b73-ab7e-de0c8e006215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884146115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1884146115
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1624733754
Short name T337
Test name
Test status
Simulation time 137914107 ps
CPU time 4.12 seconds
Started Jun 26 05:56:37 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 222420 kb
Host smart-1b2a19aa-c5e9-4de6-911c-4e7db43b8b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624733754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1624733754
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2916207704
Short name T517
Test name
Test status
Simulation time 34340621 ps
CPU time 2.5 seconds
Started Jun 26 05:56:36 PM PDT 24
Finished Jun 26 05:56:49 PM PDT 24
Peak memory 208416 kb
Host smart-e1d130ab-1203-49e2-be19-dbdbca9460aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916207704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2916207704
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2562227590
Short name T505
Test name
Test status
Simulation time 91313278 ps
CPU time 4.2 seconds
Started Jun 26 05:56:38 PM PDT 24
Finished Jun 26 05:56:53 PM PDT 24
Peak memory 208764 kb
Host smart-cb0d8496-281c-4d14-9322-cadc4da6a9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562227590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2562227590
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4173238875
Short name T536
Test name
Test status
Simulation time 279568337 ps
CPU time 3.68 seconds
Started Jun 26 05:56:36 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 207492 kb
Host smart-652e689f-0c81-4e48-b5bd-5dfb86b7ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173238875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4173238875
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.403337346
Short name T783
Test name
Test status
Simulation time 22697941 ps
CPU time 1.87 seconds
Started Jun 26 06:00:20 PM PDT 24
Finished Jun 26 06:00:24 PM PDT 24
Peak memory 207056 kb
Host smart-130ec310-3323-484f-8b80-306cc55845dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403337346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.403337346
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.136818310
Short name T864
Test name
Test status
Simulation time 118727801 ps
CPU time 2.34 seconds
Started Jun 26 05:56:41 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 206856 kb
Host smart-83f6c652-40c5-4644-ad42-2ef7a06ef9af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136818310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.136818310
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1445376611
Short name T747
Test name
Test status
Simulation time 49034638 ps
CPU time 2.75 seconds
Started Jun 26 05:56:41 PM PDT 24
Finished Jun 26 05:56:53 PM PDT 24
Peak memory 206724 kb
Host smart-7e76610c-363e-4a76-a0a3-1148a6834ef2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445376611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1445376611
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2579175394
Short name T623
Test name
Test status
Simulation time 220708578 ps
CPU time 2.95 seconds
Started Jun 26 05:56:35 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 207364 kb
Host smart-b115082a-2d82-4275-b369-4360ecc6378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579175394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2579175394
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2346908170
Short name T837
Test name
Test status
Simulation time 197049517 ps
CPU time 2.62 seconds
Started Jun 26 05:56:38 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 206936 kb
Host smart-77440116-3ed7-4590-bf2f-2fee7e54343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346908170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2346908170
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2436106871
Short name T797
Test name
Test status
Simulation time 250199596 ps
CPU time 7.1 seconds
Started Jun 26 05:56:36 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 208908 kb
Host smart-8a71483f-9560-4a2a-acad-9958eb94498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436106871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2436106871
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1460649981
Short name T395
Test name
Test status
Simulation time 148424559 ps
CPU time 4.68 seconds
Started Jun 26 05:57:26 PM PDT 24
Finished Jun 26 05:57:31 PM PDT 24
Peak memory 209968 kb
Host smart-4b23601e-10b3-482f-872e-9d6b3ce52ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460649981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1460649981
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1763137979
Short name T533
Test name
Test status
Simulation time 85699275 ps
CPU time 0.9 seconds
Started Jun 26 05:56:46 PM PDT 24
Finished Jun 26 05:56:53 PM PDT 24
Peak memory 206044 kb
Host smart-a899b7a2-01d2-40fb-801c-e9758a3b9c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763137979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1763137979
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.459773655
Short name T431
Test name
Test status
Simulation time 168298009 ps
CPU time 2.98 seconds
Started Jun 26 05:56:48 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 214708 kb
Host smart-9bcfe132-b9d7-40ee-9b99-f595b5b387d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459773655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.459773655
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.638725470
Short name T323
Test name
Test status
Simulation time 152516355 ps
CPU time 4.85 seconds
Started Jun 26 05:56:44 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 209908 kb
Host smart-944c641e-4518-4032-9308-5c950b474298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638725470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.638725470
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2484066665
Short name T332
Test name
Test status
Simulation time 81861110 ps
CPU time 2.94 seconds
Started Jun 26 05:56:45 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 209784 kb
Host smart-9e87dbe3-994c-4ec3-a367-ba806d3afc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484066665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2484066665
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.604132108
Short name T102
Test name
Test status
Simulation time 117853779 ps
CPU time 5.27 seconds
Started Jun 26 05:56:46 PM PDT 24
Finished Jun 26 05:56:58 PM PDT 24
Peak memory 214316 kb
Host smart-0099598b-4ff3-48cf-9b0d-4093bc65530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604132108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.604132108
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1903128543
Short name T308
Test name
Test status
Simulation time 91494257 ps
CPU time 3.16 seconds
Started Jun 26 05:56:46 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 214328 kb
Host smart-9015649d-a8b7-4545-b0e7-ac575f5b19d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903128543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1903128543
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2821099373
Short name T57
Test name
Test status
Simulation time 128226778 ps
CPU time 3.97 seconds
Started Jun 26 05:56:45 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 222504 kb
Host smart-e4469c11-ebac-458d-8ee7-9f678aab0db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821099373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2821099373
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3163592081
Short name T240
Test name
Test status
Simulation time 85242469 ps
CPU time 3.78 seconds
Started Jun 26 05:56:45 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 207612 kb
Host smart-09bd2035-c9cf-4c57-8ce4-1f7075982faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163592081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3163592081
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.400530484
Short name T915
Test name
Test status
Simulation time 74025130 ps
CPU time 3.57 seconds
Started Jun 26 05:56:36 PM PDT 24
Finished Jun 26 05:56:50 PM PDT 24
Peak memory 208512 kb
Host smart-2f417b6d-218b-4360-aa5b-7cfb944dd6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400530484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.400530484
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2182302370
Short name T44
Test name
Test status
Simulation time 180858951 ps
CPU time 5 seconds
Started Jun 26 05:56:41 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 207968 kb
Host smart-2d2acbfa-8b18-426d-86ed-40d5a0c2e5d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182302370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2182302370
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3285449656
Short name T921
Test name
Test status
Simulation time 504160500 ps
CPU time 4.66 seconds
Started Jun 26 05:56:42 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 208572 kb
Host smart-e9b5dee4-58b4-4a22-aa43-6224804e6383
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285449656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3285449656
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.281595848
Short name T669
Test name
Test status
Simulation time 61948468 ps
CPU time 2.92 seconds
Started Jun 26 05:56:39 PM PDT 24
Finished Jun 26 05:56:52 PM PDT 24
Peak memory 207904 kb
Host smart-651abfd5-76a4-4ac4-a1db-b289ca5ef758
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281595848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.281595848
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1158855623
Short name T643
Test name
Test status
Simulation time 4829665592 ps
CPU time 13.42 seconds
Started Jun 26 05:56:44 PM PDT 24
Finished Jun 26 05:57:05 PM PDT 24
Peak memory 209232 kb
Host smart-96331d7b-b00e-415c-966b-68bae6a61990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158855623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1158855623
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.509139077
Short name T109
Test name
Test status
Simulation time 637853114 ps
CPU time 3.29 seconds
Started Jun 26 05:56:37 PM PDT 24
Finished Jun 26 05:56:51 PM PDT 24
Peak memory 208628 kb
Host smart-3ab2181a-b641-4895-9ec0-46a1f1078156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509139077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.509139077
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2302998449
Short name T188
Test name
Test status
Simulation time 1630413816 ps
CPU time 23.37 seconds
Started Jun 26 05:56:45 PM PDT 24
Finished Jun 26 05:57:15 PM PDT 24
Peak memory 220812 kb
Host smart-a846c0a8-08c9-413c-8360-0f2807f26339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302998449 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2302998449
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2791975894
Short name T89
Test name
Test status
Simulation time 3340258088 ps
CPU time 59.59 seconds
Started Jun 26 05:56:44 PM PDT 24
Finished Jun 26 05:57:51 PM PDT 24
Peak memory 220096 kb
Host smart-7a8f9693-4dba-43ef-a186-451825064e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791975894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2791975894
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.61296770
Short name T43
Test name
Test status
Simulation time 148345748 ps
CPU time 2.89 seconds
Started Jun 26 05:56:45 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 210428 kb
Host smart-0fdcfba0-6eee-4e13-8acb-a33c4758793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61296770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.61296770
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2841308036
Short name T515
Test name
Test status
Simulation time 163935841 ps
CPU time 0.77 seconds
Started Jun 26 05:56:50 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 206044 kb
Host smart-607777ec-054d-48c5-be07-fb4008be6b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841308036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2841308036
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2108209321
Short name T31
Test name
Test status
Simulation time 753081544 ps
CPU time 5.61 seconds
Started Jun 26 05:56:58 PM PDT 24
Finished Jun 26 05:57:04 PM PDT 24
Peak memory 221880 kb
Host smart-57b0432f-79cd-4f76-b59a-bb31e0418f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108209321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2108209321
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2263224448
Short name T798
Test name
Test status
Simulation time 118375631 ps
CPU time 2.72 seconds
Started Jun 26 05:56:44 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 218368 kb
Host smart-6741715b-0353-4d39-8f81-23b799e7912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263224448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2263224448
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3691049885
Short name T377
Test name
Test status
Simulation time 86137232 ps
CPU time 2.22 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:56:59 PM PDT 24
Peak memory 214308 kb
Host smart-b8e6d48a-fcc4-47d8-89d0-98f712ae6eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691049885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3691049885
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.752001991
Short name T731
Test name
Test status
Simulation time 78908739 ps
CPU time 2.55 seconds
Started Jun 26 05:56:43 PM PDT 24
Finished Jun 26 05:56:53 PM PDT 24
Peak memory 214380 kb
Host smart-15bd09be-0e6d-45e1-9eb2-4b203f0b5b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752001991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.752001991
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2839449613
Short name T88
Test name
Test status
Simulation time 118269770 ps
CPU time 3.2 seconds
Started Jun 26 05:56:44 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 207668 kb
Host smart-5877dd09-ea15-4f64-a50b-9c70835e640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839449613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2839449613
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3207573016
Short name T603
Test name
Test status
Simulation time 591955564 ps
CPU time 7.79 seconds
Started Jun 26 05:56:44 PM PDT 24
Finished Jun 26 05:56:59 PM PDT 24
Peak memory 207148 kb
Host smart-9a06c89c-efc2-4ff6-bf7b-54c9f13adb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207573016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3207573016
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1623132042
Short name T296
Test name
Test status
Simulation time 243099133 ps
CPU time 3.22 seconds
Started Jun 26 05:56:43 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 209100 kb
Host smart-33fc337d-6df0-4ed0-99b5-52e1a347648c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623132042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1623132042
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3670600093
Short name T811
Test name
Test status
Simulation time 271117793 ps
CPU time 3.73 seconds
Started Jun 26 05:56:43 PM PDT 24
Finished Jun 26 05:56:55 PM PDT 24
Peak memory 208792 kb
Host smart-a43d5da0-040d-40d5-b228-9b5360686257
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670600093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3670600093
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2860634871
Short name T909
Test name
Test status
Simulation time 40193526 ps
CPU time 1.85 seconds
Started Jun 26 05:56:45 PM PDT 24
Finished Jun 26 05:56:54 PM PDT 24
Peak memory 206852 kb
Host smart-21423735-d417-4c09-ba15-cef2cef59972
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860634871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2860634871
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1351433555
Short name T697
Test name
Test status
Simulation time 143221641 ps
CPU time 4.03 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 210072 kb
Host smart-2b3538f4-908c-4aea-a213-fec0ae61018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351433555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1351433555
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4183912155
Short name T438
Test name
Test status
Simulation time 821585820 ps
CPU time 14.42 seconds
Started Jun 26 05:56:46 PM PDT 24
Finished Jun 26 05:57:07 PM PDT 24
Peak memory 208544 kb
Host smart-4e50af79-2703-49f7-b2f4-ae3f79d92e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183912155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4183912155
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.684958707
Short name T190
Test name
Test status
Simulation time 1061431639 ps
CPU time 19.52 seconds
Started Jun 26 05:56:54 PM PDT 24
Finished Jun 26 05:57:16 PM PDT 24
Peak memory 219368 kb
Host smart-093d3f6a-836f-43a4-b815-4d6678ddeb09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684958707 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.684958707
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.661027692
Short name T26
Test name
Test status
Simulation time 96578272 ps
CPU time 4.64 seconds
Started Jun 26 05:56:55 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 218556 kb
Host smart-c6ac73f9-c0d4-46d0-aefb-3b0a4d0bf618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661027692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.661027692
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2723609684
Short name T401
Test name
Test status
Simulation time 233885226 ps
CPU time 3.26 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:56:58 PM PDT 24
Peak memory 210616 kb
Host smart-71edec7e-24ee-4b01-a73b-18d50b0d9987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723609684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2723609684
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3912369825
Short name T591
Test name
Test status
Simulation time 23012500 ps
CPU time 0.9 seconds
Started Jun 26 05:56:52 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 206008 kb
Host smart-2639040a-7aba-4cf3-bbb7-9f04b2ccbae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912369825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3912369825
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1403791528
Short name T430
Test name
Test status
Simulation time 74552753 ps
CPU time 2.64 seconds
Started Jun 26 05:56:49 PM PDT 24
Finished Jun 26 05:56:56 PM PDT 24
Peak memory 215300 kb
Host smart-101c2b11-d5b2-4276-801e-740e45019888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403791528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1403791528
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.938635314
Short name T685
Test name
Test status
Simulation time 753434072 ps
CPU time 5.81 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:57:01 PM PDT 24
Peak memory 218292 kb
Host smart-baccd844-6fad-4fee-a088-b234925791ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938635314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.938635314
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3922315416
Short name T428
Test name
Test status
Simulation time 120081945 ps
CPU time 1.58 seconds
Started Jun 26 05:57:00 PM PDT 24
Finished Jun 26 05:57:03 PM PDT 24
Peak memory 207404 kb
Host smart-5af94a5b-9edf-4a5f-81ab-41907bb3fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922315416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3922315416
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3361848301
Short name T650
Test name
Test status
Simulation time 54579619 ps
CPU time 3.46 seconds
Started Jun 26 05:56:57 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 215336 kb
Host smart-bc03e4c2-64a3-4fca-a8e3-18996ae539aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361848301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3361848301
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1056573955
Short name T49
Test name
Test status
Simulation time 116815485 ps
CPU time 2.04 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:56:57 PM PDT 24
Peak memory 208360 kb
Host smart-3f22d85b-67a2-4306-8e25-c7dd25fb0bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056573955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1056573955
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1319628051
Short name T110
Test name
Test status
Simulation time 168170893 ps
CPU time 3.7 seconds
Started Jun 26 05:56:57 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 207392 kb
Host smart-3e51029b-416c-498a-aaba-2cca359f89ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319628051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1319628051
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4049205912
Short name T688
Test name
Test status
Simulation time 241671819 ps
CPU time 6.44 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:03 PM PDT 24
Peak memory 207560 kb
Host smart-4203a1bd-73e3-4404-8591-4540c45517ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049205912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4049205912
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.605698193
Short name T584
Test name
Test status
Simulation time 910717803 ps
CPU time 6.75 seconds
Started Jun 26 05:56:52 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 209092 kb
Host smart-514fd557-3f77-4921-ab32-738a34aa8bc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605698193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.605698193
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3297651534
Short name T2
Test name
Test status
Simulation time 226993969 ps
CPU time 5.61 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 208964 kb
Host smart-00df81f9-5f04-4eb9-a0dd-48926d19ba70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297651534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3297651534
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1387180300
Short name T567
Test name
Test status
Simulation time 328669632 ps
CPU time 6.98 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 208912 kb
Host smart-a14baaea-d27c-4229-b90d-9a83bdbafb08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387180300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1387180300
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3411817923
Short name T881
Test name
Test status
Simulation time 165793998 ps
CPU time 4.46 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:01 PM PDT 24
Peak memory 214332 kb
Host smart-3a27ae39-31bc-40a6-b82e-4150d3256508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411817923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3411817923
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3203181272
Short name T450
Test name
Test status
Simulation time 227450409 ps
CPU time 3.78 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 208484 kb
Host smart-0c0340d0-16fe-47b5-8f66-57d78705173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203181272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3203181272
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1006300050
Short name T85
Test name
Test status
Simulation time 27469743039 ps
CPU time 76.3 seconds
Started Jun 26 05:56:52 PM PDT 24
Finished Jun 26 05:58:12 PM PDT 24
Peak memory 216892 kb
Host smart-d3fa47a7-92ed-4071-8626-8458e17cba18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006300050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1006300050
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1657590740
Short name T665
Test name
Test status
Simulation time 374279382 ps
CPU time 5.66 seconds
Started Jun 26 05:56:50 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 208652 kb
Host smart-1ea8937a-0ec3-42ba-b5bd-4fb2e8f28f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657590740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1657590740
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.108766716
Short name T129
Test name
Test status
Simulation time 109298431 ps
CPU time 1.54 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:56:57 PM PDT 24
Peak memory 208644 kb
Host smart-7961955b-f7ee-456a-9220-d93dabd413f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108766716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.108766716
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.311832177
Short name T571
Test name
Test status
Simulation time 83793228 ps
CPU time 0.83 seconds
Started Jun 26 05:56:58 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 206064 kb
Host smart-f1d391a3-d073-4222-9ea8-40e893848260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311832177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.311832177
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2803503394
Short name T426
Test name
Test status
Simulation time 289716805 ps
CPU time 3.16 seconds
Started Jun 26 05:57:00 PM PDT 24
Finished Jun 26 05:57:04 PM PDT 24
Peak memory 215108 kb
Host smart-8f715d0a-dd2b-44b2-a8e8-bdc7e717ed29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803503394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2803503394
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.62859274
Short name T83
Test name
Test status
Simulation time 34689111 ps
CPU time 2.01 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:56:58 PM PDT 24
Peak memory 207708 kb
Host smart-a2b2849f-bb2a-4505-8a5d-31750d705f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62859274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.62859274
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2327944305
Short name T485
Test name
Test status
Simulation time 77760785 ps
CPU time 3.62 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:56:58 PM PDT 24
Peak memory 214296 kb
Host smart-99237e61-e714-4a10-b8b3-e3b07ccf64e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327944305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2327944305
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2222868764
Short name T824
Test name
Test status
Simulation time 240583152 ps
CPU time 4.24 seconds
Started Jun 26 05:56:57 PM PDT 24
Finished Jun 26 05:57:03 PM PDT 24
Peak memory 215108 kb
Host smart-86c44c92-020b-4459-88f9-170958e861d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222868764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2222868764
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1319341051
Short name T670
Test name
Test status
Simulation time 579045516 ps
CPU time 5.15 seconds
Started Jun 26 05:56:58 PM PDT 24
Finished Jun 26 05:57:04 PM PDT 24
Peak memory 207364 kb
Host smart-194ea47b-5923-4391-91ad-ef8b493e6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319341051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1319341051
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1294118894
Short name T818
Test name
Test status
Simulation time 138993902 ps
CPU time 2.4 seconds
Started Jun 26 05:56:57 PM PDT 24
Finished Jun 26 05:57:01 PM PDT 24
Peak memory 206908 kb
Host smart-3e58d545-2a56-4ea0-86dd-8ea9041987bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294118894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1294118894
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1636010582
Short name T367
Test name
Test status
Simulation time 298029125 ps
CPU time 3.94 seconds
Started Jun 26 05:56:51 PM PDT 24
Finished Jun 26 05:56:59 PM PDT 24
Peak memory 208848 kb
Host smart-99efbd0c-7a7e-46ef-9dba-195608a51ede
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636010582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1636010582
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.931933994
Short name T525
Test name
Test status
Simulation time 543265446 ps
CPU time 5.82 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:02 PM PDT 24
Peak memory 207932 kb
Host smart-7a75ac53-2de4-48c4-9d0c-166bbe6a97c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931933994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.931933994
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1406127399
Short name T252
Test name
Test status
Simulation time 297646146 ps
CPU time 3.13 seconds
Started Jun 26 05:56:53 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 208564 kb
Host smart-e1a52902-82b0-4e99-bdb1-59c9ead66904
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406127399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1406127399
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.335231743
Short name T722
Test name
Test status
Simulation time 29214771 ps
CPU time 2.34 seconds
Started Jun 26 05:56:59 PM PDT 24
Finished Jun 26 05:57:03 PM PDT 24
Peak memory 215972 kb
Host smart-a285f5ae-3e7a-45ac-bf18-dd57853a6af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335231743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.335231743
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.461828548
Short name T886
Test name
Test status
Simulation time 418485969 ps
CPU time 3.35 seconds
Started Jun 26 05:56:54 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 207176 kb
Host smart-5a40a64f-15c4-4e8d-9417-9cc362fd096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461828548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.461828548
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.537688334
Short name T128
Test name
Test status
Simulation time 830135008 ps
CPU time 19.79 seconds
Started Jun 26 05:56:59 PM PDT 24
Finished Jun 26 05:57:20 PM PDT 24
Peak memory 222528 kb
Host smart-3d3711f0-5014-48c1-af5d-021f212ba10a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537688334 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.537688334
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2936755402
Short name T207
Test name
Test status
Simulation time 161446695 ps
CPU time 3.87 seconds
Started Jun 26 05:56:54 PM PDT 24
Finished Jun 26 05:57:00 PM PDT 24
Peak memory 214168 kb
Host smart-6c6a2712-5cd9-43e1-abb0-9a4915784f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936755402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2936755402
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4175696070
Short name T408
Test name
Test status
Simulation time 282204990 ps
CPU time 5.99 seconds
Started Jun 26 05:56:56 PM PDT 24
Finished Jun 26 05:57:04 PM PDT 24
Peak memory 210416 kb
Host smart-79533e63-d6f8-4e18-b237-479acb5f1c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175696070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4175696070
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2046384710
Short name T503
Test name
Test status
Simulation time 37808943 ps
CPU time 0.83 seconds
Started Jun 26 05:54:07 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 206084 kb
Host smart-778193d1-81e8-436c-a4d6-5cbe4dc181d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046384710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2046384710
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3687085670
Short name T73
Test name
Test status
Simulation time 73605411 ps
CPU time 4.25 seconds
Started Jun 26 05:54:11 PM PDT 24
Finished Jun 26 05:54:16 PM PDT 24
Peak memory 218324 kb
Host smart-fca87b57-364b-467a-aaf9-794ee18e8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687085670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3687085670
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2811534859
Short name T789
Test name
Test status
Simulation time 1348094583 ps
CPU time 8.48 seconds
Started Jun 26 05:54:10 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 207464 kb
Host smart-fa81a355-568d-4183-a54c-5f50e23b1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811534859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2811534859
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.874024421
Short name T96
Test name
Test status
Simulation time 245186059 ps
CPU time 3.41 seconds
Started Jun 26 05:54:11 PM PDT 24
Finished Jun 26 05:54:16 PM PDT 24
Peak memory 214416 kb
Host smart-79c1173b-ba73-42ff-bc2c-66ffbb3bc5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874024421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.874024421
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2838750449
Short name T50
Test name
Test status
Simulation time 44813934 ps
CPU time 2.3 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 207572 kb
Host smart-56bdd36f-cc34-49f1-82e9-335d61ceb688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838750449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2838750449
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4097258910
Short name T594
Test name
Test status
Simulation time 301182102 ps
CPU time 8.94 seconds
Started Jun 26 05:54:08 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 218380 kb
Host smart-b1069218-1e43-4f97-a46b-6cec4390aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097258910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4097258910
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2611278855
Short name T754
Test name
Test status
Simulation time 47233601 ps
CPU time 2.76 seconds
Started Jun 26 05:54:09 PM PDT 24
Finished Jun 26 05:54:13 PM PDT 24
Peak memory 208632 kb
Host smart-c5c1da1e-9d84-4a0d-9070-4f198a3b84d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611278855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2611278855
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.197873587
Short name T877
Test name
Test status
Simulation time 60078454 ps
CPU time 3.06 seconds
Started Jun 26 05:54:10 PM PDT 24
Finished Jun 26 05:54:15 PM PDT 24
Peak memory 208636 kb
Host smart-6ec8c34d-ca54-4d97-a0d5-7b00ff59c9dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197873587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.197873587
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.517701967
Short name T404
Test name
Test status
Simulation time 11193013129 ps
CPU time 22.31 seconds
Started Jun 26 05:54:09 PM PDT 24
Finished Jun 26 05:54:33 PM PDT 24
Peak memory 208040 kb
Host smart-27fe7798-7a1e-4c0a-993f-fe9a82fd5881
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517701967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.517701967
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.140314506
Short name T860
Test name
Test status
Simulation time 130559079 ps
CPU time 1.74 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:17 PM PDT 24
Peak memory 206760 kb
Host smart-d2006b07-4565-4d47-84aa-f65114f53ae1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140314506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.140314506
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2484394641
Short name T856
Test name
Test status
Simulation time 786394768 ps
CPU time 5.73 seconds
Started Jun 26 05:54:12 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 209652 kb
Host smart-b1dde75d-205a-4d9b-82ff-e84232aeb2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484394641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2484394641
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3197055748
Short name T539
Test name
Test status
Simulation time 61738062 ps
CPU time 2.93 seconds
Started Jun 26 05:54:10 PM PDT 24
Finished Jun 26 05:54:14 PM PDT 24
Peak memory 208460 kb
Host smart-b0d3acbb-2c4e-4698-a176-6b041d03869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197055748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3197055748
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2194786287
Short name T660
Test name
Test status
Simulation time 313787499 ps
CPU time 6.81 seconds
Started Jun 26 05:54:10 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 208608 kb
Host smart-95e5ed59-65c5-489c-84f1-a5dcdfbfba9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194786287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2194786287
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.307635276
Short name T61
Test name
Test status
Simulation time 60046064 ps
CPU time 1.91 seconds
Started Jun 26 05:54:11 PM PDT 24
Finished Jun 26 05:54:15 PM PDT 24
Peak memory 209968 kb
Host smart-f5fc23e3-8b81-4f38-ae8b-2e79279d398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307635276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.307635276
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2521790333
Short name T455
Test name
Test status
Simulation time 45090341 ps
CPU time 0.81 seconds
Started Jun 26 05:54:16 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 206276 kb
Host smart-a47a993b-0f67-4648-83eb-df2c317aa8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521790333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2521790333
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1287091956
Short name T322
Test name
Test status
Simulation time 258935050 ps
CPU time 4.44 seconds
Started Jun 26 05:54:10 PM PDT 24
Finished Jun 26 05:54:15 PM PDT 24
Peak memory 215072 kb
Host smart-469f2aac-c1ce-4d38-b0d7-9c5003d449ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287091956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1287091956
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1674778993
Short name T434
Test name
Test status
Simulation time 310676364 ps
CPU time 6.17 seconds
Started Jun 26 05:54:11 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 222456 kb
Host smart-6e568c5c-4c97-4313-8f40-53332d07cc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674778993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1674778993
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2602975588
Short name T336
Test name
Test status
Simulation time 73627863 ps
CPU time 4 seconds
Started Jun 26 05:54:07 PM PDT 24
Finished Jun 26 05:54:12 PM PDT 24
Peak memory 214352 kb
Host smart-0e8c09db-7850-424b-a1a1-d5c190574e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602975588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2602975588
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1773649328
Short name T378
Test name
Test status
Simulation time 35721975 ps
CPU time 1.78 seconds
Started Jun 26 05:54:12 PM PDT 24
Finished Jun 26 05:54:15 PM PDT 24
Peak memory 214160 kb
Host smart-1395b615-6474-484a-a436-e785c00192f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773649328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1773649328
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1824009297
Short name T70
Test name
Test status
Simulation time 197157642 ps
CPU time 6.69 seconds
Started Jun 26 05:54:11 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 222464 kb
Host smart-a6321d2b-9dfd-4564-ad84-291ae94f6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824009297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1824009297
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3134879542
Short name T566
Test name
Test status
Simulation time 177093926 ps
CPU time 6.4 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:22 PM PDT 24
Peak memory 222372 kb
Host smart-b8c2087a-813c-4827-962a-5944768319f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134879542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3134879542
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1798371877
Short name T500
Test name
Test status
Simulation time 325767885 ps
CPU time 2.77 seconds
Started Jun 26 05:54:08 PM PDT 24
Finished Jun 26 05:54:11 PM PDT 24
Peak memory 208548 kb
Host smart-8f0d5f4c-8875-4bbc-a7d7-9c44436f65e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798371877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1798371877
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1413773416
Short name T581
Test name
Test status
Simulation time 250410245 ps
CPU time 6.64 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:22 PM PDT 24
Peak memory 207920 kb
Host smart-03fd53ba-618b-4445-a8be-ed4a06d4f350
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413773416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1413773416
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.943902996
Short name T848
Test name
Test status
Simulation time 1448856334 ps
CPU time 15.97 seconds
Started Jun 26 05:54:05 PM PDT 24
Finished Jun 26 05:54:23 PM PDT 24
Peak memory 208864 kb
Host smart-99d82d8c-9f38-4a73-926d-c0c1bd90d415
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943902996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.943902996
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4068102869
Short name T384
Test name
Test status
Simulation time 51676057 ps
CPU time 2.82 seconds
Started Jun 26 05:54:05 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 206880 kb
Host smart-1af17af6-19e9-4353-b39c-fef7d0f38d32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068102869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4068102869
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3335854983
Short name T254
Test name
Test status
Simulation time 137002024 ps
CPU time 5.32 seconds
Started Jun 26 05:54:06 PM PDT 24
Finished Jun 26 05:54:13 PM PDT 24
Peak memory 210352 kb
Host smart-db2c1b06-63f5-4873-8b43-b6b495a4527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335854983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3335854983
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1889341505
Short name T680
Test name
Test status
Simulation time 47562511 ps
CPU time 1.92 seconds
Started Jun 26 05:54:06 PM PDT 24
Finished Jun 26 05:54:09 PM PDT 24
Peak memory 208440 kb
Host smart-142a2166-4f1f-4154-b479-101186e87781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889341505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1889341505
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.314854280
Short name T366
Test name
Test status
Simulation time 2891122305 ps
CPU time 20.07 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:36 PM PDT 24
Peak memory 218340 kb
Host smart-afcb68da-19f6-4157-9438-583f2cbfe132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314854280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.314854280
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2751054589
Short name T60
Test name
Test status
Simulation time 190354899 ps
CPU time 2.34 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 210196 kb
Host smart-e6fd19a2-a5c7-46d7-8e4b-c9f75b44b76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751054589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2751054589
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3356822514
Short name T90
Test name
Test status
Simulation time 42855077 ps
CPU time 0.77 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:15 PM PDT 24
Peak memory 206016 kb
Host smart-2bb39fad-8f28-4190-aa01-c52399b228df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356822514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3356822514
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2902813896
Short name T422
Test name
Test status
Simulation time 62138360 ps
CPU time 2.92 seconds
Started Jun 26 05:54:15 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 214372 kb
Host smart-f9941499-7664-4430-af3d-02c638bcc123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902813896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2902813896
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1434763887
Short name T40
Test name
Test status
Simulation time 502333034 ps
CPU time 3.08 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 214332 kb
Host smart-1720b648-788f-47d7-ac94-ba3084e34bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434763887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1434763887
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.216439842
Short name T563
Test name
Test status
Simulation time 707271004 ps
CPU time 4.26 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 210044 kb
Host smart-958fad31-44d5-49d9-9d70-f42bbfc57e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216439842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.216439842
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.720300655
Short name T718
Test name
Test status
Simulation time 278706289 ps
CPU time 3.29 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 214328 kb
Host smart-5385d156-6b4e-448e-827d-8a4063a3f9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720300655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.720300655
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1987632593
Short name T267
Test name
Test status
Simulation time 83846794 ps
CPU time 1.9 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:17 PM PDT 24
Peak memory 214284 kb
Host smart-6912c058-d6ba-48d9-bc31-53481931f9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987632593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1987632593
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2638814085
Short name T223
Test name
Test status
Simulation time 129817193 ps
CPU time 1.93 seconds
Started Jun 26 05:54:16 PM PDT 24
Finished Jun 26 05:54:20 PM PDT 24
Peak memory 215460 kb
Host smart-aefa3646-cca7-4011-8bea-ac4fbf5cfc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638814085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2638814085
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.980621309
Short name T654
Test name
Test status
Simulation time 1695732442 ps
CPU time 5.13 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:20 PM PDT 24
Peak memory 209748 kb
Host smart-a8266e87-95ef-48e6-a2ca-9a5cde2227dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980621309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.980621309
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.61167031
Short name T651
Test name
Test status
Simulation time 256741718 ps
CPU time 4.34 seconds
Started Jun 26 05:54:15 PM PDT 24
Finished Jun 26 05:54:21 PM PDT 24
Peak memory 206968 kb
Host smart-846f1350-746a-4f8b-a7b9-b463349c7c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61167031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.61167031
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3892294799
Short name T555
Test name
Test status
Simulation time 99729342 ps
CPU time 2.79 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 206680 kb
Host smart-549cc8fa-7695-4592-977a-62a2a0854c09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892294799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3892294799
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.419761567
Short name T482
Test name
Test status
Simulation time 53302212 ps
CPU time 2.86 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 207012 kb
Host smart-285ba27c-1e02-4a76-af04-fd0bbbe44972
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419761567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.419761567
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4097243557
Short name T442
Test name
Test status
Simulation time 196123689 ps
CPU time 4.53 seconds
Started Jun 26 05:54:12 PM PDT 24
Finished Jun 26 05:54:18 PM PDT 24
Peak memory 208436 kb
Host smart-150cb3d6-97f9-445a-9e37-d66e1b86d102
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097243557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4097243557
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2971644524
Short name T845
Test name
Test status
Simulation time 235547124 ps
CPU time 2.52 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 208104 kb
Host smart-dc779a01-0206-49b5-9aaf-c30bb7eeba33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971644524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2971644524
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.880745001
Short name T684
Test name
Test status
Simulation time 79351635 ps
CPU time 1.85 seconds
Started Jun 26 05:54:16 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 208416 kb
Host smart-18177474-2d88-493d-bde1-4c26eb2bb60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880745001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.880745001
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1158243680
Short name T255
Test name
Test status
Simulation time 1040413506 ps
CPU time 39.37 seconds
Started Jun 26 05:54:19 PM PDT 24
Finished Jun 26 05:54:59 PM PDT 24
Peak memory 216912 kb
Host smart-3c89451b-8a6e-4edb-856b-5543e7c9f313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158243680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1158243680
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3026751637
Short name T917
Test name
Test status
Simulation time 1855006976 ps
CPU time 50 seconds
Started Jun 26 05:54:11 PM PDT 24
Finished Jun 26 05:55:02 PM PDT 24
Peak memory 219812 kb
Host smart-f333e8ee-a91a-40ba-93ca-177da67974e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026751637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3026751637
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1383831836
Short name T765
Test name
Test status
Simulation time 2974262165 ps
CPU time 27.42 seconds
Started Jun 26 05:54:15 PM PDT 24
Finished Jun 26 05:54:44 PM PDT 24
Peak memory 211288 kb
Host smart-10d24fb7-b417-4598-b8f5-76c5520e9a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383831836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1383831836
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.38050795
Short name T693
Test name
Test status
Simulation time 12612634 ps
CPU time 0.76 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:23 PM PDT 24
Peak memory 206072 kb
Host smart-e3a7b5dc-c84f-40c4-95da-5b94e650e6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.38050795
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.256671814
Short name T304
Test name
Test status
Simulation time 517757357 ps
CPU time 7.6 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:30 PM PDT 24
Peak memory 215420 kb
Host smart-7ff5268f-308e-407e-85af-375310a3c0aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256671814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.256671814
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2555555555
Short name T663
Test name
Test status
Simulation time 97428547 ps
CPU time 3.78 seconds
Started Jun 26 05:54:18 PM PDT 24
Finished Jun 26 05:54:23 PM PDT 24
Peak memory 208920 kb
Host smart-7d873236-7018-4905-b819-f40bfa686145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555555555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2555555555
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.329906892
Short name T24
Test name
Test status
Simulation time 1423683789 ps
CPU time 23.05 seconds
Started Jun 26 05:54:22 PM PDT 24
Finished Jun 26 05:54:46 PM PDT 24
Peak memory 214324 kb
Host smart-531a4044-81d3-4a10-88db-cd9e8f879477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329906892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.329906892
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3047547209
Short name T265
Test name
Test status
Simulation time 34473818 ps
CPU time 2.12 seconds
Started Jun 26 05:54:23 PM PDT 24
Finished Jun 26 05:54:27 PM PDT 24
Peak memory 214368 kb
Host smart-a9bc34e5-d2ce-4555-9927-129f334861d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047547209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3047547209
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1761259852
Short name T63
Test name
Test status
Simulation time 102847141 ps
CPU time 4.75 seconds
Started Jun 26 05:54:15 PM PDT 24
Finished Jun 26 05:54:22 PM PDT 24
Peak memory 210176 kb
Host smart-9f12d77f-2e4b-427b-9ad3-977bd9b5d5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761259852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1761259852
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1508439580
Short name T528
Test name
Test status
Simulation time 130740434 ps
CPU time 4.81 seconds
Started Jun 26 05:54:13 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 207484 kb
Host smart-2cfd2b5a-c3eb-49bd-b51f-7ee1ee424d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508439580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1508439580
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2564612660
Short name T599
Test name
Test status
Simulation time 76172208 ps
CPU time 3.42 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:26 PM PDT 24
Peak memory 208416 kb
Host smart-13c4b5aa-7834-4df2-a3e4-5b8ae8675d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564612660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2564612660
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4094657800
Short name T832
Test name
Test status
Simulation time 1653210671 ps
CPU time 5.08 seconds
Started Jun 26 05:54:14 PM PDT 24
Finished Jun 26 05:54:21 PM PDT 24
Peak memory 209180 kb
Host smart-b5900e06-2df4-40d9-8160-717a8d6beafb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094657800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4094657800
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2382698153
Short name T135
Test name
Test status
Simulation time 58054846 ps
CPU time 2.81 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:25 PM PDT 24
Peak memory 208244 kb
Host smart-9e793944-5bf1-4554-8735-bcf8bb7db512
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382698153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2382698153
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.155336944
Short name T608
Test name
Test status
Simulation time 148740181 ps
CPU time 3.61 seconds
Started Jun 26 05:54:16 PM PDT 24
Finished Jun 26 05:54:21 PM PDT 24
Peak memory 208704 kb
Host smart-b402f961-5c9c-40ec-8ab9-43d0657600de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155336944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.155336944
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3503252946
Short name T316
Test name
Test status
Simulation time 52128216 ps
CPU time 1.39 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:23 PM PDT 24
Peak memory 206804 kb
Host smart-adde60a6-fd6b-4333-8416-54e47f155c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503252946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3503252946
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4125538211
Short name T794
Test name
Test status
Simulation time 100008808 ps
CPU time 2.78 seconds
Started Jun 26 05:54:15 PM PDT 24
Finished Jun 26 05:54:19 PM PDT 24
Peak memory 206608 kb
Host smart-da09157d-7922-4d92-b8f5-5b4e1e0b0a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125538211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4125538211
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2860030804
Short name T236
Test name
Test status
Simulation time 739902075 ps
CPU time 10.61 seconds
Started Jun 26 05:54:22 PM PDT 24
Finished Jun 26 05:54:34 PM PDT 24
Peak memory 215840 kb
Host smart-2c06edb5-9716-488d-bb70-f52db6b3ea8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860030804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2860030804
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1591453369
Short name T285
Test name
Test status
Simulation time 62147360 ps
CPU time 3.78 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:26 PM PDT 24
Peak memory 208140 kb
Host smart-e1fb311d-f1d2-45c9-ae87-e21ba970123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591453369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1591453369
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4168864964
Short name T725
Test name
Test status
Simulation time 141609902 ps
CPU time 1.78 seconds
Started Jun 26 05:54:20 PM PDT 24
Finished Jun 26 05:54:22 PM PDT 24
Peak memory 210064 kb
Host smart-3130ae4c-45bf-4101-a5fe-eef7b02367f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168864964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4168864964
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3975266177
Short name T458
Test name
Test status
Simulation time 60167923 ps
CPU time 0.99 seconds
Started Jun 26 05:54:32 PM PDT 24
Finished Jun 26 05:54:34 PM PDT 24
Peak memory 206148 kb
Host smart-bb5851e0-999b-4fed-a41b-870f748e2d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975266177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3975266177
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.821157441
Short name T674
Test name
Test status
Simulation time 229264089 ps
CPU time 2.31 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:25 PM PDT 24
Peak memory 218672 kb
Host smart-12e8d533-1cdb-4e84-91ed-0c3bd45f72e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821157441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.821157441
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3072215203
Short name T45
Test name
Test status
Simulation time 32683980 ps
CPU time 2.14 seconds
Started Jun 26 05:54:25 PM PDT 24
Finished Jun 26 05:54:29 PM PDT 24
Peak memory 214228 kb
Host smart-c96d0891-bb92-4e5d-8baa-05fc3645f018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072215203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3072215203
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3641989151
Short name T98
Test name
Test status
Simulation time 2501932011 ps
CPU time 69.42 seconds
Started Jun 26 05:54:20 PM PDT 24
Finished Jun 26 05:55:30 PM PDT 24
Peak memory 222572 kb
Host smart-35a3b526-bb11-48bf-9662-bf5a0bb67d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641989151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3641989151
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3564501747
Short name T542
Test name
Test status
Simulation time 159168622 ps
CPU time 2.38 seconds
Started Jun 26 05:54:20 PM PDT 24
Finished Jun 26 05:54:24 PM PDT 24
Peak memory 214276 kb
Host smart-cc5c6f5c-e416-4296-91af-9f98318dc2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564501747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3564501747
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.249989672
Short name T328
Test name
Test status
Simulation time 35950566 ps
CPU time 2.54 seconds
Started Jun 26 05:54:22 PM PDT 24
Finished Jun 26 05:54:26 PM PDT 24
Peak memory 208580 kb
Host smart-4ac7c85a-d9e7-49de-b56b-b55bb4fb0dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249989672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.249989672
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2448563723
Short name T841
Test name
Test status
Simulation time 59604473 ps
CPU time 3.15 seconds
Started Jun 26 05:54:22 PM PDT 24
Finished Jun 26 05:54:27 PM PDT 24
Peak memory 209220 kb
Host smart-9ceccbb4-3f5d-4256-846d-b6918f009930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448563723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2448563723
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.123111800
Short name T440
Test name
Test status
Simulation time 635768977 ps
CPU time 7.43 seconds
Started Jun 26 05:54:23 PM PDT 24
Finished Jun 26 05:54:31 PM PDT 24
Peak memory 207876 kb
Host smart-9c8b6e11-285d-4c43-b960-afcbeee8ac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123111800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.123111800
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4281442093
Short name T767
Test name
Test status
Simulation time 103363191 ps
CPU time 2.27 seconds
Started Jun 26 05:54:23 PM PDT 24
Finished Jun 26 05:54:27 PM PDT 24
Peak memory 208784 kb
Host smart-49d9d6e4-1fca-4c97-88f3-783f914646b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281442093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4281442093
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2843320749
Short name T273
Test name
Test status
Simulation time 454705672 ps
CPU time 3.53 seconds
Started Jun 26 05:54:20 PM PDT 24
Finished Jun 26 05:54:25 PM PDT 24
Peak memory 208924 kb
Host smart-8eb4f4c4-2161-4756-bb63-a4e249520f52
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843320749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2843320749
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2281385177
Short name T196
Test name
Test status
Simulation time 144922443 ps
CPU time 4.04 seconds
Started Jun 26 05:54:21 PM PDT 24
Finished Jun 26 05:54:27 PM PDT 24
Peak memory 207036 kb
Host smart-235cf2f7-e548-4b0a-9ffb-370bd32d2031
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281385177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2281385177
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.299588050
Short name T904
Test name
Test status
Simulation time 874077387 ps
CPU time 15.86 seconds
Started Jun 26 05:54:28 PM PDT 24
Finished Jun 26 05:54:45 PM PDT 24
Peak memory 214352 kb
Host smart-5033d93b-83f2-4843-b779-d713a6e5d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299588050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.299588050
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1252109722
Short name T436
Test name
Test status
Simulation time 462479651 ps
CPU time 2.35 seconds
Started Jun 26 05:54:22 PM PDT 24
Finished Jun 26 05:54:26 PM PDT 24
Peak memory 206872 kb
Host smart-2a182a4c-bde2-49a2-a4f6-e6f0a2f6d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252109722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1252109722
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1980454722
Short name T319
Test name
Test status
Simulation time 875870898 ps
CPU time 24.86 seconds
Started Jun 26 05:54:28 PM PDT 24
Finished Jun 26 05:54:55 PM PDT 24
Peak memory 216456 kb
Host smart-24525b88-13a3-4b2c-84b7-0e9b5bf04d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980454722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1980454722
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1070497038
Short name T218
Test name
Test status
Simulation time 663579312 ps
CPU time 12.58 seconds
Started Jun 26 05:54:33 PM PDT 24
Finished Jun 26 05:54:47 PM PDT 24
Peak memory 222600 kb
Host smart-024a068c-70b1-48aa-ae6c-351a3a2defd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070497038 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1070497038
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3857445297
Short name T861
Test name
Test status
Simulation time 1037265946 ps
CPU time 7.49 seconds
Started Jun 26 05:54:22 PM PDT 24
Finished Jun 26 05:54:31 PM PDT 24
Peak memory 210536 kb
Host smart-f20c06cf-6f85-4195-9d04-b935b0b51152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857445297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3857445297
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3326895248
Short name T456
Test name
Test status
Simulation time 75305537 ps
CPU time 3.06 seconds
Started Jun 26 05:54:33 PM PDT 24
Finished Jun 26 05:54:37 PM PDT 24
Peak memory 209744 kb
Host smart-e4a482b8-de34-4e7f-8002-5f8d0af06cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326895248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3326895248
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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