Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
68.25	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	19	30	61.22

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	18	17	48.57	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	58	1			T33	1		T19	1		T43	1
auto[OpGenId]	14	1			T69	1		T215	1		T8	1
auto[OpGenSwOut]	14	1			T50	1		T53	1		T74	1
auto[OpGenHwOut]	19	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1726	1			T42	2		T10	180		T5	1
auto[StInit]	87	1			T33	1		T42	1		T49	1
auto[StCreatorRootKey]	60	1			T33	1		T35	1		T53	1
auto[StOwnerIntKey]	35	1			T1	1		T14	1		T42	1
auto[StOwnerKey]	34	1			T63	1		T66	1		T64	1
auto[StDisabled]	366	1			T33	3		T19	1		T42	6
auto[StInvalid]	50	1			T13	1		T34	1		T51	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3338

1

T1

2

T2

1

T3

1

auto[1]

105

1

T33

1

T19

1

T43

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1716	1			T42	2		T10	180		T5	1
auto[StReset]	auto[1]	10	1			T22	1		T216	1		T217	1
auto[StInit]	auto[0]	41	1			T33	1		T42	1		T49	1
auto[StInit]	auto[1]	46	1			T43	1		T29	1		T50	1
auto[StCreatorRootKey]	auto[0]	37	1			T57	1		T54	1		T190	1
auto[StCreatorRootKey]	auto[1]	23	1			T33	1		T35	1		T53	1
auto[StOwnerIntKey]	auto[0]	27	1			T1	1		T14	1		T42	1
auto[StOwnerIntKey]	auto[1]	8	1			T5	1		T61	1		T62	1
auto[StOwnerKey]	auto[0]	32	1			T63	1		T66	1		T64	1
auto[StOwnerKey]	auto[1]	2	1			T218	1		T146	1		-	-
auto[StDisabled]	auto[0]	350	1			T33	3		T42	6		T50	4
auto[StDisabled]	auto[1]	16	1			T19	1		T69	1		T215	1
auto[StInvalid]	auto[0]	50	1			T13	1		T34	1		T51	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	18	17	48.57	18

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	10	1			T22	1		T216	1		T217	1
auto[StInit]	auto[OpAdvance]	26	1			T43	1		T29	1		T5	1
auto[StInit]	auto[OpGenId]	5	1			T8	1		T47	1		T219	1
auto[StInit]	auto[OpGenSwOut]	7	1			T50	1		T53	1		T220	1
auto[StInit]	auto[OpGenHwOut]	8	1			T6	1		T221	1		T222	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T33	1		T35	1		T53	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T223	1		T224	1		T225	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T74	1		T217	1		T226	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T7	1		T227	1		T228	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T61	1		T217	1		T229	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T62	1		T230	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T5	1		T47	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	2	1			T218	1		T146	1		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T19	1		T231	1		T232	1
auto[StDisabled]	auto[OpGenId]	6	1			T69	1		T215	1		T233	1
auto[StDisabled]	auto[OpGenSwOut]	1	1			T7	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	4	1			T234	1		T235	1		T236	1