Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	72	258	78.18

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	53	227	81.07	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4426

1

T2

8

T13

5

T4

6

auto[1]

521

1

T16

1

T18

1

T33

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4426

1

T2

8

T13

5

T4

6

auto[1]

521

1

T16

1

T18

1

T33

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4344

1

T2

8

T13

5

T4

6

auto[1]

603

1

T33

1

T41

2

T42

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4344

1

T2

8

T13

5

T4

6

auto[1]

603

1

T33

1

T41

2

T42

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	400	1			T18	2		T27	3		T86	3
auto[OpGenId]	1025	1			T13	1		T4	1		T15	1
auto[OpGenSwOut]	987	1			T13	2		T4	2		T15	1
auto[OpGenHwOut]	2478	1			T2	8		T13	2		T4	3
auto[OpDisable]	57	1			T33	1		T42	1		T5	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	400	1			T18	2		T27	3		T86	3
auto[OpGenId]	1025	1			T13	1		T4	1		T15	1
auto[OpGenSwOut]	987	1			T13	2		T4	2		T15	1
auto[OpGenHwOut]	2478	1			T2	8		T13	2		T4	3
auto[OpDisable]	57	1			T33	1		T42	1		T5	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4388

1

T2

5

T13

5

T4

4

auto[1]

559

1

T2

3

T4

2

T18

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4388

1

T2

5

T13

5

T4

4

auto[1]

559

1

T2

3

T4

2

T18

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4654

1

T2

8

T13

5

T4

6

auto[1]

293

1

T86

7

T117

9

T41

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1759	1			T2	1		T13	3		T4	1
auto[1]	641	1			T2	2		T13	1		T15	1
auto[2]	622	1			T2	1		T4	2		T15	1
auto[3]	668	1			T13	1		T4	1		T15	1
auto[4]	333	1			T16	1		T86	2		T51	1
auto[5]	309	1			T2	1		T15	1		T16	1
auto[6]	317	1			T2	2		T18	1		T33	1
auto[7]	298	1			T2	1		T4	2		T33	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1257	1			T2	4		T4	2		T15	1
clear_one[1]	641	1			T2	2		T13	1		T15	1
clear_one[2]	622	1			T2	1		T4	2		T15	1
clear_one[3]	668	1			T13	1		T4	1		T15	1
clear_none	1759	1			T2	1		T13	3		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	869	1			T13	3		T18	2		T27	1
auto[StInit]	573	1			T2	1		T4	1		T16	1
auto[StCreatorRootKey]	516	1			T2	1		T4	1		T16	1
auto[StOwnerIntKey]	477	1			T2	1		T4	1		T18	1
auto[StOwnerKey]	447	1			T2	1		T4	1		T16	1
auto[StDisabled]	1768	1			T2	4		T4	2		T16	3
auto[StInvalid]	297	1			T13	2		T15	5		T34	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	869	1			T13	3		T18	2		T27	1
auto[StInit]	573	1			T2	1		T4	1		T16	1
auto[StCreatorRootKey]	516	1			T2	1		T4	1		T16	1
auto[StOwnerIntKey]	477	1			T2	1		T4	1		T18	1
auto[StOwnerKey]	447	1			T2	1		T4	1		T16	1
auto[StDisabled]	1768	1			T2	4		T4	2		T16	3
auto[StInvalid]	297	1			T13	2		T15	5		T34	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	53	227	81.07	53

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2] - auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[4] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[4] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[4] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T117	1		T238	1		T239	1
auto[0]	auto[StReset]	auto[OpGenId]	159	1			T18	1		T44	1		T45	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	148	1			T13	1		T27	1		T33	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	220	1			T13	2		T33	1		T34	1
auto[0]	auto[StInit]	auto[OpAdvance]	41	1			T117	1		T83	1		T30	1
auto[0]	auto[StInit]	auto[OpGenId]	49	1			T41	1		T42	1		T140	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	88	1			T4	1		T202	1		T43	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	204	1			T2	1		T16	1		T33	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T117	2		T208	1		T110	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	51	1			T140	1		T5	1		T184	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	35	1			T5	1		T106	1		T57	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	85	1			T33	1		T117	1		T19	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T141	1		T240	1		T241	3
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	24	1			T117	2		T203	1		T140	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T205	1		T106	1		T213	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	73	1			T86	4		T206	1		T42	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T202	1		T5	1		T242	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T140	1		T74	1		T243	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T16	1		T204	1		T5	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T42	1		T211	1		T195	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	21	1			T18	1		T140	2		T5	1
auto[0]	auto[StDisabled]	auto[OpGenId]	54	1			T16	1		T140	2		T50	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T206	1		T140	1		T5	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	169	1			T85	1		T209	1		T140	2
auto[0]	auto[StDisabled]	auto[OpDisable]	14	1			T53	1		T57	1		T244	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T34	1		T51	1		T38	1
auto[0]	auto[StInvalid]	auto[OpGenId]	26	1			T79	1		T245	1		T246	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T15	1		T51	2		T90	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	25	1			T45	1		T87	1		T247	1
auto[1]	auto[StReset]	auto[OpGenId]	13	1			T33	1		T248	1		T249	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	24	1			T50	1		T5	1		T201	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	32	1			T212	1		T250	1		T251	1
auto[1]	auto[StInit]	auto[OpAdvance]	2	1			T41	1		T252	1		-	-
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T249	1		T253	1		T94	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T42	1		T5	1		T53	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T74	1		T254	1		T255	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T27	1		T41	1		T256	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T16	1		T107	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T42	1		T248	1		T258	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T210	1		T209	1		T63	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T27	1		T259	1		T217	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T41	1		T196	1		T248	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T212	1		T258	1		T260	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T18	1		T85	1		T58	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T261	1		T262	1		T46	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T53	1		T213	1		T263	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T200	1		T264	1		T217	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T207	1		T209	1		T141	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	23	1			T203	1		T140	1		T5	1
auto[1]	auto[StDisabled]	auto[OpGenId]	61	1			T44	1		T110	1		T5	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T202	1		T5	2		T193	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T2	2		T33	1		T85	1
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T42	1		T58	1		T265	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	2	1			T87	1		T266	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	15	1			T90	1		T267	1		T268	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T13	1		T51	2		T83	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T15	1		T45	1		T269	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T86	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	13	1			T18	1		T42	2		T262	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	19	1			T53	1		T251	1		T68	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	28	1			T211	1		T5	1		T192	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T53	1		T99	1		T235	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T86	1		T183	1		T270	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	5	1			T67	1		T217	1		T271	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	15	1			T33	1		T50	1		T192	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T18	1		T272	1		T273	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T42	1		T5	1		T274	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T53	1		T265	1		T46	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T2	1		T109	1		T192	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T213	1		T248	1		T275	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T33	1		T249	1		T276	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T42	1		T277	1		T278	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	30	1			T209	1		T108	1		T192	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T279	1		T280	1		T281	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T249	1		T282	1		T124	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T5	1		T283	1		T284	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T4	1		T19	1		T194	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T117	1		T285	1		T286	3
auto[2]	auto[StDisabled]	auto[OpGenId]	64	1			T117	2		T107	2		T5	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T117	1		T53	1		T287	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T4	1		T85	1		T206	1
auto[2]	auto[StDisabled]	auto[OpDisable]	5	1			T249	1		T288	1		T289	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T55	1		T290	1		T291	1
auto[2]	auto[StInvalid]	auto[OpGenId]	16	1			T15	1		T79	1		T91	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T38	1		T267	1		T268	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T34	1		T87	1		T88	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T286	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T145	1		T292	1		T293	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	14	1			T52	1		T5	1		T294	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	42	1			T34	1		T5	1		T35	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T263	1		T101	1		T295	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T263	1		T103	1		T296	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T68	1		T215	1		T21	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	14	1			T5	1		T122	1		T297	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T298	1		T299	1		T300	3
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T57	1		T190	1		T284	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T122	1		T301	1		T302	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T85	1		T294	1		T200	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T19	1		T110	1		T262	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T202	1		T303	1		T298	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T53	1		T61	1		T304	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T4	1		T44	1		T210	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T27	1		T50	1		T298	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	9	1			T110	2		T213	1		T46	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T33	1		T42	1		T74	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T213	2		T201	1		T305	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	30	1			T208	1		T202	1		T50	1
auto[3]	auto[StDisabled]	auto[OpGenId]	49	1			T27	1		T33	1		T41	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T204	1		T140	1		T110	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T18	1		T41	1		T209	1
auto[3]	auto[StDisabled]	auto[OpDisable]	7	1			T71	1		T74	1		T76	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T90	2		T290	1		T306	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T13	1		T83	1		T214	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T247	1		T307	1		T308	2
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T15	1		T187	1		T83	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T45	1		T5	1		T217	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T50	1		T35	1		T263	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	17	1			T50	1		T294	1		T250	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T101	1		T97	1		T309	1
auto[4]	auto[StInit]	auto[OpGenId]	8	1			T42	1		T283	1		T217	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T213	1		T123	1		T281	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T63	1		T310	1		T256	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T86	1		T207	1		T311	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T205	1		T312	1		T313	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T53	1		T217	1		T314	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T194	1		T250	1		T213	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T229	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T5	1		T315	1		T21	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T110	1		T61	1		T316	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T42	1		T197	1		T213	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T317	1		T318	1		T319	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T86	1		T5	2		T191	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T182	1		T215	1		T320	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T109	1		T321	1		T322	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T283	1		T263	2		T242	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T207	1		T202	1		T50	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T16	1		T196	1		T213	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T109	1		T50	1		T5	3
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T281	1		T323	1		T324	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T45	1		T325	1		T326	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T246	1		T89	1		T327	2
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T51	1		T245	1		T328	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T245	1		T246	1		T308	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T44	1		T213	1		T283	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T213	2		T246	1		T329	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	11	1			T310	1		T61	1		T321	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T292	1		T330	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T227	1		T331	1		T332	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	2	1			T284	1		T230	1		-	-
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T5	1		T333	1		T334	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T229	1		T335	1		T336	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T97	1		T146	1		T252	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T58	1		T196	1		T337	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T338	1		T339	1		T217	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T330	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T340	1		T292	1		T228	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T341	1		T292	1		T178	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T5	1		T195	1		T200	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T342	1		T343	1		T344	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T196	1		T69	1		T61	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T345	1		T346	1		T217	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T41	1		T192	1		T347	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T86	1		T74	1		T7	1
auto[5]	auto[StDisabled]	auto[OpGenId]	21	1			T16	1		T213	1		T61	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T33	1		T42	1		T107	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T2	1		T85	1		T86	3
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T5	1		T73	1		T348	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T269	1		T349	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T350	1		T351	1		T352	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T268	1		T353	1		T354	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T15	1		T79	1		T268	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T294	1		T251	1		T274	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T213	1		T355	1		T356	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T49	1		T310	1		T261	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T92	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T248	2		T7	1		T357	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T233	1		T237	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T248	3		T358	1		T359	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T318	1		T125	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T5	1		T360	1		T361	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T299	1		T362	1		T363	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T5	1		T53	1		T310	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T364	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T57	1		T283	1		T264	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T42	1		T365	1		T281	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T2	1		T33	1		T366	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T367	1		T368	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T208	1		T122	1		T102	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T124	1		T369	1		T370	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T2	1		T85	1		T310	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T95	1		T292	1		T241	2
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T18	1		T206	1		T207	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T41	1		T213	2		T283	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T210	1		T211	2		T108	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T46	1		T309	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T371	1		T372	1		T373	1
auto[6]	auto[StInvalid]	auto[OpGenId]	2	1			T87	1		T374	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T87	1		T375	2		T376	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T51	1		T377	1		T378	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T42	1		T183	1		T257	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T34	1		T53	1		T228	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	13	1			T192	1		T61	1		T254	1
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T379	1		T223	1		T380	2
auto[7]	auto[StInit]	auto[OpGenId]	2	1			T53	1		T380	1		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T42	1		T50	1		T213	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T197	1		T7	1		T339	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T257	1		T381	1		T382	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T213	1		T383	1		T384	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T4	1		T385	1		T386	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T211	1		T36	1		T387	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T5	1		T388	1		T47	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T50	1		T217	1		T363	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T5	1		T68	1		T320	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T185	1		T80	1		T305	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T217	1		T389	1		T390	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T42	1		T316	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T33	1		T5	1		T47	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T210	1		T203	1		T108	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T248	1		T257	2		T392	2
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T4	1		T205	1		T5	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	13	1			T19	1		T213	1		T248	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T2	1		T86	1		T209	1
auto[7]	auto[StDisabled]	auto[OpDisable]	10	1			T33	1		T231	1		T292	2
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T187	1		T245	1		T354	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T38	1		T393	1		T394	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T83	1		T246	1		T267	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T52	1		T187	1		T247	2

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1257

1

T2

4

T4

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[0]

361

1

T13

1

T15

1

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

111

1

T2

2

T18

1

T85

2

clear_one[1]

auto[0]

auto[1]

auto[0]

131

1

T33

1

T41

2

T210

3

clear_one[1]

auto[0]

auto[1]

auto[1]

38

1

T42

1

T140

1

T141

2

clear_one[2]

auto[0]

auto[0]

auto[0]

340

1

T15

1

T18

2

T33

2

clear_one[2]

auto[0]

auto[0]

auto[1]

133

1

T2

1

T4

2

T85

1

clear_one[2]

auto[1]

auto[0]

auto[0]

108

1

T19

1

T209

2

T108

2

clear_one[2]

auto[1]

auto[0]

auto[1]

41

1

T117

4

T206

1

T24

1

clear_one[3]

auto[0]

auto[0]

auto[0]

366

1

T13

1

T4

1

T15

1

clear_one[3]

auto[0]

auto[1]

auto[0]

143

1

T210

1

T211

1

T141

1

clear_one[3]

auto[1]

auto[0]

auto[0]

115

1

T18

1

T19

1

T41

1

clear_one[3]

auto[1]

auto[1]

auto[0]

44

1

T140

1

T294

1

T57

1

clear_none

auto[0]

auto[0]

auto[0]

1225

1

T2

1

T13

3

T4

1

clear_none

auto[0]

auto[0]

auto[1]

135

1

T18

1

T85

1

T42

1

clear_none

auto[0]

auto[1]

auto[0]

145

1

T42

1

T211

2

T194

2

clear_none

auto[0]

auto[1]

auto[1]

41

1

T140

4

T141

1

T57

1

clear_none

auto[1]

auto[0]

auto[0]

123

1

T16

1

T33

1

T19

1

clear_none

auto[1]

auto[0]

auto[1]

29

1

T206

2

T5

1

T57

1

clear_none

auto[1]

auto[1]

auto[0]

30

1

T106

1

T57

1

T213

1

clear_none

auto[1]

auto[1]

auto[1]

31

1

T140

5

T184

3

T294

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1190	1			T2	4		T4	2		T15	1
clear_all	auto[1]	67	1			T86	3		T248	6		T263	4
clear_one[1]	auto[0]	611	1			T2	2		T13	1		T15	1
clear_one[1]	auto[1]	30	1			T41	2		T141	1		T248	4
clear_one[2]	auto[0]	581	1			T2	1		T4	2		T15	1
clear_one[2]	auto[1]	41	1			T86	1		T117	3		T248	2
clear_one[3]	auto[0]	612	1			T13	1		T4	1		T15	1
clear_one[3]	auto[1]	56	1			T41	2		T140	1		T110	3
clear_none	auto[0]	1660	1			T2	1		T13	3		T4	1
clear_none	auto[1]	99	1			T86	3		T117	6		T140	10