Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10011

1

T1

6

T2

7

T3

8

auto[Attestation]

6783

1

T1

5

T2

1

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2362	1			T1	2		T3	2		T13	1
auto[Aes]	3128	1			T1	2		T3	1		T13	2
auto[Kmac]	3015	1			T1	1		T3	3		T13	1
auto[Otbn]	3061	1			T1	2		T2	8		T13	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	6979	1			T1	3		T2	8		T3	8
auto[OpGenId]	5228	1			T1	4		T3	7		T13	2
auto[OpGenSwOut]	5149	1			T1	3		T3	6		T13	7
auto[OpGenHwOut]	6417	1			T1	4		T2	8		T13	3
auto[OpDisable]	127	1			T33	1		T44	1		T42	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9719

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

14181

1

T1

6

T2

8

T3

13

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5674	1			T1	3		T2	1		T3	6
auto[StInit]	3441	1			T1	5		T2	2		T3	2
auto[StCreatorRootKey]	2901	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2520	1			T1	4		T2	2		T3	2
auto[StOwnerKey]	2255	1			T2	2		T3	2		T4	2
auto[StDisabled]	7109	1			T2	7		T3	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	281	1			T13	1		T27	1		T33	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	84	1			T4	1		T27	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T33	1		T126	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T86	1		T117	1		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T53	1		T200	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	200	1			T117	1		T126	1		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	312	1			T13	1		T18	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	83	1			T3	1		T42	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	93	1			T14	1		T33	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T14	1		T42	2		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	60	1			T16	1		T204	1		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	188	1			T16	1		T17	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	287	1			T3	2		T18	1		T86	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	99	1			T127	1		T5	2		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	65	1			T14	1		T19	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	53	1			T204	1		T50	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	58	1			T3	1		T17	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	200	1			T16	1		T127	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	301	1			T13	5		T18	2		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	90	1			T27	1		T42	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	65	1			T33	1		T5	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T117	1		T42	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	52	1			T126	1		T203	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	168	1			T16	1		T17	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	41	1			T33	1		T42	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	102	1			T1	1		T16	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	61	1			T50	1		T196	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T3	1		T42	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	35	1			T33	1		T206	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T3	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	58	1			T33	2		T5	2		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	82	1			T50	1		T5	3		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	78	1			T33	1		T117	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	54	1			T1	1		T17	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	46	1			T19	1		T41	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	184	1			T19	1		T204	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T33	4		T42	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	88	1			T33	1		T42	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T4	1		T17	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T16	1		T5	2		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	62	1			T33	1		T193	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	177	1			T33	1		T204	2		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	56	1			T5	5		T106	1		T53	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T1	1		T33	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	66	1			T33	1		T117	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	55	1			T50	1		T110	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T33	1		T140	1		T5	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	229	1			T16	1		T18	2		T86	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	250	1			T33	1		T86	1		T34	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	78	1			T117	1		T208	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T5	1		T184	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T14	1		T33	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	42	1			T19	1		T41	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	165	1			T117	1		T205	2		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	456	1			T13	1		T18	2		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T1	1		T42	2		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	99	1			T19	1		T204	1		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	99	1			T204	1		T209	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T117	1		T19	1		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	274	1			T16	1		T18	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	402	1			T1	1		T13	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T33	1		T5	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T41	1		T42	2		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T33	1		T211	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	67	1			T207	1		T5	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	257	1			T16	1		T27	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	358	1			T1	1		T13	1		T33	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T2	1		T16	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T2	1		T42	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	106	1			T2	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	70	1			T2	1		T4	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	264	1			T2	3		T4	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	31	1			T212	2		T213	1		T214	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T51	1		T5	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T1	1		T117	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	52	1			T86	2		T193	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T204	1		T203	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	144	1			T18	1		T86	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	43	1			T50	1		T5	2		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T33	1		T205	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	92	1			T14	1		T33	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T18	2		T33	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T42	1		T209	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	256	1			T16	2		T41	1		T209	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	40	1			T42	2		T213	1		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	124	1			T42	1		T210	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T50	1		T5	2		T182	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T42	1		T210	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	84	1			T210	1		T211	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	252	1			T16	1		T33	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	42	1			T50	1		T5	1		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	105	1			T16	1		T85	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T85	1		T204	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T44	1		T63	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	78	1			T207	1		T5	2		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T2	1		T18	1		T27	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T33	1		T86	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	580	1			T13	1		T4	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T14	2		T16	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	601	1			T3	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	166	1			T3	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	596	1			T3	2		T16	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	172	1			T33	1		T117	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	570	1			T13	5		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	147	1			T3	1		T33	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	332	1			T1	1		T3	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	161	1			T1	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	341	1			T33	2		T19	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	185	1			T4	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	334	1			T16	1		T33	6		T204	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	170	1			T33	2		T117	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	410	1			T1	1		T16	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T14	1		T33	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	502	1			T33	1		T86	1		T34	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T117	1		T19	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	865	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	255	1			T33	1		T41	1		T42	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	787	1			T1	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T2	3		T4	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	760	1			T1	1		T2	4		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	160	1			T1	1		T86	2		T117	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	292	1			T18	1		T86	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	258	1			T14	1		T18	1		T33	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	435	1			T16	2		T18	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	257	1			T42	1		T210	2		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	435	1			T16	1		T33	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	275	1			T85	1		T44	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	425	1			T2	1		T16	1		T18	1