Unified Coverage Report :: Group Instance : attest_sw_binding

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29759

auto[1]

299

T86

T117

T41

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	29765	1		T1	15	T2	19	T3	26
auto[134217728:268435455]	14	1		T86	1	T298	1	T414	2
auto[268435456:402653183]	7	1		T117	1	T41	1	T415	1
auto[402653184:536870911]	7	1		T248	1	T414	1	T416	1
auto[536870912:671088639]	8	1		T140	1	T414	1	T241	1
auto[671088640:805306367]	11	1		T86	1	T41	1	T415	2
auto[805306368:939524095]	6	1		T117	1	T417	1	T241	1
auto[939524096:1073741823]	15	1		T86	1	T140	1	T248	1
auto[1073741824:1207959551]	9	1		T248	2	T418	1	T419	2
auto[1207959552:1342177279]	9	1		T110	1	T418	1	T420	1
auto[1342177280:1476395007]	9	1		T263	1	T415	1	T416	1
auto[1476395008:1610612735]	16	1		T86	1	T110	1	T286	2
auto[1610612736:1744830463]	7	1		T110	1	T415	2	T361	1
auto[1744830464:1879048191]	9	1		T86	1	T248	1	T361	1
auto[1879048192:2013265919]	5	1		T110	1	T141	1	T298	1
auto[2013265920:2147483647]	15	1		T248	1	T298	1	T415	2
auto[2147483648:2281701375]	10	1		T140	1	T110	1	T248	2
auto[2281701376:2415919103]	8	1		T238	1	T421	1	T422	1
auto[2415919104:2550136831]	10	1		T248	1	T286	1	T361	1
auto[2550136832:2684354559]	14	1		T117	1	T298	1	T414	1
auto[2684354560:2818572287]	4	1		T117	1	T317	1	T382	2
auto[2818572288:2952790015]	14	1		T86	2	T41	1	T414	1
auto[2952790016:3087007743]	12	1		T298	2	T415	1	T241	1
auto[3087007744:3221225471]	11	1		T298	1	T317	4	T414	1
auto[3221225472:3355443199]	7	1		T415	1	T318	1	T418	1
auto[3355443200:3489660927]	4	1		T415	1	T317	1	T420	1
auto[3489660928:3623878655]	8	1		T110	1	T416	1	T420	1
auto[3623878656:3758096383]	8	1		T141	1	T248	1	T286	1
auto[3758096384:3892314111]	12	1		T298	1	T418	1	T416	1
auto[3892314112:4026531839]	6	1		T263	1	T241	1	T421	1
auto[4026531840:4160749567]	9	1		T361	1	T418	1	T421	1
auto[4160749568:4294967295]	9	1		T298	1	T241	2	T318	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	29759	1		T1	15	T2	19	T3	26
auto[0:134217727]	auto[1]	6	1		T248	1	T414	1	T318	1
auto[134217728:268435455]	auto[1]	14	1		T86	1	T298	1	T414	2
auto[268435456:402653183]	auto[1]	7	1		T117	1	T41	1	T415	1
auto[402653184:536870911]	auto[1]	7	1		T248	1	T414	1	T416	1
auto[536870912:671088639]	auto[1]	8	1		T140	1	T414	1	T241	1
auto[671088640:805306367]	auto[1]	11	1		T86	1	T41	1	T415	2
auto[805306368:939524095]	auto[1]	6	1		T117	1	T417	1	T241	1
auto[939524096:1073741823]	auto[1]	15	1		T86	1	T140	1	T248	1
auto[1073741824:1207959551]	auto[1]	9	1		T248	2	T418	1	T419	2
auto[1207959552:1342177279]	auto[1]	9	1		T110	1	T418	1	T420	1
auto[1342177280:1476395007]	auto[1]	9	1		T263	1	T415	1	T416	1
auto[1476395008:1610612735]	auto[1]	16	1		T86	1	T110	1	T286	2
auto[1610612736:1744830463]	auto[1]	7	1		T110	1	T415	2	T361	1
auto[1744830464:1879048191]	auto[1]	9	1		T86	1	T248	1	T361	1
auto[1879048192:2013265919]	auto[1]	5	1		T110	1	T141	1	T298	1
auto[2013265920:2147483647]	auto[1]	15	1		T248	1	T298	1	T415	2
auto[2147483648:2281701375]	auto[1]	10	1		T140	1	T110	1	T248	2
auto[2281701376:2415919103]	auto[1]	8	1		T238	1	T421	1	T422	1
auto[2415919104:2550136831]	auto[1]	10	1		T248	1	T286	1	T361	1
auto[2550136832:2684354559]	auto[1]	14	1		T117	1	T298	1	T414	1
auto[2684354560:2818572287]	auto[1]	4	1		T117	1	T317	1	T382	2
auto[2818572288:2952790015]	auto[1]	14	1		T86	2	T41	1	T414	1
auto[2952790016:3087007743]	auto[1]	12	1		T298	2	T415	1	T241	1
auto[3087007744:3221225471]	auto[1]	11	1		T298	1	T317	4	T414	1
auto[3221225472:3355443199]	auto[1]	7	1		T415	1	T318	1	T418	1
auto[3355443200:3489660927]	auto[1]	4	1		T415	1	T317	1	T420	1
auto[3489660928:3623878655]	auto[1]	8	1		T110	1	T416	1	T420	1
auto[3623878656:3758096383]	auto[1]	8	1		T141	1	T248	1	T286	1
auto[3758096384:3892314111]	auto[1]	12	1		T298	1	T418	1	T416	1
auto[3892314112:4026531839]	auto[1]	6	1		T263	1	T241	1	T421	1
auto[4026531840:4160749567]	auto[1]	9	1		T361	1	T418	1	T421	1
auto[4160749568:4294967295]	auto[1]	9	1		T298	1	T241	2	T318	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1451

T13

T15

T16

auto[1]

1604

T13

T16

T18

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	86	1		T13	1	T18	1	T33	1
auto[134217728:268435455]	101	1		T51	1	T42	1	T29	1
auto[268435456:402653183]	90	1		T13	1	T34	1	T117	1
auto[402653184:536870911]	111	1		T13	2	T18	2	T34	2
auto[536870912:671088639]	99	1		T13	1	T15	1	T19	1
auto[671088640:805306367]	80	1		T34	1	T42	1	T49	1
auto[805306368:939524095]	94	1		T16	1	T86	1	T45	1
auto[939524096:1073741823]	96	1		T13	1	T42	1	T43	1
auto[1073741824:1207959551]	86	1		T33	1	T86	1	T51	1
auto[1207959552:1342177279]	107	1		T86	1	T34	1	T42	1
auto[1342177280:1476395007]	103	1		T16	1	T19	1	T42	1
auto[1476395008:1610612735]	79	1		T33	1	T90	1	T208	1
auto[1610612736:1744830463]	102	1		T204	1	T207	1	T202	1
auto[1744830464:1879048191]	107	1		T13	1	T33	2	T45	1
auto[1879048192:2013265919]	103	1		T27	1	T45	1	T63	1
auto[2013265920:2147483647]	78	1		T13	1	T34	1	T42	1
auto[2147483648:2281701375]	105	1		T42	1	T52	1	T49	1
auto[2281701376:2415919103]	79	1		T18	1	T33	1	T52	1
auto[2415919104:2550136831]	85	1		T42	1	T202	1	T5	2
auto[2550136832:2684354559]	78	1		T27	1	T19	1	T204	2
auto[2684354560:2818572287]	88	1		T16	1	T33	1	T51	1
auto[2818572288:2952790015]	105	1		T41	1	T43	2	T50	1
auto[2952790016:3087007743]	93	1		T15	1	T44	1	T42	1
auto[3087007744:3221225471]	102	1		T45	1	T207	1	T42	1
auto[3221225472:3355443199]	107	1		T15	1	T18	1	T27	2
auto[3355443200:3489660927]	108	1		T45	1	T90	2	T63	1
auto[3489660928:3623878655]	95	1		T13	1	T27	1	T33	1
auto[3623878656:3758096383]	98	1		T13	1	T15	1	T51	1
auto[3758096384:3892314111]	97	1		T18	1	T42	1	T90	1
auto[3892314112:4026531839]	88	1		T86	1	T117	1	T44	1
auto[4026531840:4160749567]	106	1		T13	1	T15	1	T204	1
auto[4160749568:4294967295]	99	1		T42	1	T49	1	T50	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	30	1		T13	1	T42	1	T52	1
auto[0:134217727]	auto[1]	56	1		T18	1	T33	1	T45	1
auto[134217728:268435455]	auto[0]	51	1		T51	1	T42	1	T38	1
auto[134217728:268435455]	auto[1]	50	1		T29	1	T110	1	T5	1
auto[268435456:402653183]	auto[0]	48	1		T117	1	T41	1	T49	1
auto[268435456:402653183]	auto[1]	42	1		T13	1	T34	1	T44	1
auto[402653184:536870911]	auto[0]	55	1		T13	1	T34	2	T51	1
auto[402653184:536870911]	auto[1]	56	1		T13	1	T18	2	T19	1
auto[536870912:671088639]	auto[0]	39	1		T13	1	T15	1	T52	1
auto[536870912:671088639]	auto[1]	60	1		T19	1	T63	1	T71	1
auto[671088640:805306367]	auto[0]	48	1		T34	1	T42	1	T49	1
auto[671088640:805306367]	auto[1]	32	1		T208	1	T183	1	T53	1
auto[805306368:939524095]	auto[0]	46	1		T45	1	T42	1	T5	2
auto[805306368:939524095]	auto[1]	48	1		T16	1	T86	1	T42	1
auto[939524096:1073741823]	auto[0]	43	1		T13	1	T50	2	T212	1
auto[939524096:1073741823]	auto[1]	53	1		T42	1	T43	1	T5	1
auto[1073741824:1207959551]	auto[0]	43	1		T90	1	T208	1	T202	1
auto[1073741824:1207959551]	auto[1]	43	1		T33	1	T86	1	T51	1
auto[1207959552:1342177279]	auto[0]	48	1		T34	1	T42	1	T5	1
auto[1207959552:1342177279]	auto[1]	59	1		T86	1	T208	1	T202	1
auto[1342177280:1476395007]	auto[0]	53	1		T16	1	T19	1	T42	1
auto[1342177280:1476395007]	auto[1]	50	1		T5	2	T196	1	T183	1
auto[1476395008:1610612735]	auto[0]	41	1		T5	2	T212	1	T68	1
auto[1476395008:1610612735]	auto[1]	38	1		T33	1	T90	1	T208	1
auto[1610612736:1744830463]	auto[0]	49	1		T207	1	T35	1	T294	1
auto[1610612736:1744830463]	auto[1]	53	1		T204	1	T202	1	T5	2
auto[1744830464:1879048191]	auto[0]	52	1		T13	1	T33	1	T41	1
auto[1744830464:1879048191]	auto[1]	55	1		T33	1	T45	1	T110	1
auto[1879048192:2013265919]	auto[0]	46	1		T5	1	T38	1	T53	1
auto[1879048192:2013265919]	auto[1]	57	1		T27	1	T45	1	T63	1
auto[2013265920:2147483647]	auto[0]	31	1		T42	1	T52	1	T50	1
auto[2013265920:2147483647]	auto[1]	47	1		T13	1	T34	1	T5	3
auto[2147483648:2281701375]	auto[0]	57	1		T49	1	T50	1	T5	2
auto[2147483648:2281701375]	auto[1]	48	1		T42	1	T52	1	T5	1
auto[2281701376:2415919103]	auto[0]	34	1		T49	1	T6	1	T24	1
auto[2281701376:2415919103]	auto[1]	45	1		T18	1	T33	1	T52	1
auto[2415919104:2550136831]	auto[0]	35	1		T42	1	T202	1	T5	2
auto[2415919104:2550136831]	auto[1]	50	1		T83	1	T212	1	T315	1
auto[2550136832:2684354559]	auto[0]	37	1		T19	1	T204	1	T42	1
auto[2550136832:2684354559]	auto[1]	41	1		T27	1	T204	1	T90	1
auto[2684354560:2818572287]	auto[0]	40	1		T16	1	T51	1	T204	1
auto[2684354560:2818572287]	auto[1]	48	1		T33	1	T41	1	T90	1
auto[2818572288:2952790015]	auto[0]	47	1		T43	2	T50	1	T5	2
auto[2818572288:2952790015]	auto[1]	58	1		T41	1	T5	3	T187	1
auto[2952790016:3087007743]	auto[0]	42	1		T15	1	T42	1	T53	1
auto[2952790016:3087007743]	auto[1]	51	1		T44	1	T49	1	T71	1
auto[3087007744:3221225471]	auto[0]	47	1		T45	1	T207	1	T49	1
auto[3087007744:3221225471]	auto[1]	55	1		T42	1	T110	1	T5	1
auto[3221225472:3355443199]	auto[0]	42	1		T15	1	T18	1	T49	2
auto[3221225472:3355443199]	auto[1]	65	1		T27	2	T33	1	T86	1
auto[3355443200:3489660927]	auto[0]	49	1		T90	2	T63	1	T5	2
auto[3355443200:3489660927]	auto[1]	59	1		T45	1	T196	1	T200	1
auto[3489660928:3623878655]	auto[0]	56	1		T13	1	T34	1	T5	3
auto[3489660928:3623878655]	auto[1]	39	1		T27	1	T33	1	T117	1
auto[3623878656:3758096383]	auto[0]	44	1		T15	1	T45	1	T49	1
auto[3623878656:3758096383]	auto[1]	54	1		T13	1	T51	1	T117	1
auto[3758096384:3892314111]	auto[0]	52	1		T18	1	T90	1	T49	1
auto[3758096384:3892314111]	auto[1]	45	1		T42	1	T5	1	T183	1
auto[3892314112:4026531839]	auto[0]	39	1		T117	1	T5	1	T141	1
auto[3892314112:4026531839]	auto[1]	49	1		T86	1	T44	1	T41	1
auto[4026531840:4160749567]	auto[0]	57	1		T15	1	T204	1	T196	1
auto[4026531840:4160749567]	auto[1]	49	1		T13	1	T42	1	T52	1
auto[4160749568:4294967295]	auto[0]	50	1		T49	1	T50	1	T79	1
auto[4160749568:4294967295]	auto[1]	49	1		T42	1	T106	1	T53	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1431

T13

T15

T16

auto[1]

1623

T13

T16

T18

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	98	1		T13	1	T49	1	T24	1
auto[134217728:268435455]	86	1		T27	1	T34	1	T42	1
auto[268435456:402653183]	93	1		T15	1	T33	1	T51	1
auto[402653184:536870911]	98	1		T34	1	T208	1	T202	1
auto[536870912:671088639]	105	1		T15	1	T44	1	T45	1
auto[671088640:805306367]	85	1		T45	1	T52	1	T50	1
auto[805306368:939524095]	94	1		T18	1	T207	1	T41	1
auto[939524096:1073741823]	98	1		T13	1	T27	1	T33	1
auto[1073741824:1207959551]	111	1		T51	1	T42	2	T63	1
auto[1207959552:1342177279]	98	1		T33	1	T44	1	T42	2
auto[1342177280:1476395007]	86	1		T18	1	T33	1	T45	2
auto[1476395008:1610612735]	97	1		T86	1	T34	1	T207	1
auto[1610612736:1744830463]	106	1		T51	1	T19	1	T41	2
auto[1744830464:1879048191]	91	1		T27	1	T33	1	T52	1
auto[1879048192:2013265919]	106	1		T13	1	T16	1	T86	2
auto[2013265920:2147483647]	97	1		T34	2	T49	1	T50	1
auto[2147483648:2281701375]	100	1		T13	2	T18	1	T33	1
auto[2281701376:2415919103]	96	1		T13	1	T42	1	T49	1
auto[2415919104:2550136831]	112	1		T13	1	T117	2	T45	1
auto[2550136832:2684354559]	82	1		T42	1	T90	1	T63	1
auto[2684354560:2818572287]	84	1		T13	1	T18	1	T42	1
auto[2818572288:2952790015]	91	1		T117	1	T204	1	T42	1
auto[2952790016:3087007743]	110	1		T13	1	T15	1	T27	1
auto[3087007744:3221225471]	83	1		T18	1	T34	1	T45	1
auto[3221225472:3355443199]	102	1		T16	1	T86	1	T117	1
auto[3355443200:3489660927]	82	1		T15	1	T204	1	T90	1
auto[3489660928:3623878655]	71	1		T15	1	T33	1	T51	1
auto[3623878656:3758096383]	97	1		T33	1	T86	1	T117	1
auto[3758096384:3892314111]	81	1		T13	1	T45	1	T41	1
auto[3892314112:4026531839]	111	1		T13	1	T16	1	T33	1
auto[4026531840:4160749567]	98	1		T45	1	T207	1	T42	1
auto[4160749568:4294967295]	105	1		T18	1	T27	1	T42	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	43	1		T49	1	T213	1	T257	1
auto[0:134217727]	auto[1]	55	1		T13	1	T24	1	T213	3
auto[134217728:268435455]	auto[0]	49	1		T34	1	T42	1	T90	1
auto[134217728:268435455]	auto[1]	37	1		T27	1	T203	1	T50	1
auto[268435456:402653183]	auto[0]	49	1		T15	1	T41	1	T53	1
auto[268435456:402653183]	auto[1]	44	1		T33	1	T51	1	T44	1
auto[402653184:536870911]	auto[0]	41	1		T34	1	T208	1	T202	1
auto[402653184:536870911]	auto[1]	57	1		T183	1	T214	1	T407	1
auto[536870912:671088639]	auto[0]	51	1		T15	1	T45	1	T43	1
auto[536870912:671088639]	auto[1]	54	1		T44	1	T204	1	T5	1
auto[671088640:805306367]	auto[0]	39	1		T45	1	T50	1	T5	1
auto[671088640:805306367]	auto[1]	46	1		T52	1	T196	1	T257	1
auto[805306368:939524095]	auto[0]	46	1		T18	1	T42	2	T43	1
auto[805306368:939524095]	auto[1]	48	1		T207	1	T41	1	T43	1
auto[939524096:1073741823]	auto[0]	44	1		T13	1	T33	1	T19	1
auto[939524096:1073741823]	auto[1]	54	1		T27	1	T41	1	T52	1
auto[1073741824:1207959551]	auto[0]	58	1		T51	1	T42	1	T53	1
auto[1073741824:1207959551]	auto[1]	53	1		T42	1	T63	1	T106	1
auto[1207959552:1342177279]	auto[0]	40	1		T90	1	T5	2	T38	1
auto[1207959552:1342177279]	auto[1]	58	1		T33	1	T44	1	T42	2
auto[1342177280:1476395007]	auto[0]	32	1		T36	1	T423	1	T7	1
auto[1342177280:1476395007]	auto[1]	54	1		T18	1	T33	1	T45	2
auto[1476395008:1610612735]	auto[0]	49	1		T207	1	T50	1	T196	1
auto[1476395008:1610612735]	auto[1]	48	1		T86	1	T34	1	T52	1
auto[1610612736:1744830463]	auto[0]	48	1		T208	1	T5	3	T53	3
auto[1610612736:1744830463]	auto[1]	58	1		T51	1	T19	1	T41	2
auto[1744830464:1879048191]	auto[0]	40	1		T43	1	T50	1	T79	1
auto[1744830464:1879048191]	auto[1]	51	1		T27	1	T33	1	T52	1
auto[1879048192:2013265919]	auto[0]	53	1		T13	1	T16	1	T51	1
auto[1879048192:2013265919]	auto[1]	53	1		T86	2	T90	1	T208	1
auto[2013265920:2147483647]	auto[0]	40	1		T34	1	T49	1	T50	1
auto[2013265920:2147483647]	auto[1]	57	1		T34	1	T5	2	T106	1
auto[2147483648:2281701375]	auto[0]	46	1		T13	1	T19	1	T204	1
auto[2147483648:2281701375]	auto[1]	54	1		T13	1	T18	1	T33	1
auto[2281701376:2415919103]	auto[0]	42	1		T13	1	T42	1	T49	1
auto[2281701376:2415919103]	auto[1]	54	1		T29	1	T5	1	T38	1
auto[2415919104:2550136831]	auto[0]	53	1		T13	1	T117	2	T5	1
auto[2415919104:2550136831]	auto[1]	59	1		T45	1	T42	1	T63	1
auto[2550136832:2684354559]	auto[0]	38	1		T90	1	T63	1	T50	1
auto[2550136832:2684354559]	auto[1]	44	1		T42	1	T141	1	T58	1
auto[2684354560:2818572287]	auto[0]	39	1		T18	1	T49	1	T203	1
auto[2684354560:2818572287]	auto[1]	45	1		T13	1	T42	1	T38	1
auto[2818572288:2952790015]	auto[0]	44	1		T49	1	T5	2	T53	2
auto[2818572288:2952790015]	auto[1]	47	1		T117	1	T204	1	T42	1
auto[2952790016:3087007743]	auto[0]	52	1		T15	1	T34	1	T204	1
auto[2952790016:3087007743]	auto[1]	58	1		T13	1	T27	1	T90	1
auto[3087007744:3221225471]	auto[0]	31	1		T34	1	T90	1	T49	1
auto[3087007744:3221225471]	auto[1]	52	1		T18	1	T45	1	T43	1
auto[3221225472:3355443199]	auto[0]	46	1		T117	1	T50	1	T5	1
auto[3221225472:3355443199]	auto[1]	56	1		T16	1	T86	1	T204	1
auto[3355443200:3489660927]	auto[0]	43	1		T15	1	T52	1	T202	1
auto[3355443200:3489660927]	auto[1]	39	1		T204	1	T90	1	T106	2
auto[3489660928:3623878655]	auto[0]	37	1		T15	1	T19	1	T42	3
auto[3489660928:3623878655]	auto[1]	34	1		T33	1	T51	1	T141	1
auto[3623878656:3758096383]	auto[0]	42	1		T49	1	T53	1	T212	1
auto[3623878656:3758096383]	auto[1]	55	1		T33	1	T86	1	T117	1
auto[3758096384:3892314111]	auto[0]	45	1		T13	1	T41	1	T49	2
auto[3758096384:3892314111]	auto[1]	36	1		T45	1	T52	1	T63	1
auto[3892314112:4026531839]	auto[0]	57	1		T13	1	T16	1	T45	1
auto[3892314112:4026531839]	auto[1]	54	1		T33	1	T42	1	T5	1
auto[4026531840:4160749567]	auto[0]	45	1		T207	1	T42	1	T202	1
auto[4026531840:4160749567]	auto[1]	53	1		T45	1	T208	1	T50	1
auto[4160749568:4294967295]	auto[0]	49	1		T42	1	T52	1	T79	1
auto[4160749568:4294967295]	auto[1]	56	1		T18	1	T27	1	T110	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1460

T13

T15

T16

auto[1]

1595

T13

T16

T18

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	94	1		T27	1	T34	2	T5	1
auto[134217728:268435455]	98	1		T41	1	T90	1	T63	1
auto[268435456:402653183]	100	1		T27	1	T204	2	T202	1
auto[402653184:536870911]	96	1		T15	1	T42	2	T202	1
auto[536870912:671088639]	85	1		T33	1	T117	1	T45	1
auto[671088640:805306367]	85	1		T117	1	T202	2	T50	1
auto[805306368:939524095]	91	1		T13	1	T27	1	T86	1
auto[939524096:1073741823]	91	1		T18	1	T42	2	T43	1
auto[1073741824:1207959551]	106	1		T16	1	T33	2	T50	1
auto[1207959552:1342177279]	98	1		T13	1	T33	1	T45	2
auto[1342177280:1476395007]	95	1		T19	1	T204	1	T42	2
auto[1476395008:1610612735]	130	1		T15	2	T42	1	T50	1
auto[1610612736:1744830463]	101	1		T33	1	T86	1	T117	1
auto[1744830464:1879048191]	95	1		T19	1	T42	1	T63	1
auto[1879048192:2013265919]	94	1		T33	1	T44	1	T42	3
auto[2013265920:2147483647]	111	1		T18	1	T33	1	T34	2
auto[2147483648:2281701375]	93	1		T15	1	T90	1	T52	1
auto[2281701376:2415919103]	90	1		T45	1	T41	1	T42	1
auto[2415919104:2550136831]	93	1		T15	1	T5	3	T53	1
auto[2550136832:2684354559]	105	1		T13	3	T18	1	T34	1
auto[2684354560:2818572287]	89	1		T13	1	T16	1	T27	1
auto[2818572288:2952790015]	108	1		T13	1	T18	1	T51	2
auto[2952790016:3087007743]	98	1		T49	1	T63	1	T5	4
auto[3087007744:3221225471]	94	1		T51	2	T45	1	T52	1
auto[3221225472:3355443199]	90	1		T34	1	T45	2	T207	1
auto[3355443200:3489660927]	92	1		T45	1	T42	1	T90	1
auto[3489660928:3623878655]	90	1		T27	1	T33	1	T34	1
auto[3623878656:3758096383]	93	1		T13	2	T16	1	T18	1
auto[3758096384:3892314111]	74	1		T204	1	T49	1	T5	2
auto[3892314112:4026531839]	107	1		T13	1	T33	1	T86	1
auto[4026531840:4160749567]	80	1		T13	1	T207	1	T42	1
auto[4160749568:4294967295]	89	1		T18	1	T86	1	T204	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	41	1		T5	1	T71	1	T212	2
auto[0:134217727]	auto[1]	53	1		T27	1	T34	2	T6	1
auto[134217728:268435455]	auto[0]	41	1		T90	1	T5	1	T53	1
auto[134217728:268435455]	auto[1]	57	1		T41	1	T63	1	T5	2
auto[268435456:402653183]	auto[0]	41	1		T27	1	T204	1	T213	1
auto[268435456:402653183]	auto[1]	59	1		T204	1	T202	1	T29	1
auto[402653184:536870911]	auto[0]	50	1		T15	1	T202	1	T5	3
auto[402653184:536870911]	auto[1]	46	1		T42	2	T106	1	T79	1
auto[536870912:671088639]	auto[0]	42	1		T33	1	T45	1	T49	1
auto[536870912:671088639]	auto[1]	43	1		T117	1	T42	1	T52	1
auto[671088640:805306367]	auto[0]	40	1		T117	1	T202	1	T50	1
auto[671088640:805306367]	auto[1]	45	1		T202	1	T5	1	T106	1
auto[805306368:939524095]	auto[0]	46	1		T117	1	T50	1	T84	1
auto[805306368:939524095]	auto[1]	45	1		T13	1	T27	1	T86	1
auto[939524096:1073741823]	auto[0]	36	1		T18	1	T42	2	T43	1
auto[939524096:1073741823]	auto[1]	55	1		T63	1	T5	1	T184	1
auto[1073741824:1207959551]	auto[0]	54	1		T50	1	T5	3	T38	2
auto[1073741824:1207959551]	auto[1]	52	1		T16	1	T33	2	T110	1
auto[1207959552:1342177279]	auto[0]	42	1		T13	1	T45	1	T50	1
auto[1207959552:1342177279]	auto[1]	56	1		T33	1	T45	1	T19	1
auto[1342177280:1476395007]	auto[0]	45	1		T19	1	T79	1	T30	1
auto[1342177280:1476395007]	auto[1]	50	1		T204	1	T42	2	T5	1
auto[1476395008:1610612735]	auto[0]	64	1		T15	2	T42	1	T50	1
auto[1476395008:1610612735]	auto[1]	66	1		T5	1	T38	1	T58	1
auto[1610612736:1744830463]	auto[0]	53	1		T117	1	T41	1	T202	1
auto[1610612736:1744830463]	auto[1]	48	1		T33	1	T86	1	T44	1
auto[1744830464:1879048191]	auto[0]	46	1		T19	1	T42	1	T5	1
auto[1744830464:1879048191]	auto[1]	49	1		T63	1	T141	1	T106	1
auto[1879048192:2013265919]	auto[0]	39	1		T42	1	T52	1	T5	2
auto[1879048192:2013265919]	auto[1]	55	1		T33	1	T44	1	T42	2
auto[2013265920:2147483647]	auto[0]	63	1		T34	2	T203	1	T50	2
auto[2013265920:2147483647]	auto[1]	48	1		T18	1	T33	1	T51	1
auto[2147483648:2281701375]	auto[0]	48	1		T15	1	T90	1	T52	1
auto[2147483648:2281701375]	auto[1]	45	1		T29	1	T110	1	T38	1
auto[2281701376:2415919103]	auto[0]	52	1		T42	1	T90	3	T52	1
auto[2281701376:2415919103]	auto[1]	38	1		T45	1	T41	1	T52	1
auto[2415919104:2550136831]	auto[0]	44	1		T15	1	T5	1	T53	1
auto[2415919104:2550136831]	auto[1]	49	1		T5	2	T212	1	T213	2
auto[2550136832:2684354559]	auto[0]	52	1		T13	2	T34	1	T49	1
auto[2550136832:2684354559]	auto[1]	53	1		T13	1	T18	1	T44	1
auto[2684354560:2818572287]	auto[0]	44	1		T13	1	T16	1	T50	1
auto[2684354560:2818572287]	auto[1]	45	1		T27	1	T50	2	T106	1
auto[2818572288:2952790015]	auto[0]	59	1		T13	1	T51	2	T49	1
auto[2818572288:2952790015]	auto[1]	49	1		T18	1	T45	1	T5	1
auto[2952790016:3087007743]	auto[0]	50	1		T49	1	T5	2	T79	1
auto[2952790016:3087007743]	auto[1]	48	1		T63	1	T5	2	T183	1
auto[3087007744:3221225471]	auto[0]	49	1		T51	1	T45	1	T63	1
auto[3087007744:3221225471]	auto[1]	45	1		T51	1	T52	1	T5	2
auto[3221225472:3355443199]	auto[0]	40	1		T34	1	T207	1	T41	1
auto[3221225472:3355443199]	auto[1]	50	1		T45	2	T5	1	T212	1
auto[3355443200:3489660927]	auto[0]	38	1		T42	1	T49	1	T110	1
auto[3355443200:3489660927]	auto[1]	54	1		T45	1	T90	1	T43	1
auto[3489660928:3623878655]	auto[0]	44	1		T33	1	T19	1	T42	2
auto[3489660928:3623878655]	auto[1]	46	1		T27	1	T34	1	T5	1
auto[3623878656:3758096383]	auto[0]	39	1		T13	2	T16	1	T18	1
auto[3623878656:3758096383]	auto[1]	54	1		T86	1	T90	1	T50	1
auto[3758096384:3892314111]	auto[0]	36	1		T204	1	T49	1	T5	2
auto[3758096384:3892314111]	auto[1]	38	1		T38	1	T294	1	T57	1
auto[3892314112:4026531839]	auto[0]	37	1		T204	1	T202	1	T84	1
auto[3892314112:4026531839]	auto[1]	70	1		T13	1	T33	1	T86	1
auto[4026531840:4160749567]	auto[0]	42	1		T13	1	T207	1	T42	1
auto[4026531840:4160749567]	auto[1]	38	1		T90	1	T52	1	T38	1
auto[4160749568:4294967295]	auto[0]	43	1		T5	1	T35	1	T424	1
auto[4160749568:4294967295]	auto[1]	46	1		T18	1	T86	1	T204	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1430

T13

T15

T16

auto[1]

1625

T13

T16

T18