Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2667

1

T13

11

T15

5

T16

3

auto[1]

291

1

T86

7

T117

8

T41

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T86	1		T42	2		T140	1
auto[134217728:268435455]	98	1			T33	1		T86	1		T44	1
auto[268435456:402653183]	98	1			T13	1		T41	1		T42	1
auto[402653184:536870911]	90	1			T13	1		T15	1		T27	1
auto[536870912:671088639]	95	1			T13	1		T33	1		T34	1
auto[671088640:805306367]	115	1			T18	1		T33	1		T45	1
auto[805306368:939524095]	73	1			T18	1		T86	1		T51	1
auto[939524096:1073741823]	103	1			T16	1		T86	1		T117	1
auto[1073741824:1207959551]	113	1			T16	1		T27	1		T33	1
auto[1207959552:1342177279]	89	1			T13	1		T51	1		T117	1
auto[1342177280:1476395007]	87	1			T18	1		T207	1		T41	1
auto[1476395008:1610612735]	73	1			T117	1		T204	1		T41	1
auto[1610612736:1744830463]	100	1			T42	2		T52	1		T63	1
auto[1744830464:1879048191]	93	1			T86	1		T34	1		T117	1
auto[1879048192:2013265919]	81	1			T13	2		T27	1		T90	1
auto[2013265920:2147483647]	92	1			T15	1		T34	1		T202	1
auto[2147483648:2281701375]	85	1			T86	1		T204	1		T90	3
auto[2281701376:2415919103]	83	1			T18	1		T110	2		T5	3
auto[2415919104:2550136831]	82	1			T45	1		T140	1		T5	1
auto[2550136832:2684354559]	103	1			T33	1		T204	1		T90	1
auto[2684354560:2818572287]	87	1			T15	1		T34	1		T42	1
auto[2818572288:2952790015]	77	1			T86	1		T34	1		T44	1
auto[2952790016:3087007743]	106	1			T13	2		T34	1		T207	1
auto[3087007744:3221225471]	112	1			T13	1		T15	1		T16	1
auto[3221225472:3355443199]	87	1			T86	1		T203	1		T43	1
auto[3355443200:3489660927]	81	1			T15	1		T86	1		T117	3
auto[3489660928:3623878655]	91	1			T19	1		T204	1		T52	1
auto[3623878656:3758096383]	88	1			T13	1		T117	1		T44	1
auto[3758096384:3892314111]	103	1			T18	1		T33	1		T51	1
auto[3892314112:4026531839]	100	1			T33	1		T86	1		T42	1
auto[4026531840:4160749567]	80	1			T13	1		T18	1		T27	1
auto[4160749568:4294967295]	105	1			T27	1		T51	1		T117	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	82	1			T86	1		T42	2		T5	1
auto[0:134217727]	auto[1]	6	1			T140	1		T286	1		T418	1
auto[134217728:268435455]	auto[0]	86	1			T33	1		T44	1		T42	2
auto[134217728:268435455]	auto[1]	12	1			T86	1		T41	1		T286	1
auto[268435456:402653183]	auto[0]	90	1			T13	1		T41	1		T42	1
auto[268435456:402653183]	auto[1]	8	1			T317	1		T241	2		T432	2
auto[402653184:536870911]	auto[0]	77	1			T13	1		T15	1		T27	1
auto[402653184:536870911]	auto[1]	13	1			T86	1		T140	1		T248	1
auto[536870912:671088639]	auto[0]	91	1			T13	1		T33	1		T34	1
auto[536870912:671088639]	auto[1]	4	1			T422	1		T364	1		T435	1
auto[671088640:805306367]	auto[0]	107	1			T18	1		T33	1		T45	1
auto[671088640:805306367]	auto[1]	8	1			T286	1		T361	1		T416	1
auto[805306368:939524095]	auto[0]	68	1			T18	1		T86	1		T51	1
auto[805306368:939524095]	auto[1]	5	1			T415	1		T420	1		T364	1
auto[939524096:1073741823]	auto[0]	95	1			T16	1		T86	1		T117	1
auto[939524096:1073741823]	auto[1]	8	1			T248	1		T415	1		T317	1
auto[1073741824:1207959551]	auto[0]	101	1			T16	1		T27	1		T33	1
auto[1073741824:1207959551]	auto[1]	12	1			T141	1		T248	1		T263	1
auto[1207959552:1342177279]	auto[0]	79	1			T13	1		T51	1		T45	1
auto[1207959552:1342177279]	auto[1]	10	1			T117	1		T41	1		T248	2
auto[1342177280:1476395007]	auto[0]	84	1			T18	1		T207	1		T41	1
auto[1342177280:1476395007]	auto[1]	3	1			T414	1		T241	1		T421	1
auto[1476395008:1610612735]	auto[0]	59	1			T204	1		T42	1		T43	1
auto[1476395008:1610612735]	auto[1]	14	1			T117	1		T41	1		T110	1
auto[1610612736:1744830463]	auto[0]	93	1			T42	2		T52	1		T63	1
auto[1610612736:1744830463]	auto[1]	7	1			T248	2		T422	1		T300	2
auto[1744830464:1879048191]	auto[0]	77	1			T34	1		T202	1		T58	1
auto[1744830464:1879048191]	auto[1]	16	1			T86	1		T117	1		T41	1
auto[1879048192:2013265919]	auto[0]	72	1			T13	2		T27	1		T90	1
auto[1879048192:2013265919]	auto[1]	9	1			T140	1		T414	3		T421	1
auto[2013265920:2147483647]	auto[0]	82	1			T15	1		T34	1		T202	1
auto[2013265920:2147483647]	auto[1]	10	1			T110	1		T298	1		T414	1
auto[2147483648:2281701375]	auto[0]	73	1			T204	1		T90	3		T63	1
auto[2147483648:2281701375]	auto[1]	12	1			T86	1		T263	1		T317	1
auto[2281701376:2415919103]	auto[0]	71	1			T18	1		T110	1		T5	3
auto[2281701376:2415919103]	auto[1]	12	1			T110	1		T248	1		T286	1
auto[2415919104:2550136831]	auto[0]	73	1			T45	1		T5	1		T106	1
auto[2415919104:2550136831]	auto[1]	9	1			T140	1		T298	1		T286	2
auto[2550136832:2684354559]	auto[0]	94	1			T33	1		T204	1		T90	1
auto[2550136832:2684354559]	auto[1]	9	1			T140	1		T414	1		T417	1
auto[2684354560:2818572287]	auto[0]	80	1			T15	1		T34	1		T42	1
auto[2684354560:2818572287]	auto[1]	7	1			T141	1		T361	1		T317	1
auto[2818572288:2952790015]	auto[0]	68	1			T34	1		T44	1		T42	1
auto[2818572288:2952790015]	auto[1]	9	1			T86	1		T432	1		T436	1
auto[2952790016:3087007743]	auto[0]	102	1			T13	2		T34	1		T207	1
auto[2952790016:3087007743]	auto[1]	4	1			T421	1		T422	1		T342	1
auto[3087007744:3221225471]	auto[0]	99	1			T13	1		T15	1		T16	1
auto[3087007744:3221225471]	auto[1]	13	1			T117	1		T263	1		T418	1
auto[3221225472:3355443199]	auto[0]	81	1			T203	1		T43	1		T38	1
auto[3221225472:3355443199]	auto[1]	6	1			T86	1		T421	1		T420	1
auto[3355443200:3489660927]	auto[0]	66	1			T15	1		T86	1		T41	1
auto[3355443200:3489660927]	auto[1]	15	1			T117	3		T286	1		T263	1
auto[3489660928:3623878655]	auto[0]	83	1			T19	1		T204	1		T52	1
auto[3489660928:3623878655]	auto[1]	8	1			T110	1		T416	1		T437	1
auto[3623878656:3758096383]	auto[0]	81	1			T13	1		T117	1		T44	1
auto[3623878656:3758096383]	auto[1]	7	1			T418	1		T416	1		T420	1
auto[3758096384:3892314111]	auto[0]	97	1			T18	1		T33	1		T51	1
auto[3758096384:3892314111]	auto[1]	6	1			T140	1		T415	1		T361	1
auto[3892314112:4026531839]	auto[0]	88	1			T33	1		T42	1		T5	1
auto[3892314112:4026531839]	auto[1]	12	1			T86	1		T414	2		T238	1
auto[4026531840:4160749567]	auto[0]	75	1			T13	1		T18	1		T27	1
auto[4026531840:4160749567]	auto[1]	5	1			T117	1		T248	1		T241	1
auto[4160749568:4294967295]	auto[0]	93	1			T27	1		T51	1		T117	1
auto[4160749568:4294967295]	auto[1]	12	1			T140	1		T248	2		T263	1