dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1429 1 T13 7 T15 4 T16 2
auto[1] 1626 1 T13 4 T15 1 T16 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 99 1 T27 2 T33 1 T34 1
auto[134217728:268435455] 86 1 T16 1 T45 1 T41 1
auto[268435456:402653183] 98 1 T33 1 T86 1 T51 1
auto[402653184:536870911] 83 1 T5 1 T53 1 T212 1
auto[536870912:671088639] 95 1 T13 2 T16 1 T27 1
auto[671088640:805306367] 93 1 T204 1 T43 1 T5 3
auto[805306368:939524095] 87 1 T15 1 T33 1 T117 1
auto[939524096:1073741823] 98 1 T33 1 T86 1 T42 1
auto[1073741824:1207959551] 89 1 T13 1 T18 1 T42 3
auto[1207959552:1342177279] 107 1 T204 1 T42 1 T52 1
auto[1342177280:1476395007] 94 1 T13 1 T18 1 T27 1
auto[1476395008:1610612735] 102 1 T204 1 T42 1 T5 3
auto[1610612736:1744830463] 100 1 T15 1 T86 1 T34 2
auto[1744830464:1879048191] 83 1 T19 1 T42 2 T49 1
auto[1879048192:2013265919] 104 1 T13 1 T15 2 T51 1
auto[2013265920:2147483647] 102 1 T117 1 T42 1 T5 1
auto[2147483648:2281701375] 87 1 T33 1 T51 1 T19 1
auto[2281701376:2415919103] 84 1 T33 1 T42 2 T52 1
auto[2415919104:2550136831] 94 1 T34 1 T207 1 T49 1
auto[2550136832:2684354559] 85 1 T34 1 T41 1 T90 2
auto[2684354560:2818572287] 97 1 T117 1 T41 1 T42 1
auto[2818572288:2952790015] 99 1 T13 1 T45 1 T52 1
auto[2952790016:3087007743] 107 1 T13 1 T16 1 T34 1
auto[3087007744:3221225471] 97 1 T27 1 T45 1 T43 1
auto[3221225472:3355443199] 90 1 T204 1 T52 1 T208 1
auto[3355443200:3489660927] 96 1 T33 1 T86 1 T44 2
auto[3489660928:3623878655] 92 1 T13 3 T86 1 T42 1
auto[3623878656:3758096383] 98 1 T15 1 T18 1 T44 1
auto[3758096384:3892314111] 104 1 T13 1 T18 2 T33 1
auto[3892314112:4026531839] 95 1 T51 1 T45 1 T19 1
auto[4026531840:4160749567] 104 1 T18 1 T34 1 T63 1
auto[4160749568:4294967295] 106 1 T33 1 T45 1 T202 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 40 1 T117 1 T42 1 T49 2
auto[0:134217727] auto[1] 59 1 T27 2 T33 1 T34 1
auto[134217728:268435455] auto[0] 42 1 T16 1 T41 1 T50 1
auto[134217728:268435455] auto[1] 44 1 T45 1 T110 1 T5 1
auto[268435456:402653183] auto[0] 54 1 T51 1 T45 1 T49 1
auto[268435456:402653183] auto[1] 44 1 T33 1 T86 1 T204 1
auto[402653184:536870911] auto[0] 44 1 T5 1 T212 1 T57 1
auto[402653184:536870911] auto[1] 39 1 T53 1 T57 1 T265 1
auto[536870912:671088639] auto[0] 47 1 T13 1 T27 1 T50 1
auto[536870912:671088639] auto[1] 48 1 T13 1 T16 1 T117 1
auto[671088640:805306367] auto[0] 41 1 T5 1 T196 1 T184 1
auto[671088640:805306367] auto[1] 52 1 T204 1 T43 1 T5 2
auto[805306368:939524095] auto[0] 41 1 T15 1 T117 1 T49 1
auto[805306368:939524095] auto[1] 46 1 T33 1 T45 2 T5 1
auto[939524096:1073741823] auto[0] 47 1 T38 1 T196 1 T53 1
auto[939524096:1073741823] auto[1] 51 1 T33 1 T86 1 T42 1
auto[1073741824:1207959551] auto[0] 37 1 T13 1 T42 1 T49 1
auto[1073741824:1207959551] auto[1] 52 1 T18 1 T42 2 T208 1
auto[1207959552:1342177279] auto[0] 50 1 T204 1 T53 3 T212 1
auto[1207959552:1342177279] auto[1] 57 1 T42 1 T52 1 T5 1
auto[1342177280:1476395007] auto[0] 34 1 T18 1 T19 1 T42 1
auto[1342177280:1476395007] auto[1] 60 1 T13 1 T27 1 T5 1
auto[1476395008:1610612735] auto[0] 45 1 T5 3 T53 2 T294 1
auto[1476395008:1610612735] auto[1] 57 1 T204 1 T42 1 T187 1
auto[1610612736:1744830463] auto[0] 58 1 T15 1 T34 1 T41 1
auto[1610612736:1744830463] auto[1] 42 1 T86 1 T34 1 T42 2
auto[1744830464:1879048191] auto[0] 37 1 T42 2 T49 1 T110 1
auto[1744830464:1879048191] auto[1] 46 1 T19 1 T5 2 T196 1
auto[1879048192:2013265919] auto[0] 51 1 T13 1 T15 1 T45 1
auto[1879048192:2013265919] auto[1] 53 1 T15 1 T51 1 T90 1
auto[2013265920:2147483647] auto[0] 41 1 T95 1 T285 1 T132 1
auto[2013265920:2147483647] auto[1] 61 1 T117 1 T42 1 T5 1
auto[2147483648:2281701375] auto[0] 35 1 T51 1 T19 1 T202 1
auto[2147483648:2281701375] auto[1] 52 1 T33 1 T41 1 T42 1
auto[2281701376:2415919103] auto[0] 49 1 T42 2 T52 1 T49 1
auto[2281701376:2415919103] auto[1] 35 1 T33 1 T203 1 T212 1
auto[2415919104:2550136831] auto[0] 45 1 T34 1 T207 1 T49 1
auto[2415919104:2550136831] auto[1] 49 1 T29 1 T110 1 T106 1
auto[2550136832:2684354559] auto[0] 39 1 T34 1 T90 2 T53 1
auto[2550136832:2684354559] auto[1] 46 1 T41 1 T5 2 T245 1
auto[2684354560:2818572287] auto[0] 46 1 T117 1 T41 1 T5 2
auto[2684354560:2818572287] auto[1] 51 1 T42 1 T202 1 T5 1
auto[2818572288:2952790015] auto[0] 53 1 T13 1 T49 1 T5 1
auto[2818572288:2952790015] auto[1] 46 1 T45 1 T52 1 T38 1
auto[2952790016:3087007743] auto[0] 50 1 T16 1 T34 1 T204 1
auto[2952790016:3087007743] auto[1] 57 1 T13 1 T90 1 T52 1
auto[3087007744:3221225471] auto[0] 42 1 T43 1 T63 1 T71 1
auto[3087007744:3221225471] auto[1] 55 1 T27 1 T45 1 T38 1
auto[3221225472:3355443199] auto[0] 47 1 T204 1 T52 1 T208 1
auto[3221225472:3355443199] auto[1] 43 1 T202 1 T5 1 T184 1
auto[3355443200:3489660927] auto[0] 44 1 T44 1 T207 1 T202 1
auto[3355443200:3489660927] auto[1] 52 1 T33 1 T86 1 T44 1
auto[3489660928:3623878655] auto[0] 41 1 T13 3 T90 1 T52 1
auto[3489660928:3623878655] auto[1] 51 1 T86 1 T42 1 T52 2
auto[3623878656:3758096383] auto[0] 45 1 T15 1 T90 1 T53 1
auto[3623878656:3758096383] auto[1] 53 1 T18 1 T44 1 T106 1
auto[3758096384:3892314111] auto[0] 45 1 T18 1 T51 1 T49 1
auto[3758096384:3892314111] auto[1] 59 1 T13 1 T18 1 T33 1
auto[3892314112:4026531839] auto[0] 42 1 T42 1 T208 1 T5 1
auto[3892314112:4026531839] auto[1] 53 1 T51 1 T45 1 T19 1
auto[4026531840:4160749567] auto[0] 46 1 T34 1 T63 1 T5 2
auto[4026531840:4160749567] auto[1] 58 1 T18 1 T110 2 T5 1
auto[4160749568:4294967295] auto[0] 51 1 T45 1 T202 1 T5 2
auto[4160749568:4294967295] auto[1] 55 1 T33 1 T50 1 T38 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%