Unified Coverage Report :: Group Instance : attest_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1452

1

T13

7

T15

5

T16

2

auto[1]

1603

1

T13

4

T16

1

T18

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T33	1		T34	1		T117	1
auto[134217728:268435455]	83	1			T34	1		T45	2		T204	1
auto[268435456:402653183]	91	1			T42	1		T90	2		T52	1
auto[402653184:536870911]	85	1			T13	1		T19	1		T42	1
auto[536870912:671088639]	110	1			T13	1		T15	1		T42	2
auto[671088640:805306367]	89	1			T13	1		T18	1		T51	1
auto[805306368:939524095]	89	1			T117	1		T204	1		T42	2
auto[939524096:1073741823]	115	1			T13	2		T86	1		T44	1
auto[1073741824:1207959551]	93	1			T27	1		T34	1		T51	1
auto[1207959552:1342177279]	110	1			T86	1		T51	2		T42	2
auto[1342177280:1476395007]	92	1			T18	1		T34	1		T49	1
auto[1476395008:1610612735]	78	1			T15	1		T117	1		T44	1
auto[1610612736:1744830463]	100	1			T18	1		T27	1		T33	1
auto[1744830464:1879048191]	103	1			T33	1		T42	3		T52	1
auto[1879048192:2013265919]	100	1			T33	1		T86	1		T45	1
auto[2013265920:2147483647]	95	1			T13	1		T33	2		T51	1
auto[2147483648:2281701375]	111	1			T27	1		T41	1		T52	1
auto[2281701376:2415919103]	86	1			T33	1		T34	1		T45	1
auto[2415919104:2550136831]	96	1			T15	1		T63	1		T5	1
auto[2550136832:2684354559]	78	1			T18	1		T33	1		T117	1
auto[2684354560:2818572287]	95	1			T49	1		T202	1		T43	1
auto[2818572288:2952790015]	107	1			T13	1		T16	1		T27	1
auto[2952790016:3087007743]	70	1			T13	1		T15	1		T207	1
auto[3087007744:3221225471]	109	1			T13	1		T16	1		T117	1
auto[3221225472:3355443199]	107	1			T16	1		T19	1		T41	1
auto[3355443200:3489660927]	96	1			T13	1		T45	1		T42	1
auto[3489660928:3623878655]	94	1			T86	1		T34	1		T50	3
auto[3623878656:3758096383]	87	1			T86	1		T204	1		T202	1
auto[3758096384:3892314111]	91	1			T33	1		T44	1		T42	1
auto[3892314112:4026531839]	95	1			T18	1		T5	1		T196	1
auto[4026531840:4160749567]	108	1			T15	1		T18	1		T45	1
auto[4160749568:4294967295]	104	1			T13	1		T27	1		T41	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T34	1		T42	1		T49	1
auto[0:134217727]	auto[1]	45	1			T33	1		T117	1		T63	1
auto[134217728:268435455]	auto[0]	36	1			T34	1		T204	1		T208	1
auto[134217728:268435455]	auto[1]	47	1			T45	2		T203	1		T110	1
auto[268435456:402653183]	auto[0]	39	1			T90	1		T52	1		T5	1
auto[268435456:402653183]	auto[1]	52	1			T42	1		T90	1		T63	1
auto[402653184:536870911]	auto[0]	39	1			T13	1		T19	1		T5	1
auto[402653184:536870911]	auto[1]	46	1			T42	1		T5	4		T141	1
auto[536870912:671088639]	auto[0]	54	1			T13	1		T15	1		T42	1
auto[536870912:671088639]	auto[1]	56	1			T42	1		T202	1		T43	1
auto[671088640:805306367]	auto[0]	45	1			T13	1		T51	1		T45	1
auto[671088640:805306367]	auto[1]	44	1			T18	1		T207	1		T29	1
auto[805306368:939524095]	auto[0]	40	1			T117	1		T42	1		T5	1
auto[805306368:939524095]	auto[1]	49	1			T204	1		T42	1		T5	2
auto[939524096:1073741823]	auto[0]	47	1			T13	1		T5	1		T70	1
auto[939524096:1073741823]	auto[1]	68	1			T13	1		T86	1		T44	1
auto[1073741824:1207959551]	auto[0]	45	1			T27	1		T51	1		T49	1
auto[1073741824:1207959551]	auto[1]	48	1			T34	1		T208	1		T63	1
auto[1207959552:1342177279]	auto[0]	47	1			T51	1		T42	2		T38	1
auto[1207959552:1342177279]	auto[1]	63	1			T86	1		T51	1		T5	1
auto[1342177280:1476395007]	auto[0]	39	1			T34	1		T49	1		T35	1
auto[1342177280:1476395007]	auto[1]	53	1			T18	1		T5	1		T184	1
auto[1476395008:1610612735]	auto[0]	39	1			T15	1		T117	1		T207	1
auto[1476395008:1610612735]	auto[1]	39	1			T44	1		T202	1		T425	1
auto[1610612736:1744830463]	auto[0]	56	1			T18	1		T33	1		T42	1
auto[1610612736:1744830463]	auto[1]	44	1			T27	1		T45	1		T19	1
auto[1744830464:1879048191]	auto[0]	46	1			T42	2		T50	1		T5	1
auto[1744830464:1879048191]	auto[1]	57	1			T33	1		T42	1		T52	1
auto[1879048192:2013265919]	auto[0]	44	1			T19	1		T41	1		T52	1
auto[1879048192:2013265919]	auto[1]	56	1			T33	1		T86	1		T45	1
auto[2013265920:2147483647]	auto[0]	42	1			T49	1		T50	1		T5	2
auto[2013265920:2147483647]	auto[1]	53	1			T13	1		T33	2		T51	1
auto[2147483648:2281701375]	auto[0]	58	1			T41	1		T52	1		T43	1
auto[2147483648:2281701375]	auto[1]	53	1			T27	1		T5	1		T187	1
auto[2281701376:2415919103]	auto[0]	43	1			T34	1		T203	1		T50	2
auto[2281701376:2415919103]	auto[1]	43	1			T33	1		T45	1		T90	1
auto[2415919104:2550136831]	auto[0]	47	1			T15	1		T63	1		T5	1
auto[2415919104:2550136831]	auto[1]	49	1			T196	1		T106	1		T79	1
auto[2550136832:2684354559]	auto[0]	37	1			T49	1		T5	2		T187	1
auto[2550136832:2684354559]	auto[1]	41	1			T18	1		T33	1		T117	1
auto[2684354560:2818572287]	auto[0]	43	1			T202	1		T43	1		T5	1
auto[2684354560:2818572287]	auto[1]	52	1			T49	1		T5	1		T38	1
auto[2818572288:2952790015]	auto[0]	54	1			T13	1		T16	1		T45	1
auto[2818572288:2952790015]	auto[1]	53	1			T27	1		T34	1		T90	1
auto[2952790016:3087007743]	auto[0]	31	1			T13	1		T15	1		T207	1
auto[2952790016:3087007743]	auto[1]	39	1			T41	1		T208	1		T58	1
auto[3087007744:3221225471]	auto[0]	46	1			T16	1		T117	1		T204	1
auto[3087007744:3221225471]	auto[1]	63	1			T13	1		T52	1		T141	1
auto[3221225472:3355443199]	auto[0]	53	1			T19	1		T42	2		T184	1
auto[3221225472:3355443199]	auto[1]	54	1			T16	1		T41	1		T52	1
auto[3355443200:3489660927]	auto[0]	49	1			T13	1		T42	1		T84	1
auto[3355443200:3489660927]	auto[1]	47	1			T45	1		T110	1		T5	2
auto[3489660928:3623878655]	auto[0]	52	1			T34	1		T50	2		T5	2
auto[3489660928:3623878655]	auto[1]	42	1			T86	1		T50	1		T83	1
auto[3623878656:3758096383]	auto[0]	42	1			T43	1		T50	1		T5	2
auto[3623878656:3758096383]	auto[1]	45	1			T86	1		T204	1		T202	1
auto[3758096384:3892314111]	auto[0]	48	1			T43	1		T110	1		T5	1
auto[3758096384:3892314111]	auto[1]	43	1			T33	1		T44	1		T42	1
auto[3892314112:4026531839]	auto[0]	50	1			T18	1		T212	1		T36	1
auto[3892314112:4026531839]	auto[1]	45	1			T5	1		T196	1		T201	1
auto[4026531840:4160749567]	auto[0]	45	1			T15	1		T45	1		T90	2
auto[4026531840:4160749567]	auto[1]	63	1			T18	1		T41	1		T42	1
auto[4160749568:4294967295]	auto[0]	53	1			T5	1		T71	1		T294	1
auto[4160749568:4294967295]	auto[1]	51	1			T13	1		T27	1		T41	1