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LINE 3013
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T15,T16 |
1 | 1 | Covered | T1,T15,T17 |
LINE 3013
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[58] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T15,T17,T33 |
LINE 3013
SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[61] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3013
SUB-EXPRESSION (addr_hit[62] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3080
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T50,T106,T61 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3083
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T13 |
1 | 1 | 0 | Covered | T42,T61,T125 |
1 | 1 | 1 | Covered | T1,T2,T13 |
LINE 3086
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T15,T17,T33 |
1 | 1 | 0 | Covered | T50,T61,T124 |
1 | 1 | 1 | Covered | T42,T5,T106 |
LINE 3089
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T15,T17,T33 |
1 | 1 | 0 | Covered | T42,T50,T106 |
1 | 1 | 1 | Covered | T104,T82,T105 |
LINE 3094
EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T15,T17,T33 |
1 | 1 | 0 | Covered | T149,T150 |
1 | 1 | 1 | Covered | T33,T86,T117 |
LINE 3095
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T61,T124,T151 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3098
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T149,T152 |
1 | 1 | 1 | Covered | T33,T86,T117 |
LINE 3099
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T50,T124,T153 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3106
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T13,T4 |
1 | 1 | 0 | Covered | T154,T155,T156 |
1 | 1 | 1 | Covered | T2,T13,T4 |
LINE 3109
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T15,T17,T33 |
1 | 1 | 0 | Covered | T42,T106,T61 |
1 | 1 | 1 | Covered | T157,T158,T147 |
LINE 3112
EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T159,T148,T160 |
1 | 1 | 1 | Covered | T33,T42,T50 |
LINE 3113
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T50,T106,T61 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3116
EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T33,T42,T50 |
LINE 3117
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3120
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T106,T61 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3123
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T161,T162 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3126
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T61,T125,T154 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3129
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T33,T50,T61 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3132
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T106,T61 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3135
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T33,T50,T106 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3138
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T60,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3141
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3144
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T61,T154 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3147
EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T61,T125 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3150
EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T42,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3153
EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T106,T125 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3156
EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T122 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3159
EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T123,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3162
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T61,T124,T125 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3165
EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T106,T61 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3168
EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3171
EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T42,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3174
EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T122,T123 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3177
EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T125 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3180
EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T42,T50,T106 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3183
EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3186
EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3189
EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3192
EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T106,T61 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3195
EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T124,T153,T155 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3198
EXPRESSION (addr_hit[37] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T163,T164,T165 |
1 | 1 | 1 | Covered | T33,T42,T50 |
LINE 3199
EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T42,T106,T61 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3202
EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T61,T153 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3205
EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T33,T42,T50 |
LINE 3206
EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T33,T61,T124 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3209
EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T106,T61,T125 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3212
EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T1,T166,T167 |
1 | 1 | 1 | Covered | T33,T42,T50 |
LINE 3213
EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T15,T16 |
1 | 1 | 0 | Covered | T50,T61,T125 |
1 | 1 | 1 | Covered | T13,T15,T16 |
LINE 3216
EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T168,T169 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3219
EXPRESSION (addr_hit[43] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T160 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3222
EXPRESSION (addr_hit[44] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T54,T170,T171 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3225
EXPRESSION (addr_hit[45] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T172,T173 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3228
EXPRESSION (addr_hit[46] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3231
EXPRESSION (addr_hit[47] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T165,T152 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3234
EXPRESSION (addr_hit[48] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T14,T163,T169 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3237
EXPRESSION (addr_hit[49] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T165,T174 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3240
EXPRESSION (addr_hit[50] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T175 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3243
EXPRESSION (addr_hit[51] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T176,T152 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3246
EXPRESSION (addr_hit[52] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T176 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3249
EXPRESSION (addr_hit[53] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T165,T160,T168 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3252
EXPRESSION (addr_hit[54] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3255
EXPRESSION (addr_hit[55] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T168 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3258
EXPRESSION (addr_hit[56] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T177 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3261
EXPRESSION (addr_hit[57] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T164,T173 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3264
EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T50,T61,T122 |
1 | 1 | 1 | Covered | T157,T158,T147 |
LINE 3267
EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T33,T61,T151 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 3274
EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T42,T50,T106 |
1 | 1 | 1 | Covered | T16,T18,T27 |
LINE 3665
SUB-EXPRESSION (rst_done & shadow_rst_done)
----1--- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T115,T116,T111 |
1 | 0 | Covered | T115,T116,T111 |
1 | 1 | Covered | T1,T2,T3 |