Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 98.11 98.24 100.00 99.02 98.41 91.14


Total test records in report: 1085
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1006 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.232135272 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:13 PM PDT 24 32210368 ps
T1007 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1360258391 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:08 PM PDT 24 67356195 ps
T1008 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2077686728 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:13 PM PDT 24 31259909 ps
T1009 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1468218071 Jun 27 04:44:58 PM PDT 24 Jun 27 04:45:03 PM PDT 24 89784050 ps
T1010 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.597650301 Jun 27 04:44:51 PM PDT 24 Jun 27 04:44:59 PM PDT 24 117679198 ps
T1011 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2375427552 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:09 PM PDT 24 68659154 ps
T1012 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1560895292 Jun 27 04:44:45 PM PDT 24 Jun 27 04:44:51 PM PDT 24 54338146 ps
T1013 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1065085021 Jun 27 04:44:50 PM PDT 24 Jun 27 04:44:57 PM PDT 24 24828789 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.676427321 Jun 27 04:44:43 PM PDT 24 Jun 27 04:44:48 PM PDT 24 184298026 ps
T1015 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2683710067 Jun 27 04:45:01 PM PDT 24 Jun 27 04:45:07 PM PDT 24 258331091 ps
T1016 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.370976593 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:11 PM PDT 24 26871884 ps
T1017 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4051311811 Jun 27 04:45:07 PM PDT 24 Jun 27 04:45:14 PM PDT 24 11704886 ps
T1018 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2265723464 Jun 27 04:44:50 PM PDT 24 Jun 27 04:44:56 PM PDT 24 36880358 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3017538973 Jun 27 04:44:46 PM PDT 24 Jun 27 04:44:53 PM PDT 24 66506935 ps
T1020 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3370706094 Jun 27 04:44:42 PM PDT 24 Jun 27 04:44:44 PM PDT 24 109791541 ps
T1021 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2330833224 Jun 27 04:45:04 PM PDT 24 Jun 27 04:45:11 PM PDT 24 84405625 ps
T1022 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2872014400 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:09 PM PDT 24 34238706 ps
T1023 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2865497246 Jun 27 04:44:44 PM PDT 24 Jun 27 04:44:46 PM PDT 24 25711719 ps
T1024 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4225652765 Jun 27 04:44:59 PM PDT 24 Jun 27 04:45:02 PM PDT 24 38281868 ps
T1025 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.371688938 Jun 27 04:44:43 PM PDT 24 Jun 27 04:44:48 PM PDT 24 2333037978 ps
T1026 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4273424914 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:18 PM PDT 24 144763337 ps
T1027 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.570013828 Jun 27 04:44:46 PM PDT 24 Jun 27 04:44:54 PM PDT 24 92361546 ps
T1028 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.392126505 Jun 27 04:44:48 PM PDT 24 Jun 27 04:45:01 PM PDT 24 881464323 ps
T1029 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.22857104 Jun 27 04:44:48 PM PDT 24 Jun 27 04:45:04 PM PDT 24 485275470 ps
T1030 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.410631267 Jun 27 04:45:01 PM PDT 24 Jun 27 04:45:08 PM PDT 24 299124731 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2473433999 Jun 27 04:44:46 PM PDT 24 Jun 27 04:44:52 PM PDT 24 21202411 ps
T1032 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3803519461 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:06 PM PDT 24 788599850 ps
T1033 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2671674422 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:08 PM PDT 24 324618116 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2704379121 Jun 27 04:44:45 PM PDT 24 Jun 27 04:44:54 PM PDT 24 174773323 ps
T1035 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.661844721 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:05 PM PDT 24 13014440 ps
T174 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3213366169 Jun 27 04:44:45 PM PDT 24 Jun 27 04:44:53 PM PDT 24 1050328038 ps
T1036 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1841485198 Jun 27 04:44:43 PM PDT 24 Jun 27 04:44:49 PM PDT 24 73136682 ps
T1037 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.509055177 Jun 27 04:45:01 PM PDT 24 Jun 27 04:45:06 PM PDT 24 114543101 ps
T1038 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2967822394 Jun 27 04:44:47 PM PDT 24 Jun 27 04:44:53 PM PDT 24 10614649 ps
T1039 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2894519041 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:12 PM PDT 24 14320553 ps
T1040 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.476466383 Jun 27 04:45:06 PM PDT 24 Jun 27 04:45:13 PM PDT 24 87431558 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.327416724 Jun 27 04:44:50 PM PDT 24 Jun 27 04:44:56 PM PDT 24 40116130 ps
T1042 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.792932344 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:07 PM PDT 24 14421883 ps
T1043 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4014011769 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:04 PM PDT 24 11201620 ps
T1044 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1680572854 Jun 27 04:44:46 PM PDT 24 Jun 27 04:44:53 PM PDT 24 34525916 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3158214801 Jun 27 04:44:46 PM PDT 24 Jun 27 04:44:54 PM PDT 24 53845714 ps
T1046 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2095617853 Jun 27 04:44:47 PM PDT 24 Jun 27 04:44:59 PM PDT 24 662561807 ps
T1047 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3912116742 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:09 PM PDT 24 42098022 ps
T1048 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2470096390 Jun 27 04:44:50 PM PDT 24 Jun 27 04:44:56 PM PDT 24 24722908 ps
T1049 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3523820642 Jun 27 04:44:46 PM PDT 24 Jun 27 04:44:51 PM PDT 24 24423376 ps
T1050 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3559724247 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:08 PM PDT 24 175681415 ps
T150 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4095057961 Jun 27 04:44:53 PM PDT 24 Jun 27 04:45:02 PM PDT 24 101517520 ps
T1051 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1608414932 Jun 27 04:45:04 PM PDT 24 Jun 27 04:45:11 PM PDT 24 12946537 ps
T1052 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.381453128 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:13 PM PDT 24 60859362 ps
T152 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3103731469 Jun 27 04:44:43 PM PDT 24 Jun 27 04:44:50 PM PDT 24 283370086 ps
T1053 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.743344453 Jun 27 04:44:52 PM PDT 24 Jun 27 04:45:10 PM PDT 24 1488392602 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3672373585 Jun 27 04:44:57 PM PDT 24 Jun 27 04:45:01 PM PDT 24 58970248 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4041905358 Jun 27 04:44:51 PM PDT 24 Jun 27 04:44:57 PM PDT 24 34252674 ps
T1056 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3342740666 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:08 PM PDT 24 20831917 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3499511979 Jun 27 04:44:47 PM PDT 24 Jun 27 04:44:55 PM PDT 24 117791638 ps
T1058 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2699738359 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:13 PM PDT 24 33638894 ps
T1059 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2902661198 Jun 27 04:44:33 PM PDT 24 Jun 27 04:44:38 PM PDT 24 1928301886 ps
T1060 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4224174270 Jun 27 04:44:49 PM PDT 24 Jun 27 04:44:56 PM PDT 24 298621572 ps
T1061 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.885459247 Jun 27 04:45:07 PM PDT 24 Jun 27 04:45:19 PM PDT 24 1018765711 ps
T1062 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2784004730 Jun 27 04:44:51 PM PDT 24 Jun 27 04:44:58 PM PDT 24 261325298 ps
T1063 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2377386793 Jun 27 04:44:45 PM PDT 24 Jun 27 04:44:51 PM PDT 24 110481798 ps
T1064 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2771328962 Jun 27 04:44:43 PM PDT 24 Jun 27 04:44:46 PM PDT 24 18249333 ps
T1065 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3104716911 Jun 27 04:44:49 PM PDT 24 Jun 27 04:44:56 PM PDT 24 96814056 ps
T1066 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3826046770 Jun 27 04:44:49 PM PDT 24 Jun 27 04:44:56 PM PDT 24 13750937 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3747419743 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:10 PM PDT 24 618058285 ps
T1068 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4111075439 Jun 27 04:44:49 PM PDT 24 Jun 27 04:44:55 PM PDT 24 11966993 ps
T1069 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3663542043 Jun 27 04:45:09 PM PDT 24 Jun 27 04:45:18 PM PDT 24 300740109 ps
T1070 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3374434111 Jun 27 04:44:41 PM PDT 24 Jun 27 04:44:43 PM PDT 24 51724240 ps
T1071 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4256650262 Jun 27 04:45:04 PM PDT 24 Jun 27 04:45:11 PM PDT 24 8776138 ps
T169 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3119254646 Jun 27 04:44:51 PM PDT 24 Jun 27 04:45:02 PM PDT 24 351428308 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1573725390 Jun 27 04:44:51 PM PDT 24 Jun 27 04:45:00 PM PDT 24 347487132 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1210433585 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:08 PM PDT 24 530731297 ps
T1074 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3595025735 Jun 27 04:45:01 PM PDT 24 Jun 27 04:45:07 PM PDT 24 338192323 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4241555592 Jun 27 04:44:44 PM PDT 24 Jun 27 04:44:48 PM PDT 24 14894590 ps
T1076 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2383199792 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:11 PM PDT 24 116414783 ps
T1077 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.817482430 Jun 27 04:44:47 PM PDT 24 Jun 27 04:44:54 PM PDT 24 216998682 ps
T1078 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3354547941 Jun 27 04:44:49 PM PDT 24 Jun 27 04:45:04 PM PDT 24 1257576605 ps
T1079 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.691458045 Jun 27 04:45:01 PM PDT 24 Jun 27 04:45:07 PM PDT 24 878624917 ps
T1080 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1427012534 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:10 PM PDT 24 150876441 ps
T1081 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.514185342 Jun 27 04:44:47 PM PDT 24 Jun 27 04:45:04 PM PDT 24 523252554 ps
T175 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3196996688 Jun 27 04:45:00 PM PDT 24 Jun 27 04:45:09 PM PDT 24 349470845 ps
T1082 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4032355391 Jun 27 04:44:48 PM PDT 24 Jun 27 04:44:58 PM PDT 24 172573024 ps
T1083 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2064793277 Jun 27 04:44:41 PM PDT 24 Jun 27 04:44:54 PM PDT 24 435150223 ps
T1084 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3996515879 Jun 27 04:45:04 PM PDT 24 Jun 27 04:45:10 PM PDT 24 11473975 ps
T1085 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3661170345 Jun 27 04:44:50 PM PDT 24 Jun 27 04:44:56 PM PDT 24 37904407 ps

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4239790113
Short name T16
Test name
Test status
Simulation time 1010945270 ps
CPU time 21.28 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:41 PM PDT 24
Peak memory 209196 kb
Host smart-8862ad32-b7fb-4f27-b37d-c0e1d1211a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239790113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4239790113
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.527166828
Short name T5
Test name
Test status
Simulation time 26100904802 ps
CPU time 65.91 seconds
Started Jun 27 04:46:37 PM PDT 24
Finished Jun 27 04:47:56 PM PDT 24
Peak memory 216312 kb
Host smart-685ff20d-e31a-43fc-a150-1b9ecf55d793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527166828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.527166828
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3929255038
Short name T42
Test name
Test status
Simulation time 1709211973 ps
CPU time 18.24 seconds
Started Jun 27 04:46:39 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 222624 kb
Host smart-814ae9ca-a71a-4b5a-9e6d-b772c81a1d98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929255038 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3929255038
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3480357945
Short name T10
Test name
Test status
Simulation time 2164108559 ps
CPU time 11.78 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:14 PM PDT 24
Peak memory 231248 kb
Host smart-6700341e-b451-477e-8a02-1d21d25a4c73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480357945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3480357945
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.777075820
Short name T15
Test name
Test status
Simulation time 338383379 ps
CPU time 3.29 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 214216 kb
Host smart-c9fcb608-5e56-4fad-8f4a-d9decb8fbd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777075820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.777075820
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.104841922
Short name T213
Test name
Test status
Simulation time 600589961 ps
CPU time 28.35 seconds
Started Jun 27 04:47:48 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 221300 kb
Host smart-57f2ec40-97ff-4edc-b16c-ab506599c15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104841922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.104841922
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.333920143
Short name T106
Test name
Test status
Simulation time 616337497 ps
CPU time 20.96 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 222716 kb
Host smart-380ea3ef-ec03-4cb2-be60-a98e4011a27d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333920143 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.333920143
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.633547066
Short name T248
Test name
Test status
Simulation time 803217173 ps
CPU time 15.45 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:57 PM PDT 24
Peak memory 215160 kb
Host smart-523d302c-2579-49d1-86b4-f3225d98a0eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633547066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.633547066
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3595615687
Short name T8
Test name
Test status
Simulation time 488898272 ps
CPU time 5.85 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:46:52 PM PDT 24
Peak memory 221940 kb
Host smart-52c3668d-5a39-4e70-a237-59bc83a93edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595615687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3595615687
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2335817953
Short name T111
Test name
Test status
Simulation time 434066203 ps
CPU time 9.54 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 213840 kb
Host smart-79b68e74-7c44-4566-b7cd-973e9ba87e08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335817953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2335817953
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3677381381
Short name T292
Test name
Test status
Simulation time 423566346 ps
CPU time 21 seconds
Started Jun 27 04:47:42 PM PDT 24
Finished Jun 27 04:48:07 PM PDT 24
Peak memory 222320 kb
Host smart-1db13a4a-9847-4080-a3bd-8f4e8bb9de71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677381381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3677381381
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1659910447
Short name T53
Test name
Test status
Simulation time 4174880430 ps
CPU time 33.5 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 215404 kb
Host smart-93e93977-a2b6-4abf-b4f2-564589e4f59d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659910447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1659910447
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3207091620
Short name T420
Test name
Test status
Simulation time 4436445879 ps
CPU time 55.21 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 214436 kb
Host smart-e3c08237-4934-4749-9cdd-b3b891dddd3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207091620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3207091620
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3066138815
Short name T298
Test name
Test status
Simulation time 995139395 ps
CPU time 14.3 seconds
Started Jun 27 04:47:01 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 214508 kb
Host smart-03912618-b659-416d-bd5d-6231de5e1c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066138815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3066138815
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1503845368
Short name T86
Test name
Test status
Simulation time 125621089 ps
CPU time 6.33 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 215488 kb
Host smart-e72a2233-c388-4953-ab65-5bdec3959625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503845368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1503845368
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1353369186
Short name T61
Test name
Test status
Simulation time 881113660 ps
CPU time 22.12 seconds
Started Jun 27 04:47:54 PM PDT 24
Finished Jun 27 04:48:17 PM PDT 24
Peak memory 222604 kb
Host smart-5fff1cc3-db05-4102-aed8-07834d6190db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353369186 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1353369186
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1570443788
Short name T100
Test name
Test status
Simulation time 720951157 ps
CPU time 20.08 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:21 PM PDT 24
Peak memory 214304 kb
Host smart-9ca1bd88-3067-4d8d-b47b-f3d1f2c86eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570443788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1570443788
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2472350586
Short name T415
Test name
Test status
Simulation time 723592983 ps
CPU time 18.01 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:51 PM PDT 24
Peak memory 214768 kb
Host smart-0e1954c7-8a31-4d2d-abea-bef1a3c03396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472350586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2472350586
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.723138988
Short name T1
Test name
Test status
Simulation time 148512398 ps
CPU time 4.05 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 210156 kb
Host smart-dc463c8e-e2cc-4103-b570-bfea26c21de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723138988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.723138988
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2956181927
Short name T74
Test name
Test status
Simulation time 25973602643 ps
CPU time 64.25 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:47:41 PM PDT 24
Peak memory 222484 kb
Host smart-64c8b078-4273-4dde-9dd3-51648853af92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956181927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2956181927
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4262406498
Short name T22
Test name
Test status
Simulation time 41983504 ps
CPU time 1.56 seconds
Started Jun 27 04:46:47 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 222868 kb
Host smart-8c0d9782-3729-47ca-b293-0c8c49988aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262406498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4262406498
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3361802602
Short name T35
Test name
Test status
Simulation time 111897079 ps
CPU time 3.48 seconds
Started Jun 27 04:46:19 PM PDT 24
Finished Jun 27 04:46:24 PM PDT 24
Peak memory 214264 kb
Host smart-dc540a97-82a2-4ce0-bc12-b2f5f6bc311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361802602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3361802602
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3532470177
Short name T21
Test name
Test status
Simulation time 232647043 ps
CPU time 6.47 seconds
Started Jun 27 04:47:47 PM PDT 24
Finished Jun 27 04:47:56 PM PDT 24
Peak memory 214304 kb
Host smart-be151923-9a2c-48b6-8bd0-5a17f878b788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532470177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3532470177
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3653117883
Short name T421
Test name
Test status
Simulation time 2619671122 ps
CPU time 22.92 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 215692 kb
Host smart-46f316a3-ed79-4340-b750-e414c26cd6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653117883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3653117883
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1010124930
Short name T29
Test name
Test status
Simulation time 143146975 ps
CPU time 3.41 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 218200 kb
Host smart-d2b86e5a-00f5-481d-b846-c5f9e6f6a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010124930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1010124930
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.173388078
Short name T50
Test name
Test status
Simulation time 1263716708 ps
CPU time 13.18 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:27 PM PDT 24
Peak memory 222528 kb
Host smart-3e5609a2-7443-4a1e-919d-9cbc40e43a87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173388078 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.173388078
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2680157700
Short name T142
Test name
Test status
Simulation time 49883923 ps
CPU time 2.37 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 217480 kb
Host smart-3d0e9329-8f06-44be-9ece-981f23627911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680157700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2680157700
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.552419421
Short name T118
Test name
Test status
Simulation time 389157597 ps
CPU time 2.98 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 213816 kb
Host smart-9642bafa-cf29-4f1d-b5dd-4f3b8996ff5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552419421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.552419421
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.634363414
Short name T286
Test name
Test status
Simulation time 69170449 ps
CPU time 4.64 seconds
Started Jun 27 04:46:16 PM PDT 24
Finished Jun 27 04:46:22 PM PDT 24
Peak memory 222372 kb
Host smart-2a7f6b70-c848-457e-b8c2-089fbbd0a9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634363414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.634363414
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1745308508
Short name T13
Test name
Test status
Simulation time 73516454 ps
CPU time 2.28 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 214152 kb
Host smart-881bb57c-48f9-4aed-a71c-b9e7465c6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745308508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1745308508
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1971195363
Short name T92
Test name
Test status
Simulation time 735644886 ps
CPU time 5.76 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 208552 kb
Host smart-e3c1257f-59c4-48de-b7aa-7bcbaa115455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971195363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1971195363
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3416696665
Short name T317
Test name
Test status
Simulation time 74268764 ps
CPU time 4.31 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 214196 kb
Host smart-6adb9c64-18ca-49b4-aa26-722eed324689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416696665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3416696665
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.54625757
Short name T217
Test name
Test status
Simulation time 1842194545 ps
CPU time 65.14 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 220044 kb
Host smart-6a350c6c-2362-45e2-bc1a-fb3e78dc9444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54625757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.54625757
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.976500021
Short name T104
Test name
Test status
Simulation time 61059950 ps
CPU time 0.78 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:36 PM PDT 24
Peak memory 206044 kb
Host smart-b71118a9-c832-4766-aac3-3cacbc42049c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976500021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.976500021
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2919642815
Short name T7
Test name
Test status
Simulation time 4765866617 ps
CPU time 26.85 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:47:11 PM PDT 24
Peak memory 222572 kb
Host smart-2cf647e8-c852-4a0f-b841-89ddc3d84662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919642815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2919642815
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.991080843
Short name T241
Test name
Test status
Simulation time 1116657392 ps
CPU time 6.49 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:05 PM PDT 24
Peak memory 214548 kb
Host smart-cecc8308-6e18-43b1-8cea-e0a2a89a2860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991080843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.991080843
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3400253816
Short name T165
Test name
Test status
Simulation time 155530760 ps
CPU time 3.54 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 205504 kb
Host smart-359587f4-1e1e-4a15-83a0-eb5c298c1b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400253816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3400253816
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.679838043
Short name T19
Test name
Test status
Simulation time 183473659 ps
CPU time 3.09 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 208744 kb
Host smart-b118d99c-fbf7-4a98-bb51-e11160ab4eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679838043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.679838043
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2006619306
Short name T46
Test name
Test status
Simulation time 1227101474 ps
CPU time 42.67 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 216564 kb
Host smart-272115a4-1fab-46ca-a073-c09816df02b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006619306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2006619306
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.320732035
Short name T24
Test name
Test status
Simulation time 185348287 ps
CPU time 3.34 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 222556 kb
Host smart-42fe8248-0f09-4226-8861-c1d2a923f16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320732035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.320732035
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3103731469
Short name T152
Test name
Test status
Simulation time 283370086 ps
CPU time 6.16 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:50 PM PDT 24
Peak memory 213676 kb
Host smart-d4290c41-e7e3-48af-bb4b-26c7bc0f98db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103731469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3103731469
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.172988233
Short name T230
Test name
Test status
Simulation time 339613755 ps
CPU time 13.33 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 220580 kb
Host smart-a09a3d8a-fdca-4c4d-a1d6-a84f74c87aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172988233 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.172988233
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2310748633
Short name T145
Test name
Test status
Simulation time 478143035 ps
CPU time 6.33 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:47 PM PDT 24
Peak memory 222696 kb
Host smart-1771d83a-9f72-4db8-9ec7-18a478cd4d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310748633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2310748633
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4282213738
Short name T364
Test name
Test status
Simulation time 144808670 ps
CPU time 4.1 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:32 PM PDT 24
Peak memory 215356 kb
Host smart-f56c41e4-7716-42ef-8bc7-164a71417945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282213738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4282213738
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1558546391
Short name T267
Test name
Test status
Simulation time 101882111 ps
CPU time 4.1 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 214204 kb
Host smart-cec9f452-44d2-4239-9f81-413b82ced92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558546391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1558546391
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.124116277
Short name T229
Test name
Test status
Simulation time 11577333935 ps
CPU time 35.73 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:57 PM PDT 24
Peak memory 222400 kb
Host smart-9b5f26f8-5400-47c8-b5a3-d4df2dcbb72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124116277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.124116277
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.962617974
Short name T300
Test name
Test status
Simulation time 287730382 ps
CPU time 15.96 seconds
Started Jun 27 04:47:30 PM PDT 24
Finished Jun 27 04:47:52 PM PDT 24
Peak memory 214500 kb
Host smart-caa90de3-5f75-4501-bf45-6b8654f4688d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962617974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.962617974
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3119254646
Short name T169
Test name
Test status
Simulation time 351428308 ps
CPU time 5.02 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 213556 kb
Host smart-af08080b-ee7d-4365-97ca-d4987d2338d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119254646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3119254646
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2177725274
Short name T173
Test name
Test status
Simulation time 202780361 ps
CPU time 4.27 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213664 kb
Host smart-a9f943b5-492b-4c90-92af-c8d49235c409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177725274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2177725274
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1306532468
Short name T146
Test name
Test status
Simulation time 80744778 ps
CPU time 4.65 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:57 PM PDT 24
Peak memory 222680 kb
Host smart-677d7834-df98-4488-8b74-2cc17d35d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306532468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1306532468
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2339661684
Short name T69
Test name
Test status
Simulation time 200112728 ps
CPU time 3.05 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 207848 kb
Host smart-141e8811-da81-4716-9cda-b43fcbc48020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339661684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2339661684
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2036364316
Short name T57
Test name
Test status
Simulation time 2553363467 ps
CPU time 19.91 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:24 PM PDT 24
Peak memory 215528 kb
Host smart-fbd5d9e1-2af2-4367-b6c0-d2b1fb1fee36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036364316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2036364316
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.819328815
Short name T393
Test name
Test status
Simulation time 1909997606 ps
CPU time 5.49 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 206972 kb
Host smart-5e3211d1-d5a1-4266-9fc4-336a5ee883f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819328815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.819328815
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2013634776
Short name T245
Test name
Test status
Simulation time 33561024 ps
CPU time 2.49 seconds
Started Jun 27 04:48:08 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 219740 kb
Host smart-c0eb2b49-ce24-4e99-ad42-73cc3ff78ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013634776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2013634776
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2491491679
Short name T87
Test name
Test status
Simulation time 86195993 ps
CPU time 4.43 seconds
Started Jun 27 04:46:05 PM PDT 24
Finished Jun 27 04:46:11 PM PDT 24
Peak memory 214336 kb
Host smart-bd1cfae5-69bf-4df0-8f1a-6ba084d892f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491491679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2491491679
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3515819823
Short name T170
Test name
Test status
Simulation time 926912753 ps
CPU time 3.26 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 210304 kb
Host smart-1d623d59-577d-41dd-a999-aecdc2a9f159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515819823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3515819823
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1772750651
Short name T113
Test name
Test status
Simulation time 81852406 ps
CPU time 4.8 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 213972 kb
Host smart-eb2c37c9-2924-4ed2-b489-3e73a83d6183
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772750651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1772750651
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3196996688
Short name T175
Test name
Test status
Simulation time 349470845 ps
CPU time 5.27 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 213664 kb
Host smart-f6343089-3369-4755-b106-58365476cb01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196996688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3196996688
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.413778565
Short name T11
Test name
Test status
Simulation time 844756359 ps
CPU time 12.68 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 237364 kb
Host smart-7232c045-ff6a-4ebd-ab97-c60d0b7d8dcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413778565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.413778565
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3933080502
Short name T185
Test name
Test status
Simulation time 99469511 ps
CPU time 2.12 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:31 PM PDT 24
Peak memory 206972 kb
Host smart-13fd376c-fced-4342-a083-22bfd55e073b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933080502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3933080502
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2214132432
Short name T380
Test name
Test status
Simulation time 272718005 ps
CPU time 7.34 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 214340 kb
Host smart-6b1b4258-d675-4f2c-8876-7a344bcf66c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214132432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2214132432
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2033444407
Short name T101
Test name
Test status
Simulation time 626860945 ps
CPU time 3.79 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 218496 kb
Host smart-12e69010-8862-4df1-b213-a98f48d7e620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033444407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2033444407
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2062965592
Short name T281
Test name
Test status
Simulation time 1470684116 ps
CPU time 29.52 seconds
Started Jun 27 04:47:32 PM PDT 24
Finished Jun 27 04:48:06 PM PDT 24
Peak memory 222456 kb
Host smart-a1908eaa-28ea-422d-bff1-c332f404b112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062965592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2062965592
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.978935478
Short name T144
Test name
Test status
Simulation time 99615309 ps
CPU time 1.72 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 215348 kb
Host smart-26cc93d5-6f3a-47f2-9621-14a0a49b5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978935478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.978935478
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2795299920
Short name T493
Test name
Test status
Simulation time 71362966 ps
CPU time 3.22 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:48 PM PDT 24
Peak memory 208628 kb
Host smart-672e1a37-b253-435a-bd79-63e26aa734c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795299920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2795299920
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2172565044
Short name T361
Test name
Test status
Simulation time 61646967 ps
CPU time 4.1 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:36 PM PDT 24
Peak memory 214400 kb
Host smart-5b6a8cef-3111-430b-861d-eddf90267ebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172565044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2172565044
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2815728824
Short name T249
Test name
Test status
Simulation time 466892895 ps
CPU time 5.3 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 209792 kb
Host smart-157cbdf8-de5f-4e61-837d-3608c4a80bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815728824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2815728824
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.574053747
Short name T327
Test name
Test status
Simulation time 141861430 ps
CPU time 2.62 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:31 PM PDT 24
Peak memory 222444 kb
Host smart-35eb9524-9501-40ea-8477-2400a1f294fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574053747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.574053747
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1226005685
Short name T4
Test name
Test status
Simulation time 61773529 ps
CPU time 3.02 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 206916 kb
Host smart-598e58c6-59ea-4626-9c60-7d8fdf6e505a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226005685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1226005685
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3076151306
Short name T560
Test name
Test status
Simulation time 1609136793 ps
CPU time 8.23 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 208220 kb
Host smart-7edb119d-d9e9-405f-8ebc-3b883b05f383
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076151306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3076151306
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1162396343
Short name T290
Test name
Test status
Simulation time 124247038 ps
CPU time 2.34 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 215400 kb
Host smart-72585c98-ffb2-422e-83c7-ce7aac692797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162396343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1162396343
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1447254715
Short name T635
Test name
Test status
Simulation time 109204743 ps
CPU time 2.56 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:02 PM PDT 24
Peak memory 210484 kb
Host smart-11901156-80bf-4046-a351-abb6bad0dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447254715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1447254715
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4093576507
Short name T342
Test name
Test status
Simulation time 207078715 ps
CPU time 4.02 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 214432 kb
Host smart-c9ab3aec-06f6-4659-bf38-5b112b8d7e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093576507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4093576507
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1470808426
Short name T373
Test name
Test status
Simulation time 76818266 ps
CPU time 3.25 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 214100 kb
Host smart-13f777a7-6c0b-42cc-b872-57f6b78c0e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470808426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1470808426
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.165587457
Short name T117
Test name
Test status
Simulation time 177359369 ps
CPU time 4.09 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 214300 kb
Host smart-e22f8e9f-d1f6-4df2-bb53-487634aef797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165587457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.165587457
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2313891003
Short name T237
Test name
Test status
Simulation time 98815875 ps
CPU time 4.39 seconds
Started Jun 27 04:47:33 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 214376 kb
Host smart-bcb172d9-7080-4a52-951e-9cc52e2294fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313891003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2313891003
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4278371698
Short name T379
Test name
Test status
Simulation time 117187397 ps
CPU time 3.77 seconds
Started Jun 27 04:47:35 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 221488 kb
Host smart-e24c9f48-a26a-468d-a84f-8f0131647f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278371698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4278371698
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4095057961
Short name T150
Test name
Test status
Simulation time 101517520 ps
CPU time 4.38 seconds
Started Jun 27 04:44:53 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 213652 kb
Host smart-64b6f2d7-3ff4-4604-8dfb-245c0483808c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095057961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4095057961
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.819983837
Short name T177
Test name
Test status
Simulation time 77487117 ps
CPU time 3.34 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:05 PM PDT 24
Peak memory 213620 kb
Host smart-5595cdcc-7233-4043-b353-edd111bd3878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819983837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.819983837
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.384970313
Short name T168
Test name
Test status
Simulation time 2109153027 ps
CPU time 10.34 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 213580 kb
Host smart-916da289-7c38-4064-a14c-f3b7969da9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384970313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.384970313
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2456274955
Short name T176
Test name
Test status
Simulation time 186805240 ps
CPU time 2.53 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205400 kb
Host smart-ae58d6be-9e81-4001-965e-c1ef6ac79598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456274955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2456274955
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.355819301
Short name T160
Test name
Test status
Simulation time 134491972 ps
CPU time 5.02 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:45:00 PM PDT 24
Peak memory 213780 kb
Host smart-16bdb2d9-199a-4167-bb8f-752e0db9bffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355819301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
355819301
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3389200423
Short name T143
Test name
Test status
Simulation time 107035776 ps
CPU time 3.35 seconds
Started Jun 27 04:48:14 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 222524 kb
Host smart-3e81aa24-6676-4352-8294-6ca740a9b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389200423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3389200423
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3950957506
Short name T853
Test name
Test status
Simulation time 183737412 ps
CPU time 3.12 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:45:45 PM PDT 24
Peak memory 220196 kb
Host smart-226f70a0-a220-47e8-9f0b-b66bdef7a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950957506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3950957506
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3875628529
Short name T299
Test name
Test status
Simulation time 543916736 ps
CPU time 13.89 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:54 PM PDT 24
Peak memory 222064 kb
Host smart-1cf896f8-f54c-489b-b034-573f88f4ead5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875628529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3875628529
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.337502324
Short name T793
Test name
Test status
Simulation time 465319827 ps
CPU time 8.48 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 219344 kb
Host smart-6ba0f06f-2cc2-4c64-8d96-d987c6235b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337502324 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.337502324
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4110034017
Short name T684
Test name
Test status
Simulation time 2037395970 ps
CPU time 37.05 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:46:19 PM PDT 24
Peak memory 209096 kb
Host smart-6808428f-2785-4ebc-8d2b-1eee7284c02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110034017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4110034017
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4143125700
Short name T182
Test name
Test status
Simulation time 2019373762 ps
CPU time 18.46 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 208172 kb
Host smart-03ae29a1-527d-4e64-b0f2-6a66b2360a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143125700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4143125700
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3990968332
Short name T498
Test name
Test status
Simulation time 80810069 ps
CPU time 1.74 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 206808 kb
Host smart-bacb51ab-2b13-4125-8f74-f70503246aa3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990968332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3990968332
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.447559413
Short name T227
Test name
Test status
Simulation time 247343993 ps
CPU time 3.02 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 214212 kb
Host smart-2ef604ed-0498-4b66-976c-77869bb82a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447559413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.447559413
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3485253325
Short name T224
Test name
Test status
Simulation time 637733357 ps
CPU time 3.19 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 219936 kb
Host smart-0f3c56da-7572-465c-9237-4c36b2ca74ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485253325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3485253325
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2841218477
Short name T58
Test name
Test status
Simulation time 1102892406 ps
CPU time 13.7 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:57 PM PDT 24
Peak memory 208660 kb
Host smart-7fe0c9be-45dc-40c2-8adc-267eb3d7f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841218477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2841218477
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2020701677
Short name T351
Test name
Test status
Simulation time 82742037 ps
CPU time 1.75 seconds
Started Jun 27 04:46:51 PM PDT 24
Finished Jun 27 04:47:02 PM PDT 24
Peak memory 214328 kb
Host smart-fa4d8e6e-7074-4b51-863e-d68ae0cd5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020701677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2020701677
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.434268627
Short name T236
Test name
Test status
Simulation time 355422185 ps
CPU time 13.26 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:52 PM PDT 24
Peak memory 221336 kb
Host smart-da39d6c8-08d6-4424-b1a9-f2f0abace85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434268627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.434268627
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1462246251
Short name T418
Test name
Test status
Simulation time 529105543 ps
CPU time 7.06 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 214932 kb
Host smart-8be57628-d99d-4147-ad4d-c60424cd99ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462246251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1462246251
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1130797010
Short name T51
Test name
Test status
Simulation time 164212988 ps
CPU time 2.85 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 221824 kb
Host smart-8614fee4-08ac-47bd-8a71-721b301b6405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130797010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1130797010
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.189357603
Short name T349
Test name
Test status
Simulation time 101680530 ps
CPU time 2.05 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 222480 kb
Host smart-0fde824f-a640-42ad-8b7f-93533a9900c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189357603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.189357603
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.117412378
Short name T252
Test name
Test status
Simulation time 607961815 ps
CPU time 4.01 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 214412 kb
Host smart-ab8cf1ea-5e0d-4da1-976f-95ddb54a7ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117412378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.117412378
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2979003300
Short name T318
Test name
Test status
Simulation time 246518604 ps
CPU time 4.31 seconds
Started Jun 27 04:47:01 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 215248 kb
Host smart-6a5dcafd-a93d-4ec6-ad80-8d45dfa19b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979003300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2979003300
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.623735906
Short name T340
Test name
Test status
Simulation time 2311129141 ps
CPU time 11.99 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 215292 kb
Host smart-3df3942f-92f4-4991-8107-af240538b022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623735906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.623735906
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2283580231
Short name T330
Test name
Test status
Simulation time 142529996 ps
CPU time 4.67 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 214268 kb
Host smart-df8c37b1-8c6e-4267-bf81-26a0f9654e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283580231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2283580231
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2723709602
Short name T368
Test name
Test status
Simulation time 377695577 ps
CPU time 3.56 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 214200 kb
Host smart-d1f99ee4-2c11-4149-a74d-d3f76721b5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723709602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2723709602
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2154161698
Short name T18
Test name
Test status
Simulation time 822146491 ps
CPU time 18.18 seconds
Started Jun 27 04:48:01 PM PDT 24
Finished Jun 27 04:48:21 PM PDT 24
Peak memory 214364 kb
Host smart-c4e0e472-0212-4277-9dda-a74a1a42965e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154161698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2154161698
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2477371441
Short name T133
Test name
Test status
Simulation time 274203433 ps
CPU time 4.82 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205472 kb
Host smart-31375e54-a243-4f0b-ac8a-e9c7c602028d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477371441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
477371441
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3724666613
Short name T940
Test name
Test status
Simulation time 1283810704 ps
CPU time 16.55 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 205552 kb
Host smart-91cc11bc-910a-4119-ad5c-3d817b8808dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724666613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
724666613
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.327416724
Short name T1041
Test name
Test status
Simulation time 40116130 ps
CPU time 0.87 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205416 kb
Host smart-4fd7d129-ad31-421e-a686-9d4dc988382e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327416724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.327416724
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3494418044
Short name T977
Test name
Test status
Simulation time 28620027 ps
CPU time 1.12 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 205476 kb
Host smart-37d99142-9371-45d9-825d-ca0b27d76ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494418044 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3494418044
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.655875722
Short name T986
Test name
Test status
Simulation time 135554800 ps
CPU time 1.04 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 205444 kb
Host smart-c88f1e1d-b94b-4ca2-b2d1-d038d33d473f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655875722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.655875722
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3135816436
Short name T945
Test name
Test status
Simulation time 33846549 ps
CPU time 0.7 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:45 PM PDT 24
Peak memory 205352 kb
Host smart-a42660af-322c-44e6-bbea-2ac1cbede103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135816436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3135816436
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1680572854
Short name T1044
Test name
Test status
Simulation time 34525916 ps
CPU time 2.04 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 205436 kb
Host smart-b1feaae0-0127-4955-b0ab-a27fdbb00033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680572854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1680572854
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2902661198
Short name T1059
Test name
Test status
Simulation time 1928301886 ps
CPU time 3.57 seconds
Started Jun 27 04:44:33 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 214028 kb
Host smart-d45ed3eb-7964-4e0a-8867-9338b33fe6a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902661198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2902661198
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.22857104
Short name T1029
Test name
Test status
Simulation time 485275470 ps
CPU time 10.08 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:45:04 PM PDT 24
Peak memory 213936 kb
Host smart-91a3b3ed-d54c-4d08-801a-bfcf3d6c7d06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_shadow_reg_errors_with_csr_rw.22857104
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4188109334
Short name T950
Test name
Test status
Simulation time 405350795 ps
CPU time 4.37 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 216612 kb
Host smart-fb6c1e24-f224-452f-a2aa-9600c8f1b796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188109334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4188109334
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3213366169
Short name T174
Test name
Test status
Simulation time 1050328038 ps
CPU time 4.2 seconds
Started Jun 27 04:44:45 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 213680 kb
Host smart-fd34b136-870a-4923-b4a6-f978ee5f273b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213366169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3213366169
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4072335213
Short name T157
Test name
Test status
Simulation time 231692240 ps
CPU time 4.9 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205352 kb
Host smart-ec14c2d8-8595-47d5-abfa-c0b904d9fb26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072335213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
072335213
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4219186362
Short name T943
Test name
Test status
Simulation time 6586663946 ps
CPU time 26.52 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:45:20 PM PDT 24
Peak memory 205540 kb
Host smart-a3733a37-e73f-46d8-84b2-1c7a1d2ba684
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219186362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
219186362
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3370706094
Short name T1020
Test name
Test status
Simulation time 109791541 ps
CPU time 1.36 seconds
Started Jun 27 04:44:42 PM PDT 24
Finished Jun 27 04:44:44 PM PDT 24
Peak memory 205392 kb
Host smart-95a3d93a-420f-4293-bdd6-3e222acad3dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370706094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
370706094
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2771328962
Short name T1064
Test name
Test status
Simulation time 18249333 ps
CPU time 1.3 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 221816 kb
Host smart-ce6c5ae0-6c45-4c7e-9972-89e6f3267996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771328962 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2771328962
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2473433999
Short name T1031
Test name
Test status
Simulation time 21202411 ps
CPU time 0.88 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 205444 kb
Host smart-4957352c-14ea-4d47-aa47-0b2edeb302fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473433999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2473433999
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2865497246
Short name T1023
Test name
Test status
Simulation time 25711719 ps
CPU time 0.73 seconds
Started Jun 27 04:44:44 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 205336 kb
Host smart-91235ca2-0302-4eaa-bdc7-18c107ca64ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865497246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2865497246
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.453548557
Short name T952
Test name
Test status
Simulation time 170954411 ps
CPU time 1.99 seconds
Started Jun 27 04:44:52 PM PDT 24
Finished Jun 27 04:44:59 PM PDT 24
Peak memory 205440 kb
Host smart-302f6e90-57b1-4e1a-a808-97e94e86b401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453548557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.453548557
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.817482430
Short name T1077
Test name
Test status
Simulation time 216998682 ps
CPU time 1.89 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 213792 kb
Host smart-8432d107-402c-4c8e-a02d-f19df8e9c1d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817482430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.817482430
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2372916330
Short name T978
Test name
Test status
Simulation time 307422770 ps
CPU time 6.94 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:45:00 PM PDT 24
Peak memory 213980 kb
Host smart-972b9e6e-8692-4ca5-813c-7be7f2030c01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372916330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2372916330
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1813229900
Short name T934
Test name
Test status
Simulation time 105145028 ps
CPU time 3.41 seconds
Started Jun 27 04:44:40 PM PDT 24
Finished Jun 27 04:44:45 PM PDT 24
Peak memory 213684 kb
Host smart-bc07d019-14c7-4bfc-95f6-1a9fdf22cf64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813229900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1813229900
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1478046020
Short name T971
Test name
Test status
Simulation time 15623448 ps
CPU time 1.28 seconds
Started Jun 27 04:44:45 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 205508 kb
Host smart-2bc9d952-520a-40be-8daa-3152a5879ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478046020 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1478046020
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3826046770
Short name T1066
Test name
Test status
Simulation time 13750937 ps
CPU time 1.22 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205464 kb
Host smart-0975c567-634b-4863-8bbd-47417e93b194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826046770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3826046770
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4111075439
Short name T1068
Test name
Test status
Simulation time 11966993 ps
CPU time 0.71 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:55 PM PDT 24
Peak memory 205388 kb
Host smart-e00d4b8c-2f84-47bc-a68d-b55a1d76aa41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111075439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4111075439
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2885353085
Short name T976
Test name
Test status
Simulation time 85947365 ps
CPU time 2.1 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205444 kb
Host smart-994825fe-32d0-4b00-ba99-6773774cb99c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885353085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2885353085
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3499511979
Short name T1057
Test name
Test status
Simulation time 117791638 ps
CPU time 3.22 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:55 PM PDT 24
Peak memory 218964 kb
Host smart-14f95487-342f-45b2-bdb7-c1d5e3b3371f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499511979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3499511979
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.743344453
Short name T1053
Test name
Test status
Simulation time 1488392602 ps
CPU time 13.48 seconds
Started Jun 27 04:44:52 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 214184 kb
Host smart-1185685a-f005-4b5c-96b9-040e8e03a605
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743344453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.743344453
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2251292134
Short name T949
Test name
Test status
Simulation time 71034406 ps
CPU time 2.88 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 213732 kb
Host smart-bd379468-cc9d-4c65-a54c-049a75cdf5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251292134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2251292134
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3603766094
Short name T167
Test name
Test status
Simulation time 128366331 ps
CPU time 3.9 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 213660 kb
Host smart-becddb14-49c2-4822-8e9a-463070a69904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603766094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3603766094
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3672373585
Short name T1054
Test name
Test status
Simulation time 58970248 ps
CPU time 1.96 seconds
Started Jun 27 04:44:57 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 213776 kb
Host smart-f2d0f771-d741-4841-8a02-9cb73231047c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672373585 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3672373585
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1961184794
Short name T967
Test name
Test status
Simulation time 122913832 ps
CPU time 1.55 seconds
Started Jun 27 04:44:45 PM PDT 24
Finished Jun 27 04:44:50 PM PDT 24
Peak memory 205496 kb
Host smart-789e9cdb-9184-4742-8a4a-e84edb8cfa68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961184794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1961184794
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4246900238
Short name T980
Test name
Test status
Simulation time 22353665 ps
CPU time 0.75 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:45 PM PDT 24
Peak memory 205272 kb
Host smart-eed9790b-702a-4ce7-9ab0-1a70f4b3a2bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246900238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4246900238
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1817753596
Short name T136
Test name
Test status
Simulation time 87219512 ps
CPU time 2.55 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:04 PM PDT 24
Peak memory 205604 kb
Host smart-0f3230bd-459a-47ce-918c-69ad704d8b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817753596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1817753596
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3217546115
Short name T116
Test name
Test status
Simulation time 463149937 ps
CPU time 4.01 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 213748 kb
Host smart-3410358e-7c79-4d6d-80c9-b0f9fa1b8b17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217546115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3217546115
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1077792900
Short name T992
Test name
Test status
Simulation time 80360721 ps
CPU time 3.02 seconds
Started Jun 27 04:44:52 PM PDT 24
Finished Jun 27 04:45:00 PM PDT 24
Peak memory 215480 kb
Host smart-ee846678-d9cb-4d5e-aa74-ee94f17c1899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077792900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1077792900
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1133701483
Short name T164
Test name
Test status
Simulation time 267877147 ps
CPU time 6.12 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 205320 kb
Host smart-520303f7-52d2-490b-904d-e146c62f56f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133701483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1133701483
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3107945431
Short name T928
Test name
Test status
Simulation time 111714562 ps
CPU time 1.05 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205496 kb
Host smart-5eec8ede-89df-4e4a-af09-ce33be2a3636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107945431 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3107945431
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2383199792
Short name T1076
Test name
Test status
Simulation time 116414783 ps
CPU time 1.6 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205392 kb
Host smart-0cdf71c6-5ab7-4788-be1f-7ad5fad595ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383199792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2383199792
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.995764006
Short name T987
Test name
Test status
Simulation time 55434240 ps
CPU time 0.78 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 205272 kb
Host smart-4835b9a4-abc3-4c21-82fb-c960c7d3082b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995764006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.995764006
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.691458045
Short name T1079
Test name
Test status
Simulation time 878624917 ps
CPU time 1.98 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205496 kb
Host smart-ad15d33c-e694-41f8-86ba-65c86b906848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691458045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.691458045
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1425766387
Short name T962
Test name
Test status
Simulation time 164876800 ps
CPU time 1.86 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 218320 kb
Host smart-c470ef07-784e-4512-8420-8d2d12a772b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425766387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1425766387
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.529207759
Short name T936
Test name
Test status
Simulation time 413912148 ps
CPU time 5.25 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 213884 kb
Host smart-82dafda6-e77b-4e37-b5f3-e20d7c959117
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529207759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.529207759
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1951734377
Short name T957
Test name
Test status
Simulation time 290659889 ps
CPU time 2.23 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213756 kb
Host smart-0d968ec6-ccd3-4452-8347-da206cbb5d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951734377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1951734377
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.115698415
Short name T946
Test name
Test status
Simulation time 47143834 ps
CPU time 1.82 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213704 kb
Host smart-ac9e8911-25f8-4a60-bfa0-87aa82925715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115698415 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.115698415
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3975544004
Short name T147
Test name
Test status
Simulation time 110061796 ps
CPU time 1.58 seconds
Started Jun 27 04:45:06 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 205392 kb
Host smart-6bfc649d-dc00-4164-b2b2-cf3c310d5440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975544004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3975544004
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4197676772
Short name T956
Test name
Test status
Simulation time 18682886 ps
CPU time 0.75 seconds
Started Jun 27 04:44:57 PM PDT 24
Finished Jun 27 04:45:00 PM PDT 24
Peak memory 205256 kb
Host smart-0dfb88cf-3d43-4d91-840d-189ea284c5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197676772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4197676772
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2375427552
Short name T1011
Test name
Test status
Simulation time 68659154 ps
CPU time 1.73 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 205484 kb
Host smart-4bb95651-726f-4561-838c-06073258d96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375427552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2375427552
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3663542043
Short name T1069
Test name
Test status
Simulation time 300740109 ps
CPU time 4.29 seconds
Started Jun 27 04:45:09 PM PDT 24
Finished Jun 27 04:45:18 PM PDT 24
Peak memory 213900 kb
Host smart-00b425c1-2411-466a-a043-0a66961685f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663542043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3663542043
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.885459247
Short name T1061
Test name
Test status
Simulation time 1018765711 ps
CPU time 6.04 seconds
Started Jun 27 04:45:07 PM PDT 24
Finished Jun 27 04:45:19 PM PDT 24
Peak memory 213912 kb
Host smart-84b29fad-3ccf-4fb6-b4fa-93f9e14180f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885459247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.885459247
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1626134670
Short name T930
Test name
Test status
Simulation time 50391893 ps
CPU time 2.67 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 213804 kb
Host smart-732e867d-dbb8-4a54-a86a-fca6311bfd92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626134670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1626134670
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2683710067
Short name T1015
Test name
Test status
Simulation time 258331091 ps
CPU time 2.21 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 213780 kb
Host smart-9a5b4de1-800a-48b2-a56c-1e52e7c5ce9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683710067 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2683710067
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.405998880
Short name T137
Test name
Test status
Simulation time 13023261 ps
CPU time 1.11 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:05 PM PDT 24
Peak memory 205384 kb
Host smart-47e12e64-3b90-406b-9e5f-7df05ce583ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405998880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.405998880
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4244969464
Short name T975
Test name
Test status
Simulation time 14334060 ps
CPU time 0.74 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 205368 kb
Host smart-c2716050-b6d4-4d53-96e7-7348f19eec2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244969464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4244969464
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1360258391
Short name T1007
Test name
Test status
Simulation time 67356195 ps
CPU time 2 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 205296 kb
Host smart-2f009a44-4a7b-4f53-a64a-5184900422b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360258391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1360258391
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1468218071
Short name T1009
Test name
Test status
Simulation time 89784050 ps
CPU time 2.91 seconds
Started Jun 27 04:44:58 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 213992 kb
Host smart-c23d1769-a993-42a7-88a2-f10c7e8954ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468218071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1468218071
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3747419743
Short name T1067
Test name
Test status
Simulation time 618058285 ps
CPU time 6.86 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 213952 kb
Host smart-eaa8fe53-c904-4190-89db-a281b5053bc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747419743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3747419743
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4210266218
Short name T925
Test name
Test status
Simulation time 173530903 ps
CPU time 2.44 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:06 PM PDT 24
Peak memory 213644 kb
Host smart-fa87558e-4126-4108-8127-56c788a9d012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210266218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4210266218
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3803519461
Short name T1032
Test name
Test status
Simulation time 788599850 ps
CPU time 2.76 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:06 PM PDT 24
Peak memory 205292 kb
Host smart-a682bdd8-b78b-461b-958f-f383b8a064dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803519461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3803519461
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4223395611
Short name T933
Test name
Test status
Simulation time 96751894 ps
CPU time 1.69 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:06 PM PDT 24
Peak memory 213664 kb
Host smart-f3cc4c4d-851b-40d0-854b-7e63bc6b3be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223395611 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4223395611
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.792932344
Short name T1042
Test name
Test status
Simulation time 14421883 ps
CPU time 0.88 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205296 kb
Host smart-366639a9-e492-4e5d-b3b5-19208d95c587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792932344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.792932344
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4014011769
Short name T1043
Test name
Test status
Simulation time 11201620 ps
CPU time 0.86 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:04 PM PDT 24
Peak memory 205196 kb
Host smart-ef26cc7c-de16-4fbc-802a-a30c432d3b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014011769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4014011769
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2930056292
Short name T947
Test name
Test status
Simulation time 87557404 ps
CPU time 2.78 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 205524 kb
Host smart-6950c168-d1c7-4ea8-a852-7f107a7d86ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930056292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2930056292
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1747467278
Short name T942
Test name
Test status
Simulation time 84065676 ps
CPU time 2.74 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 213956 kb
Host smart-f4f6276a-7f1d-41cb-ab45-ef817beab059
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747467278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1747467278
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2669993034
Short name T935
Test name
Test status
Simulation time 463507367 ps
CPU time 12.76 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 213836 kb
Host smart-7c1f34d6-32da-44d3-9e7f-c8ddd7e81a8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669993034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2669993034
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2837925249
Short name T981
Test name
Test status
Simulation time 899997758 ps
CPU time 5.35 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:17 PM PDT 24
Peak memory 216068 kb
Host smart-e4e1387b-3220-41dc-b8f3-76a89ef4a9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837925249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2837925249
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1872447838
Short name T924
Test name
Test status
Simulation time 37746610 ps
CPU time 1.98 seconds
Started Jun 27 04:44:58 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 213792 kb
Host smart-5b795291-762b-4c80-a8c7-8e359156139c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872447838 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1872447838
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.72190294
Short name T966
Test name
Test status
Simulation time 46393794 ps
CPU time 1.15 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 205576 kb
Host smart-fc1f40f7-444c-4155-9868-ba7c57196bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72190294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.72190294
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1921925207
Short name T932
Test name
Test status
Simulation time 17752031 ps
CPU time 0.82 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 205208 kb
Host smart-57916d75-1557-4528-9f54-baf1543e8cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921925207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1921925207
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2273160417
Short name T972
Test name
Test status
Simulation time 205499496 ps
CPU time 1.71 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:06 PM PDT 24
Peak memory 205420 kb
Host smart-849bed5b-b2bc-49ea-a50a-256abf7e84b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273160417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2273160417
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1166848008
Short name T951
Test name
Test status
Simulation time 106510216 ps
CPU time 2.46 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213948 kb
Host smart-1876644b-f871-4583-a2be-a82ae924cb2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166848008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1166848008
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3148483056
Short name T953
Test name
Test status
Simulation time 1828372281 ps
CPU time 12.9 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 213928 kb
Host smart-e7a1b55c-9ad6-4eee-af3e-eeaa70a1364e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148483056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3148483056
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3614678511
Short name T999
Test name
Test status
Simulation time 161405718 ps
CPU time 3.74 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213684 kb
Host smart-3804c97b-0454-48b8-9431-53244736bb3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614678511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3614678511
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1210433585
Short name T1073
Test name
Test status
Simulation time 530731297 ps
CPU time 5.21 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213468 kb
Host smart-6a596ec8-58eb-4e21-a2ef-ca50af602a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210433585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1210433585
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1895498917
Short name T968
Test name
Test status
Simulation time 79884128 ps
CPU time 1.24 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:06 PM PDT 24
Peak memory 205432 kb
Host smart-ad16a233-a9e0-4701-9e80-b34f03dfcb6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895498917 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1895498917
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.661844721
Short name T1035
Test name
Test status
Simulation time 13014440 ps
CPU time 1.19 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:05 PM PDT 24
Peak memory 205416 kb
Host smart-56dbf922-0386-4370-8601-7dfbdff8285f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661844721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.661844721
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4238327753
Short name T982
Test name
Test status
Simulation time 16357801 ps
CPU time 0.74 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205208 kb
Host smart-86b14778-0efe-4682-bcd3-f23dca6d19d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238327753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4238327753
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3595025735
Short name T1074
Test name
Test status
Simulation time 338192323 ps
CPU time 2.4 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205500 kb
Host smart-40c33439-5d0d-4d4a-8566-ebfc5be420f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595025735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3595025735
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.410631267
Short name T1030
Test name
Test status
Simulation time 299124731 ps
CPU time 3.73 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 220320 kb
Host smart-cb0fcdd2-8ebf-4371-8ab8-eb8610d1e2f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410631267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.410631267
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.381453128
Short name T1052
Test name
Test status
Simulation time 60859362 ps
CPU time 3.45 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 213664 kb
Host smart-4ee5c4b1-7792-4616-9632-af2951045e06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381453128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.381453128
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.597593299
Short name T1004
Test name
Test status
Simulation time 32621547 ps
CPU time 1.75 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 213600 kb
Host smart-3da15188-2fbd-493e-9a87-8c5ec97167f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597593299 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.597593299
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.509055177
Short name T1037
Test name
Test status
Simulation time 114543101 ps
CPU time 1.52 seconds
Started Jun 27 04:45:01 PM PDT 24
Finished Jun 27 04:45:06 PM PDT 24
Peak memory 205376 kb
Host smart-e5fda6fc-c493-4ebf-856f-ec4cacc6d0ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509055177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.509055177
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3511627073
Short name T994
Test name
Test status
Simulation time 10558251 ps
CPU time 0.76 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 205400 kb
Host smart-56689554-a443-4890-b69b-f4f6e9ebd5b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511627073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3511627073
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3085353318
Short name T134
Test name
Test status
Simulation time 80304360 ps
CPU time 1.43 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 205468 kb
Host smart-d00a69ad-35be-4dde-8912-5de68e2aa921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085353318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3085353318
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2671674422
Short name T1033
Test name
Test status
Simulation time 324618116 ps
CPU time 4.74 seconds
Started Jun 27 04:45:00 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213976 kb
Host smart-8d983335-1aea-447a-8825-15c2feaedc99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671674422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2671674422
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2869131561
Short name T937
Test name
Test status
Simulation time 2001710658 ps
CPU time 5.55 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 220204 kb
Host smart-f13d1fdf-2a5f-445e-bc5e-7c9320416fbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869131561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2869131561
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3559724247
Short name T1050
Test name
Test status
Simulation time 175681415 ps
CPU time 2.12 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 213712 kb
Host smart-7d324ac6-f961-4a4f-a303-bfce0f1011b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559724247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3559724247
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.336708892
Short name T163
Test name
Test status
Simulation time 207119046 ps
CPU time 6.04 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 214980 kb
Host smart-c9c5de12-340c-4892-aafe-2e54a82ace2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336708892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.336708892
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3342740666
Short name T1056
Test name
Test status
Simulation time 20831917 ps
CPU time 1.35 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 221996 kb
Host smart-796b7e7a-07e8-429c-b006-05828f4a681e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342740666 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3342740666
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1778121239
Short name T135
Test name
Test status
Simulation time 17209118 ps
CPU time 0.91 seconds
Started Jun 27 04:45:06 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205616 kb
Host smart-dc72bea6-d5d3-4935-8f09-cd2d18713306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778121239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1778121239
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2956203806
Short name T998
Test name
Test status
Simulation time 12735253 ps
CPU time 0.75 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 205312 kb
Host smart-c34ba72b-646b-47c1-a606-bc117b4117e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956203806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2956203806
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.201430201
Short name T973
Test name
Test status
Simulation time 396912658 ps
CPU time 2.08 seconds
Started Jun 27 04:45:07 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 205376 kb
Host smart-33133382-7105-421a-bf21-a737c0570eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201430201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.201430201
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.198408177
Short name T115
Test name
Test status
Simulation time 376676663 ps
CPU time 2.12 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 214016 kb
Host smart-3b1f9efc-7293-4341-b259-d2971e8360cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198408177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.198408177
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4273424914
Short name T1026
Test name
Test status
Simulation time 144763337 ps
CPU time 3.77 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:18 PM PDT 24
Peak memory 213928 kb
Host smart-3e3a27bf-789d-42cd-ac23-6c8c02c90f73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273424914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4273424914
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1427012534
Short name T1080
Test name
Test status
Simulation time 150876441 ps
CPU time 2.89 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 215732 kb
Host smart-8be3b32e-de48-4945-9411-7e1c20d6927a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427012534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1427012534
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1747672951
Short name T991
Test name
Test status
Simulation time 931595270 ps
CPU time 4.98 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 205416 kb
Host smart-5710c16a-edd9-4e28-a8e9-a27680b5d7ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747672951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
747672951
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3391950989
Short name T983
Test name
Test status
Simulation time 651717061 ps
CPU time 9.81 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 205320 kb
Host smart-1d28e26d-864e-4c20-890b-89b462e76a9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391950989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
391950989
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4255991571
Short name T1000
Test name
Test status
Simulation time 18246486 ps
CPU time 1.08 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 205484 kb
Host smart-8318fb4f-f61c-4bfa-a4de-90565d192ad9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255991571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
255991571
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2265723464
Short name T1018
Test name
Test status
Simulation time 36880358 ps
CPU time 1.42 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205464 kb
Host smart-b0a61152-357b-4f7f-b022-d7485563cc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265723464 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2265723464
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3962615944
Short name T138
Test name
Test status
Simulation time 122151003 ps
CPU time 1.12 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 205496 kb
Host smart-2f038f57-2955-489c-bf05-39e3de6d6f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962615944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3962615944
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1236507260
Short name T974
Test name
Test status
Simulation time 18441943 ps
CPU time 0.81 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 205312 kb
Host smart-aeebfc08-6a4e-40d7-8188-4958860134ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236507260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1236507260
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.371688938
Short name T1025
Test name
Test status
Simulation time 2333037978 ps
CPU time 2.82 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 205496 kb
Host smart-2f1e1b90-1af5-4a58-9273-d7921db23566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371688938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.371688938
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.597650301
Short name T1010
Test name
Test status
Simulation time 117679198 ps
CPU time 2.74 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:44:59 PM PDT 24
Peak memory 213892 kb
Host smart-19827f48-1520-43a9-91eb-bb533bd61c9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597650301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.597650301
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.713449811
Short name T961
Test name
Test status
Simulation time 149084803 ps
CPU time 4.63 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 214044 kb
Host smart-a5cd9fe5-30dd-40fa-ac5a-8f4da5276ad4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713449811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.713449811
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.570013828
Short name T1027
Test name
Test status
Simulation time 92361546 ps
CPU time 3.17 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 213724 kb
Host smart-3f4b758f-c001-498e-8979-55e0a0ac58c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570013828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.570013828
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1803954052
Short name T954
Test name
Test status
Simulation time 11450845 ps
CPU time 0.84 seconds
Started Jun 27 04:45:06 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205288 kb
Host smart-f0b75568-1dc0-4616-8847-dac4efb8cee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803954052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1803954052
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2289654215
Short name T920
Test name
Test status
Simulation time 25393797 ps
CPU time 0.77 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 205636 kb
Host smart-5c58efd2-7cb6-4c1a-b8c6-acb1e9e622a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289654215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2289654215
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4184060533
Short name T996
Test name
Test status
Simulation time 92264595 ps
CPU time 0.77 seconds
Started Jun 27 04:45:06 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205188 kb
Host smart-4b99ad6b-d8ee-470d-b2cd-e99bbd88992f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184060533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4184060533
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2326269728
Short name T970
Test name
Test status
Simulation time 32744622 ps
CPU time 0.72 seconds
Started Jun 27 04:45:07 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205208 kb
Host smart-d66af884-79a4-49d4-bb82-bf2768192b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326269728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2326269728
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2077686728
Short name T1008
Test name
Test status
Simulation time 31259909 ps
CPU time 0.82 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205636 kb
Host smart-6bd3507a-cb32-40d2-b1b2-6bcb6c624c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077686728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2077686728
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.876939314
Short name T960
Test name
Test status
Simulation time 8436885 ps
CPU time 0.78 seconds
Started Jun 27 04:45:06 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205288 kb
Host smart-399df298-57dc-4335-87ec-39eb0da83b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876939314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.876939314
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2179670227
Short name T990
Test name
Test status
Simulation time 38186893 ps
CPU time 0.77 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205348 kb
Host smart-ed85a48f-be6b-41c5-8bf7-3c6265ef21a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179670227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2179670227
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.232135272
Short name T1006
Test name
Test status
Simulation time 32210368 ps
CPU time 0.74 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205212 kb
Host smart-c845d25f-f47a-4e1d-a49a-e7970d83eb8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232135272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.232135272
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.4225652765
Short name T1024
Test name
Test status
Simulation time 38281868 ps
CPU time 0.81 seconds
Started Jun 27 04:44:59 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 205284 kb
Host smart-a5e53f36-7b6e-4db9-b404-99383016fc6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225652765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.4225652765
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3912116742
Short name T1047
Test name
Test status
Simulation time 42098022 ps
CPU time 0.84 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 205384 kb
Host smart-62b38bcc-5093-4097-9838-0a620bc719fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912116742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3912116742
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2055479551
Short name T984
Test name
Test status
Simulation time 716184497 ps
CPU time 4.44 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 205280 kb
Host smart-01313f8d-8248-44f3-9b8a-de8836859102
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055479551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
055479551
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2064793277
Short name T1083
Test name
Test status
Simulation time 435150223 ps
CPU time 12.16 seconds
Started Jun 27 04:44:41 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 205488 kb
Host smart-4237193c-f50c-480b-8c7d-3a08f57fe1aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064793277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
064793277
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.962864703
Short name T923
Test name
Test status
Simulation time 41549013 ps
CPU time 1.56 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205500 kb
Host smart-0a664738-7cfc-4e1d-bc04-d299dc1f823f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962864703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.962864703
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3158214801
Short name T1045
Test name
Test status
Simulation time 53845714 ps
CPU time 2.03 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 205572 kb
Host smart-57f2f7c7-e303-408a-a953-90082f687c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158214801 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3158214801
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3508962903
Short name T979
Test name
Test status
Simulation time 165815453 ps
CPU time 1.01 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 205360 kb
Host smart-458514e1-7f10-44a7-a7d7-edc8370f5ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508962903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3508962903
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.916440243
Short name T921
Test name
Test status
Simulation time 25402865 ps
CPU time 0.74 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 205288 kb
Host smart-11b0a01e-4f83-4c8e-ba3e-be2c9b92359a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916440243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.916440243
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2784004730
Short name T1062
Test name
Test status
Simulation time 261325298 ps
CPU time 1.59 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:44:58 PM PDT 24
Peak memory 205316 kb
Host smart-bfa69081-1ec4-4d3d-bb0a-08e90306e914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784004730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2784004730
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3777242628
Short name T119
Test name
Test status
Simulation time 127087523 ps
CPU time 2.55 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 213840 kb
Host smart-0ad72cae-c7a2-4e55-979c-06907c9b13bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777242628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3777242628
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2704379121
Short name T1034
Test name
Test status
Simulation time 174773323 ps
CPU time 4.75 seconds
Started Jun 27 04:44:45 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 213920 kb
Host smart-647003fb-8672-4d07-a47f-a8d66e96325f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704379121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2704379121
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2566987150
Short name T922
Test name
Test status
Simulation time 93235984 ps
CPU time 2.36 seconds
Started Jun 27 04:44:38 PM PDT 24
Finished Jun 27 04:44:42 PM PDT 24
Peak memory 213624 kb
Host smart-498df27d-da60-4381-8fff-0b7565250490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566987150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2566987150
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2440133095
Short name T919
Test name
Test status
Simulation time 12632608 ps
CPU time 0.84 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205332 kb
Host smart-097c59ce-d8ba-45ac-8970-2cf364ebb9b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440133095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2440133095
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2699738359
Short name T1058
Test name
Test status
Simulation time 33638894 ps
CPU time 0.76 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205208 kb
Host smart-d0abe915-ad44-4a7c-9e95-978ea1b39f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699738359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2699738359
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3996515879
Short name T1084
Test name
Test status
Simulation time 11473975 ps
CPU time 0.72 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 205388 kb
Host smart-15fa2300-2c5b-49d6-a4d7-df48ff9cd6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996515879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3996515879
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2894519041
Short name T1039
Test name
Test status
Simulation time 14320553 ps
CPU time 0.75 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 205320 kb
Host smart-2b6d281b-3653-41fe-9843-25695f582b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894519041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2894519041
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2330833224
Short name T1021
Test name
Test status
Simulation time 84405625 ps
CPU time 0.77 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205260 kb
Host smart-9a2ede4f-6dab-4f4c-95ef-1a287124c9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330833224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2330833224
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.476466383
Short name T1040
Test name
Test status
Simulation time 87431558 ps
CPU time 0.79 seconds
Started Jun 27 04:45:06 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 205204 kb
Host smart-365e345d-251d-4f40-9f54-c2e5d4ca31eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476466383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.476466383
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4256650262
Short name T1071
Test name
Test status
Simulation time 8776138 ps
CPU time 0.82 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205184 kb
Host smart-b6075c41-4c4f-4066-b342-85ba574d4424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256650262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4256650262
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.787986586
Short name T926
Test name
Test status
Simulation time 9558103 ps
CPU time 0.73 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 205292 kb
Host smart-7ad2ce70-8e54-41ad-bec6-fbd000593eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787986586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.787986586
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1481250767
Short name T944
Test name
Test status
Simulation time 9457831 ps
CPU time 0.71 seconds
Started Jun 27 04:45:09 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 205272 kb
Host smart-956a7a9a-20c1-4164-9cef-6057256d99a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481250767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1481250767
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1608414932
Short name T1051
Test name
Test status
Simulation time 12946537 ps
CPU time 0.69 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205388 kb
Host smart-357b48b5-9fdb-4083-9828-9612b48b2b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608414932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1608414932
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1841485198
Short name T1036
Test name
Test status
Simulation time 73136682 ps
CPU time 4.93 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:49 PM PDT 24
Peak memory 205364 kb
Host smart-c307907c-5009-44ae-b454-4a9bc2fc9dfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841485198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
841485198
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.514185342
Short name T1081
Test name
Test status
Simulation time 523252554 ps
CPU time 12.18 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:45:04 PM PDT 24
Peak memory 205364 kb
Host smart-dc4a52e9-318a-4c83-8031-9dc7a3e289d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514185342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.514185342
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2951972814
Short name T989
Test name
Test status
Simulation time 31664913 ps
CPU time 1.31 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:55 PM PDT 24
Peak memory 205396 kb
Host smart-d13beeaf-8c98-480a-a1f9-e588566ddd31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951972814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
951972814
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1560895292
Short name T1012
Test name
Test status
Simulation time 54338146 ps
CPU time 1.67 seconds
Started Jun 27 04:44:45 PM PDT 24
Finished Jun 27 04:44:51 PM PDT 24
Peak memory 213856 kb
Host smart-beee2d05-b0ce-4bf0-b61a-38428a15bc7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560895292 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1560895292
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1653015859
Short name T401
Test name
Test status
Simulation time 60236021 ps
CPU time 1.1 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 205436 kb
Host smart-625da44b-12d8-4b53-b82f-4405faf0adec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653015859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1653015859
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4241555592
Short name T1075
Test name
Test status
Simulation time 14894590 ps
CPU time 0.72 seconds
Started Jun 27 04:44:44 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 205224 kb
Host smart-47591356-be6a-4c74-a56c-2b4dfe814891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241555592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4241555592
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1573725390
Short name T1072
Test name
Test status
Simulation time 347487132 ps
CPU time 3.71 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:45:00 PM PDT 24
Peak memory 205324 kb
Host smart-ab7d4a95-eb13-4b14-88e0-a2007f39d157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573725390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1573725390
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.430931479
Short name T985
Test name
Test status
Simulation time 151225587 ps
CPU time 2.92 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 213972 kb
Host smart-e07f021b-eb50-499d-a3c9-ba3ce58ee15e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430931479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.430931479
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.392126505
Short name T1028
Test name
Test status
Simulation time 881464323 ps
CPU time 8.01 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 214060 kb
Host smart-82f45b6f-9a78-4755-a1ba-ff3988a4d8a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392126505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.392126505
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2994103321
Short name T1005
Test name
Test status
Simulation time 29536324 ps
CPU time 1.73 seconds
Started Jun 27 04:44:44 PM PDT 24
Finished Jun 27 04:44:47 PM PDT 24
Peak memory 213732 kb
Host smart-32c5cf66-60a7-4f08-bddd-b293e98c2a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994103321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2994103321
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3976475523
Short name T149
Test name
Test status
Simulation time 816498646 ps
CPU time 6.24 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 213584 kb
Host smart-52e0ed6c-7b90-490c-9d9b-097ebecde2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976475523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3976475523
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4018443426
Short name T929
Test name
Test status
Simulation time 31186284 ps
CPU time 0.82 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 205352 kb
Host smart-66c31608-08bf-4927-9cd3-c69bd2a833bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018443426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4018443426
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3771137150
Short name T997
Test name
Test status
Simulation time 18585136 ps
CPU time 0.96 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 205340 kb
Host smart-b92d0327-798d-44ba-a323-93d9b04440e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771137150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3771137150
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3819990400
Short name T927
Test name
Test status
Simulation time 20440983 ps
CPU time 0.79 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 205344 kb
Host smart-2b89cbd1-37c2-4684-94c3-d4510b987433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819990400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3819990400
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2569758521
Short name T958
Test name
Test status
Simulation time 57864435 ps
CPU time 0.91 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 205300 kb
Host smart-68025f33-b794-428b-a847-ff1975d95ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569758521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2569758521
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2872014400
Short name T1022
Test name
Test status
Simulation time 34238706 ps
CPU time 0.81 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 205160 kb
Host smart-3da1023f-e937-4c25-9329-2be84348fe71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872014400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2872014400
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2650200339
Short name T963
Test name
Test status
Simulation time 10316394 ps
CPU time 0.69 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205388 kb
Host smart-1fcdec9c-941a-498b-a551-4e5e014fa046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650200339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2650200339
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.370976593
Short name T1016
Test name
Test status
Simulation time 26871884 ps
CPU time 0.82 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205184 kb
Host smart-6da53400-0689-419c-beb8-833e05ab58f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370976593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.370976593
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4051311811
Short name T1017
Test name
Test status
Simulation time 11704886 ps
CPU time 0.82 seconds
Started Jun 27 04:45:07 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 205272 kb
Host smart-ec4d1d83-7a1f-419e-86f6-8aa039c8ac7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051311811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4051311811
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3997289291
Short name T964
Test name
Test status
Simulation time 28613020 ps
CPU time 0.7 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 205388 kb
Host smart-1b0f050c-bed8-4a09-8d36-ed538ba0751b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997289291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3997289291
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1923906704
Short name T938
Test name
Test status
Simulation time 11893922 ps
CPU time 0.73 seconds
Started Jun 27 04:45:04 PM PDT 24
Finished Jun 27 04:45:11 PM PDT 24
Peak memory 205248 kb
Host smart-f4947f29-a527-474a-8d13-1b1bd00db95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923906704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1923906704
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.354303921
Short name T1001
Test name
Test status
Simulation time 44824585 ps
CPU time 1.39 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 213668 kb
Host smart-7204f6d5-0634-41ef-b531-e1819ed09bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354303921 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.354303921
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3374434111
Short name T1070
Test name
Test status
Simulation time 51724240 ps
CPU time 0.97 seconds
Started Jun 27 04:44:41 PM PDT 24
Finished Jun 27 04:44:43 PM PDT 24
Peak memory 205428 kb
Host smart-616f0c74-282f-4783-90fd-95c596b96ac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374434111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3374434111
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1760861653
Short name T965
Test name
Test status
Simulation time 54664010 ps
CPU time 0.73 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 205204 kb
Host smart-f16f0ae7-fb72-4b16-a52a-953ac3c7eb8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760861653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1760861653
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3017538973
Short name T1019
Test name
Test status
Simulation time 66506935 ps
CPU time 2.56 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 205512 kb
Host smart-e990c195-faed-4d3c-a908-ab4b0e1420ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017538973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3017538973
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.368336885
Short name T1003
Test name
Test status
Simulation time 52458371 ps
CPU time 1.74 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 214044 kb
Host smart-b6caf97f-c724-40d5-82bf-37746ef03b17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368336885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.368336885
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3354547941
Short name T1078
Test name
Test status
Simulation time 1257576605 ps
CPU time 9.63 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:45:04 PM PDT 24
Peak memory 220152 kb
Host smart-19587cd3-27f8-4071-a476-fcb6cdeb2e57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354547941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3354547941
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2377386793
Short name T1063
Test name
Test status
Simulation time 110481798 ps
CPU time 2.67 seconds
Started Jun 27 04:44:45 PM PDT 24
Finished Jun 27 04:44:51 PM PDT 24
Peak memory 213672 kb
Host smart-ef448a53-95ae-4736-bc1a-30c0b6982a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377386793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2377386793
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2000822144
Short name T995
Test name
Test status
Simulation time 981249044 ps
CPU time 4.12 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:49 PM PDT 24
Peak memory 205440 kb
Host smart-922f52e9-bd0c-43c7-9aad-9472d06124ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000822144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2000822144
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1994403074
Short name T158
Test name
Test status
Simulation time 379472543 ps
CPU time 1.77 seconds
Started Jun 27 04:44:44 PM PDT 24
Finished Jun 27 04:44:50 PM PDT 24
Peak memory 213716 kb
Host smart-0f3fc30d-1698-4d3a-ada5-fb5b36854302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994403074 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1994403074
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.406898211
Short name T941
Test name
Test status
Simulation time 449736296 ps
CPU time 1.51 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205480 kb
Host smart-203f08f5-ef89-44e7-be49-c5841c0e01e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406898211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.406898211
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3661170345
Short name T1085
Test name
Test status
Simulation time 37904407 ps
CPU time 0.87 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205336 kb
Host smart-1c5361df-5b72-4f65-9c9e-795c5800c964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661170345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3661170345
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3104716911
Short name T1065
Test name
Test status
Simulation time 96814056 ps
CPU time 1.67 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205368 kb
Host smart-f94bb53c-f488-445e-8775-aa4fde643b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104716911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3104716911
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4224174270
Short name T1060
Test name
Test status
Simulation time 298621572 ps
CPU time 1.8 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 213968 kb
Host smart-1ba92234-1e7f-46fe-acaa-1e390187fdfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224174270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4224174270
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1155291179
Short name T188
Test name
Test status
Simulation time 778534285 ps
CPU time 3.74 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 215620 kb
Host smart-63c6fb60-2247-4663-9a0b-0d8c4caaa8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155291179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1155291179
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.115657367
Short name T1002
Test name
Test status
Simulation time 15719481 ps
CPU time 1.2 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205588 kb
Host smart-7d8b491b-2b76-48aa-851a-1fcd38ad5018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115657367 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.115657367
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2470096390
Short name T1048
Test name
Test status
Simulation time 24722908 ps
CPU time 0.99 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205376 kb
Host smart-37012ad7-2f77-464a-a959-f146f2fafc0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470096390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2470096390
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2581417035
Short name T993
Test name
Test status
Simulation time 24542600 ps
CPU time 0.85 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205312 kb
Host smart-9e7bfb24-f912-4261-879e-17d01ec47de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581417035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2581417035
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2418279874
Short name T969
Test name
Test status
Simulation time 105647984 ps
CPU time 1.45 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 205304 kb
Host smart-6368710f-9224-4e90-a97a-a90fc2c91534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418279874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2418279874
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2996139504
Short name T121
Test name
Test status
Simulation time 72344392 ps
CPU time 1.68 seconds
Started Jun 27 04:44:44 PM PDT 24
Finished Jun 27 04:44:49 PM PDT 24
Peak memory 213780 kb
Host smart-6d925107-1cd7-48dc-bd5a-8adfb88ea61e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996139504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2996139504
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2851514284
Short name T112
Test name
Test status
Simulation time 182212355 ps
CPU time 6.75 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:45:02 PM PDT 24
Peak memory 214060 kb
Host smart-bcfaa389-3438-482d-9d50-b691581a0931
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851514284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2851514284
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2330646426
Short name T959
Test name
Test status
Simulation time 127320074 ps
CPU time 3.04 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:44:59 PM PDT 24
Peak memory 213792 kb
Host smart-1ce514a5-9366-463e-8957-ef6e92768101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330646426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2330646426
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.467458711
Short name T939
Test name
Test status
Simulation time 175114212 ps
CPU time 1.55 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 213604 kb
Host smart-76688171-edda-4295-96fb-e7b4e7d29fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467458711 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.467458711
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3616785946
Short name T948
Test name
Test status
Simulation time 484067791 ps
CPU time 1.39 seconds
Started Jun 27 04:44:52 PM PDT 24
Finished Jun 27 04:44:58 PM PDT 24
Peak memory 205740 kb
Host smart-d5fbbc77-a16d-448e-b219-e59efd151e62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616785946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3616785946
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2967822394
Short name T1038
Test name
Test status
Simulation time 10614649 ps
CPU time 0.81 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 205172 kb
Host smart-7d16ad00-ede2-4c8b-b858-7ff3b26d094a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967822394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2967822394
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.676427321
Short name T1014
Test name
Test status
Simulation time 184298026 ps
CPU time 3.53 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 205472 kb
Host smart-82b10255-3ee1-4e8d-b5e6-8d31a7912c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676427321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.676427321
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2645960708
Short name T955
Test name
Test status
Simulation time 303370293 ps
CPU time 2.13 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:58 PM PDT 24
Peak memory 213824 kb
Host smart-27633186-4962-469d-bdc6-ba7bf091a7e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645960708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2645960708
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.339551167
Short name T120
Test name
Test status
Simulation time 603109516 ps
CPU time 8.42 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 213760 kb
Host smart-32d3630a-c3da-40ac-8a83-058689d2da11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339551167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.339551167
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1065085021
Short name T1013
Test name
Test status
Simulation time 24828789 ps
CPU time 1.66 seconds
Started Jun 27 04:44:50 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 213736 kb
Host smart-b999ecac-29e0-43ed-9ec9-5cafbf9aaee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065085021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1065085021
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3669065541
Short name T148
Test name
Test status
Simulation time 749502144 ps
CPU time 8.3 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 213624 kb
Host smart-3096a927-2543-4d24-af1b-e2610a9db6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669065541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3669065541
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1219623606
Short name T988
Test name
Test status
Simulation time 88715769 ps
CPU time 2.13 seconds
Started Jun 27 04:44:52 PM PDT 24
Finished Jun 27 04:44:59 PM PDT 24
Peak memory 214036 kb
Host smart-b2110b8e-8a40-45b5-8e29-bedb8e828d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219623606 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1219623606
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3523820642
Short name T1049
Test name
Test status
Simulation time 24423376 ps
CPU time 1.03 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:51 PM PDT 24
Peak memory 205476 kb
Host smart-eb672f09-2303-4474-903e-ad246a5ce823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523820642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3523820642
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4041905358
Short name T1055
Test name
Test status
Simulation time 34252674 ps
CPU time 0.71 seconds
Started Jun 27 04:44:51 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 205372 kb
Host smart-0f7c470b-dd38-42cb-9f11-f5e99c0d7f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041905358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4041905358
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1504754160
Short name T139
Test name
Test status
Simulation time 23395045 ps
CPU time 1.74 seconds
Started Jun 27 04:44:46 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 205512 kb
Host smart-3dcda688-afca-426c-a28d-7140f62f2d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504754160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1504754160
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4032355391
Short name T1082
Test name
Test status
Simulation time 172573024 ps
CPU time 4.86 seconds
Started Jun 27 04:44:48 PM PDT 24
Finished Jun 27 04:44:58 PM PDT 24
Peak memory 214012 kb
Host smart-8591a21b-e727-4882-83a9-15ee72fee95d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032355391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4032355391
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2095617853
Short name T1046
Test name
Test status
Simulation time 662561807 ps
CPU time 6.59 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:59 PM PDT 24
Peak memory 213844 kb
Host smart-e3f03d32-13a4-4369-a85b-bd0edea04f79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095617853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2095617853
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3761268461
Short name T931
Test name
Test status
Simulation time 109990668 ps
CPU time 4.06 seconds
Started Jun 27 04:44:49 PM PDT 24
Finished Jun 27 04:44:58 PM PDT 24
Peak memory 213620 kb
Host smart-9871d165-4846-475e-a4f4-93b6f729b0af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761268461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3761268461
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1545192567
Short name T397
Test name
Test status
Simulation time 212521115 ps
CPU time 3.49 seconds
Started Jun 27 04:44:47 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 214508 kb
Host smart-0c353046-71e7-4108-a18c-fb260cd84304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545192567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1545192567
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1500116524
Short name T631
Test name
Test status
Simulation time 11116892 ps
CPU time 0.69 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 205904 kb
Host smart-ed585285-9c26-47aa-86c5-7f82144581f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500116524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1500116524
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1481233646
Short name T141
Test name
Test status
Simulation time 107822882 ps
CPU time 2.35 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:48 PM PDT 24
Peak memory 214324 kb
Host smart-3216d6f7-c2d5-41bc-b790-18f2336c2a48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481233646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1481233646
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.621531701
Short name T632
Test name
Test status
Simulation time 143979414 ps
CPU time 5.44 seconds
Started Jun 27 04:45:27 PM PDT 24
Finished Jun 27 04:45:34 PM PDT 24
Peak memory 218252 kb
Host smart-1ec7bce3-638f-4e27-aa10-6ffbbd8aa36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621531701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.621531701
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2052633713
Short name T44
Test name
Test status
Simulation time 187451774 ps
CPU time 2.76 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:48 PM PDT 24
Peak memory 209192 kb
Host smart-bfb9308d-08fe-4500-b096-2a21982b1fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052633713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2052633713
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3121465705
Short name T890
Test name
Test status
Simulation time 485292687 ps
CPU time 4.69 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 214320 kb
Host smart-cdb4b056-3924-45fd-8fc9-5f3bb78751ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121465705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3121465705
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2583899824
Short name T371
Test name
Test status
Simulation time 150805820 ps
CPU time 5.56 seconds
Started Jun 27 04:45:44 PM PDT 24
Finished Jun 27 04:45:53 PM PDT 24
Peak memory 214184 kb
Host smart-f0315b88-520d-441c-bd09-34e175aa5db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583899824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2583899824
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.59550712
Short name T260
Test name
Test status
Simulation time 147331318 ps
CPU time 3.8 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:49 PM PDT 24
Peak memory 209544 kb
Host smart-5a15788d-92db-4ac5-a3c0-dd4352f1bacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59550712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.59550712
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.391658997
Short name T39
Test name
Test status
Simulation time 499426903 ps
CPU time 8.23 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:47 PM PDT 24
Peak memory 236992 kb
Host smart-02129f81-dcd5-4130-a0e9-35f5e780c228
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391658997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.391658997
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3265525938
Short name T619
Test name
Test status
Simulation time 2755255144 ps
CPU time 18.78 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 208596 kb
Host smart-28a142a2-84c3-43c7-9817-49d47543d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265525938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3265525938
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1525075273
Short name T749
Test name
Test status
Simulation time 40315946 ps
CPU time 2.1 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 206936 kb
Host smart-0d64eea7-3274-44d1-b59f-5b0aee315ca8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525075273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1525075273
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3423257453
Short name T785
Test name
Test status
Simulation time 105730261 ps
CPU time 3.32 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 206856 kb
Host smart-819843ba-79ee-4519-976d-cec9df786406
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423257453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3423257453
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2594808809
Short name T447
Test name
Test status
Simulation time 161828374 ps
CPU time 2.43 seconds
Started Jun 27 04:45:28 PM PDT 24
Finished Jun 27 04:45:32 PM PDT 24
Peak memory 209272 kb
Host smart-2a90c8b7-527f-477d-b027-cfe0ab081117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594808809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2594808809
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2740965505
Short name T462
Test name
Test status
Simulation time 40541851 ps
CPU time 2.03 seconds
Started Jun 27 04:45:47 PM PDT 24
Finished Jun 27 04:45:52 PM PDT 24
Peak memory 206116 kb
Host smart-d829ab78-fa5d-43f1-a2ce-632e9e9265f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740965505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2740965505
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2400284831
Short name T259
Test name
Test status
Simulation time 6620916770 ps
CPU time 32.24 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:46:18 PM PDT 24
Peak memory 209696 kb
Host smart-a3246af0-5207-4a09-bf77-a9b160c3f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400284831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2400284831
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4159974861
Short name T56
Test name
Test status
Simulation time 51557657 ps
CPU time 1.74 seconds
Started Jun 27 04:45:44 PM PDT 24
Finished Jun 27 04:45:49 PM PDT 24
Peak memory 209772 kb
Host smart-f75afe02-bda0-4705-b0c4-25e766727020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159974861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4159974861
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1535892475
Short name T826
Test name
Test status
Simulation time 97238118 ps
CPU time 0.72 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:00 PM PDT 24
Peak memory 206052 kb
Host smart-91f3e912-8fce-4682-8a35-78fc735f5cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535892475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1535892475
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3543295042
Short name T405
Test name
Test status
Simulation time 127676927 ps
CPU time 5.3 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 214180 kb
Host smart-8ea3e8ca-74a4-4790-acd2-9528c794ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543295042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3543295042
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2893704496
Short name T75
Test name
Test status
Simulation time 211209935 ps
CPU time 4.69 seconds
Started Jun 27 04:45:33 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 214200 kb
Host smart-5f15143a-afcc-4081-aa34-bb197a1b26a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893704496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2893704496
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2873503171
Short name T94
Test name
Test status
Simulation time 537813523 ps
CPU time 5.92 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 214180 kb
Host smart-939616b8-698b-4481-b9aa-c19571c63066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873503171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2873503171
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1706431635
Short name T306
Test name
Test status
Simulation time 405835236 ps
CPU time 4.45 seconds
Started Jun 27 04:45:33 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 207132 kb
Host smart-1bf0d012-72f8-4378-a4f6-b90716f529bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706431635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1706431635
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1055389137
Short name T63
Test name
Test status
Simulation time 858585996 ps
CPU time 7.67 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:45 PM PDT 24
Peak memory 222344 kb
Host smart-b173efd6-6490-4d6c-92b6-2367d9163984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055389137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1055389137
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1149914557
Short name T622
Test name
Test status
Simulation time 696763475 ps
CPU time 7.6 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:51 PM PDT 24
Peak memory 209312 kb
Host smart-193ddcaf-b708-432f-a466-a87ad5b5d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149914557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1149914557
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2387341732
Short name T205
Test name
Test status
Simulation time 23241819 ps
CPU time 1.82 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 206844 kb
Host smart-17f0605c-42f5-4410-a8b8-1d5cd3526ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387341732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2387341732
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1269326816
Short name T906
Test name
Test status
Simulation time 492183836 ps
CPU time 11.67 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 208932 kb
Host smart-266f636f-ebfa-4fc4-a5a1-840212d4ce69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269326816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1269326816
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2231561210
Short name T850
Test name
Test status
Simulation time 87317736 ps
CPU time 3.66 seconds
Started Jun 27 04:45:44 PM PDT 24
Finished Jun 27 04:45:51 PM PDT 24
Peak memory 208644 kb
Host smart-1c2d214f-955b-4a27-b433-852380aacb6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231561210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2231561210
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3618580811
Short name T439
Test name
Test status
Simulation time 57497085 ps
CPU time 2.44 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 207972 kb
Host smart-06172f4d-8d58-4028-b45d-94c1d572a864
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618580811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3618580811
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3537623912
Short name T681
Test name
Test status
Simulation time 107197720 ps
CPU time 1.9 seconds
Started Jun 27 04:45:33 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 208088 kb
Host smart-55d2c824-96fa-4960-9e9b-b2a6fb6478e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537623912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3537623912
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.958907931
Short name T758
Test name
Test status
Simulation time 120283843 ps
CPU time 3.29 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 206828 kb
Host smart-d66cdebf-7bb2-44df-8734-1cb29d56d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958907931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.958907931
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3851450659
Short name T285
Test name
Test status
Simulation time 3157807920 ps
CPU time 20.61 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:46:01 PM PDT 24
Peak memory 216720 kb
Host smart-82226272-ccc0-404a-882d-930d1114a437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851450659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3851450659
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3572212650
Short name T179
Test name
Test status
Simulation time 248316509 ps
CPU time 8.98 seconds
Started Jun 27 04:45:55 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 218656 kb
Host smart-ad7dd191-fdfd-41b0-8e16-5e555856987d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572212650 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3572212650
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1285667937
Short name T399
Test name
Test status
Simulation time 274825259 ps
CPU time 4.93 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:51 PM PDT 24
Peak memory 210116 kb
Host smart-32a43375-45f4-4cb5-a6be-9fd22735c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285667937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1285667937
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.854627264
Short name T739
Test name
Test status
Simulation time 18999339 ps
CPU time 0.81 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:31 PM PDT 24
Peak memory 206036 kb
Host smart-5d12b071-be1a-4602-81cb-07742c5e32c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854627264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.854627264
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3036328870
Short name T25
Test name
Test status
Simulation time 472907211 ps
CPU time 5.6 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 221816 kb
Host smart-ddfeb420-c479-425b-91f7-0031572f6456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036328870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3036328870
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2224386401
Short name T222
Test name
Test status
Simulation time 96682586 ps
CPU time 2.59 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 209980 kb
Host smart-8032e8ae-b7e0-4167-8fd2-50b334687266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224386401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2224386401
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2503378694
Short name T485
Test name
Test status
Simulation time 286812097 ps
CPU time 3.29 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 208348 kb
Host smart-fc5a1219-ebcd-4ad5-897d-d695d258df91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503378694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2503378694
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2735106027
Short name T838
Test name
Test status
Simulation time 65609037 ps
CPU time 2.69 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 206884 kb
Host smart-095c001d-53dd-4e1e-8963-ad72e271fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735106027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2735106027
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3351750453
Short name T512
Test name
Test status
Simulation time 86417007 ps
CPU time 3.62 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:27 PM PDT 24
Peak memory 208904 kb
Host smart-6019c70d-4f14-46c5-8d4e-4670b31c8389
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351750453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3351750453
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4127783788
Short name T628
Test name
Test status
Simulation time 705927693 ps
CPU time 5.21 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 207988 kb
Host smart-e54790b4-e9ba-4d93-b963-2aad3dd44c7d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127783788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4127783788
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2711889080
Short name T581
Test name
Test status
Simulation time 239826414 ps
CPU time 6.32 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 208044 kb
Host smart-3fed4e79-c400-4bc9-acb7-097a16e96453
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711889080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2711889080
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2095218872
Short name T860
Test name
Test status
Simulation time 1293766480 ps
CPU time 9.23 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 208716 kb
Host smart-4396cee9-0301-496f-9d1c-e889ce791d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095218872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2095218872
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1694787581
Short name T679
Test name
Test status
Simulation time 79916800 ps
CPU time 1.72 seconds
Started Jun 27 04:46:23 PM PDT 24
Finished Jun 27 04:46:27 PM PDT 24
Peak memory 207028 kb
Host smart-41ec394a-9e90-485a-a124-a5d41ab57be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694787581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1694787581
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1505399618
Short name T228
Test name
Test status
Simulation time 1056168534 ps
CPU time 33.18 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 222396 kb
Host smart-b8579f7f-54d2-4aa5-ac30-c6d392da530b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505399618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1505399618
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2047074140
Short name T343
Test name
Test status
Simulation time 222409670 ps
CPU time 5.72 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 214304 kb
Host smart-d7638229-3299-421e-a4e4-5f626e64e3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047074140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2047074140
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1436296012
Short name T417
Test name
Test status
Simulation time 115473523 ps
CPU time 4.09 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 214328 kb
Host smart-ea882d83-077f-4f6e-b858-01d106324969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436296012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1436296012
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2382971501
Short name T792
Test name
Test status
Simulation time 4194751271 ps
CPU time 47.38 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 222776 kb
Host smart-a1d05458-701f-4d58-9aa5-84186872a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382971501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2382971501
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2041555013
Short name T270
Test name
Test status
Simulation time 65744822 ps
CPU time 2.35 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:29 PM PDT 24
Peak memory 218380 kb
Host smart-19014d07-8f89-4003-b539-fed01b2dd4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041555013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2041555013
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3541919503
Short name T356
Test name
Test status
Simulation time 87837456 ps
CPU time 3.44 seconds
Started Jun 27 04:46:20 PM PDT 24
Finished Jun 27 04:46:25 PM PDT 24
Peak memory 222456 kb
Host smart-ca031b4a-bdaa-4eff-88ab-220c6528c681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541919503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3541919503
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.52751803
Short name T381
Test name
Test status
Simulation time 133556531 ps
CPU time 6.3 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 222420 kb
Host smart-d6733360-f5b1-4ca5-bf00-c11a3f73ca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52751803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.52751803
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3908266451
Short name T201
Test name
Test status
Simulation time 233333877 ps
CPU time 3.83 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 214316 kb
Host smart-c87e3290-7234-4ebc-87a4-d781b85dd1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908266451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3908266451
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2284824794
Short name T478
Test name
Test status
Simulation time 320985281 ps
CPU time 3.92 seconds
Started Jun 27 04:46:23 PM PDT 24
Finished Jun 27 04:46:28 PM PDT 24
Peak memory 208860 kb
Host smart-0c32f599-de52-458b-99ff-f87cec31b0ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284824794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2284824794
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1008638702
Short name T305
Test name
Test status
Simulation time 69206662 ps
CPU time 2.81 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:30 PM PDT 24
Peak memory 207984 kb
Host smart-fdfb129f-480e-4407-9354-7dbc24562fc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008638702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1008638702
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3427414781
Short name T275
Test name
Test status
Simulation time 308039436 ps
CPU time 6 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 214260 kb
Host smart-90ec680a-967c-4318-8f56-801a8d22b6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427414781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3427414781
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.81896352
Short name T659
Test name
Test status
Simulation time 73677376 ps
CPU time 2.95 seconds
Started Jun 27 04:46:39 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 208560 kb
Host smart-1d5d6edf-f43b-48e0-bf17-a421ae34d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81896352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.81896352
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1057935730
Short name T530
Test name
Test status
Simulation time 238446505 ps
CPU time 7.88 seconds
Started Jun 27 04:46:23 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 222332 kb
Host smart-8a6accea-cd09-4df2-af1a-4103d95a092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057935730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1057935730
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3650967023
Short name T162
Test name
Test status
Simulation time 58387852 ps
CPU time 1.88 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 209800 kb
Host smart-241c640f-6aac-4d53-9ea5-58d881b1e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650967023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3650967023
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2631260148
Short name T534
Test name
Test status
Simulation time 154262039 ps
CPU time 0.81 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 205876 kb
Host smart-1a9d3b68-a152-49de-9f56-853145bd98cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631260148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2631260148
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2970768158
Short name T523
Test name
Test status
Simulation time 188885646 ps
CPU time 3.69 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:47 PM PDT 24
Peak memory 208792 kb
Host smart-7baabee6-d7f6-41bd-9738-bc54d6520ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970768158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2970768158
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.786135832
Short name T429
Test name
Test status
Simulation time 46125880 ps
CPU time 1.76 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 207692 kb
Host smart-ac34c51b-81d9-4139-8755-9455ec1f4aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786135832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.786135832
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2347518079
Short name T98
Test name
Test status
Simulation time 7945413263 ps
CPU time 49.39 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 209512 kb
Host smart-65b8699b-1a6a-494e-9177-f3b8f9faf1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347518079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2347518079
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3955199383
Short name T266
Test name
Test status
Simulation time 66535780 ps
CPU time 2.4 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 222364 kb
Host smart-e44b1406-1aba-4eea-b56f-fa8c89a57c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955199383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3955199383
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3932285766
Short name T630
Test name
Test status
Simulation time 187290923 ps
CPU time 3.31 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 220484 kb
Host smart-0a06f0d4-b48a-403d-8c00-5d37fb12a447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932285766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3932285766
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.4141585174
Short name T580
Test name
Test status
Simulation time 106650349 ps
CPU time 4.64 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 218388 kb
Host smart-3f79beb5-369a-462b-9ca1-2f7baeb49727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141585174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4141585174
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2961347014
Short name T894
Test name
Test status
Simulation time 138848546 ps
CPU time 3.41 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 206104 kb
Host smart-32e62bd2-d140-4637-9f29-bf12786f1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961347014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2961347014
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2553808807
Short name T197
Test name
Test status
Simulation time 122620437 ps
CPU time 3.88 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:28 PM PDT 24
Peak memory 208292 kb
Host smart-2f6ab000-e162-4b09-ac62-3f901e2b3690
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553808807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2553808807
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3230109858
Short name T561
Test name
Test status
Simulation time 193773982 ps
CPU time 2.37 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 206900 kb
Host smart-66a57125-3b8d-4dc2-9838-9c27bd5942c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230109858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3230109858
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1949333611
Short name T848
Test name
Test status
Simulation time 165530453 ps
CPU time 2.38 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 218172 kb
Host smart-3ce8696c-e6bd-4e38-b409-b71503881951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949333611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1949333611
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1252793284
Short name T755
Test name
Test status
Simulation time 221701474 ps
CPU time 2.71 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:32 PM PDT 24
Peak memory 207104 kb
Host smart-c2ee15ce-bd1a-4d1a-a717-460cc610c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252793284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1252793284
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3407221273
Short name T841
Test name
Test status
Simulation time 1647108790 ps
CPU time 22.81 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:47:04 PM PDT 24
Peak memory 216664 kb
Host smart-2144e0f4-c797-4740-b347-107e491592de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407221273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3407221273
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2818773081
Short name T33
Test name
Test status
Simulation time 1659446103 ps
CPU time 11.7 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 222596 kb
Host smart-77719682-e02a-4c85-8188-93e11d26a39d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818773081 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2818773081
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.90132832
Short name T279
Test name
Test status
Simulation time 67184243 ps
CPU time 3.22 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:36 PM PDT 24
Peak memory 207636 kb
Host smart-bfa9fe39-6979-48b8-baa9-dcd8cefc0ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90132832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.90132832
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.51634263
Short name T395
Test name
Test status
Simulation time 59546913 ps
CPU time 1.95 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 210048 kb
Host smart-0cd14387-335d-48b1-b11c-3af319fe97d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51634263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.51634263
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.958920765
Short name T528
Test name
Test status
Simulation time 15548378 ps
CPU time 0.96 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:29 PM PDT 24
Peak memory 206200 kb
Host smart-3935f652-28d7-4d5d-9f81-d40698168aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958920765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.958920765
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3791427441
Short name T910
Test name
Test status
Simulation time 323873208 ps
CPU time 4.19 seconds
Started Jun 27 04:46:40 PM PDT 24
Finished Jun 27 04:46:56 PM PDT 24
Peak memory 221376 kb
Host smart-7d3729f7-b46d-4a75-902e-602822e9e556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791427441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3791427441
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.535327477
Short name T904
Test name
Test status
Simulation time 114407997 ps
CPU time 1.39 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 214188 kb
Host smart-e6c5d963-03c9-41eb-92c4-ede82c2254d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535327477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.535327477
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2668045193
Short name T376
Test name
Test status
Simulation time 50582352 ps
CPU time 1.83 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:07 PM PDT 24
Peak memory 214420 kb
Host smart-96ea6843-3348-44d5-ada3-05a662f48f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668045193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2668045193
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3486779930
Short name T308
Test name
Test status
Simulation time 75137547 ps
CPU time 3.13 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 214240 kb
Host smart-d619406d-c629-4026-a479-a3389aaf9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486779930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3486779930
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2083178063
Short name T694
Test name
Test status
Simulation time 1342362846 ps
CPU time 3.55 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:46:50 PM PDT 24
Peak memory 214300 kb
Host smart-cf8361be-9cfe-4fa2-ba8d-76e9fc96c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083178063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2083178063
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1296057009
Short name T208
Test name
Test status
Simulation time 361913298 ps
CPU time 6.64 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:52 PM PDT 24
Peak memory 207944 kb
Host smart-20445ca0-c1e5-412a-b689-6d3a5999cece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296057009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1296057009
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3742003710
Short name T385
Test name
Test status
Simulation time 270721457 ps
CPU time 3.55 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 208528 kb
Host smart-4aaf3407-e5c4-4192-8d6c-6eb4d11bb98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742003710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3742003710
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3590188488
Short name T338
Test name
Test status
Simulation time 68760452 ps
CPU time 2.78 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:31 PM PDT 24
Peak memory 207004 kb
Host smart-9901cbf7-d1e7-4367-b0f0-4dac7b9989ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590188488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3590188488
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.459466480
Short name T718
Test name
Test status
Simulation time 3515274792 ps
CPU time 21.1 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:47:05 PM PDT 24
Peak memory 208116 kb
Host smart-cd519f83-a2d6-4c8e-9d14-7a05dc11dc10
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459466480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.459466480
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1104010134
Short name T780
Test name
Test status
Simulation time 411553340 ps
CPU time 2.96 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 218064 kb
Host smart-a07bd64f-d379-4155-bf64-c54d0835f4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104010134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1104010134
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3239276920
Short name T781
Test name
Test status
Simulation time 42150597 ps
CPU time 1.65 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 206016 kb
Host smart-d8098854-c278-4502-8c74-10d0350b516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239276920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3239276920
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3727594950
Short name T695
Test name
Test status
Simulation time 1064036182 ps
CPU time 7.21 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 215984 kb
Host smart-aba0fab9-1408-4142-b213-bddd09d59795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727594950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3727594950
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2118184543
Short name T608
Test name
Test status
Simulation time 173271379 ps
CPU time 4.84 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 208112 kb
Host smart-4162ea6f-4b74-4bf9-90b9-d93fd820091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118184543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2118184543
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.411634237
Short name T131
Test name
Test status
Simulation time 72513937 ps
CPU time 1.38 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 209912 kb
Host smart-046e8ef7-4e6c-47b2-9262-9eda4a302e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411634237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.411634237
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.490832819
Short name T610
Test name
Test status
Simulation time 10091192 ps
CPU time 0.73 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 206048 kb
Host smart-2ee04f5f-995b-41fe-b926-168fd81c52b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490832819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.490832819
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3369333911
Short name T909
Test name
Test status
Simulation time 156412572 ps
CPU time 4.3 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 209308 kb
Host smart-f8af6158-0e2e-4ca6-9d73-67c70898ad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369333911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3369333911
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.534684444
Short name T271
Test name
Test status
Simulation time 101215074 ps
CPU time 2.43 seconds
Started Jun 27 04:46:51 PM PDT 24
Finished Jun 27 04:47:02 PM PDT 24
Peak memory 214288 kb
Host smart-1808c4c0-9c7f-4e3c-aa8f-1bc9e2077029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534684444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.534684444
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2451854737
Short name T103
Test name
Test status
Simulation time 167102383 ps
CPU time 4.74 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:28 PM PDT 24
Peak memory 219888 kb
Host smart-e67901f4-fa70-4119-840b-49ef6f232d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451854737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2451854737
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3924374886
Short name T214
Test name
Test status
Simulation time 102331335 ps
CPU time 2.29 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 221784 kb
Host smart-2b46cf0e-2c10-450b-b381-11787c5f84cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924374886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3924374886
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_random.88155825
Short name T587
Test name
Test status
Simulation time 9158563366 ps
CPU time 21.85 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 209172 kb
Host smart-b06e2fcd-63c8-424f-8757-aecb27b80808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88155825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.88155825
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.315804768
Short name T507
Test name
Test status
Simulation time 3861803706 ps
CPU time 36.21 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:47:08 PM PDT 24
Peak memory 209260 kb
Host smart-12da2825-4bea-4d28-bc14-fa42164d3553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315804768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.315804768
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1787133602
Short name T863
Test name
Test status
Simulation time 286999420 ps
CPU time 3.77 seconds
Started Jun 27 04:46:37 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 206924 kb
Host smart-8d40df27-14d9-4d75-ac46-d23178f4747a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787133602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1787133602
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2386483416
Short name T847
Test name
Test status
Simulation time 569164940 ps
CPU time 6.04 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 206972 kb
Host smart-d613180b-2ede-4e69-b402-259707d70525
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386483416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2386483416
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3550075510
Short name T698
Test name
Test status
Simulation time 1843837296 ps
CPU time 11.44 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:56 PM PDT 24
Peak memory 208144 kb
Host smart-f1acdb58-ce53-45b5-97f7-3d2b1280b74b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550075510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3550075510
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1212300449
Short name T183
Test name
Test status
Simulation time 210869701 ps
CPU time 3.67 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:27 PM PDT 24
Peak memory 218272 kb
Host smart-46c7de65-e0c8-4409-a8ae-754c26f53bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212300449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1212300449
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.785694578
Short name T186
Test name
Test status
Simulation time 104560952 ps
CPU time 2.52 seconds
Started Jun 27 04:46:38 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 206968 kb
Host smart-ca0665f7-33aa-48e9-afc9-46d63fdaddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785694578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.785694578
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.467468309
Short name T577
Test name
Test status
Simulation time 681197528 ps
CPU time 5.12 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 207680 kb
Host smart-11460420-75fe-4721-826f-a9aff6017c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467468309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.467468309
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.909274684
Short name T522
Test name
Test status
Simulation time 41611047 ps
CPU time 1.66 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:37 PM PDT 24
Peak memory 210120 kb
Host smart-d2eefd38-8b61-4561-9314-441317904077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909274684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.909274684
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2111151097
Short name T837
Test name
Test status
Simulation time 24721551 ps
CPU time 0.71 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 205876 kb
Host smart-9a1fc3ac-b31a-4901-b4de-8960b0c39f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111151097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2111151097
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.990990736
Short name T427
Test name
Test status
Simulation time 329549232 ps
CPU time 4.53 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 214324 kb
Host smart-ecaeccc5-5eb6-49a6-a577-a5af0b146f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990990736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.990990736
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3363726547
Short name T605
Test name
Test status
Simulation time 516579682 ps
CPU time 6.43 seconds
Started Jun 27 04:46:35 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 214204 kb
Host smart-20f4c9de-4e53-46af-8619-31b4344833c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363726547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3363726547
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.447199901
Short name T357
Test name
Test status
Simulation time 153209959 ps
CPU time 1.97 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:32 PM PDT 24
Peak memory 214504 kb
Host smart-2523657d-bdc6-445a-99bf-9099eb15d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447199901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.447199901
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3897280418
Short name T34
Test name
Test status
Simulation time 51619573 ps
CPU time 3.12 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 222296 kb
Host smart-f0f1d217-1436-4deb-aac6-4006c084a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897280418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3897280418
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.1139745788
Short name T774
Test name
Test status
Simulation time 434321908 ps
CPU time 6.21 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 209252 kb
Host smart-2d863d8b-88c1-42f1-bd70-7e21b1c4fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139745788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1139745788
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3546430482
Short name T494
Test name
Test status
Simulation time 1200789120 ps
CPU time 6.95 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 208572 kb
Host smart-ef305206-017b-4694-b13a-fab685335f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546430482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3546430482
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.106432155
Short name T347
Test name
Test status
Simulation time 406009640 ps
CPU time 3.63 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 206760 kb
Host smart-568d5545-a7b1-4f3b-8131-a292be0c01d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106432155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.106432155
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3613639444
Short name T765
Test name
Test status
Simulation time 3086130581 ps
CPU time 17.81 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 208224 kb
Host smart-af5c09fb-6261-4fb6-9557-f58c22d9bca8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613639444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3613639444
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2095554753
Short name T589
Test name
Test status
Simulation time 209973160 ps
CPU time 4.31 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:39 PM PDT 24
Peak memory 206908 kb
Host smart-8d0a991e-60c6-460a-afdd-a8b420dc90ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095554753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2095554753
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.4121792950
Short name T556
Test name
Test status
Simulation time 667158118 ps
CPU time 2.21 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 207252 kb
Host smart-5a4cb654-dfda-4e29-8869-33e4ba3b1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121792950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.4121792950
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2895395113
Short name T883
Test name
Test status
Simulation time 79101865 ps
CPU time 1.76 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 207348 kb
Host smart-3791ccc6-28da-4772-801f-4443160b3b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895395113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2895395113
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3026412041
Short name T332
Test name
Test status
Simulation time 34158553176 ps
CPU time 51.44 seconds
Started Jun 27 04:46:23 PM PDT 24
Finished Jun 27 04:47:17 PM PDT 24
Peak memory 222380 kb
Host smart-672e97b3-c5eb-43d3-a3fa-320a823c4296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026412041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3026412041
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2814253808
Short name T828
Test name
Test status
Simulation time 46854025 ps
CPU time 2.96 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 209420 kb
Host smart-4fc2cf30-a523-42df-b9d0-d9f80695ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814253808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2814253808
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3919425764
Short name T171
Test name
Test status
Simulation time 80602895 ps
CPU time 2.21 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 210276 kb
Host smart-533ac656-cbf4-4b87-a4fc-7869c942132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919425764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3919425764
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1186940742
Short name T578
Test name
Test status
Simulation time 20122153 ps
CPU time 1.01 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 206136 kb
Host smart-8dbf2b18-4ab9-4a8c-a7fa-1027dbf68dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186940742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1186940742
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3029604575
Short name T800
Test name
Test status
Simulation time 354139537 ps
CPU time 4.33 seconds
Started Jun 27 04:46:45 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 219172 kb
Host smart-21ca5fa3-25d6-444e-aae6-3b3a4dad44fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029604575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3029604575
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.762238282
Short name T425
Test name
Test status
Simulation time 29099083 ps
CPU time 1.74 seconds
Started Jun 27 04:46:37 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 207324 kb
Host smart-0be6ebd5-40e4-4250-8ac7-1b66ddfcde91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762238282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.762238282
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1337279957
Short name T353
Test name
Test status
Simulation time 132528938 ps
CPU time 2.19 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 214324 kb
Host smart-c6e9eb06-abb9-426c-8cbb-699a9ec03f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337279957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1337279957
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1114939251
Short name T52
Test name
Test status
Simulation time 199882926 ps
CPU time 3.03 seconds
Started Jun 27 04:46:42 PM PDT 24
Finished Jun 27 04:46:57 PM PDT 24
Peak memory 222240 kb
Host smart-164a2689-dc43-449e-92a5-026117b89353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114939251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1114939251
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1352167501
Short name T220
Test name
Test status
Simulation time 172966146 ps
CPU time 2.13 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 209416 kb
Host smart-a96d3650-2c16-4846-b04a-9dc8c4a488f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352167501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1352167501
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.4126935895
Short name T412
Test name
Test status
Simulation time 368380972 ps
CPU time 4.08 seconds
Started Jun 27 04:46:36 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 218224 kb
Host smart-3fd63f44-2e55-48bd-b4a3-3fde4a5b0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126935895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4126935895
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.106495076
Short name T875
Test name
Test status
Simulation time 171096250 ps
CPU time 2.69 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 206612 kb
Host smart-29ce3f17-4a4d-4572-8922-0fc4b77087e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106495076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.106495076
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3341586037
Short name T490
Test name
Test status
Simulation time 3586945051 ps
CPU time 6.07 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 208576 kb
Host smart-676fe783-a0a1-4253-a525-fc0c82cd69df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341586037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3341586037
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3372092236
Short name T194
Test name
Test status
Simulation time 67977043 ps
CPU time 3.04 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 206856 kb
Host smart-b61f49c6-7a8f-4e70-920a-e5890a38f690
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372092236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3372092236
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3035735828
Short name T846
Test name
Test status
Simulation time 1636740332 ps
CPU time 30.62 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 208476 kb
Host smart-8335a647-77af-4b99-804f-a903749fc8ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035735828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3035735828
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1498112756
Short name T725
Test name
Test status
Simulation time 118757858 ps
CPU time 2.14 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:47 PM PDT 24
Peak memory 207296 kb
Host smart-1e7e7722-6f24-4a60-9d3a-a23aa7dc51ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498112756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1498112756
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2996188981
Short name T17
Test name
Test status
Simulation time 189572089 ps
CPU time 2.62 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 207116 kb
Host smart-346d360c-6ff6-4c03-92f1-50c70acdee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996188981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2996188981
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1332084532
Short name T154
Test name
Test status
Simulation time 357669600 ps
CPU time 14.34 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 221120 kb
Host smart-e9f8ba3c-7f28-4d30-b829-fafa5f9919fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332084532 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1332084532
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.591931420
Short name T282
Test name
Test status
Simulation time 506224645 ps
CPU time 5.22 seconds
Started Jun 27 04:46:37 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 207024 kb
Host smart-c91c2ad0-69d2-4483-9457-6a939f2a9e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591931420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.591931420
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1584121447
Short name T736
Test name
Test status
Simulation time 57477806 ps
CPU time 2.59 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 209812 kb
Host smart-58c069e1-e644-484d-bbb8-07dcb1f7fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584121447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1584121447
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3101186088
Short name T472
Test name
Test status
Simulation time 53297810 ps
CPU time 0.75 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:39 PM PDT 24
Peak memory 206036 kb
Host smart-67eab462-57c2-4224-a825-833fbefc5239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101186088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3101186088
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.355531022
Short name T435
Test name
Test status
Simulation time 451891836 ps
CPU time 6.16 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 214340 kb
Host smart-47396578-df7a-423f-8b01-11932858a27a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355531022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.355531022
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1984425097
Short name T786
Test name
Test status
Simulation time 208194186 ps
CPU time 5.77 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:37 PM PDT 24
Peak memory 209572 kb
Host smart-3d2a94ad-1965-41b3-9f1d-872b99345c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984425097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1984425097
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3764569337
Short name T72
Test name
Test status
Simulation time 2048534165 ps
CPU time 21.2 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:56 PM PDT 24
Peak memory 209008 kb
Host smart-7c1a4cf1-0462-427a-b715-c652cd21a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764569337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3764569337
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4193807928
Short name T634
Test name
Test status
Simulation time 206781893 ps
CPU time 2.44 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 214244 kb
Host smart-ef626a54-4390-4bb3-96c5-e929ac5f4da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193807928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4193807928
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.3008979486
Short name T707
Test name
Test status
Simulation time 2041867514 ps
CPU time 61.34 seconds
Started Jun 27 04:46:47 PM PDT 24
Finished Jun 27 04:47:58 PM PDT 24
Peak memory 209472 kb
Host smart-5372c860-a65e-41db-8cd8-27f9262097ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008979486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3008979486
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3196038640
Short name T403
Test name
Test status
Simulation time 734145154 ps
CPU time 7.85 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 208256 kb
Host smart-067f91bb-8bdb-4a50-9701-f15c71961d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196038640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3196038640
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1441168467
Short name T550
Test name
Test status
Simulation time 158628151 ps
CPU time 2.6 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 206972 kb
Host smart-418e9aaf-e541-4e55-a8b3-1375e7e47b27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441168467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1441168467
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1993737717
Short name T701
Test name
Test status
Simulation time 5182558189 ps
CPU time 31.14 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:47:14 PM PDT 24
Peak memory 208348 kb
Host smart-5d33bb88-e784-4d65-a0d0-e73b1b49309d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993737717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1993737717
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2512114423
Short name T552
Test name
Test status
Simulation time 659135896 ps
CPU time 3.53 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 208616 kb
Host smart-0881a11f-e3d5-458d-aab7-19b41082c21c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512114423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2512114423
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2601485114
Short name T311
Test name
Test status
Simulation time 120808279 ps
CPU time 3.15 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 218272 kb
Host smart-03db5c86-338b-4ab7-bc0b-18bd42845b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601485114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2601485114
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.634653160
Short name T768
Test name
Test status
Simulation time 308784537 ps
CPU time 5.53 seconds
Started Jun 27 04:46:35 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 207800 kb
Host smart-689e6b2d-e327-4137-a87d-d036374958b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634653160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.634653160
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.910959253
Short name T685
Test name
Test status
Simulation time 1186499092 ps
CPU time 5.01 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 208228 kb
Host smart-904982d7-abb6-4144-a3b4-78175a7fb4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910959253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.910959253
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.400393088
Short name T180
Test name
Test status
Simulation time 1934561805 ps
CPU time 10.88 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 222500 kb
Host smart-c837e2f0-8ee5-4b39-b7b1-66af296411d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400393088 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.400393088
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2664559871
Short name T750
Test name
Test status
Simulation time 581164578 ps
CPU time 5.05 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:40 PM PDT 24
Peak memory 210436 kb
Host smart-11557ac2-16cf-4719-9417-2318f828755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664559871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2664559871
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.297044705
Short name T513
Test name
Test status
Simulation time 97089457 ps
CPU time 0.73 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 205940 kb
Host smart-b45dbb41-e58a-4a29-a658-9b2db2af285d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297044705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.297044705
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.630652673
Short name T434
Test name
Test status
Simulation time 79432691 ps
CPU time 2.96 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:52 PM PDT 24
Peak memory 215540 kb
Host smart-9228e9b5-cd8b-4fae-bec0-c65910db45e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630652673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.630652673
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1034583963
Short name T93
Test name
Test status
Simulation time 1242437488 ps
CPU time 8.25 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 214172 kb
Host smart-899091aa-aa0b-4b0d-a203-e8282fbcd41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034583963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1034583963
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3328763046
Short name T650
Test name
Test status
Simulation time 198254550 ps
CPU time 3.2 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 214172 kb
Host smart-31a61d7b-5a7d-4450-adc8-31a33d9a6622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328763046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3328763046
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3876586388
Short name T331
Test name
Test status
Simulation time 113586235 ps
CPU time 3.32 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 209500 kb
Host smart-6a094db2-2411-4791-989f-7c22e07e591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876586388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3876586388
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2399914239
Short name T830
Test name
Test status
Simulation time 211234242 ps
CPU time 4.63 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:31 PM PDT 24
Peak memory 207896 kb
Host smart-7543a87b-cb46-46f8-913b-069b75ae081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399914239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2399914239
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1819390625
Short name T535
Test name
Test status
Simulation time 42600802 ps
CPU time 2.38 seconds
Started Jun 27 04:46:35 PM PDT 24
Finished Jun 27 04:46:50 PM PDT 24
Peak memory 206880 kb
Host smart-6b9ecb0f-6c21-43ec-b8ad-84e5645710b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819390625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1819390625
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1369580838
Short name T529
Test name
Test status
Simulation time 36436483 ps
CPU time 2.2 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 206784 kb
Host smart-805941a8-b64d-4a61-880f-4d5c27660572
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369580838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1369580838
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3807913837
Short name T506
Test name
Test status
Simulation time 103892989 ps
CPU time 3.78 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 208584 kb
Host smart-3c1f2d11-b559-4d1d-96dc-339d1ad28c2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807913837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3807913837
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2648262061
Short name T760
Test name
Test status
Simulation time 350681450 ps
CPU time 12.18 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 208348 kb
Host smart-36ba51bc-fc2e-4c1b-86c3-29f98a3c7233
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648262061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2648262061
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3467852185
Short name T471
Test name
Test status
Simulation time 148906544 ps
CPU time 3.55 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 208232 kb
Host smart-4b2a649d-1e41-4718-8775-5511049f7ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467852185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3467852185
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2878553010
Short name T852
Test name
Test status
Simulation time 1675794589 ps
CPU time 4.04 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:39 PM PDT 24
Peak memory 208492 kb
Host smart-149af1a1-f404-4394-bcbb-168810593a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878553010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2878553010
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2461794251
Short name T178
Test name
Test status
Simulation time 6604788956 ps
CPU time 160.18 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:49:47 PM PDT 24
Peak memory 222432 kb
Host smart-9ff3d8ed-9a05-4c07-b73c-ad421a3da93d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461794251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2461794251
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3541883449
Short name T481
Test name
Test status
Simulation time 3815541089 ps
CPU time 57.38 seconds
Started Jun 27 04:46:39 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 209228 kb
Host smart-d9eb02c1-8bc6-4c7c-aa53-9416f3bcbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541883449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3541883449
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4142926964
Short name T623
Test name
Test status
Simulation time 33107793 ps
CPU time 1.85 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 210004 kb
Host smart-6a73e1c1-42ba-4fb2-aa74-ce5fe60a8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142926964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4142926964
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.41551570
Short name T504
Test name
Test status
Simulation time 140921015 ps
CPU time 0.87 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 205928 kb
Host smart-83780a8d-97e9-49de-8cfa-fd00888cdca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41551570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.41551570
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1136066349
Short name T238
Test name
Test status
Simulation time 67548112 ps
CPU time 2.51 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:56 PM PDT 24
Peak memory 214964 kb
Host smart-5fd8996c-ad7c-45ab-8226-96b17b1e7f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136066349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1136066349
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2619441548
Short name T244
Test name
Test status
Simulation time 19207652 ps
CPU time 1.39 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 207932 kb
Host smart-f8482127-edef-4d91-be64-cffde6aa5017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619441548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2619441548
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2243051119
Short name T216
Test name
Test status
Simulation time 27738265 ps
CPU time 1.85 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:40 PM PDT 24
Peak memory 206148 kb
Host smart-4c2f3e4a-6c2c-4149-8ff3-30b40e6126d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243051119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2243051119
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2242728557
Short name T712
Test name
Test status
Simulation time 315989829 ps
CPU time 5.08 seconds
Started Jun 27 04:46:38 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 207600 kb
Host smart-8a1f0236-5d9c-43f9-b2d8-597acc0164ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242728557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2242728557
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.383412413
Short name T258
Test name
Test status
Simulation time 156615655 ps
CPU time 3.85 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:47 PM PDT 24
Peak memory 207984 kb
Host smart-ab87ccc9-f490-4710-9345-b3b4a4dc8e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383412413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.383412413
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2635526361
Short name T476
Test name
Test status
Simulation time 251088623 ps
CPU time 4.92 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:50 PM PDT 24
Peak memory 207792 kb
Host smart-65f43cad-3ad9-4bd4-8244-b305c565078f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635526361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2635526361
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1189245574
Short name T753
Test name
Test status
Simulation time 1254356740 ps
CPU time 13.04 seconds
Started Jun 27 04:46:56 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 207052 kb
Host smart-19fc4232-04a8-42e8-b554-2951a213ef8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189245574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1189245574
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3551190997
Short name T611
Test name
Test status
Simulation time 340916292 ps
CPU time 2.33 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 206916 kb
Host smart-0e2772f6-be0a-4284-a6c9-b412d97c1f62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551190997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3551190997
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3477264359
Short name T769
Test name
Test status
Simulation time 1967042380 ps
CPU time 31.4 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 209204 kb
Host smart-655b1d61-4e5e-4bf8-9d5c-8084511ac74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477264359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3477264359
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4269557149
Short name T457
Test name
Test status
Simulation time 98269298 ps
CPU time 2.34 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 206756 kb
Host smart-53d1fb3b-1acf-460a-b104-48f6b527dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269557149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4269557149
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3815992745
Short name T200
Test name
Test status
Simulation time 477197276 ps
CPU time 9.49 seconds
Started Jun 27 04:46:37 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 207304 kb
Host smart-4ce977b5-d374-4868-9c87-5074062d5b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815992745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3815992745
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3225079610
Short name T870
Test name
Test status
Simulation time 107542783 ps
CPU time 2.45 seconds
Started Jun 27 04:46:45 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 210188 kb
Host smart-2bd364ba-be41-4219-868c-672595f4adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225079610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3225079610
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1554584085
Short name T674
Test name
Test status
Simulation time 44135484 ps
CPU time 0.85 seconds
Started Jun 27 04:45:56 PM PDT 24
Finished Jun 27 04:45:58 PM PDT 24
Peak memory 205984 kb
Host smart-47517941-f3e0-4b2c-a5cd-989c13f07960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554584085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1554584085
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1248551613
Short name T110
Test name
Test status
Simulation time 2315853550 ps
CPU time 31.88 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:31 PM PDT 24
Peak memory 222664 kb
Host smart-5f668c8d-5326-48e1-b719-383f9b306ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248551613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1248551613
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2877485832
Short name T798
Test name
Test status
Simulation time 497355241 ps
CPU time 3.69 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 209960 kb
Host smart-61597278-e17e-49ef-8661-55e67a52ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877485832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2877485832
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3394630908
Short name T323
Test name
Test status
Simulation time 1411626043 ps
CPU time 9.64 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 214412 kb
Host smart-5637494f-5d9f-4cae-9c4d-0e4d127e09fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394630908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3394630908
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2732378641
Short name T55
Test name
Test status
Simulation time 240068224 ps
CPU time 5.42 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:46:00 PM PDT 24
Peak memory 214264 kb
Host smart-7c37872d-165f-4dd0-b1ee-008ce6476c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732378641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2732378641
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.333329255
Short name T564
Test name
Test status
Simulation time 455358665 ps
CPU time 3.65 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:45:58 PM PDT 24
Peak memory 209316 kb
Host smart-d5a3b413-a869-4c1d-b586-3a6ea621d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333329255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.333329255
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1615724063
Short name T391
Test name
Test status
Simulation time 81174060 ps
CPU time 2.74 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:03 PM PDT 24
Peak memory 214304 kb
Host smart-755fc544-78df-4abc-b4cc-ba2f7e42e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615724063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1615724063
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2505644909
Short name T40
Test name
Test status
Simulation time 1557000040 ps
CPU time 12.94 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 237972 kb
Host smart-e65b6438-8902-441b-a533-895ff24d1e64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505644909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2505644909
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1900163527
Short name T664
Test name
Test status
Simulation time 1689357514 ps
CPU time 53.82 seconds
Started Jun 27 04:46:16 PM PDT 24
Finished Jun 27 04:47:11 PM PDT 24
Peak memory 207876 kb
Host smart-5821773d-dc34-4450-b583-bda36de1ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900163527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1900163527
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3149046825
Short name T359
Test name
Test status
Simulation time 56790201 ps
CPU time 2.91 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:45:58 PM PDT 24
Peak memory 208476 kb
Host smart-4ccf3f3d-2e64-4adf-9922-e12e53f3cf36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149046825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3149046825
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1838122684
Short name T491
Test name
Test status
Simulation time 246711229 ps
CPU time 2.86 seconds
Started Jun 27 04:45:51 PM PDT 24
Finished Jun 27 04:45:54 PM PDT 24
Peak memory 206600 kb
Host smart-00e3c68e-d05e-4bd8-95e7-392a502fcabf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838122684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1838122684
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.528789315
Short name T583
Test name
Test status
Simulation time 451297939 ps
CPU time 4.25 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 208800 kb
Host smart-d7000572-6c7c-44b3-8bfe-5570399c2d55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528789315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.528789315
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3349484335
Short name T256
Test name
Test status
Simulation time 261839741 ps
CPU time 3.72 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:03 PM PDT 24
Peak memory 218184 kb
Host smart-5ecb8900-0f55-4113-91de-e8b1013e3023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349484335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3349484335
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1880317350
Short name T757
Test name
Test status
Simulation time 305889670 ps
CPU time 3.73 seconds
Started Jun 27 04:45:55 PM PDT 24
Finished Jun 27 04:46:01 PM PDT 24
Peak memory 208820 kb
Host smart-825c5be8-5b17-4fe9-8b8a-dfab91318461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880317350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1880317350
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3115983491
Short name T336
Test name
Test status
Simulation time 917618800 ps
CPU time 18.37 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:20 PM PDT 24
Peak memory 208512 kb
Host smart-c22850e8-c923-4995-8d1c-a623018c520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115983491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3115983491
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1998020357
Short name T666
Test name
Test status
Simulation time 20056331 ps
CPU time 0.7 seconds
Started Jun 27 04:46:32 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 205848 kb
Host smart-0d7bba2b-d5a2-4527-942a-7de83f26c309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998020357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1998020357
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1069855497
Short name T437
Test name
Test status
Simulation time 217948048 ps
CPU time 2.47 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:39 PM PDT 24
Peak memory 214332 kb
Host smart-b27f9b81-68e8-4b41-b1f1-07c593e38c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069855497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1069855497
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2551864710
Short name T839
Test name
Test status
Simulation time 3896027212 ps
CPU time 7.99 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:50 PM PDT 24
Peak memory 221504 kb
Host smart-39e93d53-5761-4876-b9e0-c4ed50eca4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551864710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2551864710
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2142919697
Short name T642
Test name
Test status
Simulation time 659445590 ps
CPU time 2.79 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 206840 kb
Host smart-4c9fca02-ee85-4603-a3d9-cb8d76f8610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142919697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2142919697
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.761473241
Short name T541
Test name
Test status
Simulation time 113239943 ps
CPU time 1.97 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:36 PM PDT 24
Peak memory 214188 kb
Host smart-749cfb9e-caa4-4b23-99b1-3a2ee6ad5873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761473241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.761473241
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.701173104
Short name T601
Test name
Test status
Simulation time 74041783 ps
CPU time 2.6 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 222024 kb
Host smart-f07abf59-dfb1-482f-8440-679fc9db54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701173104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.701173104
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4120064757
Short name T70
Test name
Test status
Simulation time 34561297 ps
CPU time 2.72 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:40 PM PDT 24
Peak memory 209872 kb
Host smart-496dfb84-2aab-4011-9807-e81af381153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120064757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4120064757
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1365748162
Short name T822
Test name
Test status
Simulation time 2420718336 ps
CPU time 52.59 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 209348 kb
Host smart-90346f9d-d3bb-4dde-b653-06f07300738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365748162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1365748162
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1182756189
Short name T900
Test name
Test status
Simulation time 709801503 ps
CPU time 13.65 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 208928 kb
Host smart-09fe9950-453d-4d52-b9e2-9c43caa46f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182756189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1182756189
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.451165137
Short name T358
Test name
Test status
Simulation time 617903554 ps
CPU time 6.9 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 208528 kb
Host smart-262e4483-e9d8-45c3-866a-5476260004f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451165137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.451165137
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.350605614
Short name T737
Test name
Test status
Simulation time 252166288 ps
CPU time 3.06 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 208536 kb
Host smart-c8d3add1-5ab6-446e-9bc6-42af81816da3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350605614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.350605614
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.37342281
Short name T692
Test name
Test status
Simulation time 52002744 ps
CPU time 2.85 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 208880 kb
Host smart-8e8e2d49-4ad3-4b44-8c87-8910b8c33396
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37342281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.37342281
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1806220442
Short name T691
Test name
Test status
Simulation time 126493817 ps
CPU time 3.44 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:46:50 PM PDT 24
Peak memory 209376 kb
Host smart-12babc83-3d34-4237-af73-44b7387b976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806220442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1806220442
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1606499305
Short name T735
Test name
Test status
Simulation time 558018245 ps
CPU time 3.89 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:37 PM PDT 24
Peak memory 207688 kb
Host smart-1b439144-b605-49e0-a16d-b2fa13b0f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606499305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1606499305
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3748241575
Short name T722
Test name
Test status
Simulation time 328979347 ps
CPU time 7.93 seconds
Started Jun 27 04:46:24 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 214232 kb
Host smart-079dae6a-42bc-411e-b890-c3fc914ec350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748241575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3748241575
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.540719735
Short name T461
Test name
Test status
Simulation time 42515135 ps
CPU time 0.86 seconds
Started Jun 27 04:46:51 PM PDT 24
Finished Jun 27 04:47:01 PM PDT 24
Peak memory 206068 kb
Host smart-9d7959ef-f400-4649-a68e-6e5b6c09d91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540719735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.540719735
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3019010436
Short name T779
Test name
Test status
Simulation time 3002263150 ps
CPU time 28.4 seconds
Started Jun 27 04:46:35 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 214200 kb
Host smart-7c96aa0b-6bbf-4af3-9087-bc32d94622b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019010436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3019010436
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2605614941
Short name T374
Test name
Test status
Simulation time 355193276 ps
CPU time 4.2 seconds
Started Jun 27 04:46:38 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 214200 kb
Host smart-94a83430-05d3-4ba7-8ed2-e4087d6dbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605614941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2605614941
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2483186480
Short name T84
Test name
Test status
Simulation time 335936678 ps
CPU time 3.6 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 220088 kb
Host smart-a286ad3e-1cd7-4742-8087-2b957a901f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483186480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2483186480
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.345636460
Short name T196
Test name
Test status
Simulation time 721475796 ps
CPU time 6.52 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 214172 kb
Host smart-4750635e-ec43-4a89-9615-3748c0e33493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345636460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.345636460
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2210117407
Short name T843
Test name
Test status
Simulation time 104096266 ps
CPU time 4.26 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:47 PM PDT 24
Peak memory 206948 kb
Host smart-17a97b5e-bf16-4303-b83e-df410b31c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210117407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2210117407
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2399773195
Short name T590
Test name
Test status
Simulation time 307772779 ps
CPU time 3.98 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 208500 kb
Host smart-7682510f-8ef5-4343-aa99-469ae8d0ac9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399773195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2399773195
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3708892945
Short name T662
Test name
Test status
Simulation time 280703038 ps
CPU time 3.08 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 206916 kb
Host smart-08bf1cf3-def7-40f9-8073-3122e123b95f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708892945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3708892945
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.89395797
Short name T597
Test name
Test status
Simulation time 142970558 ps
CPU time 2.19 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:44 PM PDT 24
Peak memory 206652 kb
Host smart-e33fa251-f410-4532-b998-9811b5a06d68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89395797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.89395797
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3946404647
Short name T567
Test name
Test status
Simulation time 497384150 ps
CPU time 4.11 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 220600 kb
Host smart-1432b92c-7a65-4639-bc1f-6cabc57e8749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946404647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3946404647
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.948049402
Short name T741
Test name
Test status
Simulation time 60309925 ps
CPU time 2.58 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:46 PM PDT 24
Peak memory 206720 kb
Host smart-469ce9f3-d823-4295-9623-3c180053cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948049402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.948049402
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3765565688
Short name T67
Test name
Test status
Simulation time 1217696938 ps
CPU time 29.79 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 222468 kb
Host smart-e63ae756-9028-49ea-a12d-d5c88bed7de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765565688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3765565688
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1134464416
Short name T207
Test name
Test status
Simulation time 5707280242 ps
CPU time 63.24 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:47:48 PM PDT 24
Peak memory 214468 kb
Host smart-7a702e91-a865-4c55-b327-3dfc9fab4993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134464416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1134464416
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2367221229
Short name T172
Test name
Test status
Simulation time 49789678 ps
CPU time 1.54 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:39 PM PDT 24
Peak memory 209992 kb
Host smart-e5f4685f-a6a1-4b6c-a1eb-40120ee0ac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367221229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2367221229
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3306900160
Short name T682
Test name
Test status
Simulation time 13401643 ps
CPU time 0.77 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 205912 kb
Host smart-cf113616-dfb5-4a7a-944b-77cdd2228986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306900160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3306900160
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.518088942
Short name T36
Test name
Test status
Simulation time 3519042749 ps
CPU time 46.11 seconds
Started Jun 27 04:46:53 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 214332 kb
Host smart-592a8fe5-aa29-4c98-9d5e-a667d8df98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518088942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.518088942
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3710859899
Short name T484
Test name
Test status
Simulation time 361282396 ps
CPU time 3.99 seconds
Started Jun 27 04:46:40 PM PDT 24
Finished Jun 27 04:46:56 PM PDT 24
Peak memory 207836 kb
Host smart-f3dfa8f3-19ca-4cb3-8d7d-dc5cbc417696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710859899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3710859899
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1873498139
Short name T291
Test name
Test status
Simulation time 404178310 ps
CPU time 3.35 seconds
Started Jun 27 04:46:51 PM PDT 24
Finished Jun 27 04:47:04 PM PDT 24
Peak memory 214288 kb
Host smart-1763c8bd-125a-459c-ba9b-3c7ce5c51957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873498139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1873498139
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1445919734
Short name T307
Test name
Test status
Simulation time 612209607 ps
CPU time 4.69 seconds
Started Jun 27 04:46:51 PM PDT 24
Finished Jun 27 04:47:05 PM PDT 24
Peak memory 214272 kb
Host smart-4bd20678-bae2-4249-96b6-4cef4f45a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445919734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1445919734
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.350701003
Short name T842
Test name
Test status
Simulation time 47908951 ps
CPU time 2.62 seconds
Started Jun 27 04:46:42 PM PDT 24
Finished Jun 27 04:46:56 PM PDT 24
Peak memory 214356 kb
Host smart-98caea2d-fe80-4a2a-9992-d5235a65584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350701003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.350701003
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.317037223
Short name T390
Test name
Test status
Simulation time 191518440 ps
CPU time 4.36 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 207044 kb
Host smart-d3141ea8-2e5f-4b73-b523-7149a4ffb871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317037223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.317037223
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2577156416
Short name T527
Test name
Test status
Simulation time 29618710 ps
CPU time 2.06 seconds
Started Jun 27 04:47:07 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 206716 kb
Host smart-3290c706-a2a6-4721-9ebe-05e664b6cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577156416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2577156416
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2056936130
Short name T108
Test name
Test status
Simulation time 220524289 ps
CPU time 2.56 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 207012 kb
Host smart-c95952b8-950f-4f16-b852-b448ca42fa85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056936130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2056936130
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2938574876
Short name T297
Test name
Test status
Simulation time 475444859 ps
CPU time 12.08 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 208548 kb
Host smart-867d90c4-0748-424d-bb0d-9c3f9f717733
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938574876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2938574876
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1382399247
Short name T575
Test name
Test status
Simulation time 67092941 ps
CPU time 2.13 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 207412 kb
Host smart-66f5f033-a2b4-4915-a511-899494a45a00
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382399247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1382399247
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1980813287
Short name T495
Test name
Test status
Simulation time 359226442 ps
CPU time 2.19 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 207380 kb
Host smart-a1834cef-895e-4288-8f5c-d3f59f3d2be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980813287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1980813287
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1175378074
Short name T690
Test name
Test status
Simulation time 97763282 ps
CPU time 2.96 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 208448 kb
Host smart-90e86bf6-0ba9-40e6-b57f-7412455a300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175378074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1175378074
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.419064147
Short name T345
Test name
Test status
Simulation time 160983952 ps
CPU time 4.48 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 208428 kb
Host smart-95d38f9e-cc0e-4dbe-ac88-e7e053818ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419064147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.419064147
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2404917234
Short name T122
Test name
Test status
Simulation time 1063699294 ps
CPU time 19.7 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:31 PM PDT 24
Peak memory 220192 kb
Host smart-ac7f9eea-2e52-4072-86f9-40a91338e4cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404917234 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2404917234
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.342841239
Short name T516
Test name
Test status
Simulation time 109117994 ps
CPU time 3.25 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 208192 kb
Host smart-4ad6e003-0676-49a9-a231-7e5ba5905854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342841239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.342841239
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3803865561
Short name T913
Test name
Test status
Simulation time 114527423 ps
CPU time 1.56 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 209848 kb
Host smart-02c1fdbf-5e17-437b-9f76-e058c0593bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803865561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3803865561
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2272412009
Short name T728
Test name
Test status
Simulation time 10593122 ps
CPU time 0.78 seconds
Started Jun 27 04:46:49 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 205980 kb
Host smart-622368d9-7d96-4e6d-839e-7a739007ad9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272412009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2272412009
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3944907292
Short name T438
Test name
Test status
Simulation time 224243569 ps
CPU time 4.44 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 214648 kb
Host smart-cc373e0a-7615-417c-850c-d60c64234a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944907292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3944907292
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3950892882
Short name T23
Test name
Test status
Simulation time 382340519 ps
CPU time 4.05 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 214776 kb
Host smart-d9a66904-6850-4b0d-9876-1f879a0e1167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950892882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3950892882
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4222805420
Short name T770
Test name
Test status
Simulation time 262306946 ps
CPU time 1.44 seconds
Started Jun 27 04:46:37 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 207480 kb
Host smart-a3a146c3-ba6e-420f-b031-41896970bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222805420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4222805420
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3063761331
Short name T91
Test name
Test status
Simulation time 206928936 ps
CPU time 2.06 seconds
Started Jun 27 04:46:40 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 214412 kb
Host smart-7c023264-445e-4e64-8a0f-5cdc1c2f0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063761331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3063761331
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.850601256
Short name T767
Test name
Test status
Simulation time 199316844 ps
CPU time 7.54 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 206244 kb
Host smart-458fbbe9-2245-40b4-92a1-0b366f932062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850601256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.850601256
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4163091572
Short name T251
Test name
Test status
Simulation time 154652374 ps
CPU time 3.88 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 214184 kb
Host smart-014129cd-2010-474e-be12-1cf6a7ee6fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163091572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4163091572
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1570548180
Short name T557
Test name
Test status
Simulation time 326128299 ps
CPU time 4.48 seconds
Started Jun 27 04:46:53 PM PDT 24
Finished Jun 27 04:47:07 PM PDT 24
Peak memory 210200 kb
Host smart-f606f0c2-fbd7-411d-8e15-b24f212d681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570548180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1570548180
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3709524252
Short name T665
Test name
Test status
Simulation time 900546231 ps
CPU time 19.27 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 207932 kb
Host smart-2f50f1c4-8db1-479c-bbf5-897f78985415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709524252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3709524252
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1587932533
Short name T310
Test name
Test status
Simulation time 1308251884 ps
CPU time 3.43 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:17 PM PDT 24
Peak memory 208448 kb
Host smart-4a5e4004-8675-45c4-b5f5-86874b4bf3a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587932533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1587932533
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1351657363
Short name T648
Test name
Test status
Simulation time 514019710 ps
CPU time 12 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 207820 kb
Host smart-8af2ab24-b9b3-4f3b-825e-3012c8c3c6a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351657363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1351657363
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.417877448
Short name T700
Test name
Test status
Simulation time 3473526095 ps
CPU time 33.53 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 208924 kb
Host smart-0072472e-d4c6-40c0-984e-57782b30a5b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417877448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.417877448
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3935486561
Short name T705
Test name
Test status
Simulation time 185341377 ps
CPU time 2.35 seconds
Started Jun 27 04:47:03 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 208412 kb
Host smart-09c027e7-a428-453b-9856-ba1c96d1961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935486561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3935486561
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.523450213
Short name T618
Test name
Test status
Simulation time 631651510 ps
CPU time 3.53 seconds
Started Jun 27 04:46:52 PM PDT 24
Finished Jun 27 04:47:06 PM PDT 24
Peak memory 208496 kb
Host smart-e94f2c69-e35c-46a1-b55c-da70566e7dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523450213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.523450213
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4287695471
Short name T509
Test name
Test status
Simulation time 803184962 ps
CPU time 10.9 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 216692 kb
Host smart-f4a34af0-13e9-495e-8328-8cb7e697c87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287695471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4287695471
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2405732055
Short name T181
Test name
Test status
Simulation time 612814161 ps
CPU time 21.64 seconds
Started Jun 27 04:46:48 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 222560 kb
Host smart-43980893-31d9-4adf-89d6-7bde510847af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405732055 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2405732055
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2318189059
Short name T316
Test name
Test status
Simulation time 136930549 ps
CPU time 5.15 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 207940 kb
Host smart-5443b350-6f58-41eb-8446-329990c98b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318189059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2318189059
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3932248784
Short name T532
Test name
Test status
Simulation time 119307280 ps
CPU time 2.24 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:08 PM PDT 24
Peak memory 210200 kb
Host smart-95004a6d-859a-4090-8a18-70f299fc4096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932248784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3932248784
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3188417827
Short name T501
Test name
Test status
Simulation time 20329926 ps
CPU time 0.97 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 205628 kb
Host smart-4ef09385-6394-48e5-b468-3ea12244c781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188417827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3188417827
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.966586726
Short name T680
Test name
Test status
Simulation time 277834692 ps
CPU time 4.39 seconds
Started Jun 27 04:46:50 PM PDT 24
Finished Jun 27 04:47:04 PM PDT 24
Peak memory 222728 kb
Host smart-84d2ba87-d7a0-4c6a-9c87-eadcc3999dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966586726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.966586726
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.810711488
Short name T673
Test name
Test status
Simulation time 68842245 ps
CPU time 1.47 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:07 PM PDT 24
Peak memory 214312 kb
Host smart-ecd26fec-6087-4388-96b1-9da135cc4e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810711488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.810711488
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1994111629
Short name T90
Test name
Test status
Simulation time 155815140 ps
CPU time 2.82 seconds
Started Jun 27 04:46:47 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 214336 kb
Host smart-fa9133c1-1540-43bd-ab14-c58ba49f3c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994111629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1994111629
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3513677576
Short name T246
Test name
Test status
Simulation time 274672000 ps
CPU time 5.09 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 214276 kb
Host smart-64f560c2-399d-43d4-9cfc-05bc4efa2b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513677576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3513677576
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.665250477
Short name T651
Test name
Test status
Simulation time 209566565 ps
CPU time 4.82 seconds
Started Jun 27 04:46:52 PM PDT 24
Finished Jun 27 04:47:06 PM PDT 24
Peak memory 222504 kb
Host smart-ac86fd9d-3393-490e-ae84-2d3c3ad85315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665250477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.665250477
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3460428695
Short name T562
Test name
Test status
Simulation time 815267034 ps
CPU time 6.36 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 209408 kb
Host smart-e08a7d01-b355-4bc8-ae70-0bea8acf74a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460428695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3460428695
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4220969011
Short name T346
Test name
Test status
Simulation time 199649903 ps
CPU time 3.46 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:14 PM PDT 24
Peak memory 207644 kb
Host smart-d86c69be-49ed-46cf-8250-801fc35340fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220969011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4220969011
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.239806596
Short name T627
Test name
Test status
Simulation time 206779091 ps
CPU time 5.71 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:17 PM PDT 24
Peak memory 207344 kb
Host smart-d5e22b5a-840a-4b87-b039-a6a0dff08bb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239806596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.239806596
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3762961948
Short name T210
Test name
Test status
Simulation time 103553423 ps
CPU time 4.12 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 206904 kb
Host smart-0a1717f2-38ff-4d4b-87de-9bbb32a5eaaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762961948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3762961948
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.987586220
Short name T548
Test name
Test status
Simulation time 65884983 ps
CPU time 2.77 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 206668 kb
Host smart-c6e52ea0-14a1-4e3b-86d6-06f84f5ec618
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987586220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.987586220
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3618400296
Short name T866
Test name
Test status
Simulation time 144955726 ps
CPU time 2.8 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 214328 kb
Host smart-700b79e2-d6b0-4594-856c-7b3c35eaf71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618400296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3618400296
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3945671133
Short name T653
Test name
Test status
Simulation time 147448424 ps
CPU time 2.23 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 208196 kb
Host smart-19e0f4d1-be04-4139-a8a5-4cce285cb2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945671133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3945671133
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.770365551
Short name T829
Test name
Test status
Simulation time 60602521 ps
CPU time 2.47 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 208908 kb
Host smart-b8e06c7d-57a0-4193-9e73-32991956c74a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770365551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.770365551
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1803396227
Short name T727
Test name
Test status
Simulation time 1761165699 ps
CPU time 17.05 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:31 PM PDT 24
Peak memory 220788 kb
Host smart-4a39e112-f990-47c5-907a-60d62e9724ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803396227 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1803396227
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3411619768
Short name T262
Test name
Test status
Simulation time 90568297 ps
CPU time 4.07 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 218412 kb
Host smart-1ce77ce1-16e1-44b9-956b-d424f47a0912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411619768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3411619768
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2452314251
Short name T189
Test name
Test status
Simulation time 302070082 ps
CPU time 2.76 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:14 PM PDT 24
Peak memory 210336 kb
Host smart-1bcd40b0-3a27-4869-b276-4f9c90baad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452314251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2452314251
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2945331288
Short name T797
Test name
Test status
Simulation time 10482224 ps
CPU time 0.85 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 205940 kb
Host smart-f886497d-c134-4dd7-8110-131e46f13df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945331288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2945331288
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.957395371
Short name T382
Test name
Test status
Simulation time 121318191 ps
CPU time 6.5 seconds
Started Jun 27 04:46:53 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 214444 kb
Host smart-fc2dad53-2f2c-4ef0-84dd-5d158818ffc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957395371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.957395371
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3642584010
Short name T31
Test name
Test status
Simulation time 82527763 ps
CPU time 2.42 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 209580 kb
Host smart-029badb9-20ab-4a56-873c-dec6f4e8b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642584010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3642584010
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3098636679
Short name T540
Test name
Test status
Simulation time 243843737 ps
CPU time 3.01 seconds
Started Jun 27 04:46:47 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 209252 kb
Host smart-7b614774-cd31-4f32-807a-016421bfc5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098636679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3098636679
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1374750288
Short name T394
Test name
Test status
Simulation time 258677597 ps
CPU time 1.29 seconds
Started Jun 27 04:46:48 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 214280 kb
Host smart-15077725-4435-4c32-be10-d6d458f68a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374750288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1374750288
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1100587101
Short name T218
Test name
Test status
Simulation time 434956549 ps
CPU time 4.34 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:11 PM PDT 24
Peak memory 209436 kb
Host smart-08616b94-9553-47d3-8dbc-363d48b32b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100587101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1100587101
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2416932221
Short name T754
Test name
Test status
Simulation time 274806407 ps
CPU time 9.06 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 218208 kb
Host smart-a613105e-be8f-42fd-993a-68117817ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416932221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2416932221
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.172761412
Short name T918
Test name
Test status
Simulation time 74873076 ps
CPU time 2.95 seconds
Started Jun 27 04:46:44 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 206692 kb
Host smart-da05dd39-dbc0-41b7-91f6-d3d42956a0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172761412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.172761412
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.11187956
Short name T672
Test name
Test status
Simulation time 35874002 ps
CPU time 2.51 seconds
Started Jun 27 04:47:01 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 208860 kb
Host smart-dd1f1226-d10d-4934-8265-98c039cc5b19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11187956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.11187956
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3708987717
Short name T596
Test name
Test status
Simulation time 192863272 ps
CPU time 2.7 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 206972 kb
Host smart-40e823ff-cb04-459d-aef8-48dd9e1c9f1e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708987717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3708987717
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1782749105
Short name T85
Test name
Test status
Simulation time 747058621 ps
CPU time 6.12 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 208152 kb
Host smart-d3b5fbe7-60a1-4e51-9b50-f8b69e8595cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782749105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1782749105
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.928188810
Short name T386
Test name
Test status
Simulation time 243581386 ps
CPU time 3.11 seconds
Started Jun 27 04:46:45 PM PDT 24
Finished Jun 27 04:46:59 PM PDT 24
Peak memory 208936 kb
Host smart-aad87d5f-3c09-4007-af62-0cab7bdc063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928188810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.928188810
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.667272564
Short name T655
Test name
Test status
Simulation time 322157641 ps
CPU time 3.77 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 208324 kb
Host smart-4da07019-953b-4c9c-aeb9-4a1283f903df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667272564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.667272564
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4132064653
Short name T402
Test name
Test status
Simulation time 8787530361 ps
CPU time 96.12 seconds
Started Jun 27 04:46:56 PM PDT 24
Finished Jun 27 04:48:44 PM PDT 24
Peak memory 217460 kb
Host smart-d7ef1f07-c9d2-4bd0-a49c-27de87d5675e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132064653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4132064653
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3545693947
Short name T840
Test name
Test status
Simulation time 345791533 ps
CPU time 9.41 seconds
Started Jun 27 04:46:52 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 222348 kb
Host smart-944f8ba0-a235-4a87-95eb-875b8ecc56e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545693947 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3545693947
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3026417713
Short name T406
Test name
Test status
Simulation time 62551869 ps
CPU time 2.62 seconds
Started Jun 27 04:47:03 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 209796 kb
Host smart-1b07eb74-a2cd-408f-b9dc-ddeaa16c6f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026417713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3026417713
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2167089951
Short name T614
Test name
Test status
Simulation time 31660907 ps
CPU time 0.91 seconds
Started Jun 27 04:46:50 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 206160 kb
Host smart-023e8ac7-166a-45a9-a9c7-dd01a44c0f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167089951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2167089951
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.772345991
Short name T239
Test name
Test status
Simulation time 54070203 ps
CPU time 3.59 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 214224 kb
Host smart-53c21b0d-2849-44c6-ac24-3eb88562a0c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772345991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.772345991
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2639479290
Short name T423
Test name
Test status
Simulation time 50589404 ps
CPU time 2.19 seconds
Started Jun 27 04:47:15 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 209836 kb
Host smart-6e644f29-fbd0-4bbc-b66c-52704ba8dbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639479290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2639479290
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2720502768
Short name T325
Test name
Test status
Simulation time 527222718 ps
CPU time 3.79 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 222396 kb
Host smart-f0b4df25-fa6b-41d8-8f43-bf352d6ba003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720502768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2720502768
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.539907673
Short name T350
Test name
Test status
Simulation time 154455124 ps
CPU time 1.89 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 214140 kb
Host smart-ffe39b7b-c87d-4895-8edf-190976defd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539907673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.539907673
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2687029952
Short name T225
Test name
Test status
Simulation time 76873212 ps
CPU time 4.26 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 220108 kb
Host smart-99534b1a-bb15-4fe9-a153-1315288a4396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687029952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2687029952
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1073166849
Short name T867
Test name
Test status
Simulation time 185906749 ps
CPU time 4.27 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 207608 kb
Host smart-dc644976-606a-4eeb-b3b7-3c6bde036db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073166849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1073166849
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1502743242
Short name T253
Test name
Test status
Simulation time 67145126 ps
CPU time 3.07 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 208676 kb
Host smart-a8170e96-d6af-44ad-8ece-2c9f43f2b720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502743242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1502743242
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.885646350
Short name T799
Test name
Test status
Simulation time 277020600 ps
CPU time 2.64 seconds
Started Jun 27 04:47:07 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 206856 kb
Host smart-3bbdf6d8-91e8-4bb6-9709-48a1eb87da03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885646350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.885646350
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3501637072
Short name T579
Test name
Test status
Simulation time 113383854 ps
CPU time 3.72 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 206880 kb
Host smart-35505056-5214-4928-bf0e-887087d7bf26
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501637072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3501637072
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1949674764
Short name T772
Test name
Test status
Simulation time 218757052 ps
CPU time 3.86 seconds
Started Jun 27 04:47:01 PM PDT 24
Finished Jun 27 04:47:17 PM PDT 24
Peak memory 206904 kb
Host smart-9503fd59-02f9-4be8-8df2-22aea3088743
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949674764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1949674764
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2313713419
Short name T240
Test name
Test status
Simulation time 960737761 ps
CPU time 14.73 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 208928 kb
Host smart-f2ef05ad-0ea3-4445-a368-91b89176709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313713419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2313713419
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2015369977
Short name T686
Test name
Test status
Simulation time 268993989 ps
CPU time 3.25 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 208028 kb
Host smart-972a3ba5-c128-4f65-9517-9c5c3157db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015369977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2015369977
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.87944546
Short name T363
Test name
Test status
Simulation time 36259097964 ps
CPU time 216.83 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 216708 kb
Host smart-81e1b916-632e-4c84-bb93-2f34331be6b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87944546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.87944546
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2828995556
Short name T893
Test name
Test status
Simulation time 612860533 ps
CPU time 6.52 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 208120 kb
Host smart-904814e9-ef40-4c2f-82d8-6d008a543016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828995556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2828995556
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1815422122
Short name T697
Test name
Test status
Simulation time 222400053 ps
CPU time 2.93 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:11 PM PDT 24
Peak memory 211004 kb
Host smart-87a652a5-e6f6-4147-9c33-24ba10b66486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815422122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1815422122
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3095304477
Short name T565
Test name
Test status
Simulation time 45001983 ps
CPU time 0.83 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:17 PM PDT 24
Peak memory 206044 kb
Host smart-8ea8f814-8781-4ab9-b946-fae54d61f61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095304477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3095304477
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2433743411
Short name T568
Test name
Test status
Simulation time 212959869 ps
CPU time 2.93 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:07 PM PDT 24
Peak memory 218508 kb
Host smart-9d4b04bb-fc2b-4e5f-b89f-a58cceb79745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433743411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2433743411
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1276548113
Short name T644
Test name
Test status
Simulation time 17762463 ps
CPU time 1.33 seconds
Started Jun 27 04:47:03 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 208220 kb
Host smart-7c8b631d-ddfe-486c-ae1b-55612203f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276548113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1276548113
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2705668278
Short name T865
Test name
Test status
Simulation time 872722428 ps
CPU time 2.44 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:08 PM PDT 24
Peak memory 214328 kb
Host smart-146c149a-2dce-4fb0-8b7a-32106e5eecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705668278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2705668278
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1841322052
Short name T876
Test name
Test status
Simulation time 299335391 ps
CPU time 2.69 seconds
Started Jun 27 04:46:44 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 209188 kb
Host smart-589fd27d-0501-419b-9f82-556c60aff860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841322052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1841322052
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3194866875
Short name T184
Test name
Test status
Simulation time 31051794 ps
CPU time 2.2 seconds
Started Jun 27 04:46:41 PM PDT 24
Finished Jun 27 04:46:55 PM PDT 24
Peak memory 207564 kb
Host smart-9a236a2b-6b42-44f8-9e8d-d708f7ef7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194866875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3194866875
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1558572876
Short name T625
Test name
Test status
Simulation time 722297472 ps
CPU time 5.37 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 207852 kb
Host smart-6a279ee2-ba39-42cd-8d15-972afa99dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558572876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1558572876
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2218114585
Short name T639
Test name
Test status
Simulation time 2613533288 ps
CPU time 26.57 seconds
Started Jun 27 04:46:47 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 207892 kb
Host smart-9bea04b7-a59c-4941-b683-dc7a717cbcab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218114585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2218114585
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2635400454
Short name T508
Test name
Test status
Simulation time 27041300 ps
CPU time 1.99 seconds
Started Jun 27 04:47:15 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 208588 kb
Host smart-5bcea8d6-250e-4b16-b435-1c7d37d44525
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635400454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2635400454
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1320653730
Short name T643
Test name
Test status
Simulation time 522992689 ps
CPU time 2.59 seconds
Started Jun 27 04:46:56 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 208588 kb
Host smart-ca783bb5-989e-4a83-8467-fb762cddb8d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320653730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1320653730
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2233162165
Short name T594
Test name
Test status
Simulation time 551111667 ps
CPU time 3.73 seconds
Started Jun 27 04:46:43 PM PDT 24
Finished Jun 27 04:46:57 PM PDT 24
Peak memory 208048 kb
Host smart-f30eaa7d-2316-45b5-a0be-7d8b9544e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233162165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2233162165
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.453337210
Short name T547
Test name
Test status
Simulation time 3788231157 ps
CPU time 10.14 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 208912 kb
Host smart-7998495b-8e1e-45c6-bf7b-293929c44142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453337210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.453337210
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3362301762
Short name T324
Test name
Test status
Simulation time 360890151 ps
CPU time 13.92 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 216576 kb
Host smart-046efab9-3d7f-4aba-9702-74add59c840b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362301762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3362301762
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.554973316
Short name T123
Test name
Test status
Simulation time 1766403812 ps
CPU time 11.77 seconds
Started Jun 27 04:46:51 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 218820 kb
Host smart-30dfef5c-f944-461e-9527-e2bbba3acc94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554973316 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.554973316
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3348215154
Short name T602
Test name
Test status
Simulation time 308526014 ps
CPU time 5.43 seconds
Started Jun 27 04:46:46 PM PDT 24
Finished Jun 27 04:47:02 PM PDT 24
Peak memory 210440 kb
Host smart-67f19473-5c7f-49e3-b858-ed399f5e3acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348215154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3348215154
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2242635240
Short name T82
Test name
Test status
Simulation time 112415976 ps
CPU time 0.77 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:07 PM PDT 24
Peak memory 206048 kb
Host smart-9ebf3fb8-71b9-4cab-81fa-8b86762cce60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242635240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2242635240
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3730177054
Short name T234
Test name
Test status
Simulation time 144441847 ps
CPU time 3.97 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 209296 kb
Host smart-463d26b9-ddb4-4927-b110-00cd7fd98102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730177054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3730177054
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4106267750
Short name T411
Test name
Test status
Simulation time 79277956 ps
CPU time 1.97 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:07 PM PDT 24
Peak memory 207364 kb
Host smart-4c2586c9-083f-4f4a-9d23-ed6dda21ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106267750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4106267750
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3806092966
Short name T717
Test name
Test status
Simulation time 52755390 ps
CPU time 2.98 seconds
Started Jun 27 04:46:56 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 210096 kb
Host smart-560773b8-4c64-47a5-8ef8-7a6a98af4b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806092966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3806092966
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1817216680
Short name T880
Test name
Test status
Simulation time 270284094 ps
CPU time 6.19 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 211980 kb
Host smart-8660eb26-b40a-4114-b130-b2886fc5e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817216680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1817216680
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4098009540
Short name T132
Test name
Test status
Simulation time 56335717 ps
CPU time 1.9 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 214360 kb
Host smart-d9916bf4-3fe3-41dc-b7ca-88552f164472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098009540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4098009540
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1775238093
Short name T747
Test name
Test status
Simulation time 452746272 ps
CPU time 5.61 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:11 PM PDT 24
Peak memory 218000 kb
Host smart-1df7eafb-7264-499a-adc0-d2de7280925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775238093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1775238093
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3261816528
Short name T360
Test name
Test status
Simulation time 72787486 ps
CPU time 3.15 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:08 PM PDT 24
Peak memory 208572 kb
Host smart-a0f3fe45-c409-4f99-8273-6b93eee93225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261816528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3261816528
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1435753651
Short name T441
Test name
Test status
Simulation time 142933604 ps
CPU time 2.29 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 208812 kb
Host smart-b8e89d15-fc00-4866-82b5-7a3d676d203b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435753651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1435753651
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2640677084
Short name T525
Test name
Test status
Simulation time 51281092 ps
CPU time 2.41 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:14 PM PDT 24
Peak memory 208300 kb
Host smart-551e5354-01f4-4002-9d71-7bd95e7b29a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640677084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2640677084
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2267351969
Short name T497
Test name
Test status
Simulation time 147693181 ps
CPU time 4.94 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 208688 kb
Host smart-4cb90f1a-ad93-4d18-8428-1b9f54a48742
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267351969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2267351969
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2140506047
Short name T450
Test name
Test status
Simulation time 104921359 ps
CPU time 3.44 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 209280 kb
Host smart-a547bf5f-0764-48e4-b3cb-c12cdae028ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140506047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2140506047
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3919591462
Short name T806
Test name
Test status
Simulation time 62105887 ps
CPU time 2.75 seconds
Started Jun 27 04:46:48 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 208508 kb
Host smart-9c431871-79e8-4da3-a98f-87f01c8d2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919591462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3919591462
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1920281831
Short name T714
Test name
Test status
Simulation time 649598438 ps
CPU time 8.48 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:26 PM PDT 24
Peak memory 222528 kb
Host smart-67ad561f-546b-4f3f-97d2-a1eb69179fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920281831 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1920281831
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1627018370
Short name T588
Test name
Test status
Simulation time 163819809 ps
CPU time 4.62 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 218268 kb
Host smart-959c7bd0-a25f-411b-b7d1-025d3148bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627018370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1627018370
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1731180772
Short name T675
Test name
Test status
Simulation time 46075128 ps
CPU time 2.01 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 209660 kb
Host smart-819af4e2-5844-410b-bb17-56849343f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731180772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1731180772
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.102579544
Short name T454
Test name
Test status
Simulation time 55240992 ps
CPU time 0.91 seconds
Started Jun 27 04:47:10 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 206004 kb
Host smart-8d29f997-d5d2-4c14-bd9a-8c4abc9259b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102579544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.102579544
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.933831141
Short name T430
Test name
Test status
Simulation time 92507578 ps
CPU time 3.34 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 214204 kb
Host smart-0c8e2ea6-5d94-415e-9eef-411e5c9cdcdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933831141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.933831141
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1950932724
Short name T265
Test name
Test status
Simulation time 56935828 ps
CPU time 2.48 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:08 PM PDT 24
Peak memory 209220 kb
Host smart-0b61162c-6aef-4cea-9720-9728b0ad2f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950932724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1950932724
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3832315294
Short name T884
Test name
Test status
Simulation time 115622665 ps
CPU time 2.27 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:06 PM PDT 24
Peak memory 214508 kb
Host smart-b4ecc880-b90d-43a4-b0ea-6fbc2e13783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832315294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3832315294
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4118281055
Short name T874
Test name
Test status
Simulation time 774517455 ps
CPU time 6.66 seconds
Started Jun 27 04:46:54 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 209560 kb
Host smart-6b0c8029-7948-4a4e-a9d5-010fa13c77c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118281055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4118281055
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4246072682
Short name T518
Test name
Test status
Simulation time 92732962 ps
CPU time 3.23 seconds
Started Jun 27 04:47:03 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 217948 kb
Host smart-912e7e0b-8136-4fcc-93b9-952f2d9609b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246072682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4246072682
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2392801327
Short name T362
Test name
Test status
Simulation time 240151434 ps
CPU time 2.77 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 208272 kb
Host smart-0f04183f-751d-4ba7-94cd-3e0fc8b0cd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392801327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2392801327
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3587603928
Short name T469
Test name
Test status
Simulation time 367864011 ps
CPU time 3.36 seconds
Started Jun 27 04:46:44 PM PDT 24
Finished Jun 27 04:46:57 PM PDT 24
Peak memory 206960 kb
Host smart-f6ab7c84-1e33-4d49-bcee-7b39dbd56c97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587603928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3587603928
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2932602401
Short name T582
Test name
Test status
Simulation time 472186733 ps
CPU time 2.36 seconds
Started Jun 27 04:47:01 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 206044 kb
Host smart-31316f26-c156-4487-853d-403f1ad1351f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932602401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2932602401
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.281479692
Short name T703
Test name
Test status
Simulation time 36478980 ps
CPU time 2.3 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 206920 kb
Host smart-d8766a90-dfb4-4349-8c74-0d4e53a591de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281479692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.281479692
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1689510682
Short name T276
Test name
Test status
Simulation time 113107756 ps
CPU time 4.2 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 209096 kb
Host smart-054cb6e3-eb42-425c-a228-960971af2b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689510682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1689510682
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3320907506
Short name T443
Test name
Test status
Simulation time 40356801 ps
CPU time 2.07 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 206888 kb
Host smart-1cfe8056-c7d8-4d5c-ab8f-ad2926aa33a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320907506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3320907506
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.883253351
Short name T719
Test name
Test status
Simulation time 259870722 ps
CPU time 7.14 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 218736 kb
Host smart-21af7197-ed97-4d77-a95a-c88689843dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883253351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.883253351
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2182429586
Short name T492
Test name
Test status
Simulation time 49722672 ps
CPU time 3.16 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 207216 kb
Host smart-bc92ec27-85a6-490d-8aa1-719ba1b65cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182429586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2182429586
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2276101570
Short name T114
Test name
Test status
Simulation time 110913579 ps
CPU time 1.58 seconds
Started Jun 27 04:46:59 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 210040 kb
Host smart-798218ad-913b-4255-ae41-038d77530770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276101570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2276101570
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1292629680
Short name T871
Test name
Test status
Simulation time 13592367 ps
CPU time 0.92 seconds
Started Jun 27 04:45:52 PM PDT 24
Finished Jun 27 04:45:54 PM PDT 24
Peak memory 206064 kb
Host smart-9d6bfa11-fb32-4315-ac7a-e7faf784b187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292629680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1292629680
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2430445800
Short name T849
Test name
Test status
Simulation time 166185729 ps
CPU time 3.32 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 215452 kb
Host smart-21954ae3-f8a2-49b6-927a-939ac916eeee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430445800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2430445800
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1155739227
Short name T859
Test name
Test status
Simulation time 123430717 ps
CPU time 2.69 seconds
Started Jun 27 04:45:56 PM PDT 24
Finished Jun 27 04:46:01 PM PDT 24
Peak memory 209344 kb
Host smart-cd330cc7-1ae7-4fc6-a529-6cbe51df8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155739227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1155739227
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1826839309
Short name T897
Test name
Test status
Simulation time 383910309 ps
CPU time 3.49 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 208744 kb
Host smart-13867eff-37a2-4e15-a109-5d7bb0998afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826839309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1826839309
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2367172940
Short name T804
Test name
Test status
Simulation time 49361462 ps
CPU time 2.17 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 213752 kb
Host smart-f9647e97-e06e-4a55-8b59-20734df83840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367172940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2367172940
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3191801344
Short name T637
Test name
Test status
Simulation time 82448239 ps
CPU time 1.65 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:04 PM PDT 24
Peak memory 207060 kb
Host smart-990fb7e2-55fb-4715-a4e2-a190bd9bfb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191801344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3191801344
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3886822660
Short name T645
Test name
Test status
Simulation time 179875401 ps
CPU time 5.58 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 208608 kb
Host smart-90813a3e-455e-4afe-99a2-9807fd275756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886822660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3886822660
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4081511722
Short name T543
Test name
Test status
Simulation time 51900908 ps
CPU time 2.56 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:45:58 PM PDT 24
Peak memory 208176 kb
Host smart-e8bc0487-a05f-42cd-8f11-05b1ea419680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081511722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4081511722
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1476136569
Short name T502
Test name
Test status
Simulation time 23550755 ps
CPU time 1.81 seconds
Started Jun 27 04:45:55 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 206828 kb
Host smart-7c2b6a45-b1dd-423a-9c1c-b6d6b1984471
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476136569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1476136569
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3150346991
Short name T537
Test name
Test status
Simulation time 4253786501 ps
CPU time 33.82 seconds
Started Jun 27 04:46:16 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 208716 kb
Host smart-6c561fbd-761e-4e98-a363-062ad85cc96d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150346991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3150346991
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3009863593
Short name T2
Test name
Test status
Simulation time 965736849 ps
CPU time 6.81 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:46:02 PM PDT 24
Peak memory 207848 kb
Host smart-549a6ffe-23ed-46bf-9266-4c230c60072a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009863593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3009863593
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4000493246
Short name T764
Test name
Test status
Simulation time 145827181 ps
CPU time 3.42 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 208564 kb
Host smart-b97e7952-84ea-40bb-8bf4-a71bbbcbb925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000493246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4000493246
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3643457863
Short name T81
Test name
Test status
Simulation time 401013937 ps
CPU time 2.46 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 205424 kb
Host smart-59597b68-0a19-428a-8152-8986fd42832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643457863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3643457863
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2841065587
Short name T574
Test name
Test status
Simulation time 878012322 ps
CPU time 4.75 seconds
Started Jun 27 04:45:53 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 207492 kb
Host smart-3fca10f5-3e58-4d83-97ed-8b90bc0a5cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841065587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2841065587
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2886274245
Short name T477
Test name
Test status
Simulation time 66329996 ps
CPU time 1.46 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:04 PM PDT 24
Peak memory 209792 kb
Host smart-2905eff4-97f7-4381-8754-f8b7c9c7945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886274245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2886274245
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2777617310
Short name T455
Test name
Test status
Simulation time 11596485 ps
CPU time 0.76 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 205928 kb
Host smart-1dea8b5c-8a2b-49de-921b-7406ade1fee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777617310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2777617310
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2355107650
Short name T663
Test name
Test status
Simulation time 178724017 ps
CPU time 4.24 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 221600 kb
Host smart-e2aea588-6195-469a-9060-e01f1707a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355107650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2355107650
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.690317777
Short name T901
Test name
Test status
Simulation time 122309364 ps
CPU time 3.99 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 209116 kb
Host smart-03842e27-e845-4120-8f01-3345c7e37930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690317777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.690317777
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4245899992
Short name T377
Test name
Test status
Simulation time 304296603 ps
CPU time 2.59 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 222400 kb
Host smart-586571c7-e533-4f7c-ab1a-1e046ef78268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245899992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4245899992
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.614024019
Short name T269
Test name
Test status
Simulation time 48964314 ps
CPU time 2.62 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 214260 kb
Host smart-f9478774-b3b2-4bf6-a86a-96db4e9829d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614024019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.614024019
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.878340550
Short name T696
Test name
Test status
Simulation time 962454301 ps
CPU time 10.91 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 222352 kb
Host smart-2e3a231c-56fd-4948-aab6-cfe742cecc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878340550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.878340550
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3686952641
Short name T586
Test name
Test status
Simulation time 177246174 ps
CPU time 5.66 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 218388 kb
Host smart-61cb3d13-58f9-47e4-9917-b606edc2501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686952641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3686952641
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2368927686
Short name T365
Test name
Test status
Simulation time 261309365 ps
CPU time 2.82 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 206848 kb
Host smart-81cf6888-87f9-40b7-aa52-d9ef3114caaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368927686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2368927686
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2146915833
Short name T80
Test name
Test status
Simulation time 107093311 ps
CPU time 3.11 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 207988 kb
Host smart-3a416f8f-035a-41aa-b4e3-78ee77c8a906
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146915833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2146915833
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2428858861
Short name T818
Test name
Test status
Simulation time 156963277 ps
CPU time 2.17 seconds
Started Jun 27 04:47:13 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 208780 kb
Host smart-15e8884c-78d7-40f9-99ef-1a4331724a31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428858861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2428858861
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2363297634
Short name T570
Test name
Test status
Simulation time 98305615 ps
CPU time 2.63 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 206768 kb
Host smart-af2bc60d-3469-4860-b38a-77a213747f24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363297634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2363297634
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1927958868
Short name T778
Test name
Test status
Simulation time 710905135 ps
CPU time 2.62 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 216220 kb
Host smart-532f293b-0fd3-4a0d-bc80-d4e72930df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927958868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1927958868
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3103267094
Short name T3
Test name
Test status
Simulation time 784570911 ps
CPU time 11.65 seconds
Started Jun 27 04:46:57 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 208364 kb
Host smart-2be878ea-b6c5-41ae-993f-4dbb3cdd860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103267094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3103267094
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.484599110
Short name T319
Test name
Test status
Simulation time 9664897319 ps
CPU time 35.54 seconds
Started Jun 27 04:47:15 PM PDT 24
Finished Jun 27 04:48:00 PM PDT 24
Peak memory 215836 kb
Host smart-3feeea01-af00-4ef1-afd3-283e38eb8cdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484599110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.484599110
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2108114789
Short name T407
Test name
Test status
Simulation time 118999527 ps
CPU time 4.3 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 218088 kb
Host smart-182f83e6-3063-4908-8eca-db43aae36dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108114789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2108114789
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3420997303
Short name T64
Test name
Test status
Simulation time 30157931 ps
CPU time 2.04 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 210292 kb
Host smart-ca224a4c-c743-4bd0-8d4e-eabb6935f16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420997303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3420997303
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4245626039
Short name T711
Test name
Test status
Simulation time 56866248 ps
CPU time 0.77 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 206036 kb
Host smart-ec5a3694-bc69-4dd2-8996-13f40b2fda6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245626039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4245626039
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2627281561
Short name T416
Test name
Test status
Simulation time 219925566 ps
CPU time 10.57 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 214328 kb
Host smart-065681e6-483a-4b23-99c0-beef66a89060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627281561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2627281561
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4134351436
Short name T20
Test name
Test status
Simulation time 129240039 ps
CPU time 5.32 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 221892 kb
Host smart-4727e611-0533-4a78-8458-7b756cd1ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134351436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4134351436
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1025193767
Short name T76
Test name
Test status
Simulation time 10965757689 ps
CPU time 48.58 seconds
Started Jun 27 04:46:55 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 208664 kb
Host smart-c1b934d0-ae2a-4deb-8543-f76b248bd743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025193767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1025193767
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2579910395
Short name T99
Test name
Test status
Simulation time 120409320 ps
CPU time 4.56 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 214268 kb
Host smart-7025675f-8612-4c49-ba32-0fc537e71db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579910395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2579910395
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2095099210
Short name T352
Test name
Test status
Simulation time 144759519 ps
CPU time 3.5 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 214272 kb
Host smart-19377032-e21b-4741-b166-4283d285f144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095099210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2095099210
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3900384771
Short name T658
Test name
Test status
Simulation time 274257752 ps
CPU time 3.67 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 209496 kb
Host smart-f6ab202c-59ff-46a9-b9f6-57627cf59fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900384771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3900384771
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3475649046
Short name T889
Test name
Test status
Simulation time 726729458 ps
CPU time 24.87 seconds
Started Jun 27 04:47:13 PM PDT 24
Finished Jun 27 04:47:48 PM PDT 24
Peak memory 208904 kb
Host smart-e0d19459-e219-4399-bf77-41c955240b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475649046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3475649046
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2619014752
Short name T303
Test name
Test status
Simulation time 346249433 ps
CPU time 3.1 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 206888 kb
Host smart-f7b4b6a5-f5c0-44a4-a10c-48b9d1e891bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619014752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2619014752
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.140272948
Short name T254
Test name
Test status
Simulation time 137302180 ps
CPU time 4.81 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:18 PM PDT 24
Peak memory 208608 kb
Host smart-ee21e33e-d43f-4931-93ab-d3f53f50f1e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140272948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.140272948
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.500246109
Short name T844
Test name
Test status
Simulation time 229634633 ps
CPU time 3.35 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 208580 kb
Host smart-3fb80707-a473-484f-b3cb-92364f12d923
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500246109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.500246109
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2084505143
Short name T559
Test name
Test status
Simulation time 109750239 ps
CPU time 3.47 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:29 PM PDT 24
Peak memory 206924 kb
Host smart-7342dbaf-83ba-4665-8430-3b8a38eb1a8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084505143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2084505143
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.816415386
Short name T584
Test name
Test status
Simulation time 488349218 ps
CPU time 4.22 seconds
Started Jun 27 04:47:10 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 214320 kb
Host smart-e8dd957f-e069-44b3-a0db-d976b78db6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816415386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.816415386
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2664014017
Short name T782
Test name
Test status
Simulation time 508534843 ps
CPU time 8.16 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 208364 kb
Host smart-ef93a45a-97ef-4368-af84-529417cb12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664014017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2664014017
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3726801034
Short name T524
Test name
Test status
Simulation time 374784227 ps
CPU time 4.44 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 209164 kb
Host smart-b903eaa3-5caf-4b6d-b09e-d4392f41132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726801034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3726801034
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3414708216
Short name T159
Test name
Test status
Simulation time 87450000 ps
CPU time 2.85 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 209900 kb
Host smart-369e3add-1aef-4398-a87e-b16d44a8368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414708216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3414708216
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1593253645
Short name T448
Test name
Test status
Simulation time 13978505 ps
CPU time 0.94 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 206036 kb
Host smart-9d7865a6-1e80-4b76-9bf6-6fa3306cc680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593253645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1593253645
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1095207876
Short name T879
Test name
Test status
Simulation time 157514264 ps
CPU time 3.01 seconds
Started Jun 27 04:47:10 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 209380 kb
Host smart-7a254776-8b5b-425b-8586-e61550a7bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095207876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1095207876
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2441981678
Short name T869
Test name
Test status
Simulation time 369348659 ps
CPU time 3.01 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 214312 kb
Host smart-28f840a5-6278-4a29-8b20-d3d5f8fb1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441981678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2441981678
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2996458841
Short name T88
Test name
Test status
Simulation time 55308684 ps
CPU time 2.02 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:29 PM PDT 24
Peak memory 214328 kb
Host smart-80f42336-c081-4b8f-be3b-7ae2259e6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996458841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2996458841
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2394000028
Short name T864
Test name
Test status
Simulation time 406392783 ps
CPU time 2.8 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 214292 kb
Host smart-bc598765-e517-4b37-b735-64e333faf6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394000028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2394000028
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.485806572
Short name T761
Test name
Test status
Simulation time 540956190 ps
CPU time 4.87 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 222516 kb
Host smart-e9441cde-fac7-426c-b397-510f05f1f7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485806572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.485806572
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2575957895
Short name T283
Test name
Test status
Simulation time 1801410670 ps
CPU time 13.63 seconds
Started Jun 27 04:47:17 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 214216 kb
Host smart-83122466-5688-42e9-8a81-3fdbd0088af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575957895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2575957895
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4018867611
Short name T193
Test name
Test status
Simulation time 729792184 ps
CPU time 6.88 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 207816 kb
Host smart-46fdd42a-c19f-46f5-99f4-a7626dc54e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018867611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4018867611
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1012457328
Short name T195
Test name
Test status
Simulation time 939988059 ps
CPU time 26.87 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:47 PM PDT 24
Peak memory 208540 kb
Host smart-d5dfd46b-e5c4-44e9-98a4-e8848e9bb1b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012457328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1012457328
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2738561838
Short name T510
Test name
Test status
Simulation time 2757498530 ps
CPU time 21.06 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 208056 kb
Host smart-922f71e3-6374-4677-bc6f-2b4d6956eb42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738561838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2738561838
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.728673904
Short name T833
Test name
Test status
Simulation time 3179646094 ps
CPU time 23.56 seconds
Started Jun 27 04:47:15 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 208656 kb
Host smart-941a50d5-30f3-41d4-b47d-0766f4229c9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728673904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.728673904
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1231008148
Short name T821
Test name
Test status
Simulation time 2163415248 ps
CPU time 5.08 seconds
Started Jun 27 04:47:03 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 208760 kb
Host smart-1301bba4-3f5e-4f03-b8ce-b4530c0ff593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231008148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1231008148
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3161328832
Short name T413
Test name
Test status
Simulation time 4981827028 ps
CPU time 29.81 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 208288 kb
Host smart-e59e91c6-9e15-4292-8151-8bee2d570982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161328832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3161328832
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3989552764
Short name T603
Test name
Test status
Simulation time 123807284 ps
CPU time 2.8 seconds
Started Jun 27 04:47:13 PM PDT 24
Finished Jun 27 04:47:26 PM PDT 24
Peak memory 210088 kb
Host smart-6688ea31-5498-4de8-be2a-6b1855a8e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989552764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3989552764
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3444434005
Short name T14
Test name
Test status
Simulation time 742572151 ps
CPU time 18.04 seconds
Started Jun 27 04:47:15 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 210988 kb
Host smart-24e30816-e995-46cb-b082-bc3981e2d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444434005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3444434005
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.881750839
Short name T668
Test name
Test status
Simulation time 36484391 ps
CPU time 0.81 seconds
Started Jun 27 04:47:06 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 206064 kb
Host smart-fa1a46d0-8176-47ef-836f-5d38749c479c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881750839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.881750839
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1957479947
Short name T887
Test name
Test status
Simulation time 44492381 ps
CPU time 3.26 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 222404 kb
Host smart-9f0d350a-4fd6-46e8-a1dd-875f1c5c2691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957479947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1957479947
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2585365316
Short name T28
Test name
Test status
Simulation time 1941854100 ps
CPU time 12.04 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:26 PM PDT 24
Peak memory 222948 kb
Host smart-7ae2d0bd-a7b6-4ee2-bde1-55c187f960b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585365316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2585365316
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1597792419
Short name T59
Test name
Test status
Simulation time 122386803 ps
CPU time 2.84 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 207460 kb
Host smart-02bad5f0-8617-41e3-a233-c7ddd2ab7f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597792419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1597792419
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1308962355
Short name T802
Test name
Test status
Simulation time 187832574 ps
CPU time 1.99 seconds
Started Jun 27 04:47:10 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 214208 kb
Host smart-2973e24c-6747-4cd8-a639-bed1e7e3012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308962355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1308962355
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2453125149
Short name T803
Test name
Test status
Simulation time 99803965 ps
CPU time 3.48 seconds
Started Jun 27 04:47:04 PM PDT 24
Finished Jun 27 04:47:20 PM PDT 24
Peak memory 220412 kb
Host smart-ade1562c-3c9a-45f8-8142-d755a7291f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453125149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2453125149
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3566548122
Short name T314
Test name
Test status
Simulation time 185921631 ps
CPU time 3.47 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 222420 kb
Host smart-939369dd-0248-4658-a6b8-242603b87e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566548122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3566548122
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.39901999
Short name T766
Test name
Test status
Simulation time 45962052 ps
CPU time 3.15 seconds
Started Jun 27 04:47:07 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 214324 kb
Host smart-cd0b24ab-9001-4c6c-a588-a5593fa24062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39901999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.39901999
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1563441064
Short name T788
Test name
Test status
Simulation time 191591993 ps
CPU time 2.68 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 206728 kb
Host smart-324b204c-d41a-43ff-b433-33c2d6a9e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563441064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1563441064
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3866699932
Short name T209
Test name
Test status
Simulation time 202550002 ps
CPU time 2.94 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 206964 kb
Host smart-98b5de2b-393f-4500-8024-62f52f6a474a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866699932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3866699932
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2818451259
Short name T585
Test name
Test status
Simulation time 41403180 ps
CPU time 2.73 seconds
Started Jun 27 04:47:00 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 208784 kb
Host smart-29f331ba-da49-435c-8ce5-41430d8fb962
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818451259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2818451259
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2733422561
Short name T649
Test name
Test status
Simulation time 499843275 ps
CPU time 5.59 seconds
Started Jun 27 04:46:56 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 208236 kb
Host smart-9dc41c2d-5639-469c-a66b-6c97c8fe4205
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733422561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2733422561
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1566658242
Short name T896
Test name
Test status
Simulation time 283395608 ps
CPU time 3.04 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 207556 kb
Host smart-973b8e60-63f7-4cb3-9992-873bb0fc8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566658242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1566658242
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3059020403
Short name T126
Test name
Test status
Simulation time 136251099 ps
CPU time 3.42 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 208336 kb
Host smart-f8684d02-b23b-48e9-9231-e76a61559e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059020403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3059020403
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2066281865
Short name T155
Test name
Test status
Simulation time 541643440 ps
CPU time 8.3 seconds
Started Jun 27 04:47:02 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 220368 kb
Host smart-a03e35c6-d6a3-4068-a1d9-94fc5d081212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066281865 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2066281865
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2822685296
Short name T278
Test name
Test status
Simulation time 144996355 ps
CPU time 5.73 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:26 PM PDT 24
Peak memory 208172 kb
Host smart-809485d7-f1ce-4ece-88d3-fd55a6a3bf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822685296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2822685296
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1123977948
Short name T198
Test name
Test status
Simulation time 183980389 ps
CPU time 2.17 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 210112 kb
Host smart-cb02ad36-3a4d-41e7-bddc-70b4b4aa4095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123977948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1123977948
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3256977614
Short name T105
Test name
Test status
Simulation time 44204623 ps
CPU time 0.83 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 206064 kb
Host smart-9f766f04-ddd0-436d-95bc-501e754cd382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256977614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3256977614
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3859076816
Short name T295
Test name
Test status
Simulation time 36020454 ps
CPU time 2.61 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 215144 kb
Host smart-4b3bb232-be93-4c52-a42c-ba99028cd606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859076816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3859076816
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4096654742
Short name T9
Test name
Test status
Simulation time 6682369441 ps
CPU time 56.22 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 222924 kb
Host smart-ee310a98-152e-4310-bf8b-600b1fed0ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096654742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4096654742
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4114876329
Short name T73
Test name
Test status
Simulation time 20256938 ps
CPU time 1.51 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 208180 kb
Host smart-29a570e3-3e51-4806-a33c-d06667fcaf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114876329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4114876329
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.905947629
Short name T520
Test name
Test status
Simulation time 442365013 ps
CPU time 6.51 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 214324 kb
Host smart-eef59941-84cc-47ef-8a1d-dfea645d7c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905947629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.905947629
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.810839586
Short name T83
Test name
Test status
Simulation time 73533673 ps
CPU time 2.39 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 214276 kb
Host smart-5c6a2650-b87d-47aa-840c-9d786632ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810839586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.810839586
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1954648292
Short name T215
Test name
Test status
Simulation time 105607218 ps
CPU time 3.64 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:31 PM PDT 24
Peak memory 219860 kb
Host smart-09afbfed-2488-4163-99a3-339f8ece435e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954648292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1954648292
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4060961354
Short name T293
Test name
Test status
Simulation time 652939817 ps
CPU time 5 seconds
Started Jun 27 04:47:28 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 209072 kb
Host smart-dc93a096-5e57-4dc1-b754-2000924d2895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060961354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4060961354
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3469256291
Short name T882
Test name
Test status
Simulation time 119380082 ps
CPU time 3.74 seconds
Started Jun 27 04:47:05 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 207848 kb
Host smart-3f269770-5ac1-4111-b72c-1e585221d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469256291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3469256291
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.328530914
Short name T917
Test name
Test status
Simulation time 164804247 ps
CPU time 5.57 seconds
Started Jun 27 04:47:03 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 206968 kb
Host smart-e79ac301-7000-4106-80d0-7976ee155c6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328530914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.328530914
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3520670625
Short name T613
Test name
Test status
Simulation time 6629074090 ps
CPU time 21.13 seconds
Started Jun 27 04:47:01 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 208180 kb
Host smart-04a95806-db73-4dcf-b226-9740b6e954a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520670625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3520670625
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.755168206
Short name T617
Test name
Test status
Simulation time 49040046 ps
CPU time 2.84 seconds
Started Jun 27 04:46:58 PM PDT 24
Finished Jun 27 04:47:12 PM PDT 24
Peak memory 207100 kb
Host smart-d0b14f16-12ec-42ec-8789-4d7159c1b053
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755168206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.755168206
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2839837368
Short name T744
Test name
Test status
Simulation time 120979317 ps
CPU time 1.83 seconds
Started Jun 27 04:47:17 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 207244 kb
Host smart-59a2648e-8afa-49d0-83bd-b0a58ad77498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839837368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2839837368
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.738875219
Short name T466
Test name
Test status
Simulation time 63611843 ps
CPU time 2.31 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:22 PM PDT 24
Peak memory 207192 kb
Host smart-db938fe1-43e3-4329-b4c8-dea4e2e17d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738875219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.738875219
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1053351542
Short name T383
Test name
Test status
Simulation time 1390991997 ps
CPU time 20.03 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 216548 kb
Host smart-66b6587a-7d21-4923-a0c0-8ac9afe7c5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053351542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1053351542
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.806243987
Short name T834
Test name
Test status
Simulation time 470714432 ps
CPU time 5.23 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 209220 kb
Host smart-ac320b8f-5d11-45bd-8784-fcd2727e55bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806243987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.806243987
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1578553739
Short name T877
Test name
Test status
Simulation time 95022729 ps
CPU time 2.76 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 210572 kb
Host smart-dffae55b-fbdd-483e-8144-1cd727b49c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578553739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1578553739
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3491410784
Short name T654
Test name
Test status
Simulation time 12125661 ps
CPU time 0.7 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 206064 kb
Host smart-8e38a5fe-72a8-41fb-acfb-13da84d1071a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491410784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3491410784
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1370442634
Short name T388
Test name
Test status
Simulation time 77079216 ps
CPU time 3.24 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 214896 kb
Host smart-77456472-5410-4d93-9e7a-b8c18304764e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370442634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1370442634
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2672575897
Short name T71
Test name
Test status
Simulation time 62606953 ps
CPU time 3.24 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 209036 kb
Host smart-be13a5bc-ec89-4b90-80f7-5e549caffcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672575897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2672575897
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1652958446
Short name T370
Test name
Test status
Simulation time 180693553 ps
CPU time 3.74 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 208592 kb
Host smart-2176fd7f-2c09-4c5f-8cd3-4eb108071266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652958446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1652958446
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2017125835
Short name T38
Test name
Test status
Simulation time 104294986 ps
CPU time 3.89 seconds
Started Jun 27 04:47:09 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 222328 kb
Host smart-7a25c9a8-73a1-43e8-a955-2643c98caba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017125835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2017125835
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.883058609
Short name T809
Test name
Test status
Simulation time 213686202 ps
CPU time 4.66 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:27 PM PDT 24
Peak memory 209536 kb
Host smart-3ebb38c2-23f4-43c3-8e2d-40c419118cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883058609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.883058609
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1377174617
Short name T465
Test name
Test status
Simulation time 206326815 ps
CPU time 4.25 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 214388 kb
Host smart-6b239c4f-59fc-4124-a94a-1553e3d72a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377174617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1377174617
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2652406234
Short name T107
Test name
Test status
Simulation time 58855302 ps
CPU time 3.08 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:26 PM PDT 24
Peak memory 208144 kb
Host smart-16a49718-89f2-42ae-b0ee-d200a4308bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652406234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2652406234
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4079532622
Short name T810
Test name
Test status
Simulation time 891539856 ps
CPU time 2.72 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 206824 kb
Host smart-0500381a-a161-4389-8afd-85b9b5f51d99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079532622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4079532622
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1916236639
Short name T752
Test name
Test status
Simulation time 756130919 ps
CPU time 10.83 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:39 PM PDT 24
Peak memory 208820 kb
Host smart-f4be631c-efa1-42f0-bf58-1284fdc00ff3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916236639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1916236639
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2760308779
Short name T536
Test name
Test status
Simulation time 124981681 ps
CPU time 3.87 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 208588 kb
Host smart-fe2269f4-f5db-421a-ac58-1f938e82627d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760308779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2760308779
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2176771809
Short name T369
Test name
Test status
Simulation time 110880628 ps
CPU time 4.66 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 218212 kb
Host smart-3a2191df-be24-40dd-8dec-f0690ccdd94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176771809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2176771809
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4075288424
Short name T127
Test name
Test status
Simulation time 23347308 ps
CPU time 1.91 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 208384 kb
Host smart-52c0e52f-ad64-4b8d-848d-5730fbd832d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075288424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4075288424
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4084620787
Short name T231
Test name
Test status
Simulation time 618416098 ps
CPU time 9.37 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 222460 kb
Host smart-13459b2e-843a-45e8-ad02-6072f60ff461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084620787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4084620787
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.730413533
Short name T836
Test name
Test status
Simulation time 3524685436 ps
CPU time 19.45 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 214252 kb
Host smart-dd8ea015-60ed-4e55-bdc9-704324d9c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730413533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.730413533
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1818798401
Short name T553
Test name
Test status
Simulation time 6760488278 ps
CPU time 8.95 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:30 PM PDT 24
Peak memory 211292 kb
Host smart-306b682b-995f-4b79-aa98-6f49d4f459bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818798401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1818798401
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1542876699
Short name T467
Test name
Test status
Simulation time 25545943 ps
CPU time 0.84 seconds
Started Jun 27 04:47:25 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 206064 kb
Host smart-41856377-8c9c-4e9f-98b6-1ae708b6aed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542876699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1542876699
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2219552169
Short name T851
Test name
Test status
Simulation time 285704951 ps
CPU time 5.15 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 222316 kb
Host smart-33ea4a51-f003-4a9c-8b13-77f8b623e15a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219552169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2219552169
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4132292371
Short name T32
Test name
Test status
Simulation time 234450435 ps
CPU time 1.86 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 221740 kb
Host smart-57a6a8d8-b67a-4e2f-9134-69952232a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132292371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4132292371
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2464120724
Short name T289
Test name
Test status
Simulation time 1500014412 ps
CPU time 16.74 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 218576 kb
Host smart-2db56fc8-5a83-4c81-b80d-0d3994b6a52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464120724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2464120724
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3239855556
Short name T819
Test name
Test status
Simulation time 535265965 ps
CPU time 7.2 seconds
Started Jun 27 04:47:25 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 214396 kb
Host smart-829b29e2-0955-4804-9f63-6be11ba4da37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239855556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3239855556
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1209331237
Short name T96
Test name
Test status
Simulation time 95170133 ps
CPU time 1.91 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 222380 kb
Host smart-e0ef6418-c6a2-4989-a21d-6ec8db191877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209331237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1209331237
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3680749481
Short name T48
Test name
Test status
Simulation time 98056941 ps
CPU time 2.94 seconds
Started Jun 27 04:47:11 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 207260 kb
Host smart-13f5baa1-541e-470a-b653-01f880204266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680749481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3680749481
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2113208381
Short name T280
Test name
Test status
Simulation time 70623258 ps
CPU time 3.56 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 209916 kb
Host smart-5a6ca87a-7e23-4f96-b2b1-e2910c95f4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113208381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2113208381
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3169163002
Short name T301
Test name
Test status
Simulation time 813123332 ps
CPU time 3.83 seconds
Started Jun 27 04:47:26 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 207144 kb
Host smart-3f256ce6-2224-44c3-ae4a-2bb15e3645ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169163002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3169163002
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1193296455
Short name T732
Test name
Test status
Simulation time 48553504 ps
CPU time 2.25 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:24 PM PDT 24
Peak memory 208744 kb
Host smart-0dee1ab1-b08c-4099-993a-3bde332ba6db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193296455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1193296455
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1987133093
Short name T334
Test name
Test status
Simulation time 37413957 ps
CPU time 2.7 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 208828 kb
Host smart-d8d3203e-948f-4875-9bef-fc35b2f0be21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987133093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1987133093
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.461765450
Short name T738
Test name
Test status
Simulation time 66468764 ps
CPU time 2.17 seconds
Started Jun 27 04:47:20 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 207036 kb
Host smart-c1c788f0-9282-4c3d-8059-c1bf099d54e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461765450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.461765450
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.953401165
Short name T277
Test name
Test status
Simulation time 63253940 ps
CPU time 2.52 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:29 PM PDT 24
Peak memory 209252 kb
Host smart-1b2cb78e-1c74-48d5-bb7f-d34132043a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953401165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.953401165
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2226769843
Short name T646
Test name
Test status
Simulation time 365415667 ps
CPU time 3.73 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 207176 kb
Host smart-a67ec326-36b2-4e11-ab74-63cd2c24d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226769843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2226769843
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4290604548
Short name T257
Test name
Test status
Simulation time 2486413697 ps
CPU time 64.98 seconds
Started Jun 27 04:47:28 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 219256 kb
Host smart-79e9429a-7d20-4207-82ca-7887ccb8e0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290604548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4290604548
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3304075978
Short name T124
Test name
Test status
Simulation time 2136398117 ps
CPU time 22.3 seconds
Started Jun 27 04:47:26 PM PDT 24
Finished Jun 27 04:47:55 PM PDT 24
Peak memory 219900 kb
Host smart-ad757f73-7349-4c94-83d2-358616226456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304075978 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3304075978
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.649607347
Short name T341
Test name
Test status
Simulation time 105785062 ps
CPU time 5.14 seconds
Started Jun 27 04:47:28 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 209016 kb
Host smart-c6bfef2e-0c7e-4150-a9d5-ea9bd0b976b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649607347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.649607347
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2015917482
Short name T65
Test name
Test status
Simulation time 1126391821 ps
CPU time 17.12 seconds
Started Jun 27 04:47:12 PM PDT 24
Finished Jun 27 04:47:39 PM PDT 24
Peak memory 211024 kb
Host smart-6bd48a40-a86d-45ef-bb5a-b76b3ad49f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015917482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2015917482
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.859247375
Short name T459
Test name
Test status
Simulation time 13106095 ps
CPU time 0.91 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:31 PM PDT 24
Peak memory 206124 kb
Host smart-b3fca331-7ae3-42c7-8acc-a42fc8a0ca82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859247375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.859247375
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2451755829
Short name T26
Test name
Test status
Simulation time 935209454 ps
CPU time 2.22 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 216136 kb
Host smart-900be16e-8dcf-46bc-85f0-c2192519c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451755829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2451755829
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.157853004
Short name T660
Test name
Test status
Simulation time 277164037 ps
CPU time 4.02 seconds
Started Jun 27 04:47:29 PM PDT 24
Finished Jun 27 04:47:39 PM PDT 24
Peak memory 209108 kb
Host smart-ec605ab4-1b2a-4d3d-a987-16313793390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157853004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.157853004
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1079398865
Short name T97
Test name
Test status
Simulation time 130755109 ps
CPU time 2.51 seconds
Started Jun 27 04:47:26 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 214288 kb
Host smart-af8624e9-0a30-4322-ae98-1e6349a1501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079398865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1079398865
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3032703749
Short name T814
Test name
Test status
Simulation time 566812546 ps
CPU time 4.1 seconds
Started Jun 27 04:47:25 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 214108 kb
Host smart-04d36f17-4ce0-4c7a-be30-0c1c2ee7b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032703749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3032703749
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1310782714
Short name T629
Test name
Test status
Simulation time 763498233 ps
CPU time 3.99 seconds
Started Jun 27 04:47:21 PM PDT 24
Finished Jun 27 04:47:34 PM PDT 24
Peak memory 215732 kb
Host smart-4cd84956-6f45-4dbd-8929-c35b98864284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310782714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1310782714
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2454136674
Short name T392
Test name
Test status
Simulation time 64546334 ps
CPU time 2.98 seconds
Started Jun 27 04:47:26 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 209316 kb
Host smart-cb26102f-3d9c-4ea1-b80c-3ae49f901fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454136674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2454136674
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1928147672
Short name T404
Test name
Test status
Simulation time 74452466 ps
CPU time 2.74 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 207008 kb
Host smart-91576f25-0ca5-4c72-a5a4-464bbbd3c18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928147672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1928147672
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3567935701
Short name T333
Test name
Test status
Simulation time 77548335 ps
CPU time 3.61 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:35 PM PDT 24
Peak memory 208828 kb
Host smart-8502dcd6-f906-4dd2-8feb-97ea7cfb3587
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567935701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3567935701
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.605266490
Short name T776
Test name
Test status
Simulation time 805932597 ps
CPU time 8.57 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 207036 kb
Host smart-4040e9e6-f045-4a9f-97a0-71d576f0876b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605266490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.605266490
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1849732650
Short name T339
Test name
Test status
Simulation time 94863690 ps
CPU time 2.7 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 208908 kb
Host smart-27179364-6867-43e7-9727-12ee62fbb77e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849732650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1849732650
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2781683590
Short name T296
Test name
Test status
Simulation time 84403404 ps
CPU time 4.11 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 209968 kb
Host smart-b57e7d48-cbdc-4177-aeea-07076ac9b433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781683590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2781683590
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3981324939
Short name T452
Test name
Test status
Simulation time 207617727 ps
CPU time 2.5 seconds
Started Jun 27 04:47:22 PM PDT 24
Finished Jun 27 04:47:33 PM PDT 24
Peak memory 208880 kb
Host smart-29fd8cf0-bdbb-49e5-a710-e0a74dfaf854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981324939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3981324939
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3973189116
Short name T515
Test name
Test status
Simulation time 6855275384 ps
CPU time 60.59 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 208016 kb
Host smart-49f76686-edb5-4fb8-956b-3cdba7d3e1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973189116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3973189116
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1806624388
Short name T153
Test name
Test status
Simulation time 245967335 ps
CPU time 10.13 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 220476 kb
Host smart-9ffc5880-676e-489f-a96f-eca84a02ecf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806624388 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1806624388
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1457736204
Short name T730
Test name
Test status
Simulation time 249016243 ps
CPU time 4.4 seconds
Started Jun 27 04:47:25 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 207124 kb
Host smart-72737999-e61b-41f9-9a68-62a017be62f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457736204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1457736204
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2237028949
Short name T400
Test name
Test status
Simulation time 489385923 ps
CPU time 7.38 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 210684 kb
Host smart-6e7d5d07-62c1-47c6-9da6-fa4f138f8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237028949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2237028949
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1059107240
Short name T773
Test name
Test status
Simulation time 13700935 ps
CPU time 0.92 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 206020 kb
Host smart-0d85fc4f-2b49-49ad-9286-9d19f93baae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059107240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1059107240
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1101217099
Short name T223
Test name
Test status
Simulation time 441653820 ps
CPU time 5.22 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 222792 kb
Host smart-6f05a12c-882d-4525-a161-1118395f1bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101217099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1101217099
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1687590172
Short name T304
Test name
Test status
Simulation time 76947029 ps
CPU time 2.48 seconds
Started Jun 27 04:47:16 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 218228 kb
Host smart-81e13eef-65c9-4856-a652-0de61af2c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687590172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1687590172
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.388036784
Short name T855
Test name
Test status
Simulation time 136338802 ps
CPU time 4.28 seconds
Started Jun 27 04:47:14 PM PDT 24
Finished Jun 27 04:47:28 PM PDT 24
Peak memory 206896 kb
Host smart-5d67cb86-6cc8-4efc-8e23-33c5a8cd219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388036784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.388036784
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3971169685
Short name T49
Test name
Test status
Simulation time 172676449 ps
CPU time 2.58 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:31 PM PDT 24
Peak memory 214356 kb
Host smart-f80fa856-518c-4ed4-ba8d-87340de3c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971169685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3971169685
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2956640661
Short name T322
Test name
Test status
Simulation time 85520051 ps
CPU time 4.01 seconds
Started Jun 27 04:47:10 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 207496 kb
Host smart-789d306c-1676-449f-9b1c-11d94053c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956640661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2956640661
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2160741370
Short name T777
Test name
Test status
Simulation time 122499936 ps
CPU time 2.26 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:47:39 PM PDT 24
Peak memory 206608 kb
Host smart-2e58c036-9c14-4858-94e6-903f6dae6e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160741370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2160741370
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2718739905
Short name T499
Test name
Test status
Simulation time 460887418 ps
CPU time 3.26 seconds
Started Jun 27 04:47:24 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 206956 kb
Host smart-6b24845a-bcff-41c6-bacd-27b2995050e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718739905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2718739905
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4221428493
Short name T878
Test name
Test status
Simulation time 492254986 ps
CPU time 4.04 seconds
Started Jun 27 04:47:25 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 207020 kb
Host smart-0f1e8f94-e9dd-43f0-9639-2036f50db63e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221428493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4221428493
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.646756827
Short name T408
Test name
Test status
Simulation time 324316592 ps
CPU time 3.04 seconds
Started Jun 27 04:47:19 PM PDT 24
Finished Jun 27 04:47:32 PM PDT 24
Peak memory 206832 kb
Host smart-9e8c6787-837e-4ccc-9413-9ad9850c3808
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646756827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.646756827
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1027880614
Short name T444
Test name
Test status
Simulation time 169340406 ps
CPU time 2.72 seconds
Started Jun 27 04:47:18 PM PDT 24
Finished Jun 27 04:47:29 PM PDT 24
Peak memory 206852 kb
Host smart-c1f920ec-c1c1-49b6-a06e-00ac51a3d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027880614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1027880614
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1776333841
Short name T526
Test name
Test status
Simulation time 118527823 ps
CPU time 2.73 seconds
Started Jun 27 04:47:30 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 208584 kb
Host smart-5eedfa2b-a0ee-4b45-839d-1b7de14eb4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776333841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1776333841
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2091592445
Short name T881
Test name
Test status
Simulation time 667645537 ps
CPU time 10.67 seconds
Started Jun 27 04:47:17 PM PDT 24
Finished Jun 27 04:47:37 PM PDT 24
Peak memory 222524 kb
Host smart-619138c0-db68-4710-8f5b-60c0246e89ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091592445 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2091592445
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2912487237
Short name T824
Test name
Test status
Simulation time 832520203 ps
CPU time 6.37 seconds
Started Jun 27 04:47:23 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 209212 kb
Host smart-a2a43b24-8222-4562-ad7f-844df3b5b4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912487237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2912487237
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1553791137
Short name T166
Test name
Test status
Simulation time 160204701 ps
CPU time 3.07 seconds
Started Jun 27 04:47:17 PM PDT 24
Finished Jun 27 04:47:29 PM PDT 24
Peak memory 210416 kb
Host smart-dbd891a2-46f9-4ba5-9619-2f851fff2f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553791137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1553791137
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.299667164
Short name T787
Test name
Test status
Simulation time 38712527 ps
CPU time 0.81 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 205996 kb
Host smart-68800e41-5dc1-4ad0-8559-cf90490c2983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299667164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.299667164
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2134373877
Short name T432
Test name
Test status
Simulation time 14618780301 ps
CPU time 52.36 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 214992 kb
Host smart-29b13c55-48f1-4073-b8b7-837d5ff09257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134373877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2134373877
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.174916600
Short name T832
Test name
Test status
Simulation time 658958013 ps
CPU time 13.97 seconds
Started Jun 27 04:47:42 PM PDT 24
Finished Jun 27 04:48:00 PM PDT 24
Peak memory 222676 kb
Host smart-aeb25b15-08e4-43a1-bd50-e2b0524594cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174916600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.174916600
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3835208004
Short name T78
Test name
Test status
Simulation time 129090154 ps
CPU time 2.98 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 218316 kb
Host smart-1ab8bea8-31f2-42db-ade7-49fdfffa4870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835208004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3835208004
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2621495705
Short name T226
Test name
Test status
Simulation time 1402783208 ps
CPU time 11.53 seconds
Started Jun 27 04:47:36 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 214304 kb
Host smart-1dbf6fd1-b675-453d-84f6-1ce7fa696451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621495705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2621495705
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.781748928
Short name T202
Test name
Test status
Simulation time 40003886 ps
CPU time 2.91 seconds
Started Jun 27 04:47:30 PM PDT 24
Finished Jun 27 04:47:39 PM PDT 24
Peak memory 214208 kb
Host smart-352af067-52bb-4501-9e34-ab95b46c8c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781748928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.781748928
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.870331415
Short name T264
Test name
Test status
Simulation time 1690651994 ps
CPU time 8.08 seconds
Started Jun 27 04:47:35 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 206804 kb
Host smart-cb90376d-4419-49ae-8d08-5bb379571dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870331415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.870331415
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1509907366
Short name T598
Test name
Test status
Simulation time 140786367 ps
CPU time 2.59 seconds
Started Jun 27 04:47:39 PM PDT 24
Finished Jun 27 04:47:45 PM PDT 24
Peak memory 208820 kb
Host smart-a979595e-a895-415b-a98e-55e830f6439e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509907366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1509907366
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3815826254
Short name T463
Test name
Test status
Simulation time 966649992 ps
CPU time 11.05 seconds
Started Jun 27 04:47:35 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 208592 kb
Host smart-8cb30236-80ea-4d68-9206-9ef7ac0c5b3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815826254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3815826254
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3887967292
Short name T805
Test name
Test status
Simulation time 1203784960 ps
CPU time 9.27 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 208168 kb
Host smart-afcad451-c9da-4b84-afb5-8db4d7c30e1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887967292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3887967292
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1347947687
Short name T647
Test name
Test status
Simulation time 728064792 ps
CPU time 8.14 seconds
Started Jun 27 04:47:30 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 210184 kb
Host smart-b1342c60-ab6f-48ce-8319-67b8ffd6ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347947687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1347947687
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3604727499
Short name T638
Test name
Test status
Simulation time 46926398 ps
CPU time 2.24 seconds
Started Jun 27 04:47:43 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 206092 kb
Host smart-14937102-552e-4106-89d4-fa0138c403c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604727499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3604727499
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.4157528799
Short name T156
Test name
Test status
Simulation time 149473580 ps
CPU time 8.2 seconds
Started Jun 27 04:47:27 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 220240 kb
Host smart-343f3511-bad3-4c0c-b04a-9a3dac7786ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157528799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.4157528799
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2775778085
Short name T569
Test name
Test status
Simulation time 1165570266 ps
CPU time 6.14 seconds
Started Jun 27 04:47:43 PM PDT 24
Finished Jun 27 04:47:53 PM PDT 24
Peak memory 208852 kb
Host smart-365280c5-aa8f-4993-b52f-2621fa460848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775778085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2775778085
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4178302600
Short name T129
Test name
Test status
Simulation time 29372990 ps
CPU time 1.53 seconds
Started Jun 27 04:47:32 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 209696 kb
Host smart-ecea79d3-a2e7-4f78-b5b2-cfa71178d900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178302600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4178302600
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2410646633
Short name T616
Test name
Test status
Simulation time 45692916 ps
CPU time 0.73 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:02 PM PDT 24
Peak memory 205900 kb
Host smart-4a1e0c49-ba19-4ad3-8699-ff5f3977e27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410646633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2410646633
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1064378069
Short name T558
Test name
Test status
Simulation time 102404755 ps
CPU time 2.92 seconds
Started Jun 27 04:46:13 PM PDT 24
Finished Jun 27 04:46:18 PM PDT 24
Peak memory 219704 kb
Host smart-1fdda3a8-ba24-4f14-ae08-df821570f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064378069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1064378069
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3859072658
Short name T677
Test name
Test status
Simulation time 80395031 ps
CPU time 1.97 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:45:57 PM PDT 24
Peak memory 208444 kb
Host smart-e2a4c117-a757-4fcc-9c1b-5a19c4ffb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859072658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3859072658
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.414936849
Short name T759
Test name
Test status
Simulation time 82740365 ps
CPU time 2.72 seconds
Started Jun 27 04:45:55 PM PDT 24
Finished Jun 27 04:45:59 PM PDT 24
Peak memory 214272 kb
Host smart-8f280271-f5fb-4e93-8160-72c9221a1e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414936849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.414936849
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1791077753
Short name T470
Test name
Test status
Simulation time 70651964 ps
CPU time 2.62 seconds
Started Jun 27 04:46:00 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 222492 kb
Host smart-1dd77261-2a81-4d4a-8b8d-070acf240ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791077753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1791077753
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1578202380
Short name T43
Test name
Test status
Simulation time 323569844 ps
CPU time 3.83 seconds
Started Jun 27 04:46:00 PM PDT 24
Finished Jun 27 04:46:07 PM PDT 24
Peak memory 220392 kb
Host smart-ccfbb878-ba94-41f1-be60-27b5b9f3a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578202380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1578202380
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2134702123
Short name T571
Test name
Test status
Simulation time 74403055 ps
CPU time 3.88 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:03 PM PDT 24
Peak memory 207792 kb
Host smart-6edf151b-1e27-4128-8852-f13ee6f63d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134702123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2134702123
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1706537244
Short name T12
Test name
Test status
Simulation time 393168183 ps
CPU time 6.95 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:10 PM PDT 24
Peak memory 230104 kb
Host smart-1b19ac52-8a2c-4e05-aa33-5fdc334f4ee3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706537244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1706537244
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.572676900
Short name T519
Test name
Test status
Simulation time 5030278078 ps
CPU time 31.94 seconds
Started Jun 27 04:45:56 PM PDT 24
Finished Jun 27 04:46:30 PM PDT 24
Peak memory 208400 kb
Host smart-17302491-11bf-46b9-80fd-759f5e11371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572676900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.572676900
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2603422605
Short name T489
Test name
Test status
Simulation time 2734518409 ps
CPU time 28.19 seconds
Started Jun 27 04:45:52 PM PDT 24
Finished Jun 27 04:46:22 PM PDT 24
Peak memory 208456 kb
Host smart-0070fb92-551d-49a7-ba6b-00c707f7c33c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603422605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2603422605
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.534268503
Short name T366
Test name
Test status
Simulation time 809243757 ps
CPU time 8.75 seconds
Started Jun 27 04:46:03 PM PDT 24
Finished Jun 27 04:46:14 PM PDT 24
Peak memory 208060 kb
Host smart-4d039559-c5d7-46f7-bb6c-4f28fd0d2d65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534268503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.534268503
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2458095844
Short name T592
Test name
Test status
Simulation time 777404881 ps
CPU time 7.12 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 207004 kb
Host smart-01809fe7-72d0-43eb-bef2-01adb1764894
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458095844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2458095844
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2385295718
Short name T302
Test name
Test status
Simulation time 242464399 ps
CPU time 3.74 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 218500 kb
Host smart-0a0c4e53-ef28-49ff-bb6f-b86c4f606d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385295718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2385295718
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.148859151
Short name T468
Test name
Test status
Simulation time 1158067684 ps
CPU time 3.65 seconds
Started Jun 27 04:46:03 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 206772 kb
Host smart-0bee2754-a09e-4c92-92b9-ab25a86e55de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148859151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.148859151
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.447912638
Short name T212
Test name
Test status
Simulation time 275699728 ps
CPU time 9.75 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:12 PM PDT 24
Peak memory 214320 kb
Host smart-968f5530-e751-408d-a185-526ada853e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447912638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.447912638
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2755508802
Short name T915
Test name
Test status
Simulation time 381062272 ps
CPU time 6.1 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 219172 kb
Host smart-f5afe6e4-8bd0-4fd8-ac59-eb274758a43c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755508802 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2755508802
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2239046421
Short name T261
Test name
Test status
Simulation time 91198438 ps
CPU time 4.28 seconds
Started Jun 27 04:45:52 PM PDT 24
Finished Jun 27 04:45:58 PM PDT 24
Peak memory 214304 kb
Host smart-5cbad648-134e-4c30-bd55-6b60d09d7b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239046421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2239046421
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3092327241
Short name T912
Test name
Test status
Simulation time 55972689 ps
CPU time 3.1 seconds
Started Jun 27 04:46:05 PM PDT 24
Finished Jun 27 04:46:10 PM PDT 24
Peak memory 210512 kb
Host smart-d977773b-2463-4785-b738-0fdd864086b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092327241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3092327241
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.867703583
Short name T505
Test name
Test status
Simulation time 42280082 ps
CPU time 0.79 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 206024 kb
Host smart-76a02af5-6b31-44bf-a04c-911552d64c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867703583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.867703583
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1592011317
Short name T431
Test name
Test status
Simulation time 138397006 ps
CPU time 5.28 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 215612 kb
Host smart-b56d0bb3-87e2-43a7-96ba-676df2680006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592011317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1592011317
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.229085423
Short name T219
Test name
Test status
Simulation time 862797677 ps
CPU time 3.65 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 210288 kb
Host smart-3d1cabcc-ae7d-4cf4-a7a8-ca01a1fa9462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229085423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.229085423
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3175498649
Short name T500
Test name
Test status
Simulation time 81728058 ps
CPU time 1.39 seconds
Started Jun 27 04:47:36 PM PDT 24
Finished Jun 27 04:47:41 PM PDT 24
Peak memory 207784 kb
Host smart-3571249a-63a6-4451-9ca7-08ce0300cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175498649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3175498649
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1264146244
Short name T745
Test name
Test status
Simulation time 258460302 ps
CPU time 5.7 seconds
Started Jun 27 04:47:33 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 209316 kb
Host smart-c6cf8630-1c07-41d3-b5f5-b849484a36da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264146244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1264146244
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2005079701
Short name T771
Test name
Test status
Simulation time 347198873 ps
CPU time 2.92 seconds
Started Jun 27 04:47:28 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 214508 kb
Host smart-ab8c7b06-102a-460f-97f3-1012df8a6ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005079701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2005079701
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2332640929
Short name T486
Test name
Test status
Simulation time 70051991 ps
CPU time 2.04 seconds
Started Jun 27 04:47:30 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 208064 kb
Host smart-603e67c7-f98e-4ead-a8c1-f93ba7961c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332640929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2332640929
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1775512098
Short name T287
Test name
Test status
Simulation time 710342817 ps
CPU time 6.47 seconds
Started Jun 27 04:47:36 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 209720 kb
Host smart-391d86e1-cd36-44a6-8c9a-77d9f8cd8093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775512098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1775512098
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.238492510
Short name T756
Test name
Test status
Simulation time 93625842 ps
CPU time 1.93 seconds
Started Jun 27 04:47:44 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 208636 kb
Host smart-e5bee9d7-2a2a-4dd6-a7d6-355a78fd02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238492510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.238492510
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3250175002
Short name T483
Test name
Test status
Simulation time 1097255843 ps
CPU time 4.53 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 208416 kb
Host smart-395b804c-7eba-4cda-a9c3-262ff66b8154
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250175002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3250175002
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2134687695
Short name T816
Test name
Test status
Simulation time 106620688 ps
CPU time 2.96 seconds
Started Jun 27 04:47:34 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 207272 kb
Host smart-0360cb54-257f-4bec-992e-78cd7d0fd007
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134687695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2134687695
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1123632432
Short name T775
Test name
Test status
Simulation time 3628834748 ps
CPU time 33.77 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 208580 kb
Host smart-11a519a5-bc80-4154-9565-f1122130f838
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123632432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1123632432
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3458492471
Short name T503
Test name
Test status
Simulation time 142995275 ps
CPU time 2 seconds
Started Jun 27 04:47:44 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 207104 kb
Host smart-5e4c7164-69e8-4149-ba8b-ae0427b863cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458492471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3458492471
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2003531670
Short name T709
Test name
Test status
Simulation time 278754413 ps
CPU time 3.8 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 206972 kb
Host smart-f4a60731-aa81-4733-be2c-b0440cb9e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003531670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2003531670
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3732561731
Short name T903
Test name
Test status
Simulation time 4232337968 ps
CPU time 74.69 seconds
Started Jun 27 04:47:43 PM PDT 24
Finished Jun 27 04:49:01 PM PDT 24
Peak memory 219580 kb
Host smart-c092437f-386e-48ff-a612-f5741b31ba08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732561731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3732561731
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4224374236
Short name T763
Test name
Test status
Simulation time 112429908 ps
CPU time 2.39 seconds
Started Jun 27 04:47:40 PM PDT 24
Finished Jun 27 04:47:47 PM PDT 24
Peak memory 207960 kb
Host smart-32ad9dce-ab40-48e7-b7c4-60049a7c5c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224374236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4224374236
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1474100159
Short name T885
Test name
Test status
Simulation time 177105862 ps
CPU time 2.4 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:47 PM PDT 24
Peak memory 210340 kb
Host smart-337f624d-f099-42b2-b889-e580664d630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474100159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1474100159
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1041149959
Short name T555
Test name
Test status
Simulation time 11157140 ps
CPU time 0.84 seconds
Started Jun 27 04:47:44 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 205940 kb
Host smart-1c11532e-bd7f-4cf1-b8ab-da17495139be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041149959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1041149959
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.781120728
Short name T30
Test name
Test status
Simulation time 269625200 ps
CPU time 5.21 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:47:41 PM PDT 24
Peak memory 214340 kb
Host smart-34ca5db2-8c35-437e-a0a2-a41a489d99d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781120728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.781120728
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.410717117
Short name T312
Test name
Test status
Simulation time 52469608 ps
CPU time 2.28 seconds
Started Jun 27 04:47:32 PM PDT 24
Finished Jun 27 04:47:39 PM PDT 24
Peak memory 207724 kb
Host smart-4c58c728-c5fc-4dfa-b2d9-0da4920984af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410717117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.410717117
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3939400738
Short name T354
Test name
Test status
Simulation time 186184876 ps
CPU time 2.45 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 214348 kb
Host smart-baea8a05-7403-4dc2-ab5f-5c32c20948f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939400738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3939400738
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4276088065
Short name T652
Test name
Test status
Simulation time 52511145 ps
CPU time 2.51 seconds
Started Jun 27 04:47:30 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 214268 kb
Host smart-e9e71e11-650f-4a53-a001-48f7b3b6291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276088065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4276088065
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1627200217
Short name T892
Test name
Test status
Simulation time 50525134 ps
CPU time 3.54 seconds
Started Jun 27 04:47:36 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 217872 kb
Host smart-f577b0b8-ab3f-4e75-ae13-f6c38626231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627200217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1627200217
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2322338367
Short name T389
Test name
Test status
Simulation time 100833097 ps
CPU time 4.37 seconds
Started Jun 27 04:47:33 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 207464 kb
Host smart-7a2f2dbe-dd38-4b49-8fd7-0e64ac90f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322338367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2322338367
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2490267165
Short name T726
Test name
Test status
Simulation time 113604819 ps
CPU time 4.24 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 208704 kb
Host smart-d0f91a6d-bd06-4826-b7fd-8a2856e5411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490267165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2490267165
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.724912029
Short name T789
Test name
Test status
Simulation time 5358939082 ps
CPU time 36.43 seconds
Started Jun 27 04:47:44 PM PDT 24
Finished Jun 27 04:48:24 PM PDT 24
Peak memory 208328 kb
Host smart-80780959-0ea4-4cd3-b35e-ea913ab2a1dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724912029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.724912029
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2981827355
Short name T496
Test name
Test status
Simulation time 101566478 ps
CPU time 2.68 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 208144 kb
Host smart-9cb51706-59dc-4ad1-948f-1eb9720b396b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981827355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2981827355
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3020429700
Short name T410
Test name
Test status
Simulation time 45910836 ps
CPU time 2.53 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:47 PM PDT 24
Peak memory 206920 kb
Host smart-e844be15-b69c-4739-b0cf-e33c460a4069
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020429700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3020429700
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3610797478
Short name T633
Test name
Test status
Simulation time 223623048 ps
CPU time 2.69 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 208584 kb
Host smart-19087c15-91ce-4d27-a084-9f13a98a869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610797478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3610797478
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3896840541
Short name T620
Test name
Test status
Simulation time 135656986 ps
CPU time 2.18 seconds
Started Jun 27 04:47:33 PM PDT 24
Finished Jun 27 04:47:40 PM PDT 24
Peak memory 206636 kb
Host smart-9ad68cf4-944f-4f0b-9997-9015b78f8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896840541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3896840541
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.801153237
Short name T190
Test name
Test status
Simulation time 860041206 ps
CPU time 8.2 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:53 PM PDT 24
Peak memory 209944 kb
Host smart-ef4cfaae-7b1a-4d55-b259-8be5876dde9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801153237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.801153237
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.673832118
Short name T243
Test name
Test status
Simulation time 1326748243 ps
CPU time 8.25 seconds
Started Jun 27 04:47:31 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 207320 kb
Host smart-4da7b532-e557-488e-bcbf-6aa9ab976fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673832118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.673832118
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4113156959
Short name T128
Test name
Test status
Simulation time 119972991 ps
CPU time 2.42 seconds
Started Jun 27 04:47:42 PM PDT 24
Finished Jun 27 04:47:48 PM PDT 24
Peak memory 210156 kb
Host smart-aec66043-5c8f-4947-b8e7-2cf2e64de3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113156959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4113156959
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2365688666
Short name T514
Test name
Test status
Simulation time 48925467 ps
CPU time 0.81 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:42 PM PDT 24
Peak memory 206052 kb
Host smart-63183f27-f408-4104-a72a-b2f9259ce861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365688666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2365688666
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2669736663
Short name T835
Test name
Test status
Simulation time 82635799 ps
CPU time 1.38 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 215008 kb
Host smart-687d280f-a6be-41a7-b047-c7f6b5c69366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669736663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2669736663
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2647177322
Short name T442
Test name
Test status
Simulation time 82010376 ps
CPU time 2.41 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 207916 kb
Host smart-fb8d320a-e22a-4425-b5ab-26414b27b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647177322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2647177322
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.497258264
Short name T45
Test name
Test status
Simulation time 618568160 ps
CPU time 3.25 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:45 PM PDT 24
Peak memory 214380 kb
Host smart-3e7a1f3a-95e4-4625-bd9e-e09b0e4870d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497258264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.497258264
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3122867240
Short name T247
Test name
Test status
Simulation time 42963340 ps
CPU time 2.35 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 214196 kb
Host smart-a3b4117c-8083-41b9-a9d4-38cf8f5d0be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122867240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3122867240
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.616449461
Short name T710
Test name
Test status
Simulation time 137649637 ps
CPU time 2.48 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:45 PM PDT 24
Peak memory 209572 kb
Host smart-ada557c4-e343-4b64-b45f-48d2fb52bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616449461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.616449461
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3222869836
Short name T604
Test name
Test status
Simulation time 497768092 ps
CPU time 4.05 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:47 PM PDT 24
Peak memory 207860 kb
Host smart-4ac17f0e-0989-47ea-abd6-0251f49f622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222869836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3222869836
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1653678993
Short name T511
Test name
Test status
Simulation time 40943380 ps
CPU time 1.76 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 206860 kb
Host smart-13fa1c61-4659-4028-9074-eaa83cac2fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653678993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1653678993
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3656534648
Short name T539
Test name
Test status
Simulation time 1338721975 ps
CPU time 8.87 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 208344 kb
Host smart-1f04d771-2b3b-43d0-8e1a-36319c6e2f4e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656534648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3656534648
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2279388761
Short name T211
Test name
Test status
Simulation time 336728359 ps
CPU time 3.38 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 209256 kb
Host smart-0033e12c-072f-4a46-a003-5fc4ad89c7bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279388761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2279388761
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1154495504
Short name T612
Test name
Test status
Simulation time 121308745 ps
CPU time 4.67 seconds
Started Jun 27 04:47:43 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 208268 kb
Host smart-126f9767-a803-4215-8bf8-290aab4014d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154495504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1154495504
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2031764616
Short name T689
Test name
Test status
Simulation time 40595318 ps
CPU time 2.15 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 209204 kb
Host smart-c2988554-b5a3-4ef1-b376-f77fdaab7e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031764616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2031764616
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2401727123
Short name T409
Test name
Test status
Simulation time 43697208 ps
CPU time 2.32 seconds
Started Jun 27 04:47:43 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 208512 kb
Host smart-cff9681e-f5fe-494f-806d-00af6be1a38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401727123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2401727123
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2345341562
Short name T355
Test name
Test status
Simulation time 288167542 ps
CPU time 9.85 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 215684 kb
Host smart-8cba1af3-3eda-4e69-9652-684c6c3a9682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345341562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2345341562
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3732663090
Short name T708
Test name
Test status
Simulation time 2971119858 ps
CPU time 19.73 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:48:00 PM PDT 24
Peak memory 222696 kb
Host smart-488c1207-fc88-471a-876d-4e788921493d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732663090 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3732663090
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1527452848
Short name T482
Test name
Test status
Simulation time 378819371 ps
CPU time 4.01 seconds
Started Jun 27 04:47:42 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 214188 kb
Host smart-bd96076d-eaad-45e9-9a11-8b129d563103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527452848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1527452848
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1855607895
Short name T458
Test name
Test status
Simulation time 31861372 ps
CPU time 1.3 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 210064 kb
Host smart-ee28b457-52d6-40c2-84ca-ba36d0108c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855607895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1855607895
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3200758750
Short name T720
Test name
Test status
Simulation time 35816243 ps
CPU time 0.81 seconds
Started Jun 27 04:47:45 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 206048 kb
Host smart-02749939-9596-402c-b952-d581fafd3af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200758750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3200758750
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1960702088
Short name T422
Test name
Test status
Simulation time 430717548 ps
CPU time 11.53 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:53 PM PDT 24
Peak memory 214564 kb
Host smart-705674c4-2340-4bc4-a328-ead637789c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960702088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1960702088
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3468851121
Short name T733
Test name
Test status
Simulation time 2145983007 ps
CPU time 56.76 seconds
Started Jun 27 04:47:46 PM PDT 24
Finished Jun 27 04:48:46 PM PDT 24
Peak memory 214708 kb
Host smart-760b4ed8-9f88-4073-b040-c514662c3679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468851121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3468851121
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.395782998
Short name T615
Test name
Test status
Simulation time 43523151 ps
CPU time 2.1 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:43 PM PDT 24
Peak memory 214296 kb
Host smart-bd6e5c97-ddb3-478e-9c4a-5e6fb3741e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395782998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.395782998
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2652943223
Short name T667
Test name
Test status
Simulation time 30609245 ps
CPU time 2.01 seconds
Started Jun 27 04:47:38 PM PDT 24
Finished Jun 27 04:47:45 PM PDT 24
Peak memory 222744 kb
Host smart-342cb4d8-7610-4316-9e75-5449e2bfc089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652943223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2652943223
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1084403907
Short name T328
Test name
Test status
Simulation time 560911416 ps
CPU time 3.92 seconds
Started Jun 27 04:47:39 PM PDT 24
Finished Jun 27 04:47:47 PM PDT 24
Peak memory 214272 kb
Host smart-b82fd6cb-7f1b-4d06-8d4f-bb12f4b8adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084403907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1084403907
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1934130331
Short name T66
Test name
Test status
Simulation time 117915308 ps
CPU time 5.44 seconds
Started Jun 27 04:47:35 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 218344 kb
Host smart-dd888303-3bc2-4be8-ab24-1887183c1b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934130331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1934130331
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2683804069
Short name T823
Test name
Test status
Simulation time 634649732 ps
CPU time 15.78 seconds
Started Jun 27 04:47:39 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 214316 kb
Host smart-9236724a-00af-40c6-873e-b1abca911e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683804069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2683804069
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3090587606
Short name T449
Test name
Test status
Simulation time 127848474 ps
CPU time 3.9 seconds
Started Jun 27 04:47:40 PM PDT 24
Finished Jun 27 04:47:48 PM PDT 24
Peak memory 207900 kb
Host smart-5170cd5e-b5f9-42fb-823b-36f86c7132b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090587606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3090587606
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1276547040
Short name T451
Test name
Test status
Simulation time 913607241 ps
CPU time 25.19 seconds
Started Jun 27 04:47:39 PM PDT 24
Finished Jun 27 04:48:08 PM PDT 24
Peak memory 209212 kb
Host smart-809e5a05-ecc6-4e24-bcc5-1ffc8ec173a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276547040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1276547040
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4161326117
Short name T888
Test name
Test status
Simulation time 334623337 ps
CPU time 2.4 seconds
Started Jun 27 04:47:43 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 206824 kb
Host smart-afaaa25f-2ef8-4f75-8d4b-b7343b240030
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161326117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4161326117
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2629568225
Short name T640
Test name
Test status
Simulation time 64877630 ps
CPU time 3.25 seconds
Started Jun 27 04:47:39 PM PDT 24
Finished Jun 27 04:47:46 PM PDT 24
Peak memory 208548 kb
Host smart-2065e14c-a3b0-4737-89b6-47c15695ae2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629568225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2629568225
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3310445597
Short name T367
Test name
Test status
Simulation time 101189083 ps
CPU time 2.04 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 215884 kb
Host smart-b48e9b16-6eb0-4291-9e16-154dd1e0d462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310445597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3310445597
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2106051483
Short name T845
Test name
Test status
Simulation time 349290872 ps
CPU time 3.9 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:49 PM PDT 24
Peak memory 207060 kb
Host smart-c33e3a17-7068-429a-af2f-95a11881813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106051483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2106051483
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3939403866
Short name T203
Test name
Test status
Simulation time 437750855 ps
CPU time 6.71 seconds
Started Jun 27 04:47:40 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 207476 kb
Host smart-0cd1e6a7-e774-4b68-8d40-545675500144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939403866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3939403866
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1614517217
Short name T54
Test name
Test status
Simulation time 2173987796 ps
CPU time 5.77 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 209856 kb
Host smart-2eac0d8f-fe77-4dfe-bc2f-b4ad995b072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614517217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1614517217
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1432896843
Short name T721
Test name
Test status
Simulation time 43335389 ps
CPU time 0.87 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 206256 kb
Host smart-85042a58-9442-4ad4-a598-0403fbbe4595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432896843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1432896843
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.78550237
Short name T428
Test name
Test status
Simulation time 262768844 ps
CPU time 4.64 seconds
Started Jun 27 04:48:04 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 215192 kb
Host smart-389ef477-ec35-4a19-b293-62efa8eb3b5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78550237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.78550237
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2549847752
Short name T456
Test name
Test status
Simulation time 189739091 ps
CPU time 2.46 seconds
Started Jun 27 04:47:49 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 214328 kb
Host smart-0e6601af-3a29-4244-b8b8-04ee422ea013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549847752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2549847752
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2350778416
Short name T348
Test name
Test status
Simulation time 411497046 ps
CPU time 2.91 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 207192 kb
Host smart-035fdd78-8096-4625-8066-2e5f121bbe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350778416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2350778416
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.474221241
Short name T731
Test name
Test status
Simulation time 40416639 ps
CPU time 1.78 seconds
Started Jun 27 04:47:46 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 214272 kb
Host smart-76d20683-455a-4bbd-ba78-0d2cf178342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474221241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.474221241
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2088339331
Short name T861
Test name
Test status
Simulation time 365102831 ps
CPU time 3.43 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 220444 kb
Host smart-ee1c666c-0451-4511-bb96-b03457cea170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088339331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2088339331
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.905436948
Short name T329
Test name
Test status
Simulation time 259881750 ps
CPU time 5.86 seconds
Started Jun 27 04:47:49 PM PDT 24
Finished Jun 27 04:47:57 PM PDT 24
Peak memory 210148 kb
Host smart-53c1d357-0548-4989-a779-5277a938637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905436948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.905436948
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3833816349
Short name T895
Test name
Test status
Simulation time 200741175 ps
CPU time 3.96 seconds
Started Jun 27 04:48:07 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 217868 kb
Host smart-54148fcb-e239-465e-9e1b-a6131bb5a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833816349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3833816349
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.13166544
Short name T857
Test name
Test status
Simulation time 110674821 ps
CPU time 2.96 seconds
Started Jun 27 04:47:37 PM PDT 24
Finished Jun 27 04:47:44 PM PDT 24
Peak memory 208412 kb
Host smart-4a92bf08-bbf6-4750-9ea2-b273bfb17085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13166544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.13166544
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3504736740
Short name T740
Test name
Test status
Simulation time 46255651 ps
CPU time 2.43 seconds
Started Jun 27 04:47:48 PM PDT 24
Finished Jun 27 04:47:52 PM PDT 24
Peak memory 206828 kb
Host smart-1abf9db7-450e-4bfd-bfb4-35eb39ee5241
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504736740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3504736740
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3567687444
Short name T488
Test name
Test status
Simulation time 3354249998 ps
CPU time 20.68 seconds
Started Jun 27 04:47:51 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 208588 kb
Host smart-d1ffd478-5c16-42f5-8bb0-1f7c12e9f061
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567687444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3567687444
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3726305
Short name T676
Test name
Test status
Simulation time 58581594 ps
CPU time 2.97 seconds
Started Jun 27 04:47:49 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 206760 kb
Host smart-ccdbded6-af2a-4c49-bd9a-0c896aea3943
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3726305
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2037140707
Short name T315
Test name
Test status
Simulation time 147257748 ps
CPU time 2.46 seconds
Started Jun 27 04:47:46 PM PDT 24
Finished Jun 27 04:47:52 PM PDT 24
Peak memory 218424 kb
Host smart-f2b85cf2-d741-4ab7-8701-0e39f8be2f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037140707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2037140707
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2889099633
Short name T460
Test name
Test status
Simulation time 980616798 ps
CPU time 25.42 seconds
Started Jun 27 04:47:41 PM PDT 24
Finished Jun 27 04:48:10 PM PDT 24
Peak memory 207988 kb
Host smart-60f38228-53c3-4669-a51f-666d87ac002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889099633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2889099633
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.978669419
Short name T337
Test name
Test status
Simulation time 2021213066 ps
CPU time 20.01 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:20 PM PDT 24
Peak memory 217300 kb
Host smart-2b0cfadf-dd1e-4dd9-bfb6-4f8aa397e52d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978669419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.978669419
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3884871841
Short name T384
Test name
Test status
Simulation time 770273826 ps
CPU time 19.53 seconds
Started Jun 27 04:47:46 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 219464 kb
Host smart-51e8d463-143e-449d-b2ae-0561b73afaf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884871841 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3884871841
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1178569950
Short name T60
Test name
Test status
Simulation time 230658344 ps
CPU time 2.49 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 210144 kb
Host smart-2fb72c07-5bbe-4d5d-a5bc-d24caf79f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178569950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1178569950
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.116347641
Short name T743
Test name
Test status
Simulation time 45569955 ps
CPU time 0.74 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:14 PM PDT 24
Peak memory 206036 kb
Host smart-47a0f76b-f895-4000-8b1d-45b22d023e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116347641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.116347641
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.237674588
Short name T433
Test name
Test status
Simulation time 1233625281 ps
CPU time 13.67 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:21 PM PDT 24
Peak memory 214908 kb
Host smart-b5511a1b-8584-4c4e-bfe5-98ec8737acdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237674588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.237674588
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.945586935
Short name T572
Test name
Test status
Simulation time 216638116 ps
CPU time 2.88 seconds
Started Jun 27 04:48:05 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 209468 kb
Host smart-847b4da1-6422-4646-9446-7c98ce831aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945586935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.945586935
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2032321540
Short name T626
Test name
Test status
Simulation time 133498390 ps
CPU time 2.04 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 209232 kb
Host smart-588fbbf4-badb-4194-a905-3d88cb452baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032321540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2032321540
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1451405824
Short name T221
Test name
Test status
Simulation time 478782752 ps
CPU time 3.7 seconds
Started Jun 27 04:48:08 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 210024 kb
Host smart-0aa11e9b-f3e5-43d4-a7be-024ec66a4238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451405824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1451405824
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4224746178
Short name T320
Test name
Test status
Simulation time 457596361 ps
CPU time 5.26 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 214260 kb
Host smart-f0464a0d-c004-44c4-882d-2f49af3848a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224746178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4224746178
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1019841953
Short name T873
Test name
Test status
Simulation time 715743960 ps
CPU time 7.56 seconds
Started Jun 27 04:48:03 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 208932 kb
Host smart-47cc5b35-01f6-4167-8372-75cd508ec428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019841953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1019841953
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1593668234
Short name T812
Test name
Test status
Simulation time 98549023 ps
CPU time 2.79 seconds
Started Jun 27 04:48:08 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 206876 kb
Host smart-cfc71b0b-18ab-4759-925f-60eeca702abc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593668234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1593668234
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.4172632290
Short name T624
Test name
Test status
Simulation time 171471498 ps
CPU time 2.57 seconds
Started Jun 27 04:48:03 PM PDT 24
Finished Jun 27 04:48:07 PM PDT 24
Peak memory 206792 kb
Host smart-00897880-53d5-479b-8fda-0f33dd4f318c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172632290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.4172632290
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1448378350
Short name T464
Test name
Test status
Simulation time 31229183 ps
CPU time 2.17 seconds
Started Jun 27 04:47:49 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 207060 kb
Host smart-70e50f10-9d08-485f-b14c-3d4d83fe89b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448378350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1448378350
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1333791177
Short name T479
Test name
Test status
Simulation time 20533403 ps
CPU time 1.66 seconds
Started Jun 27 04:48:04 PM PDT 24
Finished Jun 27 04:48:06 PM PDT 24
Peak memory 215472 kb
Host smart-e869801f-e3e9-45d6-802e-4d2359740521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333791177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1333791177
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1119036161
Short name T621
Test name
Test status
Simulation time 164307893 ps
CPU time 2.53 seconds
Started Jun 27 04:47:46 PM PDT 24
Finished Jun 27 04:47:52 PM PDT 24
Peak memory 208592 kb
Host smart-73335219-95ef-49f0-9e67-0bb388f82cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119036161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1119036161
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.205330793
Short name T191
Test name
Test status
Simulation time 17630523013 ps
CPU time 21.57 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:20 PM PDT 24
Peak memory 222556 kb
Host smart-33c63d22-1ad3-466e-9849-e055cc5b51f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205330793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.205330793
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.4263661215
Short name T783
Test name
Test status
Simulation time 683927020 ps
CPU time 5.4 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:18 PM PDT 24
Peak memory 218344 kb
Host smart-df753eb7-c7d6-4850-b3ae-827d215a396e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263661215 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.4263661215
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2744476307
Short name T204
Test name
Test status
Simulation time 784421978 ps
CPU time 23.16 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:22 PM PDT 24
Peak memory 208176 kb
Host smart-c06c64cc-d973-41a3-8c02-d29e3eccc6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744476307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2744476307
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2576330459
Short name T396
Test name
Test status
Simulation time 48210994 ps
CPU time 1.8 seconds
Started Jun 27 04:47:51 PM PDT 24
Finished Jun 27 04:47:55 PM PDT 24
Peak memory 210016 kb
Host smart-64456be6-f074-4d30-bae1-94ed118bf3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576330459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2576330459
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2065701542
Short name T683
Test name
Test status
Simulation time 12333296 ps
CPU time 0.75 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:53 PM PDT 24
Peak memory 205860 kb
Host smart-5a8a922f-7cc7-4453-b7bd-657550b749e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065701542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2065701542
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3887534092
Short name T41
Test name
Test status
Simulation time 61137994 ps
CPU time 4.28 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:04 PM PDT 24
Peak memory 215180 kb
Host smart-3c22548c-41f6-4f1c-866c-0cdee043dd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887534092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3887534092
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2566252421
Short name T77
Test name
Test status
Simulation time 1055355243 ps
CPU time 7.31 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:21 PM PDT 24
Peak memory 214412 kb
Host smart-67a7117e-874b-44a8-b912-6bdaf9791e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566252421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2566252421
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4191881614
Short name T95
Test name
Test status
Simulation time 164336903 ps
CPU time 3.66 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:16 PM PDT 24
Peak memory 214308 kb
Host smart-34bc40df-fb19-442d-af25-400b5115fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191881614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4191881614
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3486340596
Short name T6
Test name
Test status
Simulation time 143833932 ps
CPU time 2.99 seconds
Started Jun 27 04:48:07 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 222336 kb
Host smart-c7c94a7c-db66-4074-b2bb-b349437e335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486340596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3486340596
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2816651541
Short name T294
Test name
Test status
Simulation time 160840397 ps
CPU time 5.12 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:18 PM PDT 24
Peak memory 214312 kb
Host smart-921be9dc-f7a5-4f60-9d15-98ad5073cf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816651541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2816651541
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.757905496
Short name T475
Test name
Test status
Simulation time 605104545 ps
CPU time 2.56 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 206572 kb
Host smart-e4c1d011-f743-4f50-b014-81f2d096daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757905496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.757905496
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1557833121
Short name T607
Test name
Test status
Simulation time 183878983 ps
CPU time 2.6 seconds
Started Jun 27 04:47:46 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 208772 kb
Host smart-81d7d9fc-9bad-480e-885d-3fadcdaf9bd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557833121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1557833121
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2477029374
Short name T600
Test name
Test status
Simulation time 51020396 ps
CPU time 1.8 seconds
Started Jun 27 04:48:07 PM PDT 24
Finished Jun 27 04:48:10 PM PDT 24
Peak memory 206844 kb
Host smart-3585e92e-5083-4f5e-8f18-b78c22b54d01
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477029374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2477029374
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.374195769
Short name T593
Test name
Test status
Simulation time 22757917 ps
CPU time 1.86 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 206988 kb
Host smart-b0d3c21a-23e6-481e-8d74-afc3ad9103b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374195769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.374195769
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2415342789
Short name T576
Test name
Test status
Simulation time 108260504 ps
CPU time 2.89 seconds
Started Jun 27 04:48:07 PM PDT 24
Finished Jun 27 04:48:11 PM PDT 24
Peak memory 210040 kb
Host smart-9f66fd7c-9e23-4c8c-a802-90f9a6885aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415342789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2415342789
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.22620663
Short name T916
Test name
Test status
Simulation time 297343813 ps
CPU time 3.96 seconds
Started Jun 27 04:47:51 PM PDT 24
Finished Jun 27 04:47:56 PM PDT 24
Peak memory 207880 kb
Host smart-414a276b-fb05-4e26-b5ba-29f4b85f3f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22620663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.22620663
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3081830046
Short name T27
Test name
Test status
Simulation time 557131112 ps
CPU time 5.58 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:18 PM PDT 24
Peak memory 209628 kb
Host smart-0d6e97f4-e861-4352-aa00-28fc65ee32fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081830046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3081830046
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.938609082
Short name T161
Test name
Test status
Simulation time 123946081 ps
CPU time 1.5 seconds
Started Jun 27 04:47:47 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 209728 kb
Host smart-d6d3cc70-4c97-4b72-9e76-740b70931815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938609082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.938609082
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3183186004
Short name T693
Test name
Test status
Simulation time 17711627 ps
CPU time 1.02 seconds
Started Jun 27 04:48:08 PM PDT 24
Finished Jun 27 04:48:10 PM PDT 24
Peak memory 206068 kb
Host smart-f04e2c40-843f-455b-a8b9-441afccda6c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183186004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3183186004
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3928499163
Short name T713
Test name
Test status
Simulation time 59384333 ps
CPU time 3.15 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:18 PM PDT 24
Peak memory 221492 kb
Host smart-95a2705d-3c9f-4a9f-8d69-207d56bf0b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928499163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3928499163
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1770001642
Short name T678
Test name
Test status
Simulation time 152837261 ps
CPU time 2.59 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 214424 kb
Host smart-5d981ab7-fa3a-4161-a233-706ada5ea327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770001642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1770001642
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.228331298
Short name T372
Test name
Test status
Simulation time 138133002 ps
CPU time 3.64 seconds
Started Jun 27 04:47:57 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 214328 kb
Host smart-8592f8e8-82c0-41ae-b73a-b6cce57fd155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228331298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.228331298
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2960555196
Short name T817
Test name
Test status
Simulation time 84206410 ps
CPU time 3.18 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 220284 kb
Host smart-21a9edfe-91bc-4c8b-8436-007a375c92d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960555196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2960555196
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1037189907
Short name T344
Test name
Test status
Simulation time 294262244 ps
CPU time 3.65 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 208504 kb
Host smart-3ad86398-7d84-4ee3-a7b9-9572f06ee0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037189907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1037189907
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1985554854
Short name T313
Test name
Test status
Simulation time 863594790 ps
CPU time 5.47 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:04 PM PDT 24
Peak memory 209900 kb
Host smart-e5282e62-8a65-4c0d-91ee-67c30680b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985554854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1985554854
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3900940456
Short name T670
Test name
Test status
Simulation time 85871955 ps
CPU time 3.76 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:56 PM PDT 24
Peak memory 208508 kb
Host smart-9860c429-2d33-4dae-838e-f720e6054bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900940456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3900940456
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.46900741
Short name T551
Test name
Test status
Simulation time 36137322 ps
CPU time 2.43 seconds
Started Jun 27 04:47:47 PM PDT 24
Finished Jun 27 04:47:52 PM PDT 24
Peak memory 208652 kb
Host smart-d8418010-9407-4b31-8f98-51fc74f6e981
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46900741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.46900741
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.927994518
Short name T657
Test name
Test status
Simulation time 2134939705 ps
CPU time 53.61 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:49:06 PM PDT 24
Peak memory 209024 kb
Host smart-bebbd6f9-15d1-4787-9f5d-cb72e50074a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927994518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.927994518
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.181719948
Short name T734
Test name
Test status
Simulation time 382036995 ps
CPU time 4.05 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:11 PM PDT 24
Peak memory 206904 kb
Host smart-9cd08678-f6b5-48d8-85e5-d3156c6cb5fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181719948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.181719948
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2754272678
Short name T542
Test name
Test status
Simulation time 455108637 ps
CPU time 3.93 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:56 PM PDT 24
Peak memory 214236 kb
Host smart-3000d8ae-0fca-413e-ac92-4e432e56da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754272678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2754272678
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2778966328
Short name T807
Test name
Test status
Simulation time 27617287 ps
CPU time 1.57 seconds
Started Jun 27 04:48:05 PM PDT 24
Finished Jun 27 04:48:07 PM PDT 24
Peak memory 206740 kb
Host smart-63530dea-ce9f-41a3-b34c-f75e69f0430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778966328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2778966328
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3162446026
Short name T820
Test name
Test status
Simulation time 3385033808 ps
CPU time 25.38 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 222472 kb
Host smart-5dc02ff9-e93c-4b42-a005-07fe14478534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162446026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3162446026
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3818043324
Short name T908
Test name
Test status
Simulation time 904025341 ps
CPU time 7.11 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:07 PM PDT 24
Peak memory 209076 kb
Host smart-59e9cdd9-5b24-47ce-8bac-7992bedeeb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818043324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3818043324
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1520707939
Short name T199
Test name
Test status
Simulation time 342097702 ps
CPU time 3.37 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 210216 kb
Host smart-d28d568b-5408-46b9-b456-6e5a39b41d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520707939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1520707939
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1782671627
Short name T724
Test name
Test status
Simulation time 33228806 ps
CPU time 0.8 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 206040 kb
Host smart-8b82b0b5-7dae-474f-9120-2603c01bcf22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782671627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1782671627
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3045732313
Short name T414
Test name
Test status
Simulation time 128292822 ps
CPU time 6.39 seconds
Started Jun 27 04:47:57 PM PDT 24
Finished Jun 27 04:48:06 PM PDT 24
Peak memory 214420 kb
Host smart-08857f37-6294-445d-b9ed-7ca5d9873b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045732313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3045732313
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.954381996
Short name T37
Test name
Test status
Simulation time 203805143 ps
CPU time 2.62 seconds
Started Jun 27 04:48:05 PM PDT 24
Finished Jun 27 04:48:08 PM PDT 24
Peak memory 208008 kb
Host smart-dc1bc9e0-837a-4ef0-b089-2e99f910a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954381996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.954381996
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1418222904
Short name T641
Test name
Test status
Simulation time 39385041 ps
CPU time 1.61 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 208060 kb
Host smart-6753b6fb-9fae-4a1e-a723-5b387bd69d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418222904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1418222904
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3671672635
Short name T102
Test name
Test status
Simulation time 130870905 ps
CPU time 5.86 seconds
Started Jun 27 04:48:05 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 208784 kb
Host smart-9d08371b-9b2d-4fcf-a3fc-57483b238b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671672635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3671672635
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2406540099
Short name T375
Test name
Test status
Simulation time 136296400 ps
CPU time 5.58 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 221604 kb
Host smart-469ac1d6-f895-45dc-9d4c-010cc4af1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406540099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2406540099
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1649761790
Short name T232
Test name
Test status
Simulation time 215781820 ps
CPU time 4.04 seconds
Started Jun 27 04:48:09 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 209224 kb
Host smart-b906e670-5c5a-49e5-9aa1-992a78bfda1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649761790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1649761790
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1972560996
Short name T242
Test name
Test status
Simulation time 2596853579 ps
CPU time 23.62 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:23 PM PDT 24
Peak memory 209552 kb
Host smart-875069e5-1929-4f64-8149-ce59aed043a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972560996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1972560996
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.16099342
Short name T748
Test name
Test status
Simulation time 23113887 ps
CPU time 1.87 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:48:00 PM PDT 24
Peak memory 207380 kb
Host smart-e02718b8-f01c-43c2-a0ee-a83593c89042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16099342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.16099342
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3316388290
Short name T595
Test name
Test status
Simulation time 824009417 ps
CPU time 7.62 seconds
Started Jun 27 04:47:57 PM PDT 24
Finished Jun 27 04:48:07 PM PDT 24
Peak memory 208020 kb
Host smart-22d16908-2085-43a5-8dba-75efa35ba909
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316388290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3316388290
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3037246323
Short name T688
Test name
Test status
Simulation time 174345763 ps
CPU time 2.46 seconds
Started Jun 27 04:48:05 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 207488 kb
Host smart-1dfe27a4-25ad-47cd-9c98-3e326b3c5de8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037246323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3037246323
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1672618902
Short name T914
Test name
Test status
Simulation time 1686555642 ps
CPU time 8.34 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:07 PM PDT 24
Peak memory 208588 kb
Host smart-9105ae8b-2963-4a73-b96e-287973f9185d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672618902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1672618902
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4046290007
Short name T801
Test name
Test status
Simulation time 299971424 ps
CPU time 7.03 seconds
Started Jun 27 04:47:54 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 208208 kb
Host smart-04cf4ce9-17ad-4458-a8ce-229ffb32b3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046290007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4046290007
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2226980732
Short name T911
Test name
Test status
Simulation time 320699261 ps
CPU time 4.77 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 207948 kb
Host smart-d87d646a-a964-44bd-b61d-35865fad1f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226980732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2226980732
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.578782440
Short name T487
Test name
Test status
Simulation time 408088674 ps
CPU time 5.65 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 209300 kb
Host smart-1badd161-07a8-4fd5-8f58-91eba433552a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578782440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.578782440
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3154545544
Short name T729
Test name
Test status
Simulation time 140381322 ps
CPU time 4.78 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:57 PM PDT 24
Peak memory 208104 kb
Host smart-5c36080c-6193-4fa2-966e-c7da5a51d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154545544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3154545544
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3514198692
Short name T549
Test name
Test status
Simulation time 93685150 ps
CPU time 3.73 seconds
Started Jun 27 04:48:15 PM PDT 24
Finished Jun 27 04:48:20 PM PDT 24
Peak memory 210128 kb
Host smart-239f5772-4096-48f2-986b-47ecb6030c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514198692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3514198692
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2725191076
Short name T858
Test name
Test status
Simulation time 24235683 ps
CPU time 0.73 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 206052 kb
Host smart-abe87e0a-d307-45c3-b5cb-8f99930cbd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725191076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2725191076
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3191305411
Short name T419
Test name
Test status
Simulation time 119344223 ps
CPU time 4.42 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 215108 kb
Host smart-aa19b2ed-a63f-4706-96a8-0178e78437a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191305411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3191305411
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.12293110
Short name T898
Test name
Test status
Simulation time 319702031 ps
CPU time 10.46 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:25 PM PDT 24
Peak memory 214236 kb
Host smart-eeca6810-5380-4953-83e9-d29468099e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12293110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.12293110
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2911151452
Short name T79
Test name
Test status
Simulation time 337654361 ps
CPU time 2.41 seconds
Started Jun 27 04:47:54 PM PDT 24
Finished Jun 27 04:47:57 PM PDT 24
Peak memory 214336 kb
Host smart-38809c52-2762-4fd9-9b4e-9eb10a83546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911151452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2911151452
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.450939006
Short name T474
Test name
Test status
Simulation time 48851283 ps
CPU time 1.47 seconds
Started Jun 27 04:47:53 PM PDT 24
Finished Jun 27 04:47:55 PM PDT 24
Peak memory 214284 kb
Host smart-e691022d-ca69-48f9-880d-1b096c85442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450939006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.450939006
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.674174746
Short name T424
Test name
Test status
Simulation time 50160560 ps
CPU time 2.58 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:17 PM PDT 24
Peak memory 209244 kb
Host smart-78aca1c6-9e6c-49f8-8472-091f6714d329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674174746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.674174746
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1973003533
Short name T669
Test name
Test status
Simulation time 81422839 ps
CPU time 3.08 seconds
Started Jun 27 04:48:05 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 209040 kb
Host smart-585b1d55-5234-4876-a46b-ca5b47621308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973003533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1973003533
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.809246220
Short name T544
Test name
Test status
Simulation time 94788762 ps
CPU time 2.51 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:55 PM PDT 24
Peak memory 206776 kb
Host smart-28bb6388-9182-481f-97c7-2f9db404e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809246220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.809246220
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.56056557
Short name T250
Test name
Test status
Simulation time 97892081 ps
CPU time 3.88 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 209072 kb
Host smart-0629bebe-109a-47e0-8e36-b78d6a8d01f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56056557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.56056557
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.116364647
Short name T699
Test name
Test status
Simulation time 57146305 ps
CPU time 2.04 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 206920 kb
Host smart-0d9d1c77-7c09-4def-b619-f0302f591dfa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116364647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.116364647
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2511725457
Short name T545
Test name
Test status
Simulation time 626268120 ps
CPU time 4.57 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:17 PM PDT 24
Peak memory 207948 kb
Host smart-3474a003-32b2-412c-90c3-fdbb4ee9d3ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511725457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2511725457
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.107919738
Short name T751
Test name
Test status
Simulation time 101946400 ps
CPU time 1.79 seconds
Started Jun 27 04:47:54 PM PDT 24
Finished Jun 27 04:47:57 PM PDT 24
Peak memory 206980 kb
Host smart-096e616e-607f-47fa-83bf-654b097deb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107919738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.107919738
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2666163117
Short name T440
Test name
Test status
Simulation time 50416081 ps
CPU time 1.94 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 208412 kb
Host smart-ffbcf039-cdba-4f9c-bdd4-cbfdb06b699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666163117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2666163117
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1312694706
Short name T899
Test name
Test status
Simulation time 333889350 ps
CPU time 6.04 seconds
Started Jun 27 04:48:03 PM PDT 24
Finished Jun 27 04:48:10 PM PDT 24
Peak memory 206928 kb
Host smart-a3ae45b6-a390-4d8d-b77d-1091a53bf0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312694706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1312694706
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3912343353
Short name T272
Test name
Test status
Simulation time 33394077 ps
CPU time 2.6 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:47:58 PM PDT 24
Peak memory 214336 kb
Host smart-64eee95d-2d87-42a3-b7cf-181ceffcb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912343353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3912343353
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2693668254
Short name T398
Test name
Test status
Simulation time 1076932883 ps
CPU time 6.09 seconds
Started Jun 27 04:47:50 PM PDT 24
Finished Jun 27 04:47:58 PM PDT 24
Peak memory 211080 kb
Host smart-8ed3dfc3-86d1-43c4-a576-3f4d10d3b5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693668254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2693668254
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3893357920
Short name T856
Test name
Test status
Simulation time 25876717 ps
CPU time 0.82 seconds
Started Jun 27 04:46:03 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 205956 kb
Host smart-6dc79488-80f5-4b86-9676-2200056c38a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893357920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3893357920
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1380078401
Short name T263
Test name
Test status
Simulation time 369813779 ps
CPU time 4.93 seconds
Started Jun 27 04:46:00 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 215344 kb
Host smart-b61611a8-b5f3-4b50-9424-20660cc1989a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380078401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1380078401
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3129066938
Short name T790
Test name
Test status
Simulation time 72518037 ps
CPU time 2.9 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:07 PM PDT 24
Peak memory 209724 kb
Host smart-a9da840d-2fc7-41e4-b1f7-9e9e7b5434f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129066938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3129066938
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2837187388
Short name T554
Test name
Test status
Simulation time 73664819 ps
CPU time 3.31 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:07 PM PDT 24
Peak memory 208604 kb
Host smart-48c10cb0-bd4e-400d-a0ea-cba4c0462d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837187388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2837187388
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3428005957
Short name T378
Test name
Test status
Simulation time 116209130 ps
CPU time 2.22 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 214212 kb
Host smart-2a2ad993-2405-4721-bd9a-b476b57039cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428005957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3428005957
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2863565830
Short name T716
Test name
Test status
Simulation time 40613326 ps
CPU time 1.46 seconds
Started Jun 27 04:46:07 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 214136 kb
Host smart-a31751a7-fe10-4a84-8447-c0c79cd268d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863565830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2863565830
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4015644079
Short name T233
Test name
Test status
Simulation time 109274494 ps
CPU time 3.22 seconds
Started Jun 27 04:46:04 PM PDT 24
Finished Jun 27 04:46:10 PM PDT 24
Peak memory 214332 kb
Host smart-298511ff-0051-434f-b16e-a39009ef6837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015644079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4015644079
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1222700726
Short name T704
Test name
Test status
Simulation time 128490934 ps
CPU time 4.06 seconds
Started Jun 27 04:46:12 PM PDT 24
Finished Jun 27 04:46:18 PM PDT 24
Peak memory 208364 kb
Host smart-01c3135b-cfb0-482e-89a3-0db80a41898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222700726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1222700726
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.628384697
Short name T473
Test name
Test status
Simulation time 69862575 ps
CPU time 3.15 seconds
Started Jun 27 04:45:55 PM PDT 24
Finished Jun 27 04:46:01 PM PDT 24
Peak memory 208656 kb
Host smart-f6baca95-a32c-437f-a7d2-01653d90e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628384697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.628384697
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2101314639
Short name T321
Test name
Test status
Simulation time 461241131 ps
CPU time 3.4 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:07 PM PDT 24
Peak memory 208584 kb
Host smart-d5f6aced-1186-47bc-816f-b1487de82433
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101314639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2101314639
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.632551491
Short name T702
Test name
Test status
Simulation time 230446462 ps
CPU time 6.31 seconds
Started Jun 27 04:46:06 PM PDT 24
Finished Jun 27 04:46:14 PM PDT 24
Peak memory 208180 kb
Host smart-880fccf2-6cb0-485a-8c66-16ebe86b95fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632551491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.632551491
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2754207436
Short name T815
Test name
Test status
Simulation time 469497595 ps
CPU time 14.95 seconds
Started Jun 27 04:46:00 PM PDT 24
Finished Jun 27 04:46:18 PM PDT 24
Peak memory 208228 kb
Host smart-90d84534-1764-4180-bcde-da2d26b8e158
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754207436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2754207436
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.4100036040
Short name T517
Test name
Test status
Simulation time 73492422 ps
CPU time 2.63 seconds
Started Jun 27 04:46:12 PM PDT 24
Finished Jun 27 04:46:17 PM PDT 24
Peak memory 214148 kb
Host smart-4cf42111-3acb-4521-80bc-5c3e08b3ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100036040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4100036040
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3276785053
Short name T521
Test name
Test status
Simulation time 1982175999 ps
CPU time 10.64 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 208764 kb
Host smart-f34c0ba4-5e13-4736-971e-b92f31c26faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276785053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3276785053
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4132202817
Short name T862
Test name
Test status
Simulation time 39071170 ps
CPU time 2.94 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 218284 kb
Host smart-b68150c6-b03e-4fec-bd59-ac88faa071bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132202817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4132202817
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3905381184
Short name T453
Test name
Test status
Simulation time 320726500 ps
CPU time 2.31 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:04 PM PDT 24
Peak memory 210096 kb
Host smart-b1f87ac1-6e8e-443e-8d47-949a14ce0225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905381184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3905381184
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1848632832
Short name T636
Test name
Test status
Simulation time 27230340 ps
CPU time 0.71 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 205936 kb
Host smart-f8110d2c-06be-40bf-acff-6a05604704b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848632832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1848632832
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1341940634
Short name T436
Test name
Test status
Simulation time 108390564 ps
CPU time 5.71 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 222424 kb
Host smart-d358822c-c5eb-4911-9f6f-46de5d755d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341940634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1341940634
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.88381408
Short name T706
Test name
Test status
Simulation time 222823175 ps
CPU time 7.94 seconds
Started Jun 27 04:46:05 PM PDT 24
Finished Jun 27 04:46:15 PM PDT 24
Peak memory 210508 kb
Host smart-10ccf2d3-bdaa-41c2-b7c2-463e5745d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88381408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.88381408
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1040527017
Short name T795
Test name
Test status
Simulation time 563151869 ps
CPU time 6.88 seconds
Started Jun 27 04:46:04 PM PDT 24
Finished Jun 27 04:46:13 PM PDT 24
Peak memory 208944 kb
Host smart-b96ca64d-a5c2-4bc4-945a-f48bf2aa442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040527017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1040527017
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3889927218
Short name T187
Test name
Test status
Simulation time 58472582 ps
CPU time 2.86 seconds
Started Jun 27 04:46:05 PM PDT 24
Finished Jun 27 04:46:10 PM PDT 24
Peak memory 220728 kb
Host smart-4ae12144-f2cc-4597-9ef7-a538a20e6b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889927218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3889927218
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2316805531
Short name T235
Test name
Test status
Simulation time 434407681 ps
CPU time 23.58 seconds
Started Jun 27 04:46:02 PM PDT 24
Finished Jun 27 04:46:29 PM PDT 24
Peak memory 220652 kb
Host smart-5a0f4e5d-7561-4854-828d-412de2cdfe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316805531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2316805531
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3388591796
Short name T273
Test name
Test status
Simulation time 655746623 ps
CPU time 5.59 seconds
Started Jun 27 04:45:56 PM PDT 24
Finished Jun 27 04:46:04 PM PDT 24
Peak memory 218388 kb
Host smart-0dbc43fb-b7ae-4cac-a041-40d0640066c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388591796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3388591796
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.985312607
Short name T274
Test name
Test status
Simulation time 995253683 ps
CPU time 10.82 seconds
Started Jun 27 04:46:03 PM PDT 24
Finished Jun 27 04:46:16 PM PDT 24
Peak memory 208724 kb
Host smart-74b28402-2e9f-4cc7-88ee-06ec7ea8aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985312607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.985312607
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1092184205
Short name T109
Test name
Test status
Simulation time 19391554 ps
CPU time 1.87 seconds
Started Jun 27 04:46:05 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 206928 kb
Host smart-6f5893af-535a-4b9a-aead-379be2c241ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092184205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1092184205
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3878886211
Short name T715
Test name
Test status
Simulation time 97467774 ps
CPU time 3.58 seconds
Started Jun 27 04:46:02 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 208124 kb
Host smart-b2b95d37-aade-4a01-80cb-3bdd95e08d4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878886211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3878886211
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3434356025
Short name T531
Test name
Test status
Simulation time 63554701 ps
CPU time 2.97 seconds
Started Jun 27 04:45:55 PM PDT 24
Finished Jun 27 04:46:00 PM PDT 24
Peak memory 208440 kb
Host smart-0c1cbdfe-be0c-4f79-83c8-9787a9fa595b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434356025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3434356025
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2775009789
Short name T671
Test name
Test status
Simulation time 161019281 ps
CPU time 2.44 seconds
Started Jun 27 04:46:13 PM PDT 24
Finished Jun 27 04:46:18 PM PDT 24
Peak memory 207992 kb
Host smart-d071114a-0e8a-49d0-84e6-f53f104d6489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775009789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2775009789
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1918313171
Short name T609
Test name
Test status
Simulation time 551362349 ps
CPU time 4.05 seconds
Started Jun 27 04:46:02 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 208232 kb
Host smart-2659a1d5-e306-4433-bff3-442c723e6816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918313171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1918313171
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2331649328
Short name T47
Test name
Test status
Simulation time 4368145140 ps
CPU time 44.6 seconds
Started Jun 27 04:46:12 PM PDT 24
Finished Jun 27 04:47:00 PM PDT 24
Peak memory 217232 kb
Host smart-873aaf3b-e4bd-421a-8ba7-05c132385e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331649328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2331649328
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1144987267
Short name T284
Test name
Test status
Simulation time 129448870 ps
CPU time 3.01 seconds
Started Jun 27 04:46:07 PM PDT 24
Finished Jun 27 04:46:11 PM PDT 24
Peak memory 214276 kb
Host smart-b14372c8-e9f3-458e-a8bd-9f4d97ac0e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144987267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1144987267
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.947691565
Short name T902
Test name
Test status
Simulation time 216336618 ps
CPU time 2.72 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:07 PM PDT 24
Peak memory 209788 kb
Host smart-c1043f66-ba5d-4547-811d-b2b04058ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947691565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.947691565
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1434192584
Short name T762
Test name
Test status
Simulation time 80997477 ps
CPU time 0.74 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:02 PM PDT 24
Peak memory 205872 kb
Host smart-da99b550-023d-4aa7-88b4-e7af18b07290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434192584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1434192584
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4227983067
Short name T811
Test name
Test status
Simulation time 151965330 ps
CPU time 4.45 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:07 PM PDT 24
Peak memory 214888 kb
Host smart-60f00c63-ca15-46f8-ac55-2b3b6293ffc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227983067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4227983067
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3158796727
Short name T872
Test name
Test status
Simulation time 197557314 ps
CPU time 2.01 seconds
Started Jun 27 04:46:03 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 217008 kb
Host smart-f4351373-79a1-46c7-996b-7c8d35df7b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158796727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3158796727
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.800293927
Short name T68
Test name
Test status
Simulation time 94556653 ps
CPU time 4.28 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 214260 kb
Host smart-0d315ee5-72d0-448a-8fc4-c9da7a352556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800293927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.800293927
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2023918746
Short name T907
Test name
Test status
Simulation time 720764224 ps
CPU time 3.61 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:46:00 PM PDT 24
Peak memory 209704 kb
Host smart-39542b32-1b4b-4cab-9e41-b7fe2dcf94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023918746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2023918746
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.464893582
Short name T268
Test name
Test status
Simulation time 40129216 ps
CPU time 2.8 seconds
Started Jun 27 04:45:57 PM PDT 24
Finished Jun 27 04:46:02 PM PDT 24
Peak memory 220408 kb
Host smart-72bb404e-0605-448f-9de9-84b1bc5e3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464893582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.464893582
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2352433963
Short name T533
Test name
Test status
Simulation time 432231031 ps
CPU time 5.43 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 220392 kb
Host smart-9039d19a-38cf-4c4a-9ce6-e704adf8b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352433963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2352433963
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2862582480
Short name T446
Test name
Test status
Simulation time 175493431 ps
CPU time 5.28 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 207264 kb
Host smart-dff3c866-ea21-4e8f-8308-626d11c09653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862582480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2862582480
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3725275239
Short name T206
Test name
Test status
Simulation time 228199621 ps
CPU time 4.55 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:08 PM PDT 24
Peak memory 207856 kb
Host smart-ad7cd83f-9c01-4814-b588-54526e8ad61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725275239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3725275239
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3495782181
Short name T825
Test name
Test status
Simulation time 181932053 ps
CPU time 2.93 seconds
Started Jun 27 04:45:59 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 208604 kb
Host smart-51986f8a-b931-4794-a3a9-02d7fced81d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495782181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3495782181
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4063393475
Short name T784
Test name
Test status
Simulation time 134561886 ps
CPU time 4.02 seconds
Started Jun 27 04:46:02 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 206768 kb
Host smart-9909c95e-0791-4f53-bb51-d7b10487ad08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063393475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4063393475
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2013751382
Short name T192
Test name
Test status
Simulation time 130003298 ps
CPU time 2.19 seconds
Started Jun 27 04:46:01 PM PDT 24
Finished Jun 27 04:46:06 PM PDT 24
Peak memory 208760 kb
Host smart-2b3f99e9-f276-48f3-b453-f2d1a484b097
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013751382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2013751382
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1946186800
Short name T746
Test name
Test status
Simulation time 81956631 ps
CPU time 3.45 seconds
Started Jun 27 04:46:04 PM PDT 24
Finished Jun 27 04:46:10 PM PDT 24
Peak memory 209544 kb
Host smart-8f3284b3-fe86-4bf1-9844-eb1deb3ea0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946186800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1946186800
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3568187842
Short name T591
Test name
Test status
Simulation time 330696190 ps
CPU time 5.85 seconds
Started Jun 27 04:46:08 PM PDT 24
Finished Jun 27 04:46:15 PM PDT 24
Peak memory 206840 kb
Host smart-c687872a-7980-409a-8fd8-bfa86a152e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568187842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3568187842
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1822139120
Short name T723
Test name
Test status
Simulation time 906174707 ps
CPU time 23.58 seconds
Started Jun 27 04:45:54 PM PDT 24
Finished Jun 27 04:46:19 PM PDT 24
Peak memory 220400 kb
Host smart-bc7acf4d-49da-4e96-b53b-4fb319ba9900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822139120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1822139120
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1583011463
Short name T687
Test name
Test status
Simulation time 82777088 ps
CPU time 5.44 seconds
Started Jun 27 04:46:04 PM PDT 24
Finished Jun 27 04:46:12 PM PDT 24
Peak memory 222520 kb
Host smart-122cb90f-6f32-4660-b197-609ddffaf1ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583011463 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1583011463
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1592500785
Short name T426
Test name
Test status
Simulation time 233029041 ps
CPU time 6.94 seconds
Started Jun 27 04:46:06 PM PDT 24
Finished Jun 27 04:46:15 PM PDT 24
Peak memory 214216 kb
Host smart-66de70cb-dc8a-4cdb-b38c-23fed1f4134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592500785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1592500785
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3126541161
Short name T130
Test name
Test status
Simulation time 187721770 ps
CPU time 2.42 seconds
Started Jun 27 04:46:06 PM PDT 24
Finished Jun 27 04:46:10 PM PDT 24
Peak memory 210212 kb
Host smart-838260bd-1421-470c-89df-d63cd4628ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126541161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3126541161
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3433157839
Short name T796
Test name
Test status
Simulation time 10489712 ps
CPU time 0.7 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:32 PM PDT 24
Peak memory 206052 kb
Host smart-069d36ef-3b98-4729-a463-7e14c663929e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433157839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3433157839
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.610210570
Short name T827
Test name
Test status
Simulation time 491711712 ps
CPU time 12.03 seconds
Started Jun 27 04:46:33 PM PDT 24
Finished Jun 27 04:46:57 PM PDT 24
Peak memory 215108 kb
Host smart-cfa9a303-0934-4f48-a35a-9273522d915f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610210570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.610210570
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.542947358
Short name T538
Test name
Test status
Simulation time 203311265 ps
CPU time 1.91 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:25 PM PDT 24
Peak memory 210168 kb
Host smart-16d1d659-301f-42d2-9d71-7cb50ebb00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542947358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.542947358
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3175605376
Short name T854
Test name
Test status
Simulation time 85409045 ps
CPU time 2.76 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:37 PM PDT 24
Peak memory 218176 kb
Host smart-06a5a1c6-0115-4264-9155-d0d40c55729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175605376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3175605376
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2113477752
Short name T326
Test name
Test status
Simulation time 135150727 ps
CPU time 2.2 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 214208 kb
Host smart-2036e3f0-3b6e-4183-806b-5b3d63b4f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113477752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2113477752
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.605672503
Short name T89
Test name
Test status
Simulation time 841816711 ps
CPU time 7.85 seconds
Started Jun 27 04:46:29 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 214728 kb
Host smart-61fa1c5f-13d2-42ff-848e-1ed92b151b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605672503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.605672503
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3745778671
Short name T831
Test name
Test status
Simulation time 313551087 ps
CPU time 3.28 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:32 PM PDT 24
Peak memory 209228 kb
Host smart-0e0dfd18-cabb-48a4-a155-08d9036ab25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745778671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3745778671
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.670149688
Short name T891
Test name
Test status
Simulation time 123402532 ps
CPU time 5.44 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:36 PM PDT 24
Peak memory 208964 kb
Host smart-54938aba-a84f-4741-a8a7-e0786a127a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670149688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.670149688
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1670427805
Short name T868
Test name
Test status
Simulation time 101182025 ps
CPU time 2.77 seconds
Started Jun 27 04:46:03 PM PDT 24
Finished Jun 27 04:46:09 PM PDT 24
Peak memory 206892 kb
Host smart-d5bb5f44-356c-4146-a3ce-2b7d74cfc80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670427805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1670427805
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4139808801
Short name T387
Test name
Test status
Simulation time 92060147 ps
CPU time 2.68 seconds
Started Jun 27 04:45:58 PM PDT 24
Finished Jun 27 04:46:04 PM PDT 24
Peak memory 206696 kb
Host smart-607f3ca4-cc89-4c32-bcb1-9d56d4b6631c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139808801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4139808801
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2682065394
Short name T742
Test name
Test status
Simulation time 2941715720 ps
CPU time 20.75 seconds
Started Jun 27 04:46:00 PM PDT 24
Finished Jun 27 04:46:24 PM PDT 24
Peak memory 208608 kb
Host smart-d89efe87-f6f2-438b-ac19-26572d25b67c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682065394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2682065394
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2232298498
Short name T606
Test name
Test status
Simulation time 158613863 ps
CPU time 2.76 seconds
Started Jun 27 04:46:39 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 207240 kb
Host smart-56bb444e-6bfb-4b21-a906-1ede795af2ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232298498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2232298498
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2646138824
Short name T808
Test name
Test status
Simulation time 71769738 ps
CPU time 2.17 seconds
Started Jun 27 04:46:27 PM PDT 24
Finished Jun 27 04:46:39 PM PDT 24
Peak memory 209772 kb
Host smart-63ebb6da-c212-4858-9e2e-378f9bc1cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646138824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2646138824
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1188593186
Short name T573
Test name
Test status
Simulation time 353651883 ps
CPU time 4.57 seconds
Started Jun 27 04:46:04 PM PDT 24
Finished Jun 27 04:46:11 PM PDT 24
Peak memory 208324 kb
Host smart-55126058-277e-490a-ade6-9782021c2629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188593186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1188593186
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2587913070
Short name T288
Test name
Test status
Simulation time 2840196145 ps
CPU time 20.61 seconds
Started Jun 27 04:46:20 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 216468 kb
Host smart-247ba087-47a3-4342-a995-cd52dd3d2e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587913070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2587913070
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2657010948
Short name T125
Test name
Test status
Simulation time 1406713408 ps
CPU time 11.91 seconds
Started Jun 27 04:46:19 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 220532 kb
Host smart-bd10ac59-8bfe-4807-887d-14da1fd7ff0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657010948 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2657010948
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.648889518
Short name T335
Test name
Test status
Simulation time 2126561395 ps
CPU time 4.97 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 208596 kb
Host smart-bed03004-e644-400a-bdd7-e437d385169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648889518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.648889518
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3441922474
Short name T599
Test name
Test status
Simulation time 773886428 ps
CPU time 2.98 seconds
Started Jun 27 04:46:23 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 210036 kb
Host smart-4daf80be-786d-494d-a013-6f6a0631ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441922474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3441922474
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1532010201
Short name T905
Test name
Test status
Simulation time 16113102 ps
CPU time 0.73 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:25 PM PDT 24
Peak memory 206044 kb
Host smart-a4078360-d938-485c-b097-685b53acad89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532010201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1532010201
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.659878534
Short name T140
Test name
Test status
Simulation time 602027833 ps
CPU time 6.87 seconds
Started Jun 27 04:46:20 PM PDT 24
Finished Jun 27 04:46:29 PM PDT 24
Peak memory 214300 kb
Host smart-1c2f304c-46d9-41d0-a1a4-c4da51a9a003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659878534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.659878534
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3751147791
Short name T546
Test name
Test status
Simulation time 1034993614 ps
CPU time 27.17 seconds
Started Jun 27 04:46:21 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 208260 kb
Host smart-c3656748-ed69-41ee-a596-7da4a5c83a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751147791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3751147791
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1692180692
Short name T656
Test name
Test status
Simulation time 27669568 ps
CPU time 1.85 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:33 PM PDT 24
Peak memory 214324 kb
Host smart-7b502dfc-7a9a-4df1-a38c-a85a42489cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692180692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1692180692
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3853901049
Short name T661
Test name
Test status
Simulation time 504322893 ps
CPU time 4.01 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:46:27 PM PDT 24
Peak memory 222328 kb
Host smart-e47ed7d1-b3f3-4e0f-9ef6-48021fdb88a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853901049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3853901049
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.85996836
Short name T62
Test name
Test status
Simulation time 153129754 ps
CPU time 2.24 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:34 PM PDT 24
Peak memory 218016 kb
Host smart-8f74dde8-a852-4938-91be-f6da4ad1b971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85996836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.85996836
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3008684001
Short name T794
Test name
Test status
Simulation time 3157849673 ps
CPU time 14.66 seconds
Started Jun 27 04:46:34 PM PDT 24
Finished Jun 27 04:47:01 PM PDT 24
Peak memory 218500 kb
Host smart-028fab91-331f-426f-ad2c-ce974e71b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008684001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3008684001
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1931049707
Short name T813
Test name
Test status
Simulation time 261499972 ps
CPU time 4.94 seconds
Started Jun 27 04:46:18 PM PDT 24
Finished Jun 27 04:46:24 PM PDT 24
Peak memory 206864 kb
Host smart-95f71087-e9ea-4046-85db-2ed2662e9b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931049707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1931049707
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1015338843
Short name T255
Test name
Test status
Simulation time 177211747 ps
CPU time 2.47 seconds
Started Jun 27 04:46:35 PM PDT 24
Finished Jun 27 04:46:49 PM PDT 24
Peak memory 208772 kb
Host smart-17590620-074b-48ee-9638-1906edfd9533
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015338843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1015338843
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3423767879
Short name T886
Test name
Test status
Simulation time 1239122460 ps
CPU time 3.49 seconds
Started Jun 27 04:46:26 PM PDT 24
Finished Jun 27 04:46:35 PM PDT 24
Peak memory 208496 kb
Host smart-30d63e19-9b12-4568-a9fb-c9a8802692dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423767879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3423767879
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1762845980
Short name T480
Test name
Test status
Simulation time 414771578 ps
CPU time 5.94 seconds
Started Jun 27 04:46:28 PM PDT 24
Finished Jun 27 04:46:43 PM PDT 24
Peak memory 207988 kb
Host smart-3235a024-12ca-4577-a7c7-6c112725882e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762845980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1762845980
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1548647712
Short name T563
Test name
Test status
Simulation time 239625191 ps
CPU time 3.49 seconds
Started Jun 27 04:46:31 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 209852 kb
Host smart-664dee57-762e-494c-a0d1-70e29054047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548647712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1548647712
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2881583381
Short name T566
Test name
Test status
Simulation time 50535978 ps
CPU time 2.6 seconds
Started Jun 27 04:46:23 PM PDT 24
Finished Jun 27 04:46:28 PM PDT 24
Peak memory 206768 kb
Host smart-7796001d-27d8-4ed1-a07a-539ff40d1a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881583381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2881583381
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1362287960
Short name T309
Test name
Test status
Simulation time 4484532097 ps
CPU time 52.84 seconds
Started Jun 27 04:46:22 PM PDT 24
Finished Jun 27 04:47:19 PM PDT 24
Peak memory 222576 kb
Host smart-59e4b298-0ca7-4a21-935b-90f589fde930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362287960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1362287960
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1377901299
Short name T151
Test name
Test status
Simulation time 6213623198 ps
CPU time 21.79 seconds
Started Jun 27 04:46:25 PM PDT 24
Finished Jun 27 04:46:52 PM PDT 24
Peak memory 222888 kb
Host smart-968e5ecd-aff9-4b89-a4e2-bea0fc15ab56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377901299 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1377901299
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2470422388
Short name T445
Test name
Test status
Simulation time 357148934 ps
CPU time 5.59 seconds
Started Jun 27 04:46:18 PM PDT 24
Finished Jun 27 04:46:25 PM PDT 24
Peak memory 218452 kb
Host smart-50a82dc1-37c0-4b35-8a54-e0e43b81f261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470422388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2470422388
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4200195905
Short name T791
Test name
Test status
Simulation time 444946304 ps
CPU time 6.52 seconds
Started Jun 27 04:46:30 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 210388 kb
Host smart-a5d73e86-8041-4e0d-a22a-7a876cf0c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200195905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4200195905
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%