Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
56508 |
1 |
|
|
T1 |
270 |
|
T2 |
249 |
|
T3 |
49 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32719 |
1 |
|
|
T1 |
144 |
|
T2 |
156 |
|
T3 |
49 |
auto[1] |
23789 |
1 |
|
|
T1 |
126 |
|
T2 |
93 |
|
T4 |
35 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28125 |
1 |
|
|
T1 |
151 |
|
T2 |
127 |
|
T3 |
25 |
auto[1] |
28383 |
1 |
|
|
T1 |
119 |
|
T2 |
122 |
|
T3 |
24 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16098 |
1 |
|
|
T1 |
75 |
|
T2 |
80 |
|
T3 |
25 |
all_values[0] |
auto[0] |
auto[1] |
16621 |
1 |
|
|
T1 |
69 |
|
T2 |
76 |
|
T3 |
24 |
all_values[0] |
auto[1] |
auto[0] |
12027 |
1 |
|
|
T1 |
76 |
|
T2 |
47 |
|
T4 |
18 |
all_values[0] |
auto[1] |
auto[1] |
11762 |
1 |
|
|
T1 |
50 |
|
T2 |
46 |
|
T4 |
17 |