Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	72	258	78.18

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	53	227	81.07	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4727

1

T1

15

T2

17

T4

13

auto[1]

522

1

T1

1

T2

1

T4

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4727

1

T1

15

T2

17

T4

13

auto[1]

522

1

T1

1

T2

1

T4

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4749

1

T1

16

T2

18

T4

14

auto[1]

500

1

T4

1

T20

1

T185

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4749

1

T1

16

T2

18

T4

14

auto[1]

500

1

T4

1

T20

1

T185

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T2	3		T17	2		T32	1
auto[OpGenId]	1101	1			T1	6		T2	4		T4	4
auto[OpGenSwOut]	1074	1			T1	5		T2	7		T4	4
auto[OpGenHwOut]	2584	1			T1	5		T2	3		T4	7
auto[OpDisable]	74	1			T2	1		T19	1		T29	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	416	1			T2	3		T17	2		T32	1
auto[OpGenId]	1101	1			T1	6		T2	4		T4	4
auto[OpGenSwOut]	1074	1			T1	5		T2	7		T4	4
auto[OpGenHwOut]	2584	1			T1	5		T2	3		T4	7
auto[OpDisable]	74	1			T2	1		T19	1		T29	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4749

1

T1

16

T2

17

T4

14

auto[1]

500

1

T2

1

T4

1

T38

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4749

1

T1

16

T2

17

T4

14

auto[1]

500

1

T2

1

T4

1

T38

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5002

1

T1

16

T2

18

T4

15

auto[1]

247

1

T17

2

T140

1

T125

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1811	1			T1	6		T2	8		T4	5
auto[1]	655	1			T1	1		T2	1		T15	1
auto[2]	713	1			T1	3		T2	2		T4	5
auto[3]	705	1			T1	2		T2	1		T4	1
auto[4]	338	1			T2	1		T4	2		T18	1
auto[5]	305	1			T1	2		T4	1		T38	1
auto[6]	365	1			T1	2		T2	3		T38	1
auto[7]	357	1			T2	2		T4	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1365	1			T1	4		T2	6		T4	4
clear_one[1]	655	1			T1	1		T2	1		T15	1
clear_one[2]	713	1			T1	3		T2	2		T4	5
clear_one[3]	705	1			T1	2		T2	1		T4	1
clear_none	1811	1			T1	6		T2	8		T4	5

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1035	1			T1	4		T2	8		T4	6
auto[StInit]	620	1			T1	3		T2	3		T4	1
auto[StCreatorRootKey]	551	1			T1	1		T2	1		T4	1
auto[StOwnerIntKey]	510	1			T1	1		T2	1		T4	2
auto[StOwnerKey]	450	1			T1	1		T2	2		T4	2
auto[StDisabled]	1771	1			T1	6		T2	3		T4	3
auto[StInvalid]	312	1			T15	2		T42	1		T43	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1035	1			T1	4		T2	8		T4	6
auto[StInit]	620	1			T1	3		T2	3		T4	1
auto[StCreatorRootKey]	551	1			T1	1		T2	1		T4	1
auto[StOwnerIntKey]	510	1			T1	1		T2	1		T4	2
auto[StOwnerKey]	450	1			T1	1		T2	2		T4	2
auto[StDisabled]	1771	1			T1	6		T2	3		T4	3
auto[StInvalid]	312	1			T15	2		T42	1		T43	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	53	227	81.07	53

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T222	1		T223	1		T224	1
auto[0]	auto[StReset]	auto[OpGenId]	191	1			T1	1		T2	2		T4	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	154	1			T1	1		T2	2		T4	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	266	1			T1	1		T2	2		T4	2
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T17	1		T32	1		T29	1
auto[0]	auto[StInit]	auto[OpGenId]	71	1			T2	1		T29	1		T31	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	77	1			T59	1		T71	1		T122	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	182	1			T1	1		T18	1		T38	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	20	1			T225	1		T123	1		T69	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	49	1			T20	1		T54	1		T66	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	59	1			T4	1		T17	1		T122	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	71	1			T192	1		T52	1		T174	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T2	1		T190	1		T63	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T59	1		T122	1		T172	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	35	1			T59	1		T125	2		T83	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T191	1		T199	1		T195	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T125	1		T203	1		T226	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T1	1		T59	1		T83	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T17	1		T185	1		T179	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T62	1		T227	1		T127	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T187	1		T203	1		T228	2
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T1	1		T39	1		T185	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T30	1		T191	1		T175	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T18	2		T59	1		T183	1
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T19	1		T62	1		T203	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T229	1		T230	1		T231	1
auto[0]	auto[StInvalid]	auto[OpGenId]	24	1			T42	1		T232	1		T233	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	28	1			T43	1		T55	1		T234	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T55	1		T234	1		T235	1
auto[1]	auto[StReset]	auto[OpGenId]	15	1			T42	1		T59	1		T63	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	14	1			T2	1		T15	1		T185	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	52	1			T18	1		T236	1		T80	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T127	1		T211	1		T237	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T203	1		T124	2		T6	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T62	1		T238	1		T239	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	21	1			T192	1		T63	1		T66	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T97	1		T240	1		T241	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T59	2		T122	1		T54	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T185	1		T63	1		T242	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T38	1		T87	1		T63	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T29	1		T79	1		T129	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T1	1		T124	1		T178	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T83	1		T243	1		T128	3
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T192	1		T244	1		T204	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T245	1		T219	1		-	-
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T72	1		T222	1		T6	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T59	1		T83	1		T105	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T18	1		T38	1		T59	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	17	1			T39	1		T187	1		T63	1
auto[1]	auto[StDisabled]	auto[OpGenId]	41	1			T17	1		T59	2		T246	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T29	1		T59	1		T83	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T17	1		T20	1		T38	1
auto[1]	auto[StDisabled]	auto[OpDisable]	16	1			T63	1		T66	1		T178	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T43	1		T230	1		T247	2
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T41	1		T235	1		T78	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T43	2		T44	1		T41	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T44	1		T248	1		T86	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T249	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T15	1		T21	2		T235	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T189	1		T21	1		T62	2
auto[2]	auto[StReset]	auto[OpGenHwOut]	51	1			T4	1		T235	1		T80	1
auto[2]	auto[StInit]	auto[OpAdvance]	10	1			T59	1		T203	1		T244	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T63	2		T62	1		T250	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T20	1		T29	1		T26	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T4	1		T251	1		T252	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T253	1		T127	1		T254	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T63	1		T128	1		T6	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T255	1		T256	1		T257	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T29	1		T80	1		T258	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T65	1		T127	1		T177	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T4	1		T189	1		T69	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T20	1		T187	1		T259	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T87	1		T59	1		T194	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T128	3		T244	1		T260	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T2	1		T174	1		T68	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T63	1		T261	1		T262	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T4	1		T183	1		T263	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T2	1		T183	1		T126	1
auto[2]	auto[StDisabled]	auto[OpGenId]	55	1			T140	1		T186	1		T189	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T1	3		T30	1		T59	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T4	1		T17	1		T18	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T29	1		T59	1		T52	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T264	1		T265	1		T266	2
auto[2]	auto[StInvalid]	auto[OpGenId]	16	1			T44	1		T103	2		T78	2
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T234	1		T91	1		T103	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T90	1		T103	1		T78	1
auto[3]	auto[StReset]	auto[OpGenId]	27	1			T42	1		T43	1		T59	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T184	1		T63	1		T267	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	55	1			T15	1		T29	1		T192	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T2	1		T198	1		T268	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T125	1		T197	1		T95	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T59	1		T173	1		T83	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T1	1		T59	1		T26	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T39	1		T269	1		T270	4
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T59	1		T125	1		T63	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T31	1		T271	1		T98	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	51	1			T1	1		T18	1		T186	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T253	1		T124	1		T272	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T122	1		T273	1		T274	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T59	1		T63	1		T123	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T18	1		T80	1		T275	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T140	1		T59	1		T126	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T122	1		T253	1		T83	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T276	1		T277	1		T278	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T192	1		T52	1		T122	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T63	1		T203	1		T178	1
auto[3]	auto[StDisabled]	auto[OpGenId]	60	1			T29	1		T59	1		T126	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T4	1		T59	1		T122	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T87	1		T140	1		T192	1
auto[3]	auto[StDisabled]	auto[OpDisable]	13	1			T70	1		T71	1		T72	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T248	1		T279	1		T280	1
auto[3]	auto[StInvalid]	auto[OpGenId]	18	1			T235	1		T248	1		T233	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T44	1		T90	1		T103	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T15	1		T78	1		T281	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T282	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T66	1		T62	1		T105	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	14	1			T63	1		T204	1		T108	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T236	1		T198	1		T62	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T63	1		T283	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	8	1			T79	1		T262	1		T273	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T122	1		T69	1		T284	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	8	1			T227	1		T285	1		T286	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T282	1		T56	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T183	1		T287	1		T288	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T124	1		T289	1		T290	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T199	1		T196	1		T275	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T98	1		T291	1		T76	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T126	2		T237	1		T292	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T293	1		T67	1		T294	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T63	1		T236	1		T295	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T218	1		T296	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	4	1			T4	1		T20	1		T187	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T63	1		T297	1		T282	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T195	1		T173	1		T298	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T39	1		T59	1		T267	1
auto[4]	auto[StDisabled]	auto[OpGenId]	29	1			T4	1		T184	1		T68	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T59	1		T244	1		T299	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T18	1		T38	1		T192	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T2	1		T300	1		T301	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T88	1		T302	1		T303	1
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T304	1		T305	1		T306	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T55	1		T307	1		T308	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T88	1		T309	1		T280	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T310	1		T74	1		T311	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T204	1		T293	1		T88	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T5	1		T193	1		T312	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T27	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T26	1		T313	1		T314	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T1	1		T278	1		T315	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T189	1		T316	1		T317	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T77	1		T318	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T179	1		T57	1		T319	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T189	1		T124	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T193	1		T195	1		T263	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T321	1		T322	1		T323	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T174	1		T324	1		T325	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T62	1		T69	1		T326	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T4	1		T38	1		T59	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T179	1		T327	1		T328	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	3	1			T124	1		T166	1		T329	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T330	1		T98	1		T331	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T87	1		T194	1		T122	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	9	1			T269	1		T332	1		T333	1
auto[5]	auto[StDisabled]	auto[OpGenId]	17	1			T1	1		T59	1		T79	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T29	1		T197	1		T334	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T87	1		T192	1		T199	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T335	1		T336	1		T289	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T303	1		T337	2		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T55	1		T89	1		T303	2
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T44	1		T55	1		T232	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T234	1		T103	1		T279	1
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T297	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T1	1		T5	1		T272	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T2	1		T43	1		T281	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	12	1			T192	1		T338	1		T69	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T96	1		T339	1		T56	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T122	1		T340	1		T341	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T193	1		T338	1		T342	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T228	1		T343	1		T57	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T59	1		T62	1		T344	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T203	1		T105	1		T345	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T123	1		T346	1		T347	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T297	1		T204	1		T348	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T105	1		T178	1		T349	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T68	1		T129	1		T228	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T193	1		T347	1		T350	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T351	1		T311	1		T352	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T310	1		T353	1		T269	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T2	1		T190	1		T62	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T191	1		T175	1		T236	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T39	1		T140	2		T189	1
auto[6]	auto[StDisabled]	auto[OpGenId]	18	1			T62	1		T354	1		T228	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T2	1		T125	1		T122	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T1	1		T38	1		T193	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T355	1		T356	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T234	1		T279	1		T357	1
auto[6]	auto[StInvalid]	auto[OpGenId]	7	1			T103	1		T230	1		T304	2
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T229	1		T358	1		T230	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T235	1		T229	1		T230	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T254	1		T46	1		T11	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T4	1		T173	1		T63	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	17	1			T44	1		T63	1		T299	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T27	1		T359	1		T328	1
auto[7]	auto[StInit]	auto[OpGenId]	9	1			T59	1		T360	1		T212	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T28	1		T254	1		T361	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	20	1			T2	1		T185	1		T236	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T362	1		T359	1		T363	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T62	1		T364	1		T365	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T2	1		T62	1		T56	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T194	1		T366	1		T178	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T270	1		T300	1		T224	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T238	1		T367	1		T365	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T62	1		T69	1		T289	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T227	1		T368	1		T369	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T320	1		T363	1		T292	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T370	1		T365	1		T359	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T68	1		T228	1		T365	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T199	1		T197	1		T242	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	11	1			T17	1		T59	1		T371	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T186	1		T197	1		T63	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T17	1		T122	1		T63	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T267	1		T297	2		T298	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T372	1		T105	1		T6	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T303	1		T373	1		T374	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T55	1		T235	1		T375	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T15	1		T234	1		T90	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T358	1		T281	1		T302	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1365

1

T1

4

T2

6

T4

4

clear_one[1]

auto[0]

auto[0]

auto[0]

377

1

T1

1

T2

1

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

123

1

T38

3

T29

1

T59

1

clear_one[1]

auto[0]

auto[1]

auto[0]

128

1

T20

1

T59

1

T193

2

clear_one[1]

auto[0]

auto[1]

auto[1]

27

1

T185

1

T83

1

T338

1

clear_one[2]

auto[0]

auto[0]

auto[0]

423

1

T1

3

T2

1

T4

3

clear_one[2]

auto[0]

auto[0]

auto[1]

121

1

T4

1

T38

1

T30

1

clear_one[2]

auto[1]

auto[0]

auto[0]

141

1

T2

1

T4

1

T17

1

clear_one[2]

auto[1]

auto[0]

auto[1]

28

1

T59

1

T63

1

T83

1

clear_one[3]

auto[0]

auto[0]

auto[0]

438

1

T1

1

T2

1

T15

2

clear_one[3]

auto[0]

auto[1]

auto[0]

110

1

T193

1

T194

2

T174

1

clear_one[3]

auto[1]

auto[0]

auto[0]

126

1

T1

1

T18

2

T87

1

clear_one[3]

auto[1]

auto[1]

auto[0]

31

1

T4

1

T140

1

T59

1

clear_none

auto[0]

auto[0]

auto[0]

1335

1

T1

6

T2

7

T4

5

clear_none

auto[0]

auto[0]

auto[1]

122

1

T2

1

T199

1

T195

1

clear_none

auto[0]

auto[1]

auto[0]

131

1

T185

1

T59

1

T122

1

clear_none

auto[0]

auto[1]

auto[1]

27

1

T185

1

T30

2

T68

1

clear_none

auto[1]

auto[0]

auto[0]

118

1

T18

2

T192

1

T59

2

clear_none

auto[1]

auto[0]

auto[1]

32

1

T187

1

T66

1

T83

1

clear_none

auto[1]

auto[1]

auto[0]

26

1

T52

1

T63

1

T259

1

clear_none

auto[1]

auto[1]

auto[1]

20

1

T297

1

T338

1

T260

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1280	1			T1	4		T2	6		T4	4
clear_all	auto[1]	85	1			T17	1		T140	1		T125	1
clear_one[1]	auto[0]	638	1			T1	1		T2	1		T15	1
clear_one[1]	auto[1]	17	1			T127	1		T128	2		T129	2
clear_one[2]	auto[0]	674	1			T1	3		T2	2		T4	5
clear_one[2]	auto[1]	39	1			T225	4		T127	5		T128	7
clear_one[3]	auto[0]	676	1			T1	2		T2	1		T4	1
clear_one[3]	auto[1]	29	1			T125	1		T228	4		T324	3
clear_none	auto[0]	1734	1			T1	6		T2	8		T4	5
clear_none	auto[1]	77	1			T17	1		T125	2		T225	3