Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11111

1

T1

31

T2

30

T3

10

auto[Attestation]

7403

1

T1

52

T2

59

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2741	1			T1	16		T2	17		T3	2
auto[Aes]	3319	1			T1	14		T2	14		T4	8
auto[Kmac]	3344	1			T1	8		T2	16		T3	5
auto[Otbn]	3226	1			T1	10		T2	10		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7331	1			T1	31		T2	30		T3	8
auto[OpGenId]	5884	1			T1	35		T2	32		T3	7
auto[OpGenSwOut]	5726	1			T1	27		T2	36		T3	9
auto[OpGenHwOut]	6904	1			T1	21		T2	21		T4	18
auto[OpDisable]	136	1			T1	2		T2	1		T4	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10230

1

T1

41

T2

42

T3

8

auto[OpDoneFail]

15751

1

T1

75

T2

78

T3

16

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6600	1			T1	38		T2	48		T3	9
auto[StInit]	3673	1			T1	18		T2	17		T3	2
auto[StCreatorRootKey]	3080	1			T1	14		T2	14		T3	2
auto[StOwnerIntKey]	2645	1			T1	8		T2	7		T3	2
auto[StOwnerKey]	2367	1			T1	7		T2	10		T3	2
auto[StDisabled]	7616	1			T1	31		T2	24		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	346	1			T3	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T1	2		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	91	1			T2	1		T4	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	80	1			T40	1		T125	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T184	1		T64	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	206	1			T4	1		T30	1		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	301	1			T4	2		T15	4		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	95	1			T2	1		T4	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	75	1			T1	1		T29	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	56	1			T185	1		T59	1		T176	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	57	1			T40	1		T29	2		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	200	1			T187	1		T125	2		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	314	1			T1	1		T2	2		T3	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	102	1			T59	1		T71	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T64	1		T63	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T2	1		T59	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	66	1			T2	1		T185	2		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	228	1			T1	2		T2	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	372	1			T3	1		T4	2		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T2	1		T39	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	61	1			T3	1		T29	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	56	1			T1	1		T2	1		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T59	1		T122	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	184	1			T1	1		T2	1		T29	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	78	1			T1	5		T2	6		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T3	1		T19	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T29	1		T59	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T1	1		T187	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T29	1		T72	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	181	1			T1	2		T2	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T1	5		T2	4		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	72	1			T29	1		T44	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T2	1		T17	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T20	1		T59	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	55	1			T189	1		T190	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	225	1			T1	1		T2	3		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T1	1		T2	2		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	100	1			T1	1		T2	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T29	1		T59	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T17	1		T29	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T2	2		T3	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	215	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T2	3		T42	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T40	1		T29	2		T59	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T2	1		T185	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T59	1		T52	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	54	1			T1	1		T17	1		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	201	1			T1	1		T185	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	310	1			T4	1		T15	5		T29	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T1	1		T2	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T2	1		T186	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T40	1		T191	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T185	1		T29	1		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	198	1			T1	2		T2	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	511	1			T1	1		T4	3		T15	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T2	1		T87	1		T187	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T87	1		T140	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T18	1		T87	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	82	1			T2	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	296	1			T1	1		T17	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	457	1			T4	1		T15	1		T185	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T1	1		T4	1		T185	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T193	1		T194	1		T173	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T185	1		T59	2		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	77	1			T40	2		T185	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	272	1			T1	1		T2	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	440	1			T4	2		T20	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	125	1			T1	1		T19	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	118	1			T174	1		T63	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T195	1		T126	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	90	1			T1	1		T38	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	254	1			T1	1		T4	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	53	1			T1	1		T2	2		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T1	1		T4	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T2	2		T40	1		T29	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T4	1		T187	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T29	1		T59	1		T183	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T1	1		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	52	1			T1	2		T2	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T1	1		T18	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T1	1		T18	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	109	1			T192	1		T59	2		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T192	1		T197	1		T173	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	266	1			T1	1		T2	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	47	1			T2	2		T4	2		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	125	1			T2	2		T39	1		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T59	1		T52	1		T175	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T59	3		T193	1		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T193	1		T198	2		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	281	1			T4	2		T140	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	52	1			T1	1		T2	2		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	93	1			T1	1		T29	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T2	1		T4	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T38	1		T59	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	80	1			T30	1		T199	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	287	1			T1	1		T38	3		T185	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T2	1		T4	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	673	1			T1	2		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	173	1			T1	1		T40	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	611	1			T2	1		T4	3		T15	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	207	1			T2	2		T185	2		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	657	1			T1	3		T2	3		T3	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	168	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	689	1			T1	1		T2	2		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T1	1		T187	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	360	1			T1	7		T2	7		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T2	1		T17	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	380	1			T1	6		T2	7		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	231	1			T2	2		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	399	1			T1	3		T2	4		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T1	1		T2	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	388	1			T1	1		T2	3		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	156	1			T2	1		T40	1		T185	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	633	1			T1	3		T2	3		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	257	1			T2	1		T4	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	939	1			T1	2		T2	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	249	1			T40	2		T185	2		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	861	1			T1	2		T2	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T1	1		T38	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	842	1			T1	2		T4	3		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	192	1			T2	2		T4	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	346	1			T1	3		T2	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	284	1			T1	1		T18	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	462	1			T1	4		T2	3		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T59	4		T193	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	473	1			T2	4		T4	4		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	223	1			T2	1		T4	1		T38	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	448	1			T1	3		T2	2		T38	3