Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31869

1

T1

136

T2

135

T3

26

auto[1]

287

1

T17

1

T140

1

T125

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31875	1			T1	136		T2	135		T3	26
auto[134217728:268435455]	5	1			T297	1		T332	1		T326	1
auto[268435456:402653183]	3	1			T225	1		T403	1		T224	1
auto[402653184:536870911]	8	1			T244	2		T228	1		T362	1
auto[536870912:671088639]	6	1			T225	1		T404	1		T359	1
auto[671088640:805306367]	6	1			T228	1		T351	1		T332	1
auto[805306368:939524095]	11	1			T126	1		T129	1		T228	1
auto[939524096:1073741823]	12	1			T17	1		T125	1		T128	2
auto[1073741824:1207959551]	14	1			T128	1		T244	1		T226	2
auto[1207959552:1342177279]	14	1			T128	2		T228	1		T222	1
auto[1342177280:1476395007]	9	1			T222	1		T351	1		T363	2
auto[1476395008:1610612735]	7	1			T125	1		T129	1		T228	1
auto[1610612736:1744830463]	9	1			T225	1		T228	2		T324	1
auto[1744830464:1879048191]	9	1			T127	1		T128	1		T362	1
auto[1879048192:2013265919]	10	1			T225	1		T128	1		T362	1
auto[2013265920:2147483647]	15	1			T226	1		T324	1		T332	2
auto[2147483648:2281701375]	6	1			T126	1		T128	1		T109	1
auto[2281701376:2415919103]	17	1			T140	1		T128	1		T244	1
auto[2415919104:2550136831]	11	1			T244	1		T228	1		T222	1
auto[2550136832:2684354559]	15	1			T128	1		T222	1		T405	1
auto[2684354560:2818572287]	9	1			T126	2		T228	2		T326	1
auto[2818572288:2952790015]	12	1			T128	1		T244	1		T222	1
auto[2952790016:3087007743]	5	1			T324	1		T362	1		T365	1
auto[3087007744:3221225471]	3	1			T324	2		T362	1		-	-
auto[3221225472:3355443199]	8	1			T127	1		T244	1		T228	1
auto[3355443200:3489660927]	8	1			T226	1		T404	1		T332	2
auto[3489660928:3623878655]	6	1			T126	1		T129	1		T404	1
auto[3623878656:3758096383]	8	1			T125	1		T225	1		T228	1
auto[3758096384:3892314111]	6	1			T128	1		T109	1		T270	1
auto[3892314112:4026531839]	12	1			T129	1		T222	1		T353	1
auto[4026531840:4160749567]	7	1			T127	1		T128	1		T222	1
auto[4160749568:4294967295]	10	1			T228	1		T109	1		T353	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31869	1			T1	136		T2	135		T3	26
auto[0:134217727]	auto[1]	6	1			T225	1		T403	1		T363	1
auto[134217728:268435455]	auto[1]	5	1			T297	1		T332	1		T326	1
auto[268435456:402653183]	auto[1]	3	1			T225	1		T403	1		T224	1
auto[402653184:536870911]	auto[1]	8	1			T244	2		T228	1		T362	1
auto[536870912:671088639]	auto[1]	6	1			T225	1		T404	1		T359	1
auto[671088640:805306367]	auto[1]	6	1			T228	1		T351	1		T332	1
auto[805306368:939524095]	auto[1]	11	1			T126	1		T129	1		T228	1
auto[939524096:1073741823]	auto[1]	12	1			T17	1		T125	1		T128	2
auto[1073741824:1207959551]	auto[1]	14	1			T128	1		T244	1		T226	2
auto[1207959552:1342177279]	auto[1]	14	1			T128	2		T228	1		T222	1
auto[1342177280:1476395007]	auto[1]	9	1			T222	1		T351	1		T363	2
auto[1476395008:1610612735]	auto[1]	7	1			T125	1		T129	1		T228	1
auto[1610612736:1744830463]	auto[1]	9	1			T225	1		T228	2		T324	1
auto[1744830464:1879048191]	auto[1]	9	1			T127	1		T128	1		T362	1
auto[1879048192:2013265919]	auto[1]	10	1			T225	1		T128	1		T362	1
auto[2013265920:2147483647]	auto[1]	15	1			T226	1		T324	1		T332	2
auto[2147483648:2281701375]	auto[1]	6	1			T126	1		T128	1		T109	1
auto[2281701376:2415919103]	auto[1]	17	1			T140	1		T128	1		T244	1
auto[2415919104:2550136831]	auto[1]	11	1			T244	1		T228	1		T222	1
auto[2550136832:2684354559]	auto[1]	15	1			T128	1		T222	1		T405	1
auto[2684354560:2818572287]	auto[1]	9	1			T126	2		T228	2		T326	1
auto[2818572288:2952790015]	auto[1]	12	1			T128	1		T244	1		T222	1
auto[2952790016:3087007743]	auto[1]	5	1			T324	1		T362	1		T365	1
auto[3087007744:3221225471]	auto[1]	3	1			T324	2		T362	1		-	-
auto[3221225472:3355443199]	auto[1]	8	1			T127	1		T244	1		T228	1
auto[3355443200:3489660927]	auto[1]	8	1			T226	1		T404	1		T332	2
auto[3489660928:3623878655]	auto[1]	6	1			T126	1		T129	1		T404	1
auto[3623878656:3758096383]	auto[1]	8	1			T125	1		T225	1		T228	1
auto[3758096384:3892314111]	auto[1]	6	1			T128	1		T109	1		T270	1
auto[3892314112:4026531839]	auto[1]	12	1			T129	1		T222	1		T353	1
auto[4026531840:4160749567]	auto[1]	7	1			T127	1		T128	1		T222	1
auto[4160749568:4294967295]	auto[1]	10	1			T228	1		T109	1		T353	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2987

1

T1

13

T2

18

T4

4

auto[1]

242

1

T140

2

T125

2

T126

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T4	1		T185	1		T140	2
auto[134217728:268435455]	102	1			T42	1		T44	1		T59	2
auto[268435456:402653183]	115	1			T2	1		T39	1		T42	1
auto[402653184:536870911]	103	1			T43	1		T59	1		T125	1
auto[536870912:671088639]	94	1			T1	2		T2	2		T234	1
auto[671088640:805306367]	106	1			T1	2		T2	2		T187	1
auto[805306368:939524095]	97	1			T4	1		T29	1		T140	1
auto[939524096:1073741823]	99	1			T2	1		T185	1		T59	2
auto[1073741824:1207959551]	93	1			T1	1		T2	1		T4	1
auto[1207959552:1342177279]	113	1			T2	1		T15	2		T17	1
auto[1342177280:1476395007]	95	1			T1	1		T29	1		T140	1
auto[1476395008:1610612735]	93	1			T1	1		T2	2		T39	1
auto[1610612736:1744830463]	74	1			T2	1		T29	1		T44	1
auto[1744830464:1879048191]	98	1			T29	1		T30	1		T122	1
auto[1879048192:2013265919]	100	1			T187	1		T29	1		T189	1
auto[2013265920:2147483647]	95	1			T1	1		T42	1		T5	1
auto[2147483648:2281701375]	102	1			T29	1		T59	2		T125	1
auto[2281701376:2415919103]	107	1			T1	1		T15	1		T8	1
auto[2415919104:2550136831]	84	1			T17	1		T19	1		T42	1
auto[2550136832:2684354559]	96	1			T17	1		T29	1		T43	1
auto[2684354560:2818572287]	116	1			T1	1		T2	1		T15	1
auto[2818572288:2952790015]	99	1			T15	1		T140	1		T44	1
auto[2952790016:3087007743]	100	1			T2	1		T39	1		T140	1
auto[3087007744:3221225471]	117	1			T15	1		T42	1		T29	2
auto[3221225472:3355443199]	90	1			T2	1		T4	1		T39	1
auto[3355443200:3489660927]	88	1			T43	1		T70	1		T126	1
auto[3489660928:3623878655]	107	1			T29	1		T59	1		T125	1
auto[3623878656:3758096383]	98	1			T1	1		T39	1		T44	1
auto[3758096384:3892314111]	124	1			T2	1		T185	2		T43	1
auto[3892314112:4026531839]	109	1			T185	1		T41	1		T235	1
auto[4026531840:4160749567]	92	1			T1	1		T17	1		T140	1
auto[4160749568:4294967295]	101	1			T1	1		T2	3		T15	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1073741824:1207959551]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	114	1			T4	1		T185	1		T140	2
auto[0:134217727]	auto[1]	8	1			T404	1		T333	1		T270	1
auto[134217728:268435455]	auto[0]	93	1			T42	1		T44	1		T59	2
auto[134217728:268435455]	auto[1]	9	1			T129	1		T226	1		T324	2
auto[268435456:402653183]	auto[0]	106	1			T2	1		T39	1		T42	1
auto[268435456:402653183]	auto[1]	9	1			T128	2		T353	1		T362	1
auto[402653184:536870911]	auto[0]	94	1			T43	1		T59	1		T125	1
auto[402653184:536870911]	auto[1]	9	1			T297	1		T228	1		T222	2
auto[536870912:671088639]	auto[0]	92	1			T1	2		T2	2		T234	1
auto[536870912:671088639]	auto[1]	2	1			T362	1		T270	1		-	-
auto[671088640:805306367]	auto[0]	98	1			T1	2		T2	2		T187	1
auto[671088640:805306367]	auto[1]	8	1			T128	1		T129	1		T109	1
auto[805306368:939524095]	auto[0]	93	1			T4	1		T29	1		T140	1
auto[805306368:939524095]	auto[1]	4	1			T109	1		T362	1		T359	1
auto[939524096:1073741823]	auto[0]	92	1			T2	1		T185	1		T59	2
auto[939524096:1073741823]	auto[1]	7	1			T225	1		T228	1		T404	1
auto[1073741824:1207959551]	auto[0]	93	1			T1	1		T2	1		T4	1
auto[1207959552:1342177279]	auto[0]	108	1			T2	1		T15	2		T17	1
auto[1207959552:1342177279]	auto[1]	5	1			T128	1		T129	1		T324	1
auto[1342177280:1476395007]	auto[0]	86	1			T1	1		T29	1		T140	1
auto[1342177280:1476395007]	auto[1]	9	1			T228	1		T226	1		T365	1
auto[1476395008:1610612735]	auto[0]	86	1			T1	1		T2	2		T39	1
auto[1476395008:1610612735]	auto[1]	7	1			T127	1		T324	1		T326	1
auto[1610612736:1744830463]	auto[0]	68	1			T2	1		T29	1		T44	1
auto[1610612736:1744830463]	auto[1]	6	1			T222	1		T362	1		T333	1
auto[1744830464:1879048191]	auto[0]	90	1			T29	1		T30	1		T122	1
auto[1744830464:1879048191]	auto[1]	8	1			T126	1		T109	1		T332	1
auto[1879048192:2013265919]	auto[0]	94	1			T187	1		T29	1		T189	1
auto[1879048192:2013265919]	auto[1]	6	1			T228	1		T362	1		T333	1
auto[2013265920:2147483647]	auto[0]	89	1			T1	1		T42	1		T5	1
auto[2013265920:2147483647]	auto[1]	6	1			T129	1		T362	1		T270	2
auto[2147483648:2281701375]	auto[0]	90	1			T29	1		T59	2		T173	1
auto[2147483648:2281701375]	auto[1]	12	1			T125	1		T225	1		T128	1
auto[2281701376:2415919103]	auto[0]	104	1			T1	1		T15	1		T8	1
auto[2281701376:2415919103]	auto[1]	3	1			T352	1		T223	1		T224	1
auto[2415919104:2550136831]	auto[0]	78	1			T17	1		T19	1		T42	1
auto[2415919104:2550136831]	auto[1]	6	1			T127	2		T128	1		T359	1
auto[2550136832:2684354559]	auto[0]	87	1			T17	1		T29	1		T43	1
auto[2550136832:2684354559]	auto[1]	9	1			T128	1		T228	1		T222	1
auto[2684354560:2818572287]	auto[0]	108	1			T1	1		T2	1		T15	1
auto[2684354560:2818572287]	auto[1]	8	1			T109	1		T324	1		T405	1
auto[2818572288:2952790015]	auto[0]	87	1			T15	1		T44	1		T125	1
auto[2818572288:2952790015]	auto[1]	12	1			T140	1		T126	1		T406	1
auto[2952790016:3087007743]	auto[0]	90	1			T2	1		T39	1		T140	1
auto[2952790016:3087007743]	auto[1]	10	1			T129	1		T404	1		T362	1
auto[3087007744:3221225471]	auto[0]	104	1			T15	1		T42	1		T29	2
auto[3087007744:3221225471]	auto[1]	13	1			T128	3		T228	1		T324	1
auto[3221225472:3355443199]	auto[0]	81	1			T2	1		T4	1		T39	1
auto[3221225472:3355443199]	auto[1]	9	1			T125	1		T222	1		T406	1
auto[3355443200:3489660927]	auto[0]	79	1			T43	1		T70	1		T62	1
auto[3355443200:3489660927]	auto[1]	9	1			T126	1		T129	1		T109	1
auto[3489660928:3623878655]	auto[0]	97	1			T29	1		T59	1		T125	1
auto[3489660928:3623878655]	auto[1]	10	1			T127	1		T128	1		T324	2
auto[3623878656:3758096383]	auto[0]	93	1			T1	1		T39	1		T44	1
auto[3623878656:3758096383]	auto[1]	5	1			T228	1		T324	1		T363	2
auto[3758096384:3892314111]	auto[0]	117	1			T2	1		T185	2		T43	1
auto[3758096384:3892314111]	auto[1]	7	1			T225	1		T128	2		T129	1
auto[3892314112:4026531839]	auto[0]	101	1			T185	1		T41	1		T235	1
auto[3892314112:4026531839]	auto[1]	8	1			T244	1		T109	1		T222	1
auto[4026531840:4160749567]	auto[0]	82	1			T1	1		T17	1		T44	1
auto[4026531840:4160749567]	auto[1]	10	1			T140	1		T324	1		T282	1
auto[4160749568:4294967295]	auto[0]	93	1			T1	1		T2	3		T15	1
auto[4160749568:4294967295]	auto[1]	8	1			T128	1		T353	1		T407	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T1

4

T2

7

T4

2

auto[1]

1809

1

T1

10

T2

11

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T1	1		T2	1		T29	1
auto[134217728:268435455]	104	1			T2	1		T42	1		T29	1
auto[268435456:402653183]	95	1			T1	1		T2	1		T4	1
auto[402653184:536870911]	88	1			T187	1		T55	1		T184	1
auto[536870912:671088639]	99	1			T4	1		T15	1		T44	1
auto[671088640:805306367]	100	1			T29	1		T30	1		T125	1
auto[805306368:939524095]	100	1			T4	1		T39	1		T29	1
auto[939524096:1073741823]	107	1			T1	1		T2	1		T15	1
auto[1073741824:1207959551]	104	1			T1	1		T17	2		T42	1
auto[1207959552:1342177279]	111	1			T2	3		T39	1		T185	1
auto[1342177280:1476395007]	104	1			T1	1		T2	2		T15	1
auto[1476395008:1610612735]	111	1			T2	1		T17	1		T42	1
auto[1610612736:1744830463]	109	1			T1	1		T43	1		T59	2
auto[1744830464:1879048191]	104	1			T2	1		T4	1		T29	1
auto[1879048192:2013265919]	117	1			T1	1		T140	1		T197	1
auto[2013265920:2147483647]	107	1			T1	1		T2	1		T17	1
auto[2147483648:2281701375]	114	1			T2	1		T39	1		T140	1
auto[2281701376:2415919103]	109	1			T15	1		T5	2		T43	1
auto[2415919104:2550136831]	111	1			T1	1		T15	1		T42	1
auto[2550136832:2684354559]	103	1			T44	1		T125	1		T52	1
auto[2684354560:2818572287]	104	1			T15	2		T185	1		T59	1
auto[2818572288:2952790015]	117	1			T2	1		T43	1		T59	1
auto[2952790016:3087007743]	100	1			T2	1		T39	2		T125	1
auto[3087007744:3221225471]	114	1			T1	1		T44	1		T55	1
auto[3221225472:3355443199]	117	1			T2	1		T19	1		T29	1
auto[3355443200:3489660927]	88	1			T5	2		T59	1		T58	1
auto[3489660928:3623878655]	108	1			T1	1		T29	1		T140	1
auto[3623878656:3758096383]	107	1			T2	1		T185	1		T5	1
auto[3758096384:3892314111]	112	1			T1	1		T2	1		T140	1
auto[3892314112:4026531839]	100	1			T1	2		T42	1		T235	1
auto[4026531840:4160749567]	112	1			T17	1		T29	1		T59	2
auto[4160749568:4294967295]	117	1			T187	1		T140	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T1	1		T44	1		T174	1
auto[0:134217727]	auto[1]	51	1			T2	1		T29	1		T234	1
auto[134217728:268435455]	auto[0]	53	1			T2	1		T42	1		T29	1
auto[134217728:268435455]	auto[1]	51	1			T63	1		T72	1		T225	1
auto[268435456:402653183]	auto[0]	42	1			T2	1		T4	1		T44	2
auto[268435456:402653183]	auto[1]	53	1			T1	1		T42	1		T185	1
auto[402653184:536870911]	auto[0]	52	1			T187	1		T55	1		T184	1
auto[402653184:536870911]	auto[1]	36	1			T83	1		T334	1		T129	1
auto[536870912:671088639]	auto[0]	46	1			T4	1		T15	1		T44	1
auto[536870912:671088639]	auto[1]	53	1			T59	1		T54	1		T242	1
auto[671088640:805306367]	auto[0]	48	1			T30	1		T189	2		T126	1
auto[671088640:805306367]	auto[1]	52	1			T29	1		T125	1		T90	1
auto[805306368:939524095]	auto[0]	37	1			T39	1		T55	1		T234	1
auto[805306368:939524095]	auto[1]	63	1			T4	1		T29	1		T140	1
auto[939524096:1073741823]	auto[0]	64	1			T2	1		T15	1		T140	1
auto[939524096:1073741823]	auto[1]	43	1			T1	1		T31	1		T90	1
auto[1073741824:1207959551]	auto[0]	52	1			T17	1		T42	1		T29	1
auto[1073741824:1207959551]	auto[1]	52	1			T1	1		T17	1		T185	2
auto[1207959552:1342177279]	auto[0]	48	1			T2	1		T185	1		T30	1
auto[1207959552:1342177279]	auto[1]	63	1			T2	2		T39	1		T33	1
auto[1342177280:1476395007]	auto[0]	45	1			T1	1		T183	1		T63	1
auto[1342177280:1476395007]	auto[1]	59	1			T2	2		T15	1		T187	1
auto[1476395008:1610612735]	auto[0]	56	1			T42	1		T125	1		T78	1
auto[1476395008:1610612735]	auto[1]	55	1			T2	1		T17	1		T58	1
auto[1610612736:1744830463]	auto[0]	55	1			T43	1		T59	1		T125	1
auto[1610612736:1744830463]	auto[1]	54	1			T1	1		T59	1		T125	1
auto[1744830464:1879048191]	auto[0]	42	1			T2	1		T59	1		T125	1
auto[1744830464:1879048191]	auto[1]	62	1			T4	1		T29	1		T5	1
auto[1879048192:2013265919]	auto[0]	61	1			T1	1		T235	1		T63	2
auto[1879048192:2013265919]	auto[1]	56	1			T140	1		T197	1		T173	1
auto[2013265920:2147483647]	auto[0]	51	1			T2	1		T39	1		T43	1
auto[2013265920:2147483647]	auto[1]	56	1			T1	1		T17	1		T190	1
auto[2147483648:2281701375]	auto[0]	48	1			T2	1		T39	1		T184	1
auto[2147483648:2281701375]	auto[1]	66	1			T140	1		T59	4		T189	1
auto[2281701376:2415919103]	auto[0]	53	1			T5	2		T43	1		T44	1
auto[2281701376:2415919103]	auto[1]	56	1			T15	1		T184	1		T71	1
auto[2415919104:2550136831]	auto[0]	50	1			T15	1		T42	1		T29	1
auto[2415919104:2550136831]	auto[1]	61	1			T1	1		T29	1		T33	1
auto[2550136832:2684354559]	auto[0]	53	1			T44	1		T125	1		T90	1
auto[2550136832:2684354559]	auto[1]	50	1			T52	1		T70	1		T197	1
auto[2684354560:2818572287]	auto[0]	43	1			T15	1		T185	1		T174	1
auto[2684354560:2818572287]	auto[1]	61	1			T15	1		T59	1		T58	1
auto[2818572288:2952790015]	auto[0]	47	1			T59	1		T125	1		T21	1
auto[2818572288:2952790015]	auto[1]	70	1			T2	1		T43	1		T183	1
auto[2952790016:3087007743]	auto[0]	51	1			T39	1		T125	1		T184	1
auto[2952790016:3087007743]	auto[1]	49	1			T2	1		T39	1		T176	1
auto[3087007744:3221225471]	auto[0]	46	1			T1	1		T44	1		T62	1
auto[3087007744:3221225471]	auto[1]	68	1			T55	1		T122	2		T173	1
auto[3221225472:3355443199]	auto[0]	53	1			T5	1		T59	1		T54	1
auto[3221225472:3355443199]	auto[1]	64	1			T2	1		T19	1		T29	1
auto[3355443200:3489660927]	auto[0]	40	1			T58	1		T190	1		T63	1
auto[3355443200:3489660927]	auto[1]	48	1			T5	2		T59	1		T174	1
auto[3489660928:3623878655]	auto[0]	47	1			T29	1		T140	1		T59	2
auto[3489660928:3623878655]	auto[1]	61	1			T1	1		T175	1		T63	2
auto[3623878656:3758096383]	auto[0]	49	1			T44	1		T55	1		T248	1
auto[3623878656:3758096383]	auto[1]	58	1			T2	1		T185	1		T5	1
auto[3758096384:3892314111]	auto[0]	45	1			T78	1		T83	1		T211	1
auto[3758096384:3892314111]	auto[1]	67	1			T1	1		T2	1		T140	1
auto[3892314112:4026531839]	auto[0]	47	1			T235	1		T63	1		T68	2
auto[3892314112:4026531839]	auto[1]	53	1			T1	2		T42	1		T248	1
auto[4026531840:4160749567]	auto[0]	60	1			T17	1		T59	2		T189	1
auto[4026531840:4160749567]	auto[1]	52	1			T29	1		T63	1		T62	1
auto[4160749568:4294967295]	auto[0]	51	1			T187	1		T43	1		T41	1
auto[4160749568:4294967295]	auto[1]	66	1			T140	1		T189	1		T235	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1563

1

T1

2

T2

7

T4

2

auto[1]

1822

1

T1

12

T2

11

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T2	1		T42	1		T185	1
auto[134217728:268435455]	89	1			T1	2		T2	2		T39	1
auto[268435456:402653183]	95	1			T1	1		T15	1		T39	1
auto[402653184:536870911]	113	1			T1	1		T4	1		T187	1
auto[536870912:671088639]	108	1			T2	1		T29	1		T140	1
auto[671088640:805306367]	129	1			T1	1		T2	2		T15	1
auto[805306368:939524095]	101	1			T44	1		T59	1		T125	1
auto[939524096:1073741823]	90	1			T1	1		T42	1		T31	1
auto[1073741824:1207959551]	119	1			T42	1		T5	1		T30	1
auto[1207959552:1342177279]	96	1			T140	1		T184	1		T189	1
auto[1342177280:1476395007]	127	1			T1	2		T39	1		T187	1
auto[1476395008:1610612735]	107	1			T2	1		T187	1		T140	1
auto[1610612736:1744830463]	117	1			T2	2		T4	1		T185	1
auto[1744830464:1879048191]	114	1			T1	1		T2	1		T17	1
auto[1879048192:2013265919]	97	1			T2	1		T29	3		T30	1
auto[2013265920:2147483647]	111	1			T1	1		T2	1		T4	1
auto[2147483648:2281701375]	108	1			T29	1		T43	2		T125	1
auto[2281701376:2415919103]	102	1			T2	1		T15	2		T140	1
auto[2415919104:2550136831]	117	1			T29	3		T140	1		T5	1
auto[2550136832:2684354559]	103	1			T4	1		T5	1		T59	1
auto[2684354560:2818572287]	92	1			T2	1		T29	1		T59	1
auto[2818572288:2952790015]	93	1			T15	1		T17	1		T29	1
auto[2952790016:3087007743]	82	1			T185	1		T44	1		T59	1
auto[3087007744:3221225471]	96	1			T19	1		T42	1		T140	1
auto[3221225472:3355443199]	107	1			T43	1		T44	2		T59	2
auto[3355443200:3489660927]	105	1			T1	2		T2	1		T17	1
auto[3489660928:3623878655]	120	1			T2	2		T185	1		T59	2
auto[3623878656:3758096383]	135	1			T1	1		T17	1		T185	1
auto[3758096384:3892314111]	109	1			T42	1		T189	1		T63	1
auto[3892314112:4026531839]	110	1			T15	2		T43	1		T125	1
auto[4026531840:4160749567]	87	1			T2	1		T185	1		T29	1
auto[4160749568:4294967295]	103	1			T1	1		T39	1		T59	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	37	1			T185	1		T44	1		T68	1
auto[0:134217727]	auto[1]	66	1			T2	1		T42	1		T29	1
auto[134217728:268435455]	auto[0]	40	1			T2	1		T39	1		T55	1
auto[134217728:268435455]	auto[1]	49	1			T1	2		T2	1		T43	1
auto[268435456:402653183]	auto[0]	43	1			T1	1		T15	1		T29	1
auto[268435456:402653183]	auto[1]	52	1			T39	1		T140	1		T184	1
auto[402653184:536870911]	auto[0]	54	1			T59	1		T52	1		T189	1
auto[402653184:536870911]	auto[1]	59	1			T1	1		T4	1		T187	1
auto[536870912:671088639]	auto[0]	47	1			T2	1		T91	1		T127	1
auto[536870912:671088639]	auto[1]	61	1			T29	1		T140	1		T63	2
auto[671088640:805306367]	auto[0]	57	1			T2	1		T15	1		T17	1
auto[671088640:805306367]	auto[1]	72	1			T1	1		T2	1		T44	1
auto[805306368:939524095]	auto[0]	40	1			T44	1		T234	1		T90	1
auto[805306368:939524095]	auto[1]	61	1			T59	1		T125	1		T248	1
auto[939524096:1073741823]	auto[0]	42	1			T42	1		T235	1		T63	1
auto[939524096:1073741823]	auto[1]	48	1			T1	1		T31	1		T63	2
auto[1073741824:1207959551]	auto[0]	51	1			T42	1		T30	1		T235	1
auto[1073741824:1207959551]	auto[1]	68	1			T5	1		T183	1		T52	1
auto[1207959552:1342177279]	auto[0]	50	1			T184	1		T189	1		T63	1
auto[1207959552:1342177279]	auto[1]	46	1			T140	1		T173	1		T63	1
auto[1342177280:1476395007]	auto[0]	62	1			T39	1		T43	1		T44	1
auto[1342177280:1476395007]	auto[1]	65	1			T1	2		T187	1		T29	1
auto[1476395008:1610612735]	auto[0]	50	1			T187	1		T140	1		T125	1
auto[1476395008:1610612735]	auto[1]	57	1			T2	1		T5	1		T59	1
auto[1610612736:1744830463]	auto[0]	41	1			T4	1		T184	1		T90	1
auto[1610612736:1744830463]	auto[1]	76	1			T2	2		T185	1		T5	1
auto[1744830464:1879048191]	auto[0]	47	1			T59	1		T55	1		T235	1
auto[1744830464:1879048191]	auto[1]	67	1			T1	1		T2	1		T17	1
auto[1879048192:2013265919]	auto[0]	54	1			T2	1		T29	1		T30	1
auto[1879048192:2013265919]	auto[1]	43	1			T29	2		T267	1		T83	2
auto[2013265920:2147483647]	auto[0]	49	1			T39	1		T44	1		T59	1
auto[2013265920:2147483647]	auto[1]	62	1			T1	1		T2	1		T4	1
auto[2147483648:2281701375]	auto[0]	49	1			T43	1		T125	1		T41	1
auto[2147483648:2281701375]	auto[1]	59	1			T29	1		T43	1		T33	1
auto[2281701376:2415919103]	auto[0]	53	1			T2	1		T140	1		T31	1
auto[2281701376:2415919103]	auto[1]	49	1			T15	2		T54	1		T83	1
auto[2415919104:2550136831]	auto[0]	54	1			T29	1		T140	1		T5	1
auto[2415919104:2550136831]	auto[1]	63	1			T29	2		T59	1		T122	2
auto[2550136832:2684354559]	auto[0]	55	1			T4	1		T63	1		T68	1
auto[2550136832:2684354559]	auto[1]	48	1			T5	1		T59	1		T198	1
auto[2684354560:2818572287]	auto[0]	47	1			T2	1		T59	1		T54	2
auto[2684354560:2818572287]	auto[1]	45	1			T29	1		T58	1		T173	1
auto[2818572288:2952790015]	auto[0]	47	1			T5	1		T22	1		T91	1
auto[2818572288:2952790015]	auto[1]	46	1			T15	1		T17	1		T29	1
auto[2952790016:3087007743]	auto[0]	39	1			T44	1		T52	1		T62	2
auto[2952790016:3087007743]	auto[1]	43	1			T185	1		T59	1		T235	1
auto[3087007744:3221225471]	auto[0]	44	1			T42	1		T140	1		T5	1
auto[3087007744:3221225471]	auto[1]	52	1			T19	1		T59	1		T184	1
auto[3221225472:3355443199]	auto[0]	42	1			T43	1		T44	1		T59	1
auto[3221225472:3355443199]	auto[1]	65	1			T44	1		T59	1		T125	1
auto[3355443200:3489660927]	auto[0]	51	1			T1	1		T17	1		T42	1
auto[3355443200:3489660927]	auto[1]	54	1			T1	1		T2	1		T52	1
auto[3489660928:3623878655]	auto[0]	58	1			T59	2		T33	1		T267	2
auto[3489660928:3623878655]	auto[1]	62	1			T2	2		T185	1		T189	1
auto[3623878656:3758096383]	auto[0]	61	1			T185	1		T29	1		T52	1
auto[3623878656:3758096383]	auto[1]	74	1			T1	1		T17	1		T140	1
auto[3758096384:3892314111]	auto[0]	44	1			T42	1		T63	1		T62	1
auto[3758096384:3892314111]	auto[1]	65	1			T189	1		T54	1		T297	1
auto[3892314112:4026531839]	auto[0]	47	1			T15	1		T43	1		T125	1
auto[3892314112:4026531839]	auto[1]	63	1			T15	1		T183	1		T189	1
auto[4026531840:4160749567]	auto[0]	53	1			T2	1		T185	1		T29	1
auto[4026531840:4160749567]	auto[1]	34	1			T174	1		T60	1		T54	2
auto[4160749568:4294967295]	auto[0]	55	1			T39	1		T235	1		T63	3
auto[4160749568:4294967295]	auto[1]	48	1			T1	1		T59	1		T8	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1574

1

T1

4

T2

6

T4

2

auto[1]

1811

1

T1

10

T2

12

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T1	1		T2	1		T4	1
auto[134217728:268435455]	103	1			T17	1		T185	1		T59	1
auto[268435456:402653183]	129	1			T59	1		T52	1		T122	1
auto[402653184:536870911]	85	1			T1	1		T2	2		T39	1
auto[536870912:671088639]	115	1			T185	2		T5	1		T59	3
auto[671088640:805306367]	115	1			T2	1		T29	1		T5	1
auto[805306368:939524095]	93	1			T17	1		T5	1		T44	1
auto[939524096:1073741823]	97	1			T2	1		T15	1		T43	1
auto[1073741824:1207959551]	108	1			T1	1		T29	2		T140	1
auto[1207959552:1342177279]	93	1			T52	1		T190	1		T235	1
auto[1342177280:1476395007]	112	1			T2	1		T4	1		T15	1
auto[1476395008:1610612735]	97	1			T2	1		T17	1		T59	4
auto[1610612736:1744830463]	109	1			T1	1		T2	2		T17	1
auto[1744830464:1879048191]	125	1			T1	1		T42	1		T44	1
auto[1879048192:2013265919]	114	1			T185	1		T29	1		T140	1
auto[2013265920:2147483647]	94	1			T1	1		T2	2		T29	2
auto[2147483648:2281701375]	103	1			T44	1		T183	1		T189	1
auto[2281701376:2415919103]	103	1			T17	1		T39	2		T42	1
auto[2415919104:2550136831]	114	1			T1	1		T15	1		T42	1
auto[2550136832:2684354559]	106	1			T1	1		T2	1		T185	1
auto[2684354560:2818572287]	105	1			T2	1		T15	1		T29	1
auto[2818572288:2952790015]	98	1			T1	1		T39	1		T187	1
auto[2952790016:3087007743]	91	1			T1	2		T2	2		T15	1
auto[3087007744:3221225471]	109	1			T39	1		T42	1		T187	1
auto[3221225472:3355443199]	117	1			T42	1		T55	1		T184	1
auto[3355443200:3489660927]	113	1			T1	1		T2	2		T4	1
auto[3489660928:3623878655]	89	1			T140	1		T59	1		T125	1
auto[3623878656:3758096383]	108	1			T29	1		T140	1		T5	1
auto[3758096384:3892314111]	100	1			T1	1		T2	1		T4	1
auto[3892314112:4026531839]	97	1			T29	1		T44	1		T184	1
auto[4026531840:4160749567]	116	1			T15	1		T43	1		T44	1
auto[4160749568:4294967295]	115	1			T1	1		T15	1		T29	2