Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2987

1

T1

13

T2

18

T4

4

auto[1]

269

1

T17

4

T140

2

T125

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T2	2		T39	1		T185	1
auto[134217728:268435455]	98	1			T140	1		T43	1		T59	1
auto[268435456:402653183]	108	1			T1	1		T29	1		T140	1
auto[402653184:536870911]	81	1			T2	1		T17	1		T185	1
auto[536870912:671088639]	108	1			T2	1		T15	1		T39	1
auto[671088640:805306367]	122	1			T42	1		T44	1		T59	1
auto[805306368:939524095]	119	1			T17	1		T185	1		T125	1
auto[939524096:1073741823]	96	1			T1	2		T39	1		T5	1
auto[1073741824:1207959551]	103	1			T1	1		T2	1		T19	1
auto[1207959552:1342177279]	102	1			T2	2		T4	1		T17	1
auto[1342177280:1476395007]	91	1			T2	1		T125	2		T234	1
auto[1476395008:1610612735]	90	1			T29	1		T140	1		T5	1
auto[1610612736:1744830463]	90	1			T2	1		T59	1		T41	1
auto[1744830464:1879048191]	104	1			T1	1		T43	1		T44	1
auto[1879048192:2013265919]	96	1			T2	1		T29	1		T140	1
auto[2013265920:2147483647]	118	1			T1	1		T2	1		T17	2
auto[2147483648:2281701375]	112	1			T4	1		T187	2		T29	2
auto[2281701376:2415919103]	118	1			T1	1		T4	1		T15	1
auto[2415919104:2550136831]	107	1			T185	1		T29	1		T44	1
auto[2550136832:2684354559]	117	1			T2	1		T39	1		T42	1
auto[2684354560:2818572287]	105	1			T15	1		T17	1		T42	1
auto[2818572288:2952790015]	87	1			T1	1		T17	1		T29	1
auto[2952790016:3087007743]	98	1			T2	1		T185	1		T43	1
auto[3087007744:3221225471]	107	1			T17	1		T29	1		T189	1
auto[3221225472:3355443199]	94	1			T39	1		T42	1		T190	1
auto[3355443200:3489660927]	83	1			T1	1		T2	1		T39	1
auto[3489660928:3623878655]	97	1			T1	1		T4	1		T17	1
auto[3623878656:3758096383]	92	1			T2	1		T15	1		T29	1
auto[3758096384:3892314111]	106	1			T1	1		T43	1		T59	1
auto[3892314112:4026531839]	100	1			T1	2		T2	2		T15	2
auto[4026531840:4160749567]	101	1			T2	1		T15	1		T29	2
auto[4160749568:4294967295]	98	1			T187	1		T59	1		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T2	2		T39	1		T185	1
auto[0:134217727]	auto[1]	13	1			T297	1		T244	1		T406	1
auto[134217728:268435455]	auto[0]	90	1			T140	1		T43	1		T59	1
auto[134217728:268435455]	auto[1]	8	1			T332	1		T362	1		T326	1
auto[268435456:402653183]	auto[0]	98	1			T1	1		T29	1		T30	1
auto[268435456:402653183]	auto[1]	10	1			T140	1		T244	1		T365	2
auto[402653184:536870911]	auto[0]	75	1			T2	1		T17	1		T185	1
auto[402653184:536870911]	auto[1]	6	1			T228	1		T226	1		T332	1
auto[536870912:671088639]	auto[0]	101	1			T2	1		T15	1		T39	1
auto[536870912:671088639]	auto[1]	7	1			T225	1		T404	1		T333	1
auto[671088640:805306367]	auto[0]	110	1			T42	1		T44	1		T59	1
auto[671088640:805306367]	auto[1]	12	1			T225	3		T127	1		T353	1
auto[805306368:939524095]	auto[0]	108	1			T17	1		T185	1		T55	1
auto[805306368:939524095]	auto[1]	11	1			T125	1		T128	1		T324	1
auto[939524096:1073741823]	auto[0]	87	1			T1	2		T39	1		T5	1
auto[939524096:1073741823]	auto[1]	9	1			T127	1		T109	2		T222	1
auto[1073741824:1207959551]	auto[0]	97	1			T1	1		T2	1		T19	1
auto[1073741824:1207959551]	auto[1]	6	1			T125	1		T362	1		T365	2
auto[1207959552:1342177279]	auto[0]	95	1			T2	2		T4	1		T43	1
auto[1207959552:1342177279]	auto[1]	7	1			T17	1		T128	1		T244	1
auto[1342177280:1476395007]	auto[0]	84	1			T2	1		T125	1		T234	1
auto[1342177280:1476395007]	auto[1]	7	1			T125	1		T297	1		T226	1
auto[1476395008:1610612735]	auto[0]	85	1			T29	1		T5	1		T44	1
auto[1476395008:1610612735]	auto[1]	5	1			T140	1		T222	1		T324	1
auto[1610612736:1744830463]	auto[0]	82	1			T2	1		T59	1		T41	1
auto[1610612736:1744830463]	auto[1]	8	1			T297	1		T127	1		T129	2
auto[1744830464:1879048191]	auto[0]	96	1			T1	1		T43	1		T44	1
auto[1744830464:1879048191]	auto[1]	8	1			T127	1		T128	2		T222	1
auto[1879048192:2013265919]	auto[0]	92	1			T2	1		T29	1		T140	1
auto[1879048192:2013265919]	auto[1]	4	1			T128	1		T352	2		T245	1
auto[2013265920:2147483647]	auto[0]	109	1			T1	1		T2	1		T17	2
auto[2013265920:2147483647]	auto[1]	9	1			T125	1		T225	1		T127	1
auto[2147483648:2281701375]	auto[0]	103	1			T4	1		T187	2		T29	2
auto[2147483648:2281701375]	auto[1]	9	1			T226	1		T324	1		T407	1
auto[2281701376:2415919103]	auto[0]	109	1			T1	1		T4	1		T15	1
auto[2281701376:2415919103]	auto[1]	9	1			T244	1		T324	2		T332	1
auto[2415919104:2550136831]	auto[0]	99	1			T185	1		T29	1		T44	1
auto[2415919104:2550136831]	auto[1]	8	1			T244	1		T332	1		T362	1
auto[2550136832:2684354559]	auto[0]	106	1			T2	1		T39	1		T42	1
auto[2550136832:2684354559]	auto[1]	11	1			T226	1		T405	1		T362	1
auto[2684354560:2818572287]	auto[0]	89	1			T15	1		T42	1		T29	1
auto[2684354560:2818572287]	auto[1]	16	1			T17	1		T128	1		T109	1
auto[2818572288:2952790015]	auto[0]	75	1			T1	1		T29	1		T55	1
auto[2818572288:2952790015]	auto[1]	12	1			T17	1		T127	1		T128	1
auto[2952790016:3087007743]	auto[0]	89	1			T2	1		T185	1		T43	1
auto[2952790016:3087007743]	auto[1]	9	1			T126	1		T226	1		T332	1
auto[3087007744:3221225471]	auto[0]	101	1			T17	1		T29	1		T189	1
auto[3087007744:3221225471]	auto[1]	6	1			T297	1		T222	1		T359	1
auto[3221225472:3355443199]	auto[0]	88	1			T39	1		T42	1		T190	1
auto[3221225472:3355443199]	auto[1]	6	1			T126	1		T405	1		T359	1
auto[3355443200:3489660927]	auto[0]	79	1			T1	1		T2	1		T39	1
auto[3355443200:3489660927]	auto[1]	4	1			T362	1		T333	2		T270	1
auto[3489660928:3623878655]	auto[0]	85	1			T1	1		T4	1		T42	1
auto[3489660928:3623878655]	auto[1]	12	1			T17	1		T126	1		T128	2
auto[3623878656:3758096383]	auto[0]	83	1			T2	1		T15	1		T29	1
auto[3623878656:3758096383]	auto[1]	9	1			T127	1		T109	1		T222	1
auto[3758096384:3892314111]	auto[0]	99	1			T1	1		T43	1		T59	1
auto[3758096384:3892314111]	auto[1]	7	1			T225	1		T128	1		T244	1
auto[3892314112:4026531839]	auto[0]	91	1			T1	2		T2	2		T15	2
auto[3892314112:4026531839]	auto[1]	9	1			T109	2		T404	1		T362	2
auto[4026531840:4160749567]	auto[0]	94	1			T2	1		T15	1		T29	2
auto[4026531840:4160749567]	auto[1]	7	1			T244	1		T228	1		T353	1
auto[4160749568:4294967295]	auto[0]	93	1			T187	1		T59	1		T55	1
auto[4160749568:4294967295]	auto[1]	5	1			T225	1		T228	1		T109	1