Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7016

1

T1

33

T2

30

T4

7

auto[1]

313

1

T17

1

T140

2

T125

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2972	1			T1	14		T2	11		T4	3
auto[134217728:268435455]	159	1			T1	1		T5	1		T59	1
auto[268435456:402653183]	157	1			T1	2		T39	1		T185	2
auto[402653184:536870911]	151	1			T1	1		T2	1		T29	1
auto[536870912:671088639]	149	1			T4	1		T15	2		T29	1
auto[671088640:805306367]	132	1			T1	2		T2	2		T42	2
auto[805306368:939524095]	148	1			T1	1		T185	1		T140	1
auto[939524096:1073741823]	142	1			T2	1		T39	1		T140	1
auto[1073741824:1207959551]	143	1			T185	1		T29	1		T44	2
auto[1207959552:1342177279]	134	1			T2	1		T17	2		T42	1
auto[1342177280:1476395007]	115	1			T2	1		T44	1		T184	1
auto[1476395008:1610612735]	146	1			T1	1		T2	2		T42	1
auto[1610612736:1744830463]	152	1			T2	1		T15	1		T17	1
auto[1744830464:1879048191]	148	1			T2	1		T39	1		T44	1
auto[1879048192:2013265919]	122	1			T1	2		T15	1		T17	1
auto[2013265920:2147483647]	139	1			T1	2		T4	1		T59	1
auto[2147483648:2281701375]	149	1			T39	1		T29	1		T59	2
auto[2281701376:2415919103]	114	1			T1	2		T2	1		T15	1
auto[2415919104:2550136831]	107	1			T2	2		T29	1		T140	1
auto[2550136832:2684354559]	126	1			T2	1		T185	1		T187	1
auto[2684354560:2818572287]	157	1			T29	2		T44	1		T184	1
auto[2818572288:2952790015]	149	1			T15	1		T17	1		T43	1
auto[2952790016:3087007743]	134	1			T2	1		T4	1		T15	1
auto[3087007744:3221225471]	151	1			T2	1		T19	1		T140	1
auto[3221225472:3355443199]	121	1			T39	1		T29	1		T140	2
auto[3355443200:3489660927]	157	1			T1	1		T4	1		T42	2
auto[3489660928:3623878655]	148	1			T1	1		T15	1		T42	1
auto[3623878656:3758096383]	128	1			T1	1		T29	2		T43	1
auto[3758096384:3892314111]	129	1			T2	1		T185	1		T59	1
auto[3892314112:4026531839]	153	1			T1	1		T2	2		T15	1
auto[4026531840:4160749567]	166	1			T17	1		T140	1		T44	1
auto[4160749568:4294967295]	131	1			T1	1		T30	1		T59	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2966	1			T1	14		T2	11		T4	3
auto[0:134217727]	auto[1]	6	1			T140	1		T226	1		T270	1
auto[134217728:268435455]	auto[0]	147	1			T1	1		T5	1		T59	1
auto[134217728:268435455]	auto[1]	12	1			T225	2		T109	1		T324	1
auto[268435456:402653183]	auto[0]	148	1			T1	2		T39	1		T185	2
auto[268435456:402653183]	auto[1]	9	1			T225	1		T228	1		T226	1
auto[402653184:536870911]	auto[0]	142	1			T1	1		T2	1		T29	1
auto[402653184:536870911]	auto[1]	9	1			T225	1		T228	1		T226	1
auto[536870912:671088639]	auto[0]	134	1			T4	1		T15	2		T29	1
auto[536870912:671088639]	auto[1]	15	1			T128	1		T109	1		T226	1
auto[671088640:805306367]	auto[0]	123	1			T1	2		T2	2		T42	2
auto[671088640:805306367]	auto[1]	9	1			T126	1		T128	1		T406	1
auto[805306368:939524095]	auto[0]	138	1			T1	1		T185	1		T44	1
auto[805306368:939524095]	auto[1]	10	1			T140	1		T125	1		T128	2
auto[939524096:1073741823]	auto[0]	135	1			T2	1		T39	1		T140	1
auto[939524096:1073741823]	auto[1]	7	1			T324	1		T353	2		T365	2
auto[1073741824:1207959551]	auto[0]	130	1			T185	1		T29	1		T44	2
auto[1073741824:1207959551]	auto[1]	13	1			T225	1		T228	1		T226	2
auto[1207959552:1342177279]	auto[0]	131	1			T2	1		T17	2		T42	1
auto[1207959552:1342177279]	auto[1]	3	1			T226	1		T362	1		T410	1
auto[1342177280:1476395007]	auto[0]	108	1			T2	1		T44	1		T184	1
auto[1342177280:1476395007]	auto[1]	7	1			T228	1		T362	1		T407	1
auto[1476395008:1610612735]	auto[0]	132	1			T1	1		T2	2		T42	1
auto[1476395008:1610612735]	auto[1]	14	1			T222	1		T324	1		T405	1
auto[1610612736:1744830463]	auto[0]	142	1			T2	1		T15	1		T29	3
auto[1610612736:1744830463]	auto[1]	10	1			T17	1		T125	1		T225	1
auto[1744830464:1879048191]	auto[0]	136	1			T2	1		T39	1		T44	1
auto[1744830464:1879048191]	auto[1]	12	1			T128	1		T226	1		T324	1
auto[1879048192:2013265919]	auto[0]	114	1			T1	2		T15	1		T17	1
auto[1879048192:2013265919]	auto[1]	8	1			T126	1		T297	1		T324	1
auto[2013265920:2147483647]	auto[0]	127	1			T1	2		T4	1		T59	1
auto[2013265920:2147483647]	auto[1]	12	1			T125	1		T109	2		T222	2
auto[2147483648:2281701375]	auto[0]	140	1			T39	1		T29	1		T59	2
auto[2147483648:2281701375]	auto[1]	9	1			T128	1		T324	1		T405	1
auto[2281701376:2415919103]	auto[0]	105	1			T1	2		T2	1		T15	1
auto[2281701376:2415919103]	auto[1]	9	1			T324	1		T332	1		T365	1
auto[2415919104:2550136831]	auto[0]	97	1			T2	2		T29	1		T140	1
auto[2415919104:2550136831]	auto[1]	10	1			T244	1		T129	1		T362	1
auto[2550136832:2684354559]	auto[0]	117	1			T2	1		T185	1		T187	1
auto[2550136832:2684354559]	auto[1]	9	1			T127	1		T128	1		T109	1
auto[2684354560:2818572287]	auto[0]	146	1			T29	2		T44	1		T184	1
auto[2684354560:2818572287]	auto[1]	11	1			T128	1		T244	2		T228	1
auto[2818572288:2952790015]	auto[0]	138	1			T15	1		T17	1		T43	1
auto[2818572288:2952790015]	auto[1]	11	1			T244	1		T363	1		T411	1
auto[2952790016:3087007743]	auto[0]	123	1			T2	1		T4	1		T15	1
auto[2952790016:3087007743]	auto[1]	11	1			T128	1		T226	1		T404	1
auto[3087007744:3221225471]	auto[0]	143	1			T2	1		T19	1		T140	1
auto[3087007744:3221225471]	auto[1]	8	1			T228	1		T324	1		T405	1
auto[3221225472:3355443199]	auto[0]	116	1			T39	1		T29	1		T140	2
auto[3221225472:3355443199]	auto[1]	5	1			T404	1		T405	1		T333	1
auto[3355443200:3489660927]	auto[0]	146	1			T1	1		T4	1		T42	2
auto[3355443200:3489660927]	auto[1]	11	1			T244	2		T228	1		T222	1
auto[3489660928:3623878655]	auto[0]	135	1			T1	1		T15	1		T42	1
auto[3489660928:3623878655]	auto[1]	13	1			T125	1		T225	3		T226	1
auto[3623878656:3758096383]	auto[0]	118	1			T1	1		T29	2		T43	1
auto[3623878656:3758096383]	auto[1]	10	1			T244	1		T129	1		T270	1
auto[3758096384:3892314111]	auto[0]	120	1			T2	1		T185	1		T59	1
auto[3758096384:3892314111]	auto[1]	9	1			T128	2		T129	1		T109	1
auto[3892314112:4026531839]	auto[0]	140	1			T1	1		T2	2		T15	1
auto[3892314112:4026531839]	auto[1]	13	1			T244	2		T109	1		T324	2
auto[4026531840:4160749567]	auto[0]	153	1			T17	1		T140	1		T44	1
auto[4026531840:4160749567]	auto[1]	13	1			T225	1		T324	1		T353	2
auto[4160749568:4294967295]	auto[0]	126	1			T1	1		T30	1		T59	2
auto[4160749568:4294967295]	auto[1]	5	1			T126	1		T129	1		T226	1