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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4506 1 T1 22 T2 14 T4 6
auto[1] 2264 1 T1 6 T2 22 T4 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 194 1 T187 2 T43 2 T31 2
auto[134217728:268435455] 196 1 T1 2 T2 2 T15 2
auto[268435456:402653183] 232 1 T1 2 T17 2 T39 2
auto[402653184:536870911] 228 1 T4 2 T15 4 T140 2
auto[536870912:671088639] 194 1 T2 2 T29 2 T140 2
auto[671088640:805306367] 216 1 T2 4 T185 2 T29 2
auto[805306368:939524095] 224 1 T1 2 T2 2 T39 2
auto[939524096:1073741823] 202 1 T2 6 T140 2 T125 4
auto[1073741824:1207959551] 202 1 T39 2 T234 2 T33 2
auto[1207959552:1342177279] 164 1 T187 2 T44 2 T59 2
auto[1342177280:1476395007] 162 1 T29 2 T5 2 T44 2
auto[1476395008:1610612735] 238 1 T1 4 T15 4 T29 4
auto[1610612736:1744830463] 194 1 T15 2 T5 2 T44 2
auto[1744830464:1879048191] 212 1 T1 2 T2 2 T4 2
auto[1879048192:2013265919] 244 1 T1 2 T17 2 T39 2
auto[2013265920:2147483647] 222 1 T54 6 T62 4 T91 2
auto[2147483648:2281701375] 206 1 T39 2 T42 6 T30 4
auto[2281701376:2415919103] 180 1 T1 2 T4 2 T31 2
auto[2415919104:2550136831] 248 1 T1 2 T2 2 T29 2
auto[2550136832:2684354559] 194 1 T2 2 T17 2 T5 2
auto[2684354560:2818572287] 236 1 T2 2 T4 2 T5 2
auto[2818572288:2952790015] 174 1 T2 2 T29 2 T5 2
auto[2952790016:3087007743] 180 1 T2 2 T185 2 T140 2
auto[3087007744:3221225471] 256 1 T1 2 T2 2 T17 2
auto[3221225472:3355443199] 232 1 T15 2 T5 2 T43 2
auto[3355443200:3489660927] 214 1 T1 2 T2 2 T29 2
auto[3489660928:3623878655] 192 1 T1 2 T44 2 T59 2
auto[3623878656:3758096383] 230 1 T42 2 T29 2 T189 2
auto[3758096384:3892314111] 234 1 T2 2 T17 2 T187 2
auto[3892314112:4026531839] 226 1 T1 2 T2 2 T44 2
auto[4026531840:4160749567] 244 1 T1 2 T185 4 T140 2
auto[4160749568:4294967295] 200 1 T29 6 T140 2 T43 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 126 1 T43 2 T90 2 T63 4
auto[0:134217727] auto[1] 68 1 T187 2 T31 2 T21 2
auto[134217728:268435455] auto[0] 140 1 T1 2 T2 2 T185 4
auto[134217728:268435455] auto[1] 56 1 T15 2 T42 2 T44 2
auto[268435456:402653183] auto[0] 140 1 T1 2 T17 2 T235 2
auto[268435456:402653183] auto[1] 92 1 T39 2 T29 2 T33 2
auto[402653184:536870911] auto[0] 152 1 T15 4 T140 2 T59 2
auto[402653184:536870911] auto[1] 76 1 T4 2 T43 2 T122 2
auto[536870912:671088639] auto[0] 132 1 T29 2 T140 2 T59 2
auto[536870912:671088639] auto[1] 62 1 T2 2 T189 2 T63 2
auto[671088640:805306367] auto[0] 142 1 T185 2 T140 4 T5 2
auto[671088640:805306367] auto[1] 74 1 T2 4 T29 2 T62 4
auto[805306368:939524095] auto[0] 154 1 T2 2 T39 2 T43 2
auto[805306368:939524095] auto[1] 70 1 T1 2 T44 2 T52 2
auto[939524096:1073741823] auto[0] 128 1 T2 4 T140 2 T125 4
auto[939524096:1073741823] auto[1] 74 1 T2 2 T122 2 T68 2
auto[1073741824:1207959551] auto[0] 144 1 T39 2 T234 2 T33 2
auto[1073741824:1207959551] auto[1] 58 1 T58 2 T203 4 T69 2
auto[1207959552:1342177279] auto[0] 102 1 T59 2 T52 2 T90 2
auto[1207959552:1342177279] auto[1] 62 1 T187 2 T44 2 T63 2
auto[1342177280:1476395007] auto[0] 110 1 T29 2 T44 2 T59 2
auto[1342177280:1476395007] auto[1] 52 1 T5 2 T190 2 T267 2
auto[1476395008:1610612735] auto[0] 162 1 T1 4 T15 2 T29 2
auto[1476395008:1610612735] auto[1] 76 1 T15 2 T29 2 T189 2
auto[1610612736:1744830463] auto[0] 120 1 T15 2 T5 2 T44 2
auto[1610612736:1744830463] auto[1] 74 1 T70 2 T175 2 T248 2
auto[1744830464:1879048191] auto[0] 156 1 T1 2 T4 2 T29 2
auto[1744830464:1879048191] auto[1] 56 1 T2 2 T202 2 T69 2
auto[1879048192:2013265919] auto[0] 170 1 T1 2 T17 2 T39 2
auto[1879048192:2013265919] auto[1] 74 1 T63 2 T54 2 T79 2
auto[2013265920:2147483647] auto[0] 144 1 T54 4 T62 2 T91 2
auto[2013265920:2147483647] auto[1] 78 1 T54 2 T62 2 T26 2
auto[2147483648:2281701375] auto[0] 140 1 T39 2 T42 4 T30 2
auto[2147483648:2281701375] auto[1] 66 1 T42 2 T30 2 T63 2
auto[2281701376:2415919103] auto[0] 114 1 T1 2 T4 2 T31 2
auto[2281701376:2415919103] auto[1] 66 1 T173 2 T176 2 T60 2
auto[2415919104:2550136831] auto[0] 168 1 T29 2 T184 2 T235 2
auto[2415919104:2550136831] auto[1] 80 1 T1 2 T2 2 T8 2
auto[2550136832:2684354559] auto[0] 146 1 T17 2 T5 2 T52 2
auto[2550136832:2684354559] auto[1] 48 1 T2 2 T55 2 T176 2
auto[2684354560:2818572287] auto[0] 162 1 T4 2 T5 2 T44 2
auto[2684354560:2818572287] auto[1] 74 1 T2 2 T63 2 T62 2
auto[2818572288:2952790015] auto[0] 118 1 T2 2 T29 2 T5 2
auto[2818572288:2952790015] auto[1] 56 1 T59 2 T63 2 T62 2
auto[2952790016:3087007743] auto[0] 112 1 T185 2 T140 2 T41 2
auto[2952790016:3087007743] auto[1] 68 1 T2 2 T83 2 T243 2
auto[3087007744:3221225471] auto[0] 146 1 T1 2 T2 2 T17 2
auto[3087007744:3221225471] auto[1] 110 1 T19 2 T42 2 T59 2
auto[3221225472:3355443199] auto[0] 148 1 T15 2 T5 2 T43 2
auto[3221225472:3355443199] auto[1] 84 1 T90 2 T235 2 T248 2
auto[3355443200:3489660927] auto[0] 138 1 T1 2 T2 2 T29 2
auto[3355443200:3489660927] auto[1] 76 1 T55 2 T52 2 T126 2
auto[3489660928:3623878655] auto[0] 128 1 T1 2 T44 2 T59 2
auto[3489660928:3623878655] auto[1] 64 1 T122 2 T83 2 T9 2
auto[3623878656:3758096383] auto[0] 162 1 T42 2 T189 2 T198 2
auto[3623878656:3758096383] auto[1] 68 1 T29 2 T235 2 T24 2
auto[3758096384:3892314111] auto[0] 142 1 T5 2 T59 2 T184 2
auto[3758096384:3892314111] auto[1] 92 1 T2 2 T17 2 T187 2
auto[3892314112:4026531839] auto[0] 152 1 T44 2 T184 2 T173 2
auto[3892314112:4026531839] auto[1] 74 1 T1 2 T2 2 T184 2
auto[4026531840:4160749567] auto[0] 156 1 T1 2 T185 2 T140 2
auto[4026531840:4160749567] auto[1] 88 1 T185 2 T59 6 T63 2
auto[4160749568:4294967295] auto[0] 152 1 T29 4 T140 2 T43 2
auto[4160749568:4294967295] auto[1] 48 1 T29 2 T41 2 T71 2

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