Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
877 |
1 |
|
|
T1 |
4 |
|
T2 |
8 |
|
T4 |
7 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
480 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T4 |
4 |
auto[1] |
397 |
1 |
|
|
T2 |
2 |
|
T4 |
3 |
|
T29 |
2 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T4 |
5 |
auto[1] |
536 |
1 |
|
|
T1 |
3 |
|
T2 |
4 |
|
T4 |
2 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
518 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T4 |
5 |
auto[1] |
359 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T4 |
2 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
190 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
3 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
87 |
1 |
|
|
T29 |
1 |
|
T52 |
2 |
|
T60 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
151 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T60 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
90 |
1 |
|
|
T2 |
1 |
|
T29 |
1 |
|
T52 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
203 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T4 |
1 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
156 |
1 |
|
|
T4 |
1 |
|
T29 |
1 |
|
T52 |
2 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |