Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 98.15 98.30 100.00 99.02 98.41 91.24


Total test records in report: 1090
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1006 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2663770324 Jun 28 04:42:28 PM PDT 24 Jun 28 04:42:30 PM PDT 24 110271906 ps
T1007 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3981767150 Jun 28 04:43:26 PM PDT 24 Jun 28 04:43:28 PM PDT 24 16056288 ps
T1008 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3495893345 Jun 28 04:42:56 PM PDT 24 Jun 28 04:42:59 PM PDT 24 51067112 ps
T1009 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1483790387 Jun 28 04:42:39 PM PDT 24 Jun 28 04:42:42 PM PDT 24 149143408 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2391182052 Jun 28 04:42:37 PM PDT 24 Jun 28 04:42:44 PM PDT 24 2114013468 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3131489001 Jun 28 04:42:39 PM PDT 24 Jun 28 04:42:41 PM PDT 24 122662178 ps
T1012 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3195900223 Jun 28 04:43:07 PM PDT 24 Jun 28 04:43:12 PM PDT 24 295867308 ps
T1013 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1852240107 Jun 28 04:43:06 PM PDT 24 Jun 28 04:43:09 PM PDT 24 259733277 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2798278146 Jun 28 04:42:40 PM PDT 24 Jun 28 04:42:44 PM PDT 24 95934185 ps
T1015 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.787712088 Jun 28 04:43:17 PM PDT 24 Jun 28 04:43:19 PM PDT 24 18472373 ps
T1016 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1440130363 Jun 28 04:43:05 PM PDT 24 Jun 28 04:43:20 PM PDT 24 381155934 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2430781948 Jun 28 04:42:27 PM PDT 24 Jun 28 04:42:32 PM PDT 24 182590821 ps
T1018 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3800539631 Jun 28 04:43:26 PM PDT 24 Jun 28 04:43:28 PM PDT 24 35360643 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1112084511 Jun 28 04:43:10 PM PDT 24 Jun 28 04:43:12 PM PDT 24 183999141 ps
T1020 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3294259810 Jun 28 04:43:07 PM PDT 24 Jun 28 04:43:10 PM PDT 24 80963665 ps
T1021 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2637941104 Jun 28 04:43:05 PM PDT 24 Jun 28 04:43:07 PM PDT 24 71291300 ps
T1022 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2262271652 Jun 28 04:43:21 PM PDT 24 Jun 28 04:43:23 PM PDT 24 119852169 ps
T153 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1675599317 Jun 28 04:43:18 PM PDT 24 Jun 28 04:43:27 PM PDT 24 524520145 ps
T1023 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4215465421 Jun 28 04:43:16 PM PDT 24 Jun 28 04:43:24 PM PDT 24 266575912 ps
T1024 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3643501066 Jun 28 04:43:19 PM PDT 24 Jun 28 04:43:22 PM PDT 24 33539900 ps
T1025 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.227829603 Jun 28 04:43:20 PM PDT 24 Jun 28 04:43:22 PM PDT 24 12592404 ps
T1026 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2746903874 Jun 28 04:43:06 PM PDT 24 Jun 28 04:43:11 PM PDT 24 886001595 ps
T1027 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1803298871 Jun 28 04:42:57 PM PDT 24 Jun 28 04:43:00 PM PDT 24 59295952 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2246752205 Jun 28 04:43:08 PM PDT 24 Jun 28 04:43:11 PM PDT 24 38180565 ps
T1029 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1511013629 Jun 28 04:43:08 PM PDT 24 Jun 28 04:43:13 PM PDT 24 308934343 ps
T1030 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2298912648 Jun 28 04:43:19 PM PDT 24 Jun 28 04:43:23 PM PDT 24 123667971 ps
T1031 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.492781219 Jun 28 04:43:15 PM PDT 24 Jun 28 04:43:17 PM PDT 24 26233070 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.869174231 Jun 28 04:42:39 PM PDT 24 Jun 28 04:42:47 PM PDT 24 265012510 ps
T1033 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3658056341 Jun 28 04:43:06 PM PDT 24 Jun 28 04:43:09 PM PDT 24 50496651 ps
T154 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2418365822 Jun 28 04:43:14 PM PDT 24 Jun 28 04:43:20 PM PDT 24 810626138 ps
T1034 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3024429450 Jun 28 04:43:20 PM PDT 24 Jun 28 04:43:24 PM PDT 24 643600494 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.657492565 Jun 28 04:42:40 PM PDT 24 Jun 28 04:42:42 PM PDT 24 287625650 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1190123711 Jun 28 04:43:06 PM PDT 24 Jun 28 04:43:08 PM PDT 24 10620167 ps
T1037 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.518422425 Jun 28 04:42:59 PM PDT 24 Jun 28 04:43:00 PM PDT 24 8536362 ps
T1038 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1072592178 Jun 28 04:42:55 PM PDT 24 Jun 28 04:43:00 PM PDT 24 755352103 ps
T1039 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3754301292 Jun 28 04:42:55 PM PDT 24 Jun 28 04:42:56 PM PDT 24 26897854 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1183588011 Jun 28 04:43:21 PM PDT 24 Jun 28 04:43:24 PM PDT 24 106135716 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2965174136 Jun 28 04:43:05 PM PDT 24 Jun 28 04:43:06 PM PDT 24 40388551 ps
T1042 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2947576532 Jun 28 04:43:08 PM PDT 24 Jun 28 04:43:11 PM PDT 24 403975106 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3750731789 Jun 28 04:42:25 PM PDT 24 Jun 28 04:42:27 PM PDT 24 22539027 ps
T1044 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1086549418 Jun 28 04:42:42 PM PDT 24 Jun 28 04:42:43 PM PDT 24 52525599 ps
T1045 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1907430159 Jun 28 04:43:18 PM PDT 24 Jun 28 04:43:21 PM PDT 24 11937655 ps
T144 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.624343190 Jun 28 04:42:55 PM PDT 24 Jun 28 04:43:01 PM PDT 24 411637458 ps
T1046 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3284436487 Jun 28 04:43:14 PM PDT 24 Jun 28 04:43:15 PM PDT 24 16798452 ps
T1047 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1141697447 Jun 28 04:43:21 PM PDT 24 Jun 28 04:43:23 PM PDT 24 12311388 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1381361932 Jun 28 04:42:30 PM PDT 24 Jun 28 04:42:32 PM PDT 24 32302656 ps
T1049 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2493013716 Jun 28 04:43:20 PM PDT 24 Jun 28 04:43:23 PM PDT 24 318664284 ps
T1050 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2981412623 Jun 28 04:43:29 PM PDT 24 Jun 28 04:43:32 PM PDT 24 40611220 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1215806380 Jun 28 04:42:26 PM PDT 24 Jun 28 04:42:52 PM PDT 24 7122901437 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4150576054 Jun 28 04:43:03 PM PDT 24 Jun 28 04:43:05 PM PDT 24 34932658 ps
T1053 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4182658613 Jun 28 04:43:20 PM PDT 24 Jun 28 04:43:26 PM PDT 24 439065490 ps
T1054 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2918637671 Jun 28 04:42:25 PM PDT 24 Jun 28 04:42:35 PM PDT 24 402029302 ps
T155 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1448290293 Jun 28 04:42:40 PM PDT 24 Jun 28 04:42:51 PM PDT 24 302656583 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.90045783 Jun 28 04:42:27 PM PDT 24 Jun 28 04:42:28 PM PDT 24 32404908 ps
T1056 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3562371445 Jun 28 04:43:04 PM PDT 24 Jun 28 04:43:06 PM PDT 24 40783877 ps
T1057 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1703161882 Jun 28 04:43:18 PM PDT 24 Jun 28 04:43:22 PM PDT 24 59426171 ps
T1058 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3477201984 Jun 28 04:43:15 PM PDT 24 Jun 28 04:43:17 PM PDT 24 166252967 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.630816092 Jun 28 04:42:40 PM PDT 24 Jun 28 04:42:43 PM PDT 24 56611053 ps
T1060 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2861048254 Jun 28 04:42:53 PM PDT 24 Jun 28 04:42:56 PM PDT 24 141262573 ps
T1061 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2608024275 Jun 28 04:42:56 PM PDT 24 Jun 28 04:43:10 PM PDT 24 608262528 ps
T1062 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1023614333 Jun 28 04:42:26 PM PDT 24 Jun 28 04:42:35 PM PDT 24 234612995 ps
T1063 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.825230161 Jun 28 04:42:37 PM PDT 24 Jun 28 04:42:39 PM PDT 24 64038767 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1946666305 Jun 28 04:43:16 PM PDT 24 Jun 28 04:43:18 PM PDT 24 84537876 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1217879733 Jun 28 04:42:28 PM PDT 24 Jun 28 04:42:31 PM PDT 24 38041227 ps
T1066 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3675496510 Jun 28 04:43:26 PM PDT 24 Jun 28 04:43:28 PM PDT 24 40720135 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.241358065 Jun 28 04:43:18 PM PDT 24 Jun 28 04:43:21 PM PDT 24 13329450 ps
T1068 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2416893884 Jun 28 04:43:06 PM PDT 24 Jun 28 04:43:09 PM PDT 24 12199579 ps
T1069 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3399645903 Jun 28 04:42:40 PM PDT 24 Jun 28 04:42:41 PM PDT 24 16976467 ps
T1070 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3362207328 Jun 28 04:43:15 PM PDT 24 Jun 28 04:43:17 PM PDT 24 60352515 ps
T1071 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3397116957 Jun 28 04:42:28 PM PDT 24 Jun 28 04:42:30 PM PDT 24 38600064 ps
T1072 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2528677781 Jun 28 04:42:54 PM PDT 24 Jun 28 04:42:57 PM PDT 24 414607373 ps
T1073 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2866080970 Jun 28 04:42:54 PM PDT 24 Jun 28 04:42:56 PM PDT 24 33918453 ps
T1074 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.241566275 Jun 28 04:43:05 PM PDT 24 Jun 28 04:43:08 PM PDT 24 127638257 ps
T1075 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1533586236 Jun 28 04:43:08 PM PDT 24 Jun 28 04:43:13 PM PDT 24 296209725 ps
T1076 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1055836841 Jun 28 04:43:17 PM PDT 24 Jun 28 04:43:20 PM PDT 24 29816319 ps
T1077 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3475727320 Jun 28 04:43:16 PM PDT 24 Jun 28 04:43:18 PM PDT 24 16134285 ps
T147 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4281952175 Jun 28 04:42:57 PM PDT 24 Jun 28 04:43:05 PM PDT 24 469094380 ps
T1078 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3331782186 Jun 28 04:43:14 PM PDT 24 Jun 28 04:43:20 PM PDT 24 184987009 ps
T1079 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.549668808 Jun 28 04:43:19 PM PDT 24 Jun 28 04:43:21 PM PDT 24 27004627 ps
T1080 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1526268771 Jun 28 04:43:05 PM PDT 24 Jun 28 04:43:14 PM PDT 24 1381206449 ps
T1081 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1666487603 Jun 28 04:43:07 PM PDT 24 Jun 28 04:43:09 PM PDT 24 21827388 ps
T1082 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.949462764 Jun 28 04:43:21 PM PDT 24 Jun 28 04:43:25 PM PDT 24 110626583 ps
T1083 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3737704960 Jun 28 04:43:17 PM PDT 24 Jun 28 04:43:19 PM PDT 24 23293575 ps
T1084 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1790887606 Jun 28 04:42:56 PM PDT 24 Jun 28 04:42:58 PM PDT 24 25218312 ps
T1085 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2184458718 Jun 28 04:42:27 PM PDT 24 Jun 28 04:42:30 PM PDT 24 469391576 ps
T1086 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1523968206 Jun 28 04:43:26 PM PDT 24 Jun 28 04:43:28 PM PDT 24 11570567 ps
T1087 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.760224244 Jun 28 04:43:07 PM PDT 24 Jun 28 04:43:11 PM PDT 24 57414462 ps
T1088 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4266232068 Jun 28 04:43:10 PM PDT 24 Jun 28 04:43:13 PM PDT 24 58383149 ps
T1089 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2378010333 Jun 28 04:42:40 PM PDT 24 Jun 28 04:42:46 PM PDT 24 406270045 ps
T1090 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2239496044 Jun 28 04:43:16 PM PDT 24 Jun 28 04:43:18 PM PDT 24 24354272 ps

Test location /workspace/coverage/default/9.keymgr_stress_all.3178671067
Short name T1
Test name
Test status
Simulation time 2793401590 ps
CPU time 19.56 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 221916 kb
Host smart-7c830101-6af0-40dc-97b6-e191f516da5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178671067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3178671067
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3604994617
Short name T63
Test name
Test status
Simulation time 2017495520 ps
CPU time 26.83 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:49 PM PDT 24
Peak memory 222580 kb
Host smart-1b61c0c6-e600-4bc9-a5f1-62eb7aa82a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604994617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3604994617
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2006462766
Short name T62
Test name
Test status
Simulation time 2881428134 ps
CPU time 27.49 seconds
Started Jun 28 04:45:38 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 222744 kb
Host smart-1acfef5f-a034-4744-94e5-d9e30d59c5b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006462766 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2006462766
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2061655695
Short name T29
Test name
Test status
Simulation time 1389482385 ps
CPU time 15.89 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:37 PM PDT 24
Peak memory 222712 kb
Host smart-2d04734f-1aa1-4b70-9538-26a1b70d6cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061655695 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2061655695
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3132275827
Short name T12
Test name
Test status
Simulation time 1616259758 ps
CPU time 12.6 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 239148 kb
Host smart-d3ba2a83-0d3f-4faf-b872-04e66d4d4a37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132275827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3132275827
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1355571934
Short name T2
Test name
Test status
Simulation time 318855498 ps
CPU time 18.41 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 222676 kb
Host smart-202062a9-a691-4cb1-904e-eab6b5e5f54e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355571934 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1355571934
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2569286321
Short name T235
Test name
Test status
Simulation time 413469366 ps
CPU time 4.13 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 207196 kb
Host smart-3398e5fc-49c2-47e6-a7e8-081cc22c599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569286321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2569286321
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.516021186
Short name T8
Test name
Test status
Simulation time 226623675 ps
CPU time 2.83 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 209616 kb
Host smart-4bdc74f3-1457-4549-a0cb-8124bc66dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516021186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.516021186
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1859658065
Short name T128
Test name
Test status
Simulation time 635718666 ps
CPU time 17.75 seconds
Started Jun 28 04:45:48 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 214328 kb
Host smart-3919e866-7e2f-42f3-891d-048981219297
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859658065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1859658065
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.152904946
Short name T114
Test name
Test status
Simulation time 566010164 ps
CPU time 7.08 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:34 PM PDT 24
Peak memory 219948 kb
Host smart-353f4a87-01b3-4fa1-8678-069a00808c85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152904946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.152904946
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2431135108
Short name T5
Test name
Test status
Simulation time 234002564 ps
CPU time 4.34 seconds
Started Jun 28 04:44:32 PM PDT 24
Finished Jun 28 04:44:39 PM PDT 24
Peak memory 222356 kb
Host smart-a71182d4-0310-4adf-8d71-d39d507c62ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431135108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2431135108
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.946766205
Short name T83
Test name
Test status
Simulation time 11006706950 ps
CPU time 72.05 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 222548 kb
Host smart-e7dc8f35-901a-4438-ab9e-4994214976e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946766205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.946766205
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1400207828
Short name T362
Test name
Test status
Simulation time 2135868737 ps
CPU time 39.53 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 214484 kb
Host smart-12401d16-f775-46dd-b13d-d53530210d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400207828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1400207828
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4187303297
Short name T59
Test name
Test status
Simulation time 1303436348 ps
CPU time 34.25 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 221012 kb
Host smart-7c5824d7-adb3-43e6-9d1e-9f120d823f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187303297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4187303297
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3576425639
Short name T363
Test name
Test status
Simulation time 1597042832 ps
CPU time 10.04 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 214888 kb
Host smart-9bd7ca38-909a-4a70-932c-ef70c44134bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576425639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3576425639
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1008444411
Short name T27
Test name
Test status
Simulation time 325136621 ps
CPU time 8.7 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:14 PM PDT 24
Peak memory 214220 kb
Host smart-0e95a3b1-9209-4c23-9d27-84eb4b6ca25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008444411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1008444411
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3821042252
Short name T48
Test name
Test status
Simulation time 90338545 ps
CPU time 1.68 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:43 PM PDT 24
Peak memory 210068 kb
Host smart-8960fdf7-361f-43ff-994e-21e128d56226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821042252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3821042252
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4113810950
Short name T69
Test name
Test status
Simulation time 2653847938 ps
CPU time 52.32 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:47:10 PM PDT 24
Peak memory 220300 kb
Host smart-d389be4f-a42f-444f-8705-78ed9c391458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113810950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4113810950
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3386885463
Short name T228
Test name
Test status
Simulation time 2639660866 ps
CPU time 36.62 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 215680 kb
Host smart-ba248549-6eb8-4763-8393-bc52efd6c3cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386885463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3386885463
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1761225686
Short name T127
Test name
Test status
Simulation time 403595760 ps
CPU time 4.12 seconds
Started Jun 28 04:45:37 PM PDT 24
Finished Jun 28 04:45:41 PM PDT 24
Peak memory 214416 kb
Host smart-fa740aa1-d5d3-4a6f-b256-365dfa305d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761225686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1761225686
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.874527479
Short name T203
Test name
Test status
Simulation time 1844397236 ps
CPU time 42.66 seconds
Started Jun 28 04:46:42 PM PDT 24
Finished Jun 28 04:47:26 PM PDT 24
Peak memory 217272 kb
Host smart-c3341099-19ac-47f3-b45c-fcbf9a87a42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874527479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.874527479
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3300178206
Short name T46
Test name
Test status
Simulation time 733191315 ps
CPU time 7.03 seconds
Started Jun 28 04:46:48 PM PDT 24
Finished Jun 28 04:46:57 PM PDT 24
Peak memory 218296 kb
Host smart-9d13f94f-1489-4897-ac3b-ce0522687dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300178206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3300178206
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1637766496
Short name T25
Test name
Test status
Simulation time 48763293 ps
CPU time 1.77 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 222728 kb
Host smart-9463e445-7651-4103-a502-136a088c61a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637766496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1637766496
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.235632745
Short name T365
Test name
Test status
Simulation time 704944215 ps
CPU time 35.06 seconds
Started Jun 28 04:44:44 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 215532 kb
Host smart-930332a7-49ed-44b7-8302-17d24c83a0fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235632745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.235632745
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4276203802
Short name T160
Test name
Test status
Simulation time 79104082 ps
CPU time 3.85 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:47 PM PDT 24
Peak memory 218664 kb
Host smart-5245c097-43df-4176-b37f-c9f2b73137b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276203802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4276203802
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.768754197
Short name T95
Test name
Test status
Simulation time 204366791 ps
CPU time 5.36 seconds
Started Jun 28 04:45:09 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 222080 kb
Host smart-8732e892-506f-4e0a-ac0f-545b937e5725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768754197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.768754197
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1834835573
Short name T270
Test name
Test status
Simulation time 2009582724 ps
CPU time 30.31 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 215028 kb
Host smart-0e7d3b17-7985-4600-93f8-56bd08e8f774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834835573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1834835573
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3544629086
Short name T207
Test name
Test status
Simulation time 71270370 ps
CPU time 3.29 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 218408 kb
Host smart-e9d975cf-2cda-4ca2-b719-cf9c3b1fa1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544629086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3544629086
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2414853403
Short name T150
Test name
Test status
Simulation time 151787580 ps
CPU time 5.05 seconds
Started Jun 28 04:43:14 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 213648 kb
Host smart-94c38597-789b-40af-8676-7068aabbed20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414853403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2414853403
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2061459317
Short name T204
Test name
Test status
Simulation time 9745743577 ps
CPU time 27.12 seconds
Started Jun 28 04:46:24 PM PDT 24
Finished Jun 28 04:46:52 PM PDT 24
Peak memory 222772 kb
Host smart-26377fc5-67ea-4196-bc43-3c13fb12a24b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061459317 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2061459317
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1645917259
Short name T955
Test name
Test status
Simulation time 659372775 ps
CPU time 7.84 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:16 PM PDT 24
Peak memory 213916 kb
Host smart-6953d408-6b2f-49b1-9895-6044fb6e97f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645917259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1645917259
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1892503682
Short name T93
Test name
Test status
Simulation time 818959789 ps
CPU time 9.06 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:31 PM PDT 24
Peak memory 214284 kb
Host smart-72b85e5c-a2b1-4c63-ad8c-42a4201e7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892503682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1892503682
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1351956205
Short name T125
Test name
Test status
Simulation time 169524297 ps
CPU time 5.03 seconds
Started Jun 28 04:44:53 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 215120 kb
Host smart-5e53e7bf-797a-4e13-8ca2-40de711e7a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351956205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1351956205
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.703349838
Short name T224
Test name
Test status
Simulation time 1259263716 ps
CPU time 17.65 seconds
Started Jun 28 04:45:40 PM PDT 24
Finished Jun 28 04:45:58 PM PDT 24
Peak memory 214204 kb
Host smart-72466ef4-035c-4fc8-9661-cb8d2535b47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703349838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.703349838
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.461781100
Short name T423
Test name
Test status
Simulation time 37055890 ps
CPU time 0.75 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:23 PM PDT 24
Peak memory 205992 kb
Host smart-770523e0-7cf7-4e62-9940-4dc0dc061e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461781100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.461781100
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2320339537
Short name T56
Test name
Test status
Simulation time 2391061154 ps
CPU time 46.71 seconds
Started Jun 28 04:45:33 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 215192 kb
Host smart-ac6a859c-45e8-4aa1-af25-1f3a9853da2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320339537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2320339537
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2565326748
Short name T31
Test name
Test status
Simulation time 108134217 ps
CPU time 2.17 seconds
Started Jun 28 04:45:17 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 216988 kb
Host smart-cc07fe56-d5cc-4bf5-ba8b-ed5f1b90842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565326748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2565326748
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4006847853
Short name T103
Test name
Test status
Simulation time 221707960 ps
CPU time 5.09 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:45:59 PM PDT 24
Peak memory 215492 kb
Host smart-ac588682-ff17-4f19-a9e5-3795f5ef828c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006847853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4006847853
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.462195569
Short name T124
Test name
Test status
Simulation time 441498118 ps
CPU time 15.88 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 222620 kb
Host smart-31e1073b-3031-43fd-a6d0-9fba91c9bfda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462195569 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.462195569
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3395663201
Short name T146
Test name
Test status
Simulation time 399181901 ps
CPU time 7.05 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:29 PM PDT 24
Peak memory 213744 kb
Host smart-dfec52fa-4da8-492e-ad8c-02b587ccb671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395663201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3395663201
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3991039411
Short name T76
Test name
Test status
Simulation time 6066231728 ps
CPU time 28.73 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:53 PM PDT 24
Peak memory 222544 kb
Host smart-09028540-b76c-4ffb-baa9-94105e0d41eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991039411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3991039411
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2973062629
Short name T289
Test name
Test status
Simulation time 52034103400 ps
CPU time 86.65 seconds
Started Jun 28 04:46:23 PM PDT 24
Finished Jun 28 04:47:50 PM PDT 24
Peak memory 216744 kb
Host smart-6edb0f3c-5d04-4857-af5e-24c2541b1f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973062629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2973062629
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.525030772
Short name T43
Test name
Test status
Simulation time 640177321 ps
CPU time 4.02 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 214296 kb
Host smart-856ee00f-bce1-48fa-87fe-4009fbef5647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525030772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.525030772
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.72387543
Short name T332
Test name
Test status
Simulation time 3585340355 ps
CPU time 93.44 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 214952 kb
Host smart-4db5757c-87dc-489e-bd64-8b84f5ad89d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72387543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.72387543
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1645434889
Short name T303
Test name
Test status
Simulation time 301429981 ps
CPU time 4.05 seconds
Started Jun 28 04:46:04 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 214292 kb
Host smart-c94748d2-27b9-4376-a033-12af9dd093bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645434889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1645434889
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1019708798
Short name T141
Test name
Test status
Simulation time 297098673 ps
CPU time 8.24 seconds
Started Jun 28 04:43:09 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 213572 kb
Host smart-8b081d2b-fef8-4322-9dcd-f6b79a040442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019708798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1019708798
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2669850862
Short name T219
Test name
Test status
Simulation time 1943728133 ps
CPU time 18.06 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 215348 kb
Host smart-f9099a07-7ad9-426b-b372-d3e9808a0c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669850862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2669850862
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4070859433
Short name T179
Test name
Test status
Simulation time 1955267005 ps
CPU time 19.65 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:37 PM PDT 24
Peak memory 222388 kb
Host smart-7d290a57-9459-4762-aaa9-f6989340fd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070859433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4070859433
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3612549290
Short name T72
Test name
Test status
Simulation time 466123432 ps
CPU time 17.19 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:42 PM PDT 24
Peak memory 222604 kb
Host smart-fc80c425-039d-478a-9183-d0ccc9cb88fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612549290 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3612549290
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1147783421
Short name T498
Test name
Test status
Simulation time 117712815 ps
CPU time 3.4 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:43 PM PDT 24
Peak memory 209856 kb
Host smart-1d2a1ad9-97f1-488a-9af6-fdae86a03b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147783421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1147783421
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4166480262
Short name T28
Test name
Test status
Simulation time 115902435 ps
CPU time 4.75 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 218408 kb
Host smart-81351f04-9e26-44da-9670-3d0aff85cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166480262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4166480262
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.749342685
Short name T143
Test name
Test status
Simulation time 97675906 ps
CPU time 2.49 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:29 PM PDT 24
Peak memory 213564 kb
Host smart-8d9bf639-d239-48c2-b2cf-56d5c698b572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749342685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
749342685
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.4029965465
Short name T148
Test name
Test status
Simulation time 147192121 ps
CPU time 6.02 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:13 PM PDT 24
Peak memory 213620 kb
Host smart-d62c18fe-d1bc-4539-926a-f9c85f5e4848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029965465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.4029965465
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1037327928
Short name T24
Test name
Test status
Simulation time 140133704 ps
CPU time 1.95 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 210076 kb
Host smart-8017f217-c104-4bf5-81a8-22d97343b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037327928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1037327928
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.115176752
Short name T159
Test name
Test status
Simulation time 464568746 ps
CPU time 2.86 seconds
Started Jun 28 04:46:10 PM PDT 24
Finished Jun 28 04:46:14 PM PDT 24
Peak memory 216852 kb
Host smart-b98950bf-ed76-4e9f-940b-e27ef0ce61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115176752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.115176752
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2889124019
Short name T161
Test name
Test status
Simulation time 254868900 ps
CPU time 4.31 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 217704 kb
Host smart-7ac98434-db2c-42ba-bb61-83a7a77b3a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889124019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2889124019
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1261831608
Short name T357
Test name
Test status
Simulation time 65247564 ps
CPU time 2.27 seconds
Started Jun 28 04:44:24 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 214152 kb
Host smart-e20c71ad-9d78-4e3f-8dd2-2d2040405bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261831608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1261831608
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3250318108
Short name T231
Test name
Test status
Simulation time 187596517 ps
CPU time 3.1 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:44:59 PM PDT 24
Peak memory 219160 kb
Host smart-167bf82e-daa9-4d49-8045-817c89510337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250318108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3250318108
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3961203454
Short name T317
Test name
Test status
Simulation time 80804990 ps
CPU time 1.87 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:14 PM PDT 24
Peak memory 208772 kb
Host smart-19c4d30a-68db-4913-adfe-9bb0a9627db1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961203454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3961203454
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4244205799
Short name T352
Test name
Test status
Simulation time 55588086 ps
CPU time 3.73 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 214360 kb
Host smart-e49d7981-f053-472b-8451-dae2f7f0af21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244205799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4244205799
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4185882251
Short name T347
Test name
Test status
Simulation time 6779250372 ps
CPU time 44.29 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:46:01 PM PDT 24
Peak memory 208300 kb
Host smart-4c988b06-8344-4306-9f41-c7aea4d2291a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185882251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4185882251
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.209902249
Short name T218
Test name
Test status
Simulation time 923563041 ps
CPU time 30.18 seconds
Started Jun 28 04:45:35 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 215116 kb
Host smart-251d3a2e-55b2-43b9-9a8e-c66f58165d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209902249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.209902249
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4205067762
Short name T77
Test name
Test status
Simulation time 44789356483 ps
CPU time 484.43 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:54:08 PM PDT 24
Peak memory 220912 kb
Host smart-b5814827-1f39-408d-a0f2-6be43b0842c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205067762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4205067762
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.272995016
Short name T297
Test name
Test status
Simulation time 33845838 ps
CPU time 2.54 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 214740 kb
Host smart-49e3faaf-9510-4f73-97f4-5bdc7ed0c947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272995016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.272995016
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3944874385
Short name T417
Test name
Test status
Simulation time 543799038 ps
CPU time 8.29 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:44:42 PM PDT 24
Peak memory 215204 kb
Host smart-834011e6-3c6e-48c1-be87-ed6548e3b8b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944874385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3944874385
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1668236703
Short name T64
Test name
Test status
Simulation time 208424246 ps
CPU time 3.93 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 210288 kb
Host smart-db1fd8fd-293c-44c9-9694-e3baa8be1cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668236703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1668236703
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1799392265
Short name T162
Test name
Test status
Simulation time 94093209 ps
CPU time 3.59 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 217724 kb
Host smart-7a7948c5-59df-42c9-ab55-40ec4bed4fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799392265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1799392265
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.198701860
Short name T163
Test name
Test status
Simulation time 114221008 ps
CPU time 3.02 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:26 PM PDT 24
Peak memory 216744 kb
Host smart-b72e3d50-6ccd-44df-bac3-96cfac295250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198701860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.198701860
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2041639656
Short name T4
Test name
Test status
Simulation time 1113824923 ps
CPU time 11.01 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:32 PM PDT 24
Peak memory 219496 kb
Host smart-41051e4f-4e33-44b8-bd1d-04b77976016f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041639656 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2041639656
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3508691348
Short name T266
Test name
Test status
Simulation time 84440293 ps
CPU time 1.63 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:06 PM PDT 24
Peak memory 214228 kb
Host smart-145944aa-f135-4de0-a9f4-3af9b6846fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508691348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3508691348
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3226550600
Short name T281
Test name
Test status
Simulation time 156715653 ps
CPU time 3.83 seconds
Started Jun 28 04:45:19 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 214256 kb
Host smart-78857864-cf0a-4ed1-bfaf-f4426c54fae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226550600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3226550600
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.49589943
Short name T175
Test name
Test status
Simulation time 183280517 ps
CPU time 5.01 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:36 PM PDT 24
Peak memory 208064 kb
Host smart-011adaed-9224-4006-ba25-0d046eebe2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49589943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.49589943
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.971886766
Short name T249
Test name
Test status
Simulation time 103439370 ps
CPU time 4.08 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 214840 kb
Host smart-8787d6f5-8ca1-4af7-9901-76689a19b4dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971886766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.971886766
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3876506822
Short name T7
Test name
Test status
Simulation time 668507561 ps
CPU time 27.26 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 214896 kb
Host smart-1bdcda5a-d7ba-4b82-8332-8bab7e89b278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876506822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3876506822
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.361381439
Short name T55
Test name
Test status
Simulation time 142466439 ps
CPU time 2.79 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:58 PM PDT 24
Peak memory 214268 kb
Host smart-da0c10e7-4648-4619-bfd6-dd0be9dc68ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361381439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.361381439
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2418365822
Short name T154
Test name
Test status
Simulation time 810626138 ps
CPU time 6.13 seconds
Started Jun 28 04:43:14 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 205568 kb
Host smart-c7550e2f-2d38-40af-8826-d2ea29e722b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418365822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2418365822
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1891874190
Short name T151
Test name
Test status
Simulation time 176185704 ps
CPU time 4.88 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:25 PM PDT 24
Peak memory 213640 kb
Host smart-d0d2c499-fe37-4282-9df1-52785216e12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891874190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1891874190
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3461789869
Short name T145
Test name
Test status
Simulation time 421593598 ps
CPU time 3.83 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:02 PM PDT 24
Peak memory 213696 kb
Host smart-8bda5cbb-4d40-4fd9-b98a-231f47e25684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461789869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3461789869
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1943823602
Short name T51
Test name
Test status
Simulation time 273778416 ps
CPU time 7.16 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:37 PM PDT 24
Peak memory 233380 kb
Host smart-3ab191cb-3237-4753-8dd1-14a55dda5d25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943823602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1943823602
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3272193929
Short name T13
Test name
Test status
Simulation time 559160981 ps
CPU time 17.48 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:49 PM PDT 24
Peak memory 234660 kb
Host smart-19ca2a06-6bad-4da6-98d3-648c8157140f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272193929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3272193929
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1675599317
Short name T153
Test name
Test status
Simulation time 524520145 ps
CPU time 7.31 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:27 PM PDT 24
Peak memory 205536 kb
Host smart-fb893890-bfac-4314-b407-c6f5a95f95b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675599317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1675599317
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2097881131
Short name T304
Test name
Test status
Simulation time 97547263 ps
CPU time 2.11 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 216816 kb
Host smart-5a22f538-eaa5-4b99-811a-b5d373bccf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097881131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2097881131
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.1558575685
Short name T751
Test name
Test status
Simulation time 660754772 ps
CPU time 8.89 seconds
Started Jun 28 04:44:10 PM PDT 24
Finished Jun 28 04:44:22 PM PDT 24
Peak memory 209620 kb
Host smart-1a53e261-e536-4618-8fff-6076951358dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558575685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1558575685
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2431076795
Short name T323
Test name
Test status
Simulation time 830759421 ps
CPU time 5.37 seconds
Started Jun 28 04:44:17 PM PDT 24
Finished Jun 28 04:44:26 PM PDT 24
Peak memory 207408 kb
Host smart-8f0de717-7f5b-4389-bdd9-346fd88e2039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431076795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2431076795
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.750413209
Short name T78
Test name
Test status
Simulation time 226345755 ps
CPU time 5.26 seconds
Started Jun 28 04:45:00 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 222252 kb
Host smart-cb89f962-2097-4b1d-8e70-12a4cbb75b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750413209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.750413209
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1161446148
Short name T388
Test name
Test status
Simulation time 1097154531 ps
CPU time 2.72 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 210248 kb
Host smart-3a3c7d0f-8c1f-43d1-881c-6d7ce7f1f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161446148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1161446148
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2408499258
Short name T682
Test name
Test status
Simulation time 116769939 ps
CPU time 3.03 seconds
Started Jun 28 04:45:02 PM PDT 24
Finished Jun 28 04:45:06 PM PDT 24
Peak memory 208448 kb
Host smart-360cb719-f2d3-43f8-9b68-7338aa50a34e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408499258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2408499258
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1493770255
Short name T262
Test name
Test status
Simulation time 321872679 ps
CPU time 4.22 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 208492 kb
Host smart-dc5c5185-9888-4594-bd34-3b73da90514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493770255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1493770255
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2738887040
Short name T275
Test name
Test status
Simulation time 801500177 ps
CPU time 7.12 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 208140 kb
Host smart-afca5451-9c50-4dd6-a639-236ebdaf3e9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738887040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2738887040
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1048470135
Short name T217
Test name
Test status
Simulation time 204579335 ps
CPU time 4.07 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 214596 kb
Host smart-ca46a63b-97e1-4f23-8a80-54b666fb696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048470135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1048470135
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3632534158
Short name T214
Test name
Test status
Simulation time 174873821 ps
CPU time 6.63 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:25 PM PDT 24
Peak memory 214224 kb
Host smart-e7662d5d-d46f-4505-9c23-7e6d902a0bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632534158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3632534158
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2626938102
Short name T65
Test name
Test status
Simulation time 1114489316 ps
CPU time 15.95 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:45 PM PDT 24
Peak memory 222284 kb
Host smart-c5f32748-a6f6-4a3a-b1fb-8210497265b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626938102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2626938102
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2605086117
Short name T174
Test name
Test status
Simulation time 453570303 ps
CPU time 9.47 seconds
Started Jun 28 04:45:40 PM PDT 24
Finished Jun 28 04:45:50 PM PDT 24
Peak memory 209260 kb
Host smart-d2a0ad29-4858-49f1-82e9-6547c1b16d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605086117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2605086117
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2944189306
Short name T240
Test name
Test status
Simulation time 1034841120 ps
CPU time 8.36 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 214304 kb
Host smart-c67b2dd2-60b1-4e0f-a07b-8d80f8dfdeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944189306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2944189306
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2464026254
Short name T107
Test name
Test status
Simulation time 44673563 ps
CPU time 2.37 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:46 PM PDT 24
Peak memory 214224 kb
Host smart-05a62d9c-2f16-448f-8b7d-8f563caa1253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464026254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2464026254
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2372347642
Short name T282
Test name
Test status
Simulation time 40945164 ps
CPU time 3.1 seconds
Started Jun 28 04:46:42 PM PDT 24
Finished Jun 28 04:46:45 PM PDT 24
Peak memory 214840 kb
Host smart-2bb2aa0c-35b7-41a2-ab73-403c758bb195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372347642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2372347642
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2417643691
Short name T356
Test name
Test status
Simulation time 7455347768 ps
CPU time 77.24 seconds
Started Jun 28 04:44:42 PM PDT 24
Finished Jun 28 04:46:02 PM PDT 24
Peak memory 222460 kb
Host smart-802ba49a-cdcb-4726-b7f6-9d10a09fad41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417643691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2417643691
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2534800452
Short name T213
Test name
Test status
Simulation time 1285463812 ps
CPU time 9.9 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:50 PM PDT 24
Peak memory 214308 kb
Host smart-0dd27712-faf4-40a7-ad00-0db22bf0935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534800452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2534800452
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1023614333
Short name T1062
Test name
Test status
Simulation time 234612995 ps
CPU time 7.54 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 205592 kb
Host smart-87d00272-f8ef-4264-9f0c-9b8a81a6c1e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023614333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
023614333
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2506996800
Short name T942
Test name
Test status
Simulation time 643270474 ps
CPU time 16.35 seconds
Started Jun 28 04:42:29 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 205416 kb
Host smart-5f0cb3de-e67e-43ac-a8bd-ea1ca3fbd273
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506996800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
506996800
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1381361932
Short name T1048
Test name
Test status
Simulation time 32302656 ps
CPU time 1.11 seconds
Started Jun 28 04:42:30 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 205372 kb
Host smart-1e00a633-ffb7-4fd1-a49f-18b2edec30b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381361932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
381361932
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2146709772
Short name T968
Test name
Test status
Simulation time 52049401 ps
CPU time 1.18 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:28 PM PDT 24
Peak memory 213652 kb
Host smart-83569f41-a70e-4891-8a3b-8efaa7de2f04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146709772 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2146709772
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1829363927
Short name T953
Test name
Test status
Simulation time 70289286 ps
CPU time 0.94 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:29 PM PDT 24
Peak memory 205356 kb
Host smart-46fc54b3-02df-4ecd-a3d6-c80c474a7001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829363927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1829363927
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.90045783
Short name T1055
Test name
Test status
Simulation time 32404908 ps
CPU time 0.84 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:28 PM PDT 24
Peak memory 205380 kb
Host smart-83848d03-9812-4162-8875-2393cfbe7e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90045783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.90045783
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3388067572
Short name T972
Test name
Test status
Simulation time 242629100 ps
CPU time 2.9 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 205484 kb
Host smart-f2d45b0a-5d85-41d6-83d2-f164bb432c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388067572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3388067572
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3837372486
Short name T984
Test name
Test status
Simulation time 120411946 ps
CPU time 3.58 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 214000 kb
Host smart-409a7bd8-076b-4c3a-80d7-3ab833026e31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837372486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3837372486
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2184458718
Short name T1085
Test name
Test status
Simulation time 469391576 ps
CPU time 2.26 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 213696 kb
Host smart-540d16b9-3d09-4b1e-a54c-9d6d99b461eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184458718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2184458718
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.692011455
Short name T970
Test name
Test status
Simulation time 143350939 ps
CPU time 5.93 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 205376 kb
Host smart-4bb28110-5d42-44a0-bf75-289d9f40df57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692011455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
692011455
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4185706998
Short name T957
Test name
Test status
Simulation time 1128838353 ps
CPU time 9.19 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:37 PM PDT 24
Peak memory 205596 kb
Host smart-c17c6b8a-3ec9-4337-846b-de41131f910d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185706998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
185706998
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1215806380
Short name T1051
Test name
Test status
Simulation time 7122901437 ps
CPU time 24.73 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:52 PM PDT 24
Peak memory 205616 kb
Host smart-85896ec6-c62e-43b9-98c8-63035af564a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215806380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
215806380
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3448432856
Short name T950
Test name
Test status
Simulation time 163150615 ps
CPU time 1.17 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 205316 kb
Host smart-4451738e-de14-4164-b56c-30df2a68aa86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448432856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
448432856
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3708924347
Short name T940
Test name
Test status
Simulation time 45023984 ps
CPU time 2.02 seconds
Started Jun 28 04:42:30 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 213672 kb
Host smart-456a8417-6224-4410-b9bc-5a0b8e905300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708924347 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3708924347
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1054187909
Short name T137
Test name
Test status
Simulation time 109863221 ps
CPU time 1.58 seconds
Started Jun 28 04:42:29 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 205388 kb
Host smart-49f741ef-3e88-4c99-a0b5-27e9035bffa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054187909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1054187909
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1984119698
Short name T965
Test name
Test status
Simulation time 30467700 ps
CPU time 0.66 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:28 PM PDT 24
Peak memory 205204 kb
Host smart-68dd37e8-83fc-4fca-ab66-1528d3c59080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984119698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1984119698
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3950129994
Short name T135
Test name
Test status
Simulation time 104783470 ps
CPU time 4.03 seconds
Started Jun 28 04:42:30 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 205412 kb
Host smart-4f9769c3-d64c-4804-b5af-c896345fe6a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950129994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3950129994
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1008819012
Short name T978
Test name
Test status
Simulation time 319921028 ps
CPU time 2.33 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:31 PM PDT 24
Peak memory 213980 kb
Host smart-295c2392-2870-4695-bc97-667364c6d655
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008819012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1008819012
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2918637671
Short name T1054
Test name
Test status
Simulation time 402029302 ps
CPU time 8.64 seconds
Started Jun 28 04:42:25 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 213812 kb
Host smart-48fff54d-7b7d-4e88-95b8-f563fa45e5e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918637671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2918637671
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1217879733
Short name T1065
Test name
Test status
Simulation time 38041227 ps
CPU time 2.74 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:31 PM PDT 24
Peak memory 213768 kb
Host smart-5d8a8869-3527-47fe-afed-bab5079ca0e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217879733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1217879733
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2947576532
Short name T1042
Test name
Test status
Simulation time 403975106 ps
CPU time 1.61 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 213656 kb
Host smart-06dde6b1-33ef-4605-8c24-41509bf844ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947576532 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2947576532
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2416893884
Short name T1068
Test name
Test status
Simulation time 12199579 ps
CPU time 1.1 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 205416 kb
Host smart-c59238eb-c9a9-44ce-a74d-8bde7e01856d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416893884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2416893884
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2965174136
Short name T1041
Test name
Test status
Simulation time 40388551 ps
CPU time 0.71 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:06 PM PDT 24
Peak memory 205208 kb
Host smart-9eb7f50d-bd40-420f-bcb0-8562fd3969bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965174136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2965174136
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.241566275
Short name T1074
Test name
Test status
Simulation time 127638257 ps
CPU time 2.42 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 205492 kb
Host smart-5c33994d-7fb2-4496-81ad-42b29163f6f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241566275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.241566275
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.255627186
Short name T979
Test name
Test status
Simulation time 249474352 ps
CPU time 2.41 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 214008 kb
Host smart-6f3a5f4b-298c-491c-b51e-5dd5d3e00b64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255627186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.255627186
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3095794779
Short name T993
Test name
Test status
Simulation time 105473921 ps
CPU time 3.57 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:13 PM PDT 24
Peak memory 213632 kb
Host smart-f5262c32-0063-4de8-8585-74edae464b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095794779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3095794779
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1054436223
Short name T152
Test name
Test status
Simulation time 461972464 ps
CPU time 4.82 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 214736 kb
Host smart-d6141d69-1902-4b2a-94aa-bd4eb3cc60b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054436223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1054436223
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.564753979
Short name T935
Test name
Test status
Simulation time 27822276 ps
CPU time 1.17 seconds
Started Jun 28 04:43:03 PM PDT 24
Finished Jun 28 04:43:05 PM PDT 24
Peak memory 205384 kb
Host smart-38b079d0-947a-46d8-ba01-7475d33c66cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564753979 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.564753979
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3658056341
Short name T1033
Test name
Test status
Simulation time 50496651 ps
CPU time 1.22 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 205436 kb
Host smart-fa44333a-5dc7-442e-8d36-ca60cb7793ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658056341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3658056341
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1666487603
Short name T1081
Test name
Test status
Simulation time 21827388 ps
CPU time 0.98 seconds
Started Jun 28 04:43:07 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 205400 kb
Host smart-c7809bcd-5cd1-45f7-8098-2319c4edc68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666487603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1666487603
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3562371445
Short name T1056
Test name
Test status
Simulation time 40783877 ps
CPU time 1.94 seconds
Started Jun 28 04:43:04 PM PDT 24
Finished Jun 28 04:43:06 PM PDT 24
Peak memory 213696 kb
Host smart-8aaa11ce-7785-4025-9fb4-cb2d8248cb95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562371445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3562371445
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1418131825
Short name T966
Test name
Test status
Simulation time 193933328 ps
CPU time 5.02 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 213940 kb
Host smart-44f2c689-adc7-46ef-87b8-1adf94187b11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418131825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1418131825
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3195900223
Short name T1012
Test name
Test status
Simulation time 295867308 ps
CPU time 3.88 seconds
Started Jun 28 04:43:07 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 219928 kb
Host smart-7bc3b39d-fed4-4253-ad37-a167b4b5fbc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195900223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3195900223
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2404734009
Short name T986
Test name
Test status
Simulation time 71210958 ps
CPU time 1.97 seconds
Started Jun 28 04:43:04 PM PDT 24
Finished Jun 28 04:43:07 PM PDT 24
Peak memory 213744 kb
Host smart-ac4faaf9-97a7-44d9-93d3-53518c3ee4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404734009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2404734009
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1721450706
Short name T158
Test name
Test status
Simulation time 151725527 ps
CPU time 5.17 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 214652 kb
Host smart-ac04668d-e214-45f3-8745-f60d47c47e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721450706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1721450706
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3921489203
Short name T1000
Test name
Test status
Simulation time 119150604 ps
CPU time 2.13 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 213736 kb
Host smart-3c6100f4-858b-4e1c-87a3-fde211808912
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921489203 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3921489203
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3173228492
Short name T1005
Test name
Test status
Simulation time 19575131 ps
CPU time 1.26 seconds
Started Jun 28 04:43:09 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 205316 kb
Host smart-932fcc81-6450-4f7d-956a-5837064c143f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173228492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3173228492
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1190123711
Short name T1036
Test name
Test status
Simulation time 10620167 ps
CPU time 0.69 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 205280 kb
Host smart-3a3adfc9-a181-4522-af09-b7817d94166c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190123711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1190123711
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.760224244
Short name T1087
Test name
Test status
Simulation time 57414462 ps
CPU time 2.54 seconds
Started Jun 28 04:43:07 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 205412 kb
Host smart-e45de4ec-8811-4528-8867-b39c1925504e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760224244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.760224244
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2087092824
Short name T969
Test name
Test status
Simulation time 263780067 ps
CPU time 1.7 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 213804 kb
Host smart-e94a5a2d-ab7d-470b-9022-2b334d75565d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087092824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2087092824
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1533586236
Short name T1075
Test name
Test status
Simulation time 296209725 ps
CPU time 4.38 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:13 PM PDT 24
Peak memory 214056 kb
Host smart-0982309c-04a1-45ce-9f4a-f65c7cc68554
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533586236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1533586236
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2864297250
Short name T934
Test name
Test status
Simulation time 80922284 ps
CPU time 2.36 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 213616 kb
Host smart-6d96b501-733e-413d-9f54-bd7f225dddc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864297250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2864297250
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.327285097
Short name T941
Test name
Test status
Simulation time 31036418 ps
CPU time 1.59 seconds
Started Jun 28 04:43:10 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 205412 kb
Host smart-b19d8d9e-bf48-4c3d-afa6-7b83313aa4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327285097 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.327285097
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1112084511
Short name T1019
Test name
Test status
Simulation time 183999141 ps
CPU time 1.77 seconds
Started Jun 28 04:43:10 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 205144 kb
Host smart-f2c00375-a7f3-4d40-b2e8-9dd912005c01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112084511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1112084511
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3738389986
Short name T930
Test name
Test status
Simulation time 15414600 ps
CPU time 0.77 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 205308 kb
Host smart-28ba33da-2046-4234-bf8a-69d5a1e63fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738389986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3738389986
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4266232068
Short name T1088
Test name
Test status
Simulation time 58383149 ps
CPU time 2.55 seconds
Started Jun 28 04:43:10 PM PDT 24
Finished Jun 28 04:43:13 PM PDT 24
Peak memory 205112 kb
Host smart-0608803d-5417-47f7-808c-195ab456ad8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266232068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4266232068
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.96974705
Short name T973
Test name
Test status
Simulation time 241173822 ps
CPU time 1.61 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 214120 kb
Host smart-99ea2c1e-c78d-4dcf-afe4-5f909d9d2d30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96974705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow
_reg_errors.96974705
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1526268771
Short name T1080
Test name
Test status
Simulation time 1381206449 ps
CPU time 8.69 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:14 PM PDT 24
Peak memory 220096 kb
Host smart-1755cf5b-554d-4693-a6ae-4a977a0af009
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526268771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1526268771
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1511013629
Short name T1029
Test name
Test status
Simulation time 308934343 ps
CPU time 4 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:13 PM PDT 24
Peak memory 216324 kb
Host smart-1a52d89d-7a8d-4aec-80a1-8bdab68bebf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511013629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1511013629
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.481597711
Short name T948
Test name
Test status
Simulation time 94358150 ps
CPU time 1.32 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 205452 kb
Host smart-7fefecea-c00f-4b9a-9a37-42a3b2d881c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481597711 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.481597711
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.241358065
Short name T1067
Test name
Test status
Simulation time 13329450 ps
CPU time 1.08 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 205492 kb
Host smart-c3a2ab66-fced-4162-9f79-81a12b4d505e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241358065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.241358065
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.515104533
Short name T931
Test name
Test status
Simulation time 44721560 ps
CPU time 0.73 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 205212 kb
Host smart-94386403-d1b9-4c32-b4bf-c29170fb7b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515104533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.515104533
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3767861994
Short name T139
Test name
Test status
Simulation time 215294627 ps
CPU time 1.97 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 205500 kb
Host smart-38595ffc-4eac-4f20-a7e4-e45091b6a3fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767861994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3767861994
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4078953297
Short name T116
Test name
Test status
Simulation time 284540515 ps
CPU time 2.38 seconds
Started Jun 28 04:43:09 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 214008 kb
Host smart-9cda6ae9-71ee-4209-b375-57244ca3b39b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078953297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4078953297
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.659415473
Short name T958
Test name
Test status
Simulation time 272548492 ps
CPU time 5.71 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:15 PM PDT 24
Peak memory 213840 kb
Host smart-7cbee8df-b19f-4917-8da8-c319377e6c1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659415473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.659415473
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.388242345
Short name T954
Test name
Test status
Simulation time 114629500 ps
CPU time 1.87 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 213712 kb
Host smart-71130a42-83fc-47d0-81c5-af41b02400ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388242345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.388242345
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.949462764
Short name T1082
Test name
Test status
Simulation time 110626583 ps
CPU time 2.01 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:25 PM PDT 24
Peak memory 221828 kb
Host smart-dfa18573-2fa3-494a-87e8-588151f2bb9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949462764 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.949462764
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2262271652
Short name T1022
Test name
Test status
Simulation time 119852169 ps
CPU time 1.17 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 205416 kb
Host smart-2b5649b8-9ce4-48ae-9f70-9583b42d5d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262271652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2262271652
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3182940270
Short name T959
Test name
Test status
Simulation time 19291639 ps
CPU time 0.74 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 205268 kb
Host smart-b2c05476-f4c0-4923-bc35-e2f08bdab606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182940270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3182940270
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3362207328
Short name T1070
Test name
Test status
Simulation time 60352515 ps
CPU time 1.78 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:17 PM PDT 24
Peak memory 205468 kb
Host smart-305af2c8-7994-4440-b6aa-af180272dc9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362207328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3362207328
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3477201984
Short name T1058
Test name
Test status
Simulation time 166252967 ps
CPU time 1.8 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:17 PM PDT 24
Peak memory 214008 kb
Host smart-fe396a40-6972-453d-b11c-dbd9ea0b3ce4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477201984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3477201984
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3331782186
Short name T1078
Test name
Test status
Simulation time 184987009 ps
CPU time 4.77 seconds
Started Jun 28 04:43:14 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 220408 kb
Host smart-14baffd4-3a11-4c59-86cf-540c4a78fe92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331782186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3331782186
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3024429450
Short name T1034
Test name
Test status
Simulation time 643600494 ps
CPU time 2.7 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 213764 kb
Host smart-c2411123-c322-49ea-8ab5-4dd73daa139b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024429450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3024429450
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1183588011
Short name T1040
Test name
Test status
Simulation time 106135716 ps
CPU time 1.51 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 205472 kb
Host smart-b06ab98d-3715-4a3d-bc84-b6635b2864dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183588011 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1183588011
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2162474321
Short name T133
Test name
Test status
Simulation time 107383487 ps
CPU time 1.23 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 205448 kb
Host smart-2ed85db6-7052-4925-a229-1c15aa15a76b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162474321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2162474321
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1907430159
Short name T1045
Test name
Test status
Simulation time 11937655 ps
CPU time 0.71 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 205268 kb
Host smart-ee92ad51-a484-4b06-a2f1-33438d94c830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907430159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1907430159
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3921353129
Short name T983
Test name
Test status
Simulation time 252318182 ps
CPU time 1.37 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 205516 kb
Host smart-45b35324-a937-48d9-890b-1d6ce9a9b999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921353129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3921353129
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3222089083
Short name T118
Test name
Test status
Simulation time 202965511 ps
CPU time 5.44 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 213916 kb
Host smart-68d6051d-6113-4aac-a696-2f82d8a6ccea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222089083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3222089083
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2726040210
Short name T962
Test name
Test status
Simulation time 396726810 ps
CPU time 13.92 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:30 PM PDT 24
Peak memory 213912 kb
Host smart-c7933b1a-b06c-4177-9d17-b452c7a7dc79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726040210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2726040210
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1703161882
Short name T1057
Test name
Test status
Simulation time 59426171 ps
CPU time 2.25 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:22 PM PDT 24
Peak memory 213784 kb
Host smart-493afadc-e1d1-4aba-90ed-755f2c0a6001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703161882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1703161882
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.966318365
Short name T998
Test name
Test status
Simulation time 27531441 ps
CPU time 1.48 seconds
Started Jun 28 04:43:19 PM PDT 24
Finished Jun 28 04:43:22 PM PDT 24
Peak memory 213684 kb
Host smart-620dd133-9008-4e0e-a8bf-d9ed209a063c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966318365 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.966318365
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1946666305
Short name T1064
Test name
Test status
Simulation time 84537876 ps
CPU time 1.17 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 205516 kb
Host smart-39d31fd9-f543-4e42-8a4a-c601fc7ac2ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946666305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1946666305
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.829433534
Short name T994
Test name
Test status
Simulation time 9858826 ps
CPU time 0.83 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:19 PM PDT 24
Peak memory 205388 kb
Host smart-8cc7ea3c-5041-419d-b3bf-d60369d9439e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829433534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.829433534
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1137858708
Short name T134
Test name
Test status
Simulation time 55504928 ps
CPU time 2.4 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 205488 kb
Host smart-b79b8ccd-0f86-438f-ad71-7ec793c06b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137858708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1137858708
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4033477986
Short name T960
Test name
Test status
Simulation time 57098269 ps
CPU time 1.82 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 213852 kb
Host smart-41a8c9b0-2b4e-4a71-8316-732b48d0040a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033477986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4033477986
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4152558603
Short name T952
Test name
Test status
Simulation time 1997528525 ps
CPU time 6.83 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:25 PM PDT 24
Peak memory 213764 kb
Host smart-ea6ff12a-68e5-462d-81d5-804570af543d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152558603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4152558603
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1664954817
Short name T985
Test name
Test status
Simulation time 345499105 ps
CPU time 3.43 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 213752 kb
Host smart-91c451ff-9c43-4e1a-9a74-032ea1b5a7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664954817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1664954817
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2481104087
Short name T149
Test name
Test status
Simulation time 167733406 ps
CPU time 5.76 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:26 PM PDT 24
Peak memory 213620 kb
Host smart-bf58a79b-8df2-48b3-b125-34db86d1bfee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481104087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2481104087
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2493013716
Short name T1049
Test name
Test status
Simulation time 318664284 ps
CPU time 1.57 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 205544 kb
Host smart-74e99e8c-d47a-406b-bc39-94ed66eae036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493013716 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2493013716
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3415893871
Short name T967
Test name
Test status
Simulation time 33050296 ps
CPU time 1 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:19 PM PDT 24
Peak memory 205316 kb
Host smart-0c432001-873c-4082-9280-049acefa88ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415893871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3415893871
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3066203438
Short name T971
Test name
Test status
Simulation time 8671482 ps
CPU time 0.73 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:19 PM PDT 24
Peak memory 205384 kb
Host smart-2d2dbbf4-047a-4341-9c4d-254dd01a93b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066203438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3066203438
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3928419599
Short name T131
Test name
Test status
Simulation time 138557641 ps
CPU time 2.13 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:25 PM PDT 24
Peak memory 205456 kb
Host smart-dab2ff2c-f02f-4b44-8c4c-918fc89c9b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928419599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3928419599
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2298912648
Short name T1030
Test name
Test status
Simulation time 123667971 ps
CPU time 2.04 seconds
Started Jun 28 04:43:19 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 213936 kb
Host smart-4d0aa89c-f66e-47fc-afea-acd104dedde0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298912648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2298912648
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2873840064
Short name T1004
Test name
Test status
Simulation time 315237863 ps
CPU time 6.3 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 213912 kb
Host smart-ca4ee299-6179-4483-891d-3998c2cdbed9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873840064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2873840064
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4269962414
Short name T999
Test name
Test status
Simulation time 39914633 ps
CPU time 2.65 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 213756 kb
Host smart-8f1fc366-89ad-4f67-b2e8-7d1713f803eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269962414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.4269962414
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1068237550
Short name T932
Test name
Test status
Simulation time 34108666 ps
CPU time 2.02 seconds
Started Jun 28 04:43:19 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 214008 kb
Host smart-1c931e2b-93af-44c5-b10d-3e9be13778fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068237550 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1068237550
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1055836841
Short name T1076
Test name
Test status
Simulation time 29816319 ps
CPU time 1.3 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 205444 kb
Host smart-39890385-2f7e-4592-a670-ffc41bb88b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055836841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1055836841
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2239496044
Short name T1090
Test name
Test status
Simulation time 24354272 ps
CPU time 0.87 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 205288 kb
Host smart-873b181d-3ecd-4664-a2b0-da50406dbec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239496044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2239496044
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4182658613
Short name T1053
Test name
Test status
Simulation time 439065490 ps
CPU time 4.2 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:26 PM PDT 24
Peak memory 205760 kb
Host smart-80ef62b7-f920-4051-ac9b-f7b0b35cf9c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182658613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4182658613
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2156328555
Short name T976
Test name
Test status
Simulation time 144511679 ps
CPU time 2.42 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 213912 kb
Host smart-1c783013-82f0-4374-8333-53529f2b2528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156328555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2156328555
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4215465421
Short name T1023
Test name
Test status
Simulation time 266575912 ps
CPU time 7.19 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 219888 kb
Host smart-bf1700de-9aae-4505-8042-e945bcc6998d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215465421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4215465421
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2795654733
Short name T991
Test name
Test status
Simulation time 146505660 ps
CPU time 3.26 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 213632 kb
Host smart-af2be06a-5098-4f4f-b6fb-29cbe0b66e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795654733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2795654733
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4211499043
Short name T132
Test name
Test status
Simulation time 807882873 ps
CPU time 4.77 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 205492 kb
Host smart-65127b15-566b-4b6e-a8c9-4457b846f15d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211499043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
211499043
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3111476474
Short name T936
Test name
Test status
Simulation time 544241067 ps
CPU time 14.45 seconds
Started Jun 28 04:42:25 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 205548 kb
Host smart-d897c2c6-954f-4baa-bd95-02a9bc01d6f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111476474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
111476474
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3750731789
Short name T1043
Test name
Test status
Simulation time 22539027 ps
CPU time 0.93 seconds
Started Jun 28 04:42:25 PM PDT 24
Finished Jun 28 04:42:27 PM PDT 24
Peak memory 205356 kb
Host smart-43f3e0ce-9abc-46ed-9855-b912276e16ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750731789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
750731789
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.657492565
Short name T1035
Test name
Test status
Simulation time 287625650 ps
CPU time 1.66 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:42 PM PDT 24
Peak memory 213876 kb
Host smart-a54c398b-65e8-4c1f-9c8c-2b42ca1eaa62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657492565 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.657492565
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1498837350
Short name T947
Test name
Test status
Simulation time 26567762 ps
CPU time 0.87 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 205348 kb
Host smart-3d4e7c9c-6975-488f-9d36-cdf2eb86dc19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498837350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1498837350
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3397116957
Short name T1071
Test name
Test status
Simulation time 38600064 ps
CPU time 0.75 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 205276 kb
Host smart-db0a888d-461b-4751-a354-fea2ad820c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397116957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3397116957
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2663770324
Short name T1006
Test name
Test status
Simulation time 110271906 ps
CPU time 1.62 seconds
Started Jun 28 04:42:28 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 205288 kb
Host smart-8817f1ea-3854-4275-8b41-88b8599686b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663770324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2663770324
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1597129529
Short name T119
Test name
Test status
Simulation time 156929072 ps
CPU time 4.69 seconds
Started Jun 28 04:42:25 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 218092 kb
Host smart-eed695e2-948c-4b38-acbc-7b1a0bd5cebb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597129529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1597129529
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2430781948
Short name T1017
Test name
Test status
Simulation time 182590821 ps
CPU time 4.06 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 219856 kb
Host smart-5e1029e6-a0bc-46ab-b0c3-fff2ea6ee231
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430781948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2430781948
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1008665267
Short name T170
Test name
Test status
Simulation time 298079378 ps
CPU time 3.38 seconds
Started Jun 28 04:42:24 PM PDT 24
Finished Jun 28 04:42:28 PM PDT 24
Peak memory 216764 kb
Host smart-9fd9d033-f8ba-432a-b437-067b0f9f58d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008665267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1008665267
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2979934701
Short name T156
Test name
Test status
Simulation time 393077185 ps
CPU time 4.16 seconds
Started Jun 28 04:42:30 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 213612 kb
Host smart-fc454c35-cf50-424f-aea4-92a5a6bb33a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979934701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2979934701
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1141697447
Short name T1047
Test name
Test status
Simulation time 12311388 ps
CPU time 0.71 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 205272 kb
Host smart-b05ed2a8-70d4-4a41-83d8-0257a0ab8421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141697447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1141697447
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3378608149
Short name T926
Test name
Test status
Simulation time 11407636 ps
CPU time 0.88 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:16 PM PDT 24
Peak memory 205388 kb
Host smart-bea92c14-3b17-4767-8b0d-eb06fe5a4184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378608149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3378608149
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3043549065
Short name T980
Test name
Test status
Simulation time 32654646 ps
CPU time 0.69 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:16 PM PDT 24
Peak memory 205276 kb
Host smart-1bbc7628-ad00-4350-bccf-73cc1f213e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043549065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3043549065
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.235915093
Short name T946
Test name
Test status
Simulation time 14304697 ps
CPU time 0.73 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:16 PM PDT 24
Peak memory 205208 kb
Host smart-3a192538-e728-4c25-91c0-f32fe60eb68d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235915093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.235915093
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3106185935
Short name T927
Test name
Test status
Simulation time 39299678 ps
CPU time 0.76 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 205212 kb
Host smart-079bb2bf-1951-43fc-a002-5b0b09a8b391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106185935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3106185935
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3517212083
Short name T945
Test name
Test status
Simulation time 10904736 ps
CPU time 0.7 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 205284 kb
Host smart-e0f0f0ed-86d6-4d77-b2eb-85d4ff1f0975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517212083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3517212083
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3257715733
Short name T928
Test name
Test status
Simulation time 12547037 ps
CPU time 0.71 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:16 PM PDT 24
Peak memory 205308 kb
Host smart-5eb8f3bf-f4d6-4bb4-a36e-2aeee0040071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257715733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3257715733
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.492781219
Short name T1031
Test name
Test status
Simulation time 26233070 ps
CPU time 0.78 seconds
Started Jun 28 04:43:15 PM PDT 24
Finished Jun 28 04:43:17 PM PDT 24
Peak memory 205200 kb
Host smart-aaffa7ce-62e3-4148-bf0a-142d09ab6c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492781219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.492781219
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3284436487
Short name T1046
Test name
Test status
Simulation time 16798452 ps
CPU time 0.74 seconds
Started Jun 28 04:43:14 PM PDT 24
Finished Jun 28 04:43:15 PM PDT 24
Peak memory 205212 kb
Host smart-59ca6ce6-24d7-4052-bfc2-cc22b4d46705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284436487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3284436487
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3475727320
Short name T1077
Test name
Test status
Simulation time 16134285 ps
CPU time 0.77 seconds
Started Jun 28 04:43:16 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 205560 kb
Host smart-01694d1c-b0d2-4ea5-ac30-7bd16d7ba1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475727320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3475727320
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3085086488
Short name T989
Test name
Test status
Simulation time 1904801112 ps
CPU time 10.91 seconds
Started Jun 28 04:42:43 PM PDT 24
Finished Jun 28 04:42:54 PM PDT 24
Peak memory 205452 kb
Host smart-bedecefc-229f-40a9-a891-de02a179067c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085086488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
085086488
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2391182052
Short name T1010
Test name
Test status
Simulation time 2114013468 ps
CPU time 6.35 seconds
Started Jun 28 04:42:37 PM PDT 24
Finished Jun 28 04:42:44 PM PDT 24
Peak memory 205436 kb
Host smart-5f18aa4b-8d2b-480b-b2c1-2f0c32c56eb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391182052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
391182052
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3885977178
Short name T929
Test name
Test status
Simulation time 238960320 ps
CPU time 1.2 seconds
Started Jun 28 04:42:37 PM PDT 24
Finished Jun 28 04:42:39 PM PDT 24
Peak memory 205384 kb
Host smart-e191d650-6ecd-434c-89c2-490eabe3ddb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885977178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
885977178
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3916593149
Short name T964
Test name
Test status
Simulation time 14180098 ps
CPU time 1.19 seconds
Started Jun 28 04:42:38 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 205472 kb
Host smart-20049669-3716-44e4-abd3-d1d44cabfc52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916593149 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3916593149
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.630816092
Short name T1059
Test name
Test status
Simulation time 56611053 ps
CPU time 1.22 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:43 PM PDT 24
Peak memory 205584 kb
Host smart-b0fa7547-acef-495e-802a-bf2819cf3761
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630816092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.630816092
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3399645903
Short name T1069
Test name
Test status
Simulation time 16976467 ps
CPU time 0.72 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:41 PM PDT 24
Peak memory 205268 kb
Host smart-af599dc1-b2ca-4eac-b23a-e7c5034a2dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399645903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3399645903
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2798278146
Short name T1014
Test name
Test status
Simulation time 95934185 ps
CPU time 2.58 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:44 PM PDT 24
Peak memory 205548 kb
Host smart-6667f219-b532-4463-9e60-ba87c552bfcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798278146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2798278146
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3728097230
Short name T120
Test name
Test status
Simulation time 441379791 ps
CPU time 3.67 seconds
Started Jun 28 04:42:39 PM PDT 24
Finished Jun 28 04:42:43 PM PDT 24
Peak memory 213928 kb
Host smart-3ff0b3f1-26b1-4db1-9299-87f52b1cd407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728097230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3728097230
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.623608390
Short name T982
Test name
Test status
Simulation time 136447187 ps
CPU time 4.19 seconds
Started Jun 28 04:42:38 PM PDT 24
Finished Jun 28 04:42:43 PM PDT 24
Peak memory 214016 kb
Host smart-579442fa-376b-442d-944d-7f5ca2b30d37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623608390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.623608390
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4224583293
Short name T949
Test name
Test status
Simulation time 302647034 ps
CPU time 5.24 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:47 PM PDT 24
Peak memory 216860 kb
Host smart-f2d3285c-806f-4e95-af89-f6638521811e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224583293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4224583293
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3611510145
Short name T382
Test name
Test status
Simulation time 135998359 ps
CPU time 5.07 seconds
Started Jun 28 04:42:38 PM PDT 24
Finished Jun 28 04:42:44 PM PDT 24
Peak memory 205512 kb
Host smart-7f78845e-4123-4106-b628-606bbc7379f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611510145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3611510145
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.549668808
Short name T1079
Test name
Test status
Simulation time 27004627 ps
CPU time 0.76 seconds
Started Jun 28 04:43:19 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 205212 kb
Host smart-42449890-031c-44eb-927d-60af0fa59c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549668808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.549668808
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.227829603
Short name T1025
Test name
Test status
Simulation time 12592404 ps
CPU time 0.74 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:22 PM PDT 24
Peak memory 205384 kb
Host smart-c960dff3-63e6-4882-a95f-42907ca41278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227829603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.227829603
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1792190145
Short name T987
Test name
Test status
Simulation time 32906820 ps
CPU time 0.78 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:19 PM PDT 24
Peak memory 205252 kb
Host smart-dcafc9de-fccf-4bd6-b292-bac74060c086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792190145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1792190145
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3643501066
Short name T1024
Test name
Test status
Simulation time 33539900 ps
CPU time 0.72 seconds
Started Jun 28 04:43:19 PM PDT 24
Finished Jun 28 04:43:22 PM PDT 24
Peak memory 205512 kb
Host smart-fee70f2d-a8d5-451f-96b3-b683dd59e43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643501066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3643501066
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3737704960
Short name T1083
Test name
Test status
Simulation time 23293575 ps
CPU time 0.83 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:19 PM PDT 24
Peak memory 205384 kb
Host smart-bbfaa8f0-fe33-4e04-a86c-cb3061c1fdf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737704960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3737704960
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2718684157
Short name T988
Test name
Test status
Simulation time 40663974 ps
CPU time 0.77 seconds
Started Jun 28 04:43:18 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 205384 kb
Host smart-583f3728-46af-4c38-b0a7-6640dab56e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718684157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2718684157
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.787712088
Short name T1015
Test name
Test status
Simulation time 18472373 ps
CPU time 0.73 seconds
Started Jun 28 04:43:17 PM PDT 24
Finished Jun 28 04:43:19 PM PDT 24
Peak memory 205388 kb
Host smart-46d295b7-f6fe-410b-b85b-b1474725013d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787712088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.787712088
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.657409771
Short name T938
Test name
Test status
Simulation time 18009224 ps
CPU time 0.89 seconds
Started Jun 28 04:43:21 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 205196 kb
Host smart-e71cb147-bbbb-4186-90e7-31335e9b49bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657409771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.657409771
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4157929898
Short name T925
Test name
Test status
Simulation time 23425400 ps
CPU time 0.8 seconds
Started Jun 28 04:43:20 PM PDT 24
Finished Jun 28 04:43:22 PM PDT 24
Peak memory 205352 kb
Host smart-7d8e290d-a85c-4a0e-9257-95c2e9e8ef50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157929898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4157929898
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2513374703
Short name T975
Test name
Test status
Simulation time 25910130 ps
CPU time 0.73 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205384 kb
Host smart-e5300189-70d1-44cd-adc1-7976c35140aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513374703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2513374703
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3733417077
Short name T939
Test name
Test status
Simulation time 773692878 ps
CPU time 5.14 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:47 PM PDT 24
Peak memory 205420 kb
Host smart-b3d0fb31-b410-417e-8a1b-acc5e0ad142e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733417077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
733417077
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3531236039
Short name T933
Test name
Test status
Simulation time 4339029277 ps
CPU time 7.56 seconds
Started Jun 28 04:42:39 PM PDT 24
Finished Jun 28 04:42:47 PM PDT 24
Peak memory 205592 kb
Host smart-7b37b1a5-1777-41f8-ba2e-711641313590
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531236039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
531236039
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3131489001
Short name T1011
Test name
Test status
Simulation time 122662178 ps
CPU time 1.29 seconds
Started Jun 28 04:42:39 PM PDT 24
Finished Jun 28 04:42:41 PM PDT 24
Peak memory 213592 kb
Host smart-c2f9fa1b-0e32-4702-b754-7e953ca390ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131489001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
131489001
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.825230161
Short name T1063
Test name
Test status
Simulation time 64038767 ps
CPU time 1.68 seconds
Started Jun 28 04:42:37 PM PDT 24
Finished Jun 28 04:42:39 PM PDT 24
Peak memory 213808 kb
Host smart-82cc4078-b294-4e77-97d1-4c9fd0de2c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825230161 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.825230161
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.551482050
Short name T995
Test name
Test status
Simulation time 47826449 ps
CPU time 1.03 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:42 PM PDT 24
Peak memory 205428 kb
Host smart-9827ba42-3b4c-4056-9be8-adb94530d779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551482050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.551482050
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1086549418
Short name T1044
Test name
Test status
Simulation time 52525599 ps
CPU time 0.69 seconds
Started Jun 28 04:42:42 PM PDT 24
Finished Jun 28 04:42:43 PM PDT 24
Peak memory 205284 kb
Host smart-94e94025-dbac-4939-b053-6a8381ef9450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086549418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1086549418
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2198809194
Short name T956
Test name
Test status
Simulation time 103421004 ps
CPU time 2.48 seconds
Started Jun 28 04:42:39 PM PDT 24
Finished Jun 28 04:42:42 PM PDT 24
Peak memory 205556 kb
Host smart-d4913252-65b6-4ec1-b832-1099e3eba47e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198809194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2198809194
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1483790387
Short name T1009
Test name
Test status
Simulation time 149143408 ps
CPU time 1.94 seconds
Started Jun 28 04:42:39 PM PDT 24
Finished Jun 28 04:42:42 PM PDT 24
Peak memory 213836 kb
Host smart-ae58affe-1cce-4a36-aeed-80d8b34de4b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483790387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1483790387
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.869174231
Short name T1032
Test name
Test status
Simulation time 265012510 ps
CPU time 7.86 seconds
Started Jun 28 04:42:39 PM PDT 24
Finished Jun 28 04:42:47 PM PDT 24
Peak memory 220112 kb
Host smart-0c8aa33e-6dff-4705-85f4-91db5d618664
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869174231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.869174231
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.398259479
Short name T974
Test name
Test status
Simulation time 320836523 ps
CPU time 2.35 seconds
Started Jun 28 04:42:37 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 213680 kb
Host smart-5bbb91b5-5aa6-4048-9cb9-aca59106a1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398259479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.398259479
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1448290293
Short name T155
Test name
Test status
Simulation time 302656583 ps
CPU time 9.7 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:51 PM PDT 24
Peak memory 205496 kb
Host smart-1114f404-0be5-4348-88ce-6fd5446e4c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448290293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1448290293
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2981412623
Short name T1050
Test name
Test status
Simulation time 40611220 ps
CPU time 0.72 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 205384 kb
Host smart-f14c2190-d244-4031-8c2a-33c4bc98f358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981412623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2981412623
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1303413695
Short name T944
Test name
Test status
Simulation time 12522466 ps
CPU time 0.71 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205384 kb
Host smart-a1338c85-1b07-4e23-bca0-284135f88c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303413695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1303413695
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4110816870
Short name T943
Test name
Test status
Simulation time 10144030 ps
CPU time 0.69 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205324 kb
Host smart-b62952da-d58a-403a-91e1-4e15de2ba215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110816870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4110816870
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4041397354
Short name T1002
Test name
Test status
Simulation time 14697794 ps
CPU time 0.89 seconds
Started Jun 28 04:43:25 PM PDT 24
Finished Jun 28 04:43:26 PM PDT 24
Peak memory 205236 kb
Host smart-7cc0a5b7-5718-492c-b13b-771e812178ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041397354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4041397354
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3800539631
Short name T1018
Test name
Test status
Simulation time 35360643 ps
CPU time 0.71 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205304 kb
Host smart-7399799f-37d8-4296-9f2e-bc85730e64ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800539631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3800539631
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3981767150
Short name T1007
Test name
Test status
Simulation time 16056288 ps
CPU time 0.76 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205364 kb
Host smart-3431e675-517b-4c9c-baa4-c5df8a1d8f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981767150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3981767150
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1344837370
Short name T1003
Test name
Test status
Simulation time 39798631 ps
CPU time 0.75 seconds
Started Jun 28 04:43:29 PM PDT 24
Finished Jun 28 04:43:32 PM PDT 24
Peak memory 205332 kb
Host smart-0d4e2b23-11bc-48ab-8442-11ab2372bf04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344837370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1344837370
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3675496510
Short name T1066
Test name
Test status
Simulation time 40720135 ps
CPU time 0.72 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205384 kb
Host smart-f96fca13-9d29-40c2-8c48-5b2a75ee9638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675496510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3675496510
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1523968206
Short name T1086
Test name
Test status
Simulation time 11570567 ps
CPU time 0.71 seconds
Started Jun 28 04:43:26 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 205284 kb
Host smart-305e6e35-7769-4614-bdec-8b83014a4ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523968206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1523968206
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.929468741
Short name T1001
Test name
Test status
Simulation time 13735258 ps
CPU time 0.71 seconds
Started Jun 28 04:43:25 PM PDT 24
Finished Jun 28 04:43:26 PM PDT 24
Peak memory 205280 kb
Host smart-3a8d98cd-46d5-4f35-a388-998bc043b5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929468741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.929468741
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.204232936
Short name T171
Test name
Test status
Simulation time 315161945 ps
CPU time 1.43 seconds
Started Jun 28 04:42:53 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 213796 kb
Host smart-31a0e66b-3055-4f7a-a165-13af25d975c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204232936 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.204232936
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1803298871
Short name T1027
Test name
Test status
Simulation time 59295952 ps
CPU time 0.9 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:00 PM PDT 24
Peak memory 205316 kb
Host smart-879b9913-7bbe-4c7c-934f-27fba9039868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803298871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1803298871
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3754301292
Short name T1039
Test name
Test status
Simulation time 26897854 ps
CPU time 0.75 seconds
Started Jun 28 04:42:55 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 205332 kb
Host smart-cf0b2d0f-1bae-4b62-bd44-229ee891da1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754301292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3754301292
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1072592178
Short name T1038
Test name
Test status
Simulation time 755352103 ps
CPU time 3.57 seconds
Started Jun 28 04:42:55 PM PDT 24
Finished Jun 28 04:43:00 PM PDT 24
Peak memory 205400 kb
Host smart-cb11cd07-3a15-4762-ae46-3ef160fc00a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072592178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1072592178
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2574045907
Short name T113
Test name
Test status
Simulation time 246277899 ps
CPU time 2.64 seconds
Started Jun 28 04:42:38 PM PDT 24
Finished Jun 28 04:42:42 PM PDT 24
Peak memory 213876 kb
Host smart-9eaf62fd-ac29-4e35-a7a1-52927330bb30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574045907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2574045907
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2378010333
Short name T1089
Test name
Test status
Simulation time 406270045 ps
CPU time 4.43 seconds
Started Jun 28 04:42:40 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 220116 kb
Host smart-8bb3dc6a-e430-4f0c-87f0-c343e0295c73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378010333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2378010333
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2386161746
Short name T961
Test name
Test status
Simulation time 229057757 ps
CPU time 2.99 seconds
Started Jun 28 04:42:38 PM PDT 24
Finished Jun 28 04:42:41 PM PDT 24
Peak memory 215848 kb
Host smart-411a7aca-caac-42a0-9702-f485b7c2f843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386161746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2386161746
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.624343190
Short name T144
Test name
Test status
Simulation time 411637458 ps
CPU time 5.54 seconds
Started Jun 28 04:42:55 PM PDT 24
Finished Jun 28 04:43:01 PM PDT 24
Peak memory 213712 kb
Host smart-0858cffe-d146-4139-9c1f-d641639cf0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624343190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
624343190
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1848782247
Short name T997
Test name
Test status
Simulation time 83247286 ps
CPU time 1.24 seconds
Started Jun 28 04:42:55 PM PDT 24
Finished Jun 28 04:42:57 PM PDT 24
Peak memory 216748 kb
Host smart-16e36178-4513-4594-9733-c56baff28d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848782247 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1848782247
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2866080970
Short name T1073
Test name
Test status
Simulation time 33918453 ps
CPU time 1.04 seconds
Started Jun 28 04:42:54 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 205320 kb
Host smart-62b1627b-3fa5-47ff-8db0-78b7a80adee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866080970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2866080970
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1748039644
Short name T990
Test name
Test status
Simulation time 31138591 ps
CPU time 0.8 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 205308 kb
Host smart-17a68260-3f4e-4cc2-96e1-096f19fb8bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748039644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1748039644
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3988056185
Short name T136
Test name
Test status
Simulation time 183674240 ps
CPU time 1.7 seconds
Started Jun 28 04:42:56 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 205492 kb
Host smart-972531d2-f7ae-4173-9e5f-d43048235a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988056185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3988056185
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2757963319
Short name T115
Test name
Test status
Simulation time 132878442 ps
CPU time 2.78 seconds
Started Jun 28 04:42:54 PM PDT 24
Finished Jun 28 04:42:58 PM PDT 24
Peak memory 214008 kb
Host smart-aa0c3411-7d3f-4d0b-a43d-d80a5226f60a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757963319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2757963319
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1407995000
Short name T977
Test name
Test status
Simulation time 887944980 ps
CPU time 8.27 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:06 PM PDT 24
Peak memory 214100 kb
Host smart-c1066c05-d892-4730-a4b8-70869e8ba36d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407995000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1407995000
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2528677781
Short name T1072
Test name
Test status
Simulation time 414607373 ps
CPU time 2.69 seconds
Started Jun 28 04:42:54 PM PDT 24
Finished Jun 28 04:42:57 PM PDT 24
Peak memory 213760 kb
Host smart-b4521f78-4deb-492b-9058-237f8a5e66bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528677781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2528677781
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3495893345
Short name T1008
Test name
Test status
Simulation time 51067112 ps
CPU time 2.11 seconds
Started Jun 28 04:42:56 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 219084 kb
Host smart-32b46dfa-5d33-4596-8038-90fb626be420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495893345 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3495893345
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1790887606
Short name T1084
Test name
Test status
Simulation time 25218312 ps
CPU time 1.19 seconds
Started Jun 28 04:42:56 PM PDT 24
Finished Jun 28 04:42:58 PM PDT 24
Peak memory 205392 kb
Host smart-de7806a1-ce09-467d-a1a4-0f7964186ee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790887606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1790887606
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.518422425
Short name T1037
Test name
Test status
Simulation time 8536362 ps
CPU time 0.77 seconds
Started Jun 28 04:42:59 PM PDT 24
Finished Jun 28 04:43:00 PM PDT 24
Peak memory 205272 kb
Host smart-e5af43e1-8af1-45ec-b89d-e056604bd201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518422425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.518422425
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3591910249
Short name T992
Test name
Test status
Simulation time 360325398 ps
CPU time 2.52 seconds
Started Jun 28 04:42:56 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 205496 kb
Host smart-8b267ee2-8a0d-4ff5-baa3-31e0882fa7ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591910249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3591910249
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.688397138
Short name T117
Test name
Test status
Simulation time 226855473 ps
CPU time 1.75 seconds
Started Jun 28 04:42:54 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 214004 kb
Host smart-60b05ee6-0cd2-4458-8850-6a3b4f7367b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688397138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.688397138
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.224913050
Short name T121
Test name
Test status
Simulation time 500232332 ps
CPU time 10.19 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 221304 kb
Host smart-21563459-e894-408b-8232-82fda54422a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224913050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.224913050
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1815934482
Short name T951
Test name
Test status
Simulation time 58200973 ps
CPU time 2.44 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:01 PM PDT 24
Peak memory 213592 kb
Host smart-22e377ac-0a8c-48b7-97ee-f785a4c38572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815934482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1815934482
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2975359941
Short name T381
Test name
Test status
Simulation time 403102210 ps
CPU time 8.42 seconds
Started Jun 28 04:42:55 PM PDT 24
Finished Jun 28 04:43:04 PM PDT 24
Peak memory 205544 kb
Host smart-5e63cc8f-d2e0-4d48-a49d-2973c0c31dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975359941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2975359941
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1852240107
Short name T1013
Test name
Test status
Simulation time 259733277 ps
CPU time 1.81 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 213604 kb
Host smart-749dbfa5-0230-40f5-869e-e8b9e52d4537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852240107 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1852240107
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.97162624
Short name T138
Test name
Test status
Simulation time 164114199 ps
CPU time 0.97 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 205356 kb
Host smart-3587e07e-78bf-4297-a482-f18ea25fec08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97162624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.97162624
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2323106907
Short name T963
Test name
Test status
Simulation time 17768641 ps
CPU time 0.81 seconds
Started Jun 28 04:42:55 PM PDT 24
Finished Jun 28 04:42:57 PM PDT 24
Peak memory 205332 kb
Host smart-b5ff9a29-ada1-464d-897a-eb47a9194831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323106907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2323106907
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2016998682
Short name T996
Test name
Test status
Simulation time 98270174 ps
CPU time 1.34 seconds
Started Jun 28 04:43:07 PM PDT 24
Finished Jun 28 04:43:10 PM PDT 24
Peak memory 205436 kb
Host smart-30f23d9f-384c-4c55-a44e-4357ee7cbfa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016998682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2016998682
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2861048254
Short name T1060
Test name
Test status
Simulation time 141262573 ps
CPU time 2.47 seconds
Started Jun 28 04:42:53 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 213836 kb
Host smart-53f78dd2-b720-4bb9-9463-eb36a9ff352c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861048254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2861048254
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2608024275
Short name T1061
Test name
Test status
Simulation time 608262528 ps
CPU time 11.89 seconds
Started Jun 28 04:42:56 PM PDT 24
Finished Jun 28 04:43:10 PM PDT 24
Peak memory 213912 kb
Host smart-f4700a84-9cc1-41ab-b587-4560f84d978b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608024275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2608024275
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4225908712
Short name T937
Test name
Test status
Simulation time 271189122 ps
CPU time 2.16 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:00 PM PDT 24
Peak memory 213736 kb
Host smart-3771bc8b-2a12-4722-8486-acb12a72b5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225908712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4225908712
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4281952175
Short name T147
Test name
Test status
Simulation time 469094380 ps
CPU time 6.27 seconds
Started Jun 28 04:42:57 PM PDT 24
Finished Jun 28 04:43:05 PM PDT 24
Peak memory 213764 kb
Host smart-f04d5095-5f6d-4d03-a5ba-8f8b282ce822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281952175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4281952175
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4150576054
Short name T1052
Test name
Test status
Simulation time 34932658 ps
CPU time 1.29 seconds
Started Jun 28 04:43:03 PM PDT 24
Finished Jun 28 04:43:05 PM PDT 24
Peak memory 213708 kb
Host smart-d133b232-2c2d-4aa2-bd66-6aed9e388e17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150576054 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4150576054
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2246752205
Short name T1028
Test name
Test status
Simulation time 38180565 ps
CPU time 1.71 seconds
Started Jun 28 04:43:08 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 205488 kb
Host smart-20ab76ff-abb2-4457-883d-0984433de7b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246752205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2246752205
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2637941104
Short name T1021
Test name
Test status
Simulation time 71291300 ps
CPU time 0.86 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:07 PM PDT 24
Peak memory 205308 kb
Host smart-5a1eca8f-8ad2-4b9d-8d85-d3950291eacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637941104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2637941104
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3294259810
Short name T1020
Test name
Test status
Simulation time 80963665 ps
CPU time 1.36 seconds
Started Jun 28 04:43:07 PM PDT 24
Finished Jun 28 04:43:10 PM PDT 24
Peak memory 205440 kb
Host smart-f3e6a9f7-bc53-44a3-b3d0-e424540cdc82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294259810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3294259810
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2746903874
Short name T1026
Test name
Test status
Simulation time 886001595 ps
CPU time 2.9 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 214024 kb
Host smart-8d673778-2dd7-4167-a206-1bcdfee0648b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746903874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2746903874
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1440130363
Short name T1016
Test name
Test status
Simulation time 381155934 ps
CPU time 13.93 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 213892 kb
Host smart-55ff272c-5a6a-4dde-bcae-2f2994201b12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440130363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1440130363
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3216781106
Short name T981
Test name
Test status
Simulation time 88629869 ps
CPU time 1.61 seconds
Started Jun 28 04:43:06 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 213572 kb
Host smart-e3091ad9-7d0a-42e1-a1fa-26bc2d0a642e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216781106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3216781106
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1401208084
Short name T142
Test name
Test status
Simulation time 117917307 ps
CPU time 2.8 seconds
Started Jun 28 04:43:05 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 213716 kb
Host smart-68687bb4-5a7d-496a-9ec0-a1c1248d4641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401208084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1401208084
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1867361954
Short name T447
Test name
Test status
Simulation time 310030746 ps
CPU time 1.06 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 205984 kb
Host smart-0b4e83ae-d912-41c3-9c28-a2d31a841f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867361954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1867361954
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2035770203
Short name T359
Test name
Test status
Simulation time 57609578 ps
CPU time 3.77 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 215604 kb
Host smart-b743da42-ae77-4f98-be88-e86019856169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035770203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2035770203
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.342941367
Short name T23
Test name
Test status
Simulation time 279001404 ps
CPU time 2.3 seconds
Started Jun 28 04:44:21 PM PDT 24
Finished Jun 28 04:44:25 PM PDT 24
Peak memory 221392 kb
Host smart-da349178-f4b8-47bb-86c6-10d97a5cc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342941367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.342941367
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2226348769
Short name T900
Test name
Test status
Simulation time 114214877 ps
CPU time 3.16 seconds
Started Jun 28 04:44:12 PM PDT 24
Finished Jun 28 04:44:20 PM PDT 24
Peak memory 207792 kb
Host smart-ef82bd44-ea9a-4121-b9e0-41c375eb4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226348769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2226348769
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.996605370
Short name T248
Test name
Test status
Simulation time 93452491 ps
CPU time 2.69 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 214336 kb
Host smart-74cfdbda-c0bd-4a9f-a446-beb76a401397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996605370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.996605370
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1969891199
Short name T409
Test name
Test status
Simulation time 128209668 ps
CPU time 3.04 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 214328 kb
Host smart-34cabab0-d5d2-4f4a-8976-402e3fb519dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969891199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1969891199
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3857084169
Short name T795
Test name
Test status
Simulation time 69979829 ps
CPU time 3.2 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:20 PM PDT 24
Peak memory 208376 kb
Host smart-c26dda7a-bc4c-48ef-9dd1-3ee5cf721bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857084169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3857084169
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1568369111
Short name T740
Test name
Test status
Simulation time 134569647 ps
CPU time 3.42 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:20 PM PDT 24
Peak memory 208608 kb
Host smart-56de954c-d661-45ff-8033-55440477e9a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568369111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1568369111
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3652429933
Short name T540
Test name
Test status
Simulation time 50843834 ps
CPU time 2.1 seconds
Started Jun 28 04:44:13 PM PDT 24
Finished Jun 28 04:44:19 PM PDT 24
Peak memory 208764 kb
Host smart-f90a2830-5508-498b-a9c9-e512b8e4cfc4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652429933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3652429933
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2728676296
Short name T199
Test name
Test status
Simulation time 46157061 ps
CPU time 2.61 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:17 PM PDT 24
Peak memory 206992 kb
Host smart-769e0466-ea4f-4941-a4f0-63104f7ebd96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728676296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2728676296
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3309700999
Short name T559
Test name
Test status
Simulation time 278075994 ps
CPU time 3.83 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:44:28 PM PDT 24
Peak memory 208208 kb
Host smart-ccd11c9a-6d90-4571-9fc4-596955bca1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309700999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3309700999
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.436414814
Short name T401
Test name
Test status
Simulation time 150958368 ps
CPU time 3.39 seconds
Started Jun 28 04:44:11 PM PDT 24
Finished Jun 28 04:44:18 PM PDT 24
Peak memory 208188 kb
Host smart-8845dbae-6ee7-439a-8079-4e46831ae5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436414814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.436414814
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3089054824
Short name T300
Test name
Test status
Simulation time 1314800158 ps
CPU time 18.06 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:40 PM PDT 24
Peak memory 222572 kb
Host smart-05bba679-363e-4c30-b9db-4eaf68e60c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089054824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3089054824
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.771235545
Short name T165
Test name
Test status
Simulation time 972040650 ps
CPU time 9.24 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:31 PM PDT 24
Peak memory 221316 kb
Host smart-65f024b3-ccb6-4c5c-8eec-8656ec470ad7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771235545 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.771235545
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2357059036
Short name T797
Test name
Test status
Simulation time 1329445038 ps
CPU time 5.65 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:28 PM PDT 24
Peak memory 209132 kb
Host smart-b9b526e6-2b04-47cb-9cbe-0a4912ad8eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357059036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2357059036
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3668343707
Short name T392
Test name
Test status
Simulation time 240911849 ps
CPU time 3.01 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:31 PM PDT 24
Peak memory 210812 kb
Host smart-5131fec8-26da-4bd3-b6fe-966cba06b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668343707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3668343707
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2023251248
Short name T17
Test name
Test status
Simulation time 38432933 ps
CPU time 2.65 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 214924 kb
Host smart-28744cf1-8a41-408c-b37b-03893247e3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023251248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2023251248
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1508209830
Short name T310
Test name
Test status
Simulation time 408311640 ps
CPU time 4.81 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 218076 kb
Host smart-bb0e9bcb-4980-4bbf-8215-d2d3b9020472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508209830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1508209830
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3787433881
Short name T565
Test name
Test status
Simulation time 350240628 ps
CPU time 3.06 seconds
Started Jun 28 04:44:16 PM PDT 24
Finished Jun 28 04:44:23 PM PDT 24
Peak memory 219836 kb
Host smart-df0cde33-edbf-4397-b3e8-4eb158e344ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787433881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3787433881
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.213678131
Short name T555
Test name
Test status
Simulation time 8676734841 ps
CPU time 62.16 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:45:26 PM PDT 24
Peak memory 208956 kb
Host smart-b736ea5f-9ac7-4083-add9-8c424c41c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213678131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.213678131
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1507974752
Short name T14
Test name
Test status
Simulation time 1619395730 ps
CPU time 14.48 seconds
Started Jun 28 04:44:21 PM PDT 24
Finished Jun 28 04:44:37 PM PDT 24
Peak memory 230616 kb
Host smart-09fee0d9-344e-40b3-b93d-60481b6ca9da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507974752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1507974752
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1573479865
Short name T864
Test name
Test status
Simulation time 306769870 ps
CPU time 3.04 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 208500 kb
Host smart-ebf1f9cf-9aaa-491e-a5f9-d98e61eb99dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573479865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1573479865
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4048068940
Short name T573
Test name
Test status
Simulation time 96665249 ps
CPU time 4.11 seconds
Started Jun 28 04:44:21 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 208640 kb
Host smart-e4d933fc-77a0-4783-9d8a-01f987acb74b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048068940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4048068940
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.497665637
Short name T722
Test name
Test status
Simulation time 2752539349 ps
CPU time 37.3 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 209064 kb
Host smart-cd8d23c1-82c2-4b5a-9888-7b0fedd279ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497665637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.497665637
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4173245910
Short name T683
Test name
Test status
Simulation time 75420993 ps
CPU time 3.48 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:26 PM PDT 24
Peak memory 208588 kb
Host smart-6cfa6c44-a54e-4f31-8438-3b835fe75d90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173245910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4173245910
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2855819782
Short name T505
Test name
Test status
Simulation time 1700580790 ps
CPU time 11.22 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:41 PM PDT 24
Peak memory 208244 kb
Host smart-a1697113-42af-4f0f-8b1e-167371848611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855819782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2855819782
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1735765472
Short name T612
Test name
Test status
Simulation time 12766343380 ps
CPU time 19.15 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:41 PM PDT 24
Peak memory 208852 kb
Host smart-c465adf7-14c7-464b-a7fc-2e7e013c9b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735765472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1735765472
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.493783134
Short name T804
Test name
Test status
Simulation time 44937494 ps
CPU time 2.12 seconds
Started Jun 28 04:44:19 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 210160 kb
Host smart-e2ec41cc-2d94-4089-a535-e48aa0939ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493783134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.493783134
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.450848068
Short name T523
Test name
Test status
Simulation time 63720474 ps
CPU time 0.78 seconds
Started Jun 28 04:44:56 PM PDT 24
Finished Jun 28 04:44:57 PM PDT 24
Peak memory 206028 kb
Host smart-b815e5aa-9202-48de-b6e3-1318dfd6dc0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450848068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.450848068
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2059967253
Short name T333
Test name
Test status
Simulation time 61574307 ps
CPU time 4.27 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 214368 kb
Host smart-1f58d461-77a6-41dc-b20a-625f0d3fecec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059967253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2059967253
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1524403494
Short name T847
Test name
Test status
Simulation time 351100653 ps
CPU time 3.93 seconds
Started Jun 28 04:45:00 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 220316 kb
Host smart-5c091d0c-128d-49e3-8ad3-ce149898cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524403494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1524403494
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4293196425
Short name T876
Test name
Test status
Simulation time 650305914 ps
CPU time 4.15 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:45:00 PM PDT 24
Peak memory 210108 kb
Host smart-d90e7e86-9119-4acd-b645-c1c1c2c9e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293196425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4293196425
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2017619688
Short name T376
Test name
Test status
Simulation time 101977543 ps
CPU time 2.22 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 208656 kb
Host smart-11d98121-2284-45f9-907c-48bab3be75b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017619688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2017619688
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4144326141
Short name T851
Test name
Test status
Simulation time 225926977 ps
CPU time 5.52 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 214372 kb
Host smart-fd0a43dd-b06c-4873-aef6-2158753075a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144326141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4144326141
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3028319030
Short name T237
Test name
Test status
Simulation time 613169435 ps
CPU time 7.93 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 209864 kb
Host smart-14e1ddc1-f157-4029-a58b-267ea74bd901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028319030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3028319030
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3940526073
Short name T557
Test name
Test status
Simulation time 1123185093 ps
CPU time 4.11 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 206780 kb
Host smart-bd5b41a6-e83b-44bd-94f8-19b7a003cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940526073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3940526073
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2400803694
Short name T366
Test name
Test status
Simulation time 4272910281 ps
CPU time 35.84 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 207932 kb
Host smart-79227eba-6f75-4968-bf90-c97837512e0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400803694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2400803694
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3220543586
Short name T687
Test name
Test status
Simulation time 6692211152 ps
CPU time 65.43 seconds
Started Jun 28 04:45:00 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 207996 kb
Host smart-0fc273a4-a0cf-4cff-a001-cabb6c106e76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220543586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3220543586
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2074006949
Short name T646
Test name
Test status
Simulation time 32173411 ps
CPU time 2.39 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 206976 kb
Host smart-2aecad6b-dbfa-4b2b-810c-8609b215456a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074006949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2074006949
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2119179842
Short name T364
Test name
Test status
Simulation time 407977374 ps
CPU time 3.44 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:44:59 PM PDT 24
Peak memory 218312 kb
Host smart-6bb96920-f2be-497a-9d70-6b3455eb47be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119179842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2119179842
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1945056393
Short name T499
Test name
Test status
Simulation time 255900001 ps
CPU time 4.76 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 207052 kb
Host smart-6379005b-9bd4-46af-be55-091c60d4629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945056393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1945056393
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3267422203
Short name T785
Test name
Test status
Simulation time 160542880 ps
CPU time 6.9 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:45:02 PM PDT 24
Peak memory 222124 kb
Host smart-94286c93-25d9-43a1-a2e6-4eccada5e6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267422203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3267422203
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3454990147
Short name T331
Test name
Test status
Simulation time 790132977 ps
CPU time 4.2 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:45:00 PM PDT 24
Peak memory 218420 kb
Host smart-ccf0d33a-4e5d-46d9-82af-76e295d6148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454990147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3454990147
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2804064774
Short name T383
Test name
Test status
Simulation time 1042248824 ps
CPU time 5.35 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 211100 kb
Host smart-a74daa82-ce15-43f6-b05e-816cca5bd87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804064774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2804064774
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3887379612
Short name T731
Test name
Test status
Simulation time 51390641 ps
CPU time 0.79 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:44:59 PM PDT 24
Peak memory 205940 kb
Host smart-a10b8fb7-97ea-4a8a-adf7-12ebac275214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887379612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3887379612
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2476838453
Short name T915
Test name
Test status
Simulation time 288933656 ps
CPU time 3.42 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 209052 kb
Host smart-19ab23c5-566e-471a-91c0-e48963de943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476838453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2476838453
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3492341472
Short name T280
Test name
Test status
Simulation time 32171172 ps
CPU time 2.24 seconds
Started Jun 28 04:45:00 PM PDT 24
Finished Jun 28 04:45:04 PM PDT 24
Peak memory 214324 kb
Host smart-08e1f34e-9eae-4e8e-81ab-a634b96021fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492341472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3492341472
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.776238750
Short name T807
Test name
Test status
Simulation time 131575190 ps
CPU time 2.74 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 219500 kb
Host smart-fe4bae5c-9e4d-4433-ae77-80b3df9868c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776238750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.776238750
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2279266838
Short name T587
Test name
Test status
Simulation time 364482857 ps
CPU time 7.75 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 208228 kb
Host smart-77367385-10d0-42a6-8fcd-431bb281ce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279266838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2279266838
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2364851723
Short name T867
Test name
Test status
Simulation time 63749980 ps
CPU time 2.34 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:02 PM PDT 24
Peak memory 206964 kb
Host smart-5bc0b04c-124d-4fe4-b833-7f7e9dab2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364851723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2364851723
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2489155771
Short name T752
Test name
Test status
Simulation time 88636993 ps
CPU time 3.16 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:02 PM PDT 24
Peak memory 206944 kb
Host smart-3a761730-d2d7-486e-b7aa-1b7d8b7ca942
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489155771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2489155771
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1309911926
Short name T368
Test name
Test status
Simulation time 107453536 ps
CPU time 3.27 seconds
Started Jun 28 04:44:53 PM PDT 24
Finished Jun 28 04:44:57 PM PDT 24
Peak memory 206720 kb
Host smart-fc11e682-7a42-46d0-9a1d-dd985637517d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309911926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1309911926
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3425177090
Short name T801
Test name
Test status
Simulation time 127871104 ps
CPU time 4.11 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 207308 kb
Host smart-7616c1bc-d396-4897-9439-e0485ced017e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425177090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3425177090
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1082115771
Short name T551
Test name
Test status
Simulation time 83434204 ps
CPU time 1.47 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:00 PM PDT 24
Peak memory 207128 kb
Host smart-eda8016d-af24-4d47-b026-44e2bb7e412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082115771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1082115771
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1852465866
Short name T883
Test name
Test status
Simulation time 77823826 ps
CPU time 3.28 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 208264 kb
Host smart-9ef48e9c-3414-401f-9c36-0810250a29e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852465866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1852465866
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1004137521
Short name T301
Test name
Test status
Simulation time 887658084 ps
CPU time 16.48 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 216188 kb
Host smart-cca4fc93-2f89-481c-826e-338175eb5540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004137521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1004137521
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.969966481
Short name T294
Test name
Test status
Simulation time 1049808940 ps
CPU time 13.19 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 222492 kb
Host smart-acedaffe-42fb-48de-8bac-5b994bb5a0a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969966481 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.969966481
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2195633069
Short name T809
Test name
Test status
Simulation time 365785100 ps
CPU time 5.1 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 208772 kb
Host smart-6e1c564d-04e4-44d2-80dc-64300e4dedb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195633069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2195633069
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.575647211
Short name T387
Test name
Test status
Simulation time 111204307 ps
CPU time 1.6 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:44:57 PM PDT 24
Peak memory 210020 kb
Host smart-eca42600-4e66-4980-9e37-0a1276a5f496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575647211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.575647211
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1070972756
Short name T432
Test name
Test status
Simulation time 51961743 ps
CPU time 0.73 seconds
Started Jun 28 04:44:52 PM PDT 24
Finished Jun 28 04:44:54 PM PDT 24
Peak memory 206048 kb
Host smart-7e85fd38-7399-47a7-bb2e-0fe0ffdd861f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070972756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1070972756
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2195908756
Short name T109
Test name
Test status
Simulation time 230896543 ps
CPU time 4.87 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 215472 kb
Host smart-be9184dc-f3e9-4f55-acb7-f6d7220e2030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195908756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2195908756
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3734018539
Short name T718
Test name
Test status
Simulation time 320397412 ps
CPU time 3.1 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 206096 kb
Host smart-9d319183-0f8b-4f2b-b78e-2266dbb256f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734018539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3734018539
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1023568450
Short name T707
Test name
Test status
Simulation time 1106194544 ps
CPU time 11.8 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:11 PM PDT 24
Peak memory 214384 kb
Host smart-2c824a49-29c4-4f93-908c-0a353e1f598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023568450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1023568450
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2876403154
Short name T674
Test name
Test status
Simulation time 26707388 ps
CPU time 1.82 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:04 PM PDT 24
Peak memory 214344 kb
Host smart-22f9f510-6aad-4ed6-840d-1941a01e1713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876403154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2876403154
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3485500550
Short name T910
Test name
Test status
Simulation time 402514520 ps
CPU time 3.92 seconds
Started Jun 28 04:44:52 PM PDT 24
Finished Jun 28 04:44:57 PM PDT 24
Peak memory 222484 kb
Host smart-f5c76da1-6241-4589-a743-bbacfa8d4cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485500550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3485500550
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1771297936
Short name T267
Test name
Test status
Simulation time 173080178 ps
CPU time 2.96 seconds
Started Jun 28 04:44:53 PM PDT 24
Finished Jun 28 04:44:56 PM PDT 24
Peak memory 210080 kb
Host smart-068eeeb4-a44c-4666-b3f0-959147cb9b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771297936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1771297936
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1765331336
Short name T439
Test name
Test status
Simulation time 105587051 ps
CPU time 2.99 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:02 PM PDT 24
Peak memory 206860 kb
Host smart-f7667a59-5636-4b58-a47d-2f130e3bca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765331336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1765331336
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3365722787
Short name T705
Test name
Test status
Simulation time 4969812994 ps
CPU time 20.99 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:23 PM PDT 24
Peak memory 208456 kb
Host smart-acbb3a96-115c-4ce2-8eee-daab4d361da6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365722787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3365722787
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.638952829
Short name T654
Test name
Test status
Simulation time 1155045350 ps
CPU time 6.17 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 208000 kb
Host smart-3f4448ff-4a67-451f-9387-ec80b59351a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638952829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.638952829
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1879230272
Short name T609
Test name
Test status
Simulation time 124949527 ps
CPU time 2.42 seconds
Started Jun 28 04:44:52 PM PDT 24
Finished Jun 28 04:44:55 PM PDT 24
Peak memory 207108 kb
Host smart-cfaa076a-de87-4488-a583-54dbb554eb3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879230272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1879230272
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2618136063
Short name T257
Test name
Test status
Simulation time 141376215 ps
CPU time 4.15 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:06 PM PDT 24
Peak memory 214336 kb
Host smart-2b31fffb-a535-4d0a-a578-e8fc278d13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618136063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2618136063
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1476952299
Short name T618
Test name
Test status
Simulation time 195987333 ps
CPU time 2.67 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:02 PM PDT 24
Peak memory 206864 kb
Host smart-015bf2a8-3094-4582-8774-f1c52ed47f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476952299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1476952299
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2408677099
Short name T75
Test name
Test status
Simulation time 668030430 ps
CPU time 25.04 seconds
Started Jun 28 04:44:51 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 215836 kb
Host smart-f944dfd9-d25f-467d-8718-f0324d8c88fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408677099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2408677099
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3600187814
Short name T824
Test name
Test status
Simulation time 280586271 ps
CPU time 5.83 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:06 PM PDT 24
Peak memory 222428 kb
Host smart-3cd319d6-56cf-4628-a3e0-97a1e8c9fa14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600187814 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3600187814
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1975199135
Short name T261
Test name
Test status
Simulation time 112008824 ps
CPU time 3.69 seconds
Started Jun 28 04:44:53 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 208544 kb
Host smart-8f1befa7-da12-4657-844e-0dfe120108ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975199135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1975199135
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2934149005
Short name T586
Test name
Test status
Simulation time 44971049 ps
CPU time 0.83 seconds
Started Jun 28 04:44:59 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 206076 kb
Host smart-b1291e38-c1c1-4ea6-8cbe-b949892081c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934149005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2934149005
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2835167576
Short name T547
Test name
Test status
Simulation time 5134064373 ps
CPU time 31.26 seconds
Started Jun 28 04:44:56 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 214252 kb
Host smart-888792f1-59af-4a0f-8614-6a7eba17a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835167576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2835167576
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.96265774
Short name T501
Test name
Test status
Simulation time 60370907 ps
CPU time 2.79 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 210516 kb
Host smart-e57f00b1-ac78-46ef-91a4-f267d9ef3133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96265774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.96265774
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1472701829
Short name T279
Test name
Test status
Simulation time 121502351 ps
CPU time 4.18 seconds
Started Jun 28 04:44:56 PM PDT 24
Finished Jun 28 04:45:02 PM PDT 24
Peak memory 222240 kb
Host smart-afba0b34-8484-4d0a-982a-ca3c3227e83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472701829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1472701829
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.383798904
Short name T11
Test name
Test status
Simulation time 138495006 ps
CPU time 5.61 seconds
Started Jun 28 04:44:54 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 222588 kb
Host smart-83779418-edac-4ae3-9c76-2b23b0c049d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383798904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.383798904
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1249935300
Short name T272
Test name
Test status
Simulation time 277115643 ps
CPU time 9.86 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:09 PM PDT 24
Peak memory 218348 kb
Host smart-46e3f902-75ce-4ce4-b4c7-d4dcd16d924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249935300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1249935300
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1922161088
Short name T755
Test name
Test status
Simulation time 30357283 ps
CPU time 2.3 seconds
Started Jun 28 04:45:00 PM PDT 24
Finished Jun 28 04:45:04 PM PDT 24
Peak memory 206852 kb
Host smart-a4e68784-5b24-4608-88e7-d9a9ae113de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922161088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1922161088
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3308984389
Short name T541
Test name
Test status
Simulation time 461172785 ps
CPU time 3.57 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 206952 kb
Host smart-45d872bc-c384-4a0b-9339-0eef70d03aef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308984389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3308984389
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.598513579
Short name T726
Test name
Test status
Simulation time 495794110 ps
CPU time 5.73 seconds
Started Jun 28 04:45:01 PM PDT 24
Finished Jun 28 04:45:08 PM PDT 24
Peak memory 208188 kb
Host smart-f66c4475-d541-4d00-b4fc-1c6e0e55dea9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598513579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.598513579
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2011434386
Short name T815
Test name
Test status
Simulation time 151193973 ps
CPU time 3.56 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 207600 kb
Host smart-72a19ab4-ded3-4f09-9216-d557d9191de0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011434386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2011434386
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3967741255
Short name T253
Test name
Test status
Simulation time 85320609 ps
CPU time 3.28 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 214300 kb
Host smart-7fca9d19-ee6e-47d6-9b62-759d5067188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967741255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3967741255
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2446839066
Short name T585
Test name
Test status
Simulation time 1505399360 ps
CPU time 35.2 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:35 PM PDT 24
Peak memory 208364 kb
Host smart-4f9645b9-4db3-4d0d-9d3c-d1054e147d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446839066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2446839066
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1298021795
Short name T909
Test name
Test status
Simulation time 209226199 ps
CPU time 5.78 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 208716 kb
Host smart-78b31dde-afa1-4cf0-9e2d-8e8f4e6904a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298021795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1298021795
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1222838784
Short name T385
Test name
Test status
Simulation time 300314159 ps
CPU time 7.01 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 211116 kb
Host smart-805d2daf-5c57-443f-b53a-03b23c579c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222838784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1222838784
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3119566762
Short name T608
Test name
Test status
Simulation time 50771113 ps
CPU time 0.72 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 205808 kb
Host smart-250e5158-cd97-4ec4-b21c-fa386e2a7114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119566762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3119566762
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3300484320
Short name T225
Test name
Test status
Simulation time 341389155 ps
CPU time 9.41 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 214416 kb
Host smart-07b9545c-0ad0-4dc5-8478-2bee55390f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300484320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3300484320
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1822889051
Short name T732
Test name
Test status
Simulation time 88822781 ps
CPU time 3.15 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:11 PM PDT 24
Peak memory 219492 kb
Host smart-aaed825c-6657-4195-a086-d8cb63cadc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822889051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1822889051
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.880926961
Short name T96
Test name
Test status
Simulation time 99433270 ps
CPU time 2.42 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 209880 kb
Host smart-168ed7af-77e5-474a-ac78-9f9c6ad6786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880926961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.880926961
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3937280688
Short name T634
Test name
Test status
Simulation time 130758713 ps
CPU time 4.77 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:11 PM PDT 24
Peak memory 206284 kb
Host smart-cd095e51-6f4f-4502-91c4-65b0cbd1af9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937280688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3937280688
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1734136809
Short name T908
Test name
Test status
Simulation time 990407292 ps
CPU time 7.29 seconds
Started Jun 28 04:45:02 PM PDT 24
Finished Jun 28 04:45:11 PM PDT 24
Peak memory 207580 kb
Host smart-7a120a7e-de5a-4fc5-94bc-d633a7536116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734136809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1734136809
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3075124726
Short name T558
Test name
Test status
Simulation time 181212378 ps
CPU time 4.79 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:09 PM PDT 24
Peak memory 207000 kb
Host smart-32994321-09e0-4804-b89c-19370bd64c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075124726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3075124726
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3836331853
Short name T603
Test name
Test status
Simulation time 100827740 ps
CPU time 2.67 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 206820 kb
Host smart-a6cbdefe-e0b4-4427-a4db-9a0c39d16ac7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836331853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3836331853
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.786659756
Short name T753
Test name
Test status
Simulation time 445910414 ps
CPU time 5.68 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 208336 kb
Host smart-1db03db9-c7ce-4f75-913b-7ab9fef78d74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786659756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.786659756
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.932737039
Short name T581
Test name
Test status
Simulation time 222698391 ps
CPU time 3.36 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 206988 kb
Host smart-4ba66195-7c99-464b-a52f-c09d560251ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932737039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.932737039
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3478786773
Short name T768
Test name
Test status
Simulation time 421708937 ps
CPU time 3.51 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 209912 kb
Host smart-3ae02d16-3f00-4c21-812c-12ed0086c314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478786773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3478786773
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3548810780
Short name T693
Test name
Test status
Simulation time 218147465 ps
CPU time 2.62 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:08 PM PDT 24
Peak memory 208428 kb
Host smart-1b15e453-4cb0-4e55-9261-142bbef12338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548810780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3548810780
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1626315049
Short name T902
Test name
Test status
Simulation time 931125201 ps
CPU time 11.05 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 219828 kb
Host smart-4ffdbaf7-4723-49f3-a0d0-6041d1d4a761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626315049 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1626315049
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1515741442
Short name T842
Test name
Test status
Simulation time 137966529 ps
CPU time 3.86 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 209348 kb
Host smart-741e12b8-67d8-4098-9c73-828d1b85ebdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515741442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1515741442
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4119583627
Short name T553
Test name
Test status
Simulation time 35463116 ps
CPU time 0.81 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:14 PM PDT 24
Peak memory 205944 kb
Host smart-aa32c163-db2e-423f-89c9-83c7fb68d040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119583627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4119583627
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1127990795
Short name T412
Test name
Test status
Simulation time 45992901 ps
CPU time 2.77 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:09 PM PDT 24
Peak memory 215232 kb
Host smart-0ee06579-4e2b-4274-8458-edfcbe3a203b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127990795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1127990795
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.882751532
Short name T67
Test name
Test status
Simulation time 3210666078 ps
CPU time 25.4 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 214752 kb
Host smart-cfdbc5ce-19b0-4123-84e4-68d7d6e82bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882751532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.882751532
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1723519175
Short name T794
Test name
Test status
Simulation time 170914261 ps
CPU time 3.84 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 219708 kb
Host smart-3ead1aa4-f526-4086-bd22-c2bfd3df8eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723519175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1723519175
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1594066706
Short name T307
Test name
Test status
Simulation time 915991495 ps
CPU time 15.41 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:25 PM PDT 24
Peak memory 222360 kb
Host smart-fa2ed786-2876-4a7a-94c4-b27b8a79533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594066706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1594066706
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.657276389
Short name T635
Test name
Test status
Simulation time 113251987 ps
CPU time 3.41 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:45:18 PM PDT 24
Peak memory 209512 kb
Host smart-691e4d1e-aa33-49ae-ba9d-c896e1792204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657276389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.657276389
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2490351908
Short name T187
Test name
Test status
Simulation time 390850667 ps
CPU time 4.69 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 208276 kb
Host smart-8b4ed32a-a5e0-49f5-86d8-2691fd9049bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490351908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2490351908
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1519288090
Short name T771
Test name
Test status
Simulation time 482476451 ps
CPU time 3.7 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 208376 kb
Host smart-27975e54-dcb9-4ccc-b62e-fa0d92eeddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519288090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1519288090
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.477116928
Short name T843
Test name
Test status
Simulation time 527575349 ps
CPU time 2.39 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 208904 kb
Host smart-5e58078b-6aa2-4f5d-8a8c-abf5f96ed2e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477116928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.477116928
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2718127609
Short name T613
Test name
Test status
Simulation time 21013857 ps
CPU time 1.59 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:08 PM PDT 24
Peak memory 207864 kb
Host smart-f2202de7-4c18-4483-b00d-be201e47e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718127609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2718127609
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1956678064
Short name T786
Test name
Test status
Simulation time 179469924 ps
CPU time 3.41 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 208568 kb
Host smart-200d02fb-c9b0-43d2-b6a8-347cc94ae93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956678064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1956678064
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2218695694
Short name T180
Test name
Test status
Simulation time 2347238967 ps
CPU time 21.91 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 216400 kb
Host smart-0b75f3d3-fac0-4667-bb1b-855313c9c2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218695694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2218695694
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4164970878
Short name T291
Test name
Test status
Simulation time 639075920 ps
CPU time 13.91 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:25 PM PDT 24
Peak memory 208808 kb
Host smart-172ee66c-0662-4a0f-b204-a5d96e9a5a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164970878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4164970878
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1691426140
Short name T588
Test name
Test status
Simulation time 69557900 ps
CPU time 1.38 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 209756 kb
Host smart-3bf61913-ded2-4f3e-b561-f5892e2560d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691426140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1691426140
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.999474735
Short name T496
Test name
Test status
Simulation time 31505010 ps
CPU time 0.78 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 206060 kb
Host smart-e4924b81-d864-4b86-b057-a32fcb96b04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999474735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.999474735
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3520125412
Short name T416
Test name
Test status
Simulation time 155107384 ps
CPU time 4.89 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:09 PM PDT 24
Peak memory 214328 kb
Host smart-fd0ffcf2-297e-42a7-8447-f8445756e708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520125412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3520125412
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2643245111
Short name T606
Test name
Test status
Simulation time 76430755 ps
CPU time 2.3 seconds
Started Jun 28 04:45:02 PM PDT 24
Finished Jun 28 04:45:06 PM PDT 24
Peak memory 214132 kb
Host smart-bbd5929e-f9d8-469f-a01f-97b6dbdf4600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643245111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2643245111
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1695919884
Short name T550
Test name
Test status
Simulation time 56761035 ps
CPU time 1.82 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 214340 kb
Host smart-488ca564-2665-4ade-b32a-c0f9ef3b0690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695919884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1695919884
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3607837965
Short name T233
Test name
Test status
Simulation time 51217910 ps
CPU time 3.29 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 206700 kb
Host smart-1b2840da-7993-4a7d-95cf-06f0ea282b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607837965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3607837965
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1493369671
Short name T913
Test name
Test status
Simulation time 306509795 ps
CPU time 2.01 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 214244 kb
Host smart-53cf38d7-ee42-4037-bef7-82e6e818e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493369671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1493369671
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1212161673
Short name T292
Test name
Test status
Simulation time 380323292 ps
CPU time 6.14 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 207508 kb
Host smart-62cabd05-af1c-438f-9b2b-f846114053e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212161673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1212161673
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.4190271119
Short name T636
Test name
Test status
Simulation time 2942481845 ps
CPU time 51.44 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:46:04 PM PDT 24
Peak memory 208620 kb
Host smart-1d6a7f5b-b1cb-45bb-92bc-99223184de4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190271119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.4190271119
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3945524893
Short name T626
Test name
Test status
Simulation time 2248947914 ps
CPU time 10.18 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 208812 kb
Host smart-d0b182de-5bf1-4e1d-9ab2-ab4e198935b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945524893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3945524893
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3424835569
Short name T38
Test name
Test status
Simulation time 24600571 ps
CPU time 1.95 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:08 PM PDT 24
Peak memory 206892 kb
Host smart-21741cf4-0400-4f0a-bede-5f76122e5cf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424835569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3424835569
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2324263159
Short name T428
Test name
Test status
Simulation time 432880662 ps
CPU time 2.34 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:06 PM PDT 24
Peak memory 209580 kb
Host smart-6095ae26-a027-4af9-9473-d30d2229e937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324263159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2324263159
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3004558097
Short name T556
Test name
Test status
Simulation time 143183074 ps
CPU time 2.19 seconds
Started Jun 28 04:45:09 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 206784 kb
Host smart-ed7f271b-342b-4565-8c11-d4bfc82b198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004558097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3004558097
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.978468317
Short name T68
Test name
Test status
Simulation time 477271791 ps
CPU time 19.02 seconds
Started Jun 28 04:45:07 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 222464 kb
Host smart-79e833b8-23fe-4aaa-b8af-b65c6c569821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978468317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.978468317
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3217938216
Short name T169
Test name
Test status
Simulation time 1286618595 ps
CPU time 8.29 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 217568 kb
Host smart-0fd18f18-e79c-42e3-a1db-34e0a309055c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217938216 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3217938216
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1505146531
Short name T268
Test name
Test status
Simulation time 115903378 ps
CPU time 3.79 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 214296 kb
Host smart-6469afe6-9452-46be-bd5c-07c116939039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505146531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1505146531
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2822784830
Short name T827
Test name
Test status
Simulation time 240888800 ps
CPU time 2.75 seconds
Started Jun 28 04:45:09 PM PDT 24
Finished Jun 28 04:45:13 PM PDT 24
Peak memory 210136 kb
Host smart-95be8025-db89-436e-9e01-638b2516f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822784830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2822784830
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3978271894
Short name T733
Test name
Test status
Simulation time 38647903 ps
CPU time 0.72 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:19 PM PDT 24
Peak memory 206052 kb
Host smart-76f8f3e6-c405-4299-9989-3b717920491b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978271894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3978271894
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3291005173
Short name T33
Test name
Test status
Simulation time 51770028 ps
CPU time 1.98 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 220000 kb
Host smart-d7df4bac-f1b9-4ec5-96c7-dc295137ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291005173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3291005173
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2362041613
Short name T341
Test name
Test status
Simulation time 530651720 ps
CPU time 2.39 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:19 PM PDT 24
Peak memory 210396 kb
Host smart-ff432653-7639-472a-9a31-21c1c9efb390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362041613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2362041613
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2465673613
Short name T308
Test name
Test status
Simulation time 225690843 ps
CPU time 5.09 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 214324 kb
Host smart-7f3dd7a6-4f47-4c1f-aa96-93dfba0621e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465673613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2465673613
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.836463074
Short name T825
Test name
Test status
Simulation time 409609735 ps
CPU time 2.56 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:10 PM PDT 24
Peak memory 214276 kb
Host smart-bed92fb0-7f89-4437-b110-ef1649a7dd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836463074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.836463074
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4010782880
Short name T792
Test name
Test status
Simulation time 149650809 ps
CPU time 2.22 seconds
Started Jun 28 04:45:05 PM PDT 24
Finished Jun 28 04:45:08 PM PDT 24
Peak memory 219916 kb
Host smart-0e2e3462-c617-496d-913c-67df3ef2d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010782880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4010782880
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2297155656
Short name T185
Test name
Test status
Simulation time 132703104 ps
CPU time 4.29 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 222440 kb
Host smart-e7730add-5da4-4608-b3e6-c2ee708cbc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297155656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2297155656
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1902993947
Short name T770
Test name
Test status
Simulation time 159818860 ps
CPU time 5.86 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 208388 kb
Host smart-717d2016-de94-4f05-81b9-4af353b62468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902993947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1902993947
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.790929834
Short name T510
Test name
Test status
Simulation time 123606072 ps
CPU time 5.1 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:15 PM PDT 24
Peak memory 208668 kb
Host smart-b2ca9707-aa44-443d-a6a1-3e99b8fb0671
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790929834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.790929834
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.882914043
Short name T251
Test name
Test status
Simulation time 3871709761 ps
CPU time 7.29 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 208636 kb
Host smart-f0fddd52-d4c2-45b3-8502-697ca9de4d3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882914043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.882914043
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2255991277
Short name T532
Test name
Test status
Simulation time 38117616 ps
CPU time 2.16 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 215588 kb
Host smart-343f8a03-6d76-4b34-8894-a376879061f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255991277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2255991277
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1193903616
Short name T798
Test name
Test status
Simulation time 291728472 ps
CPU time 2.45 seconds
Started Jun 28 04:45:03 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 206784 kb
Host smart-6cdad5c1-e46d-48be-b16a-0117a6cc9f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193903616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1193903616
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2155307819
Short name T6
Test name
Test status
Simulation time 1381022245 ps
CPU time 46.07 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:46:01 PM PDT 24
Peak memory 222356 kb
Host smart-ed08d349-2c95-46f3-8ec9-96c3376d2fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155307819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2155307819
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.797646641
Short name T166
Test name
Test status
Simulation time 466873145 ps
CPU time 17.22 seconds
Started Jun 28 04:45:10 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 221820 kb
Host smart-af0c61ff-6caf-41a3-88e5-5540e769f8c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797646641 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.797646641
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2421583078
Short name T360
Test name
Test status
Simulation time 422642268 ps
CPU time 5.04 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 218264 kb
Host smart-deb82124-d4a2-4420-9606-d21c27366f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421583078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2421583078
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.210251631
Short name T379
Test name
Test status
Simulation time 440143874 ps
CPU time 2.5 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 210360 kb
Host smart-062ac92e-3e7c-4eed-8f4a-1f317f86b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210251631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.210251631
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1356299412
Short name T665
Test name
Test status
Simulation time 13432907 ps
CPU time 0.68 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:18 PM PDT 24
Peak memory 205980 kb
Host smart-e8ee787d-4f9f-438c-8333-5b10082f42c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356299412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1356299412
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3592044843
Short name T351
Test name
Test status
Simulation time 28517156 ps
CPU time 2.26 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:14 PM PDT 24
Peak memory 214212 kb
Host smart-5d829367-964e-4036-8bbd-67469dd21d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592044843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3592044843
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3822409708
Short name T9
Test name
Test status
Simulation time 122673138 ps
CPU time 3.29 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 208748 kb
Host smart-11469597-de02-497c-a675-ccd343567b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822409708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3822409708
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.564063200
Short name T336
Test name
Test status
Simulation time 93591117 ps
CPU time 2.96 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:11 PM PDT 24
Peak memory 206996 kb
Host smart-4e9ab747-b4a2-47e0-8604-e953a2ba558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564063200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.564063200
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3665330824
Short name T26
Test name
Test status
Simulation time 264508208 ps
CPU time 6.69 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:25 PM PDT 24
Peak memory 222380 kb
Host smart-bd98566b-6236-4b6c-a932-d78a9eac2695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665330824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3665330824
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2166866476
Short name T264
Test name
Test status
Simulation time 122674964 ps
CPU time 3.73 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 214268 kb
Host smart-a51bcf1e-af80-4a22-a37b-e19cb525b6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166866476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2166866476
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.147752727
Short name T288
Test name
Test status
Simulation time 56143562 ps
CPU time 3.73 seconds
Started Jun 28 04:45:11 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 208264 kb
Host smart-50650047-3f64-452e-8e47-6fa4d3a944c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147752727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.147752727
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.938996356
Short name T835
Test name
Test status
Simulation time 268307190 ps
CPU time 4.59 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:18 PM PDT 24
Peak memory 208276 kb
Host smart-628b4c87-6256-4a4d-860e-3f9505eaded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938996356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.938996356
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1716557037
Short name T743
Test name
Test status
Simulation time 302633566 ps
CPU time 3.05 seconds
Started Jun 28 04:45:04 PM PDT 24
Finished Jun 28 04:45:08 PM PDT 24
Peak memory 206916 kb
Host smart-eb02ec26-da3f-43e7-a88c-46d0a8594519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716557037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1716557037
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2925903638
Short name T911
Test name
Test status
Simulation time 331367130 ps
CPU time 6.55 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 208472 kb
Host smart-7b6c8531-3307-4459-939c-a08ce5984247
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925903638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2925903638
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.115315246
Short name T568
Test name
Test status
Simulation time 579581620 ps
CPU time 5.12 seconds
Started Jun 28 04:45:10 PM PDT 24
Finished Jun 28 04:45:16 PM PDT 24
Peak memory 208896 kb
Host smart-58c609f5-8150-4677-9c5c-475078cf1ea5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115315246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.115315246
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1319475220
Short name T595
Test name
Test status
Simulation time 383209732 ps
CPU time 5.96 seconds
Started Jun 28 04:45:06 PM PDT 24
Finished Jun 28 04:45:14 PM PDT 24
Peak memory 207972 kb
Host smart-9b98af55-6bde-4631-85e4-2789f44ed8f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319475220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1319475220
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1339733260
Short name T805
Test name
Test status
Simulation time 843942304 ps
CPU time 11.01 seconds
Started Jun 28 04:45:08 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 209528 kb
Host smart-6b8500a7-fd8b-47e3-ad05-0ef4bf48134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339733260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1339733260
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.149167654
Short name T402
Test name
Test status
Simulation time 129921428 ps
CPU time 3.59 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 206604 kb
Host smart-12b38fa6-216f-4ae7-9940-09f2752acc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149167654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.149167654
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3044630029
Short name T108
Test name
Test status
Simulation time 159920164 ps
CPU time 4.28 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:23 PM PDT 24
Peak memory 210252 kb
Host smart-65edd2bb-4d0a-4483-ba92-b328ade4600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044630029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3044630029
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2882522612
Short name T512
Test name
Test status
Simulation time 3801675186 ps
CPU time 29.35 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:48 PM PDT 24
Peak memory 211752 kb
Host smart-db16853d-4c42-4e39-ac02-20c330f0a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882522612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2882522612
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.4064071620
Short name T579
Test name
Test status
Simulation time 30168846 ps
CPU time 0.9 seconds
Started Jun 28 04:45:19 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 206168 kb
Host smart-e07b2bce-2627-423c-8ff7-fbb1e642a5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064071620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.4064071620
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2304518308
Short name T468
Test name
Test status
Simulation time 661470251 ps
CPU time 2.15 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 209764 kb
Host smart-f27bac6b-221c-40a4-8ba3-b39f9e12a24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304518308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2304518308
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.902906658
Short name T826
Test name
Test status
Simulation time 213608593 ps
CPU time 2.43 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:19 PM PDT 24
Peak memory 214332 kb
Host smart-38e654b2-aac0-4254-87fb-fa187c1e8962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902906658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.902906658
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3535749675
Short name T758
Test name
Test status
Simulation time 255975901 ps
CPU time 6.05 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 220700 kb
Host smart-7c92daab-2fb1-4a76-b1fb-5ebc1b47ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535749675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3535749675
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1484325852
Short name T774
Test name
Test status
Simulation time 121933461 ps
CPU time 2.19 seconds
Started Jun 28 04:45:17 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 214936 kb
Host smart-1bb01bf2-db95-4d17-bb4c-05663d769b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484325852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1484325852
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1991592492
Short name T921
Test name
Test status
Simulation time 1006886193 ps
CPU time 10.13 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:26 PM PDT 24
Peak memory 218396 kb
Host smart-cac9537d-c815-4548-95e3-b4b6108014ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991592492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1991592492
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1134933221
Short name T424
Test name
Test status
Simulation time 322536938 ps
CPU time 3.01 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 208416 kb
Host smart-69e6d931-6f8a-4a6e-9cb1-654e36de9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134933221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1134933221
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4130161544
Short name T569
Test name
Test status
Simulation time 635202814 ps
CPU time 5.63 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 208028 kb
Host smart-3b16062d-2aa3-4f90-b864-3aac0c09fff5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130161544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4130161544
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1575969137
Short name T767
Test name
Test status
Simulation time 118588468 ps
CPU time 3.19 seconds
Started Jun 28 04:45:12 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 207036 kb
Host smart-de1b7a58-ee78-4ac3-9bc3-1f4b859c80ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575969137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1575969137
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.305319038
Short name T111
Test name
Test status
Simulation time 38764849 ps
CPU time 2.42 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 208720 kb
Host smart-018fe1c8-bf5c-4af2-90be-1365614d25e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305319038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.305319038
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3249677811
Short name T173
Test name
Test status
Simulation time 87532696 ps
CPU time 3.09 seconds
Started Jun 28 04:45:19 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 218348 kb
Host smart-03492db0-1a95-48f4-ad18-4996acd177ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249677811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3249677811
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3624050393
Short name T426
Test name
Test status
Simulation time 86784284 ps
CPU time 3.31 seconds
Started Jun 28 04:45:19 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 208724 kb
Host smart-2af5d5c6-1aad-4ddd-a86f-c1417f4005ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624050393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3624050393
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2318261483
Short name T531
Test name
Test status
Simulation time 38057438 ps
CPU time 2.86 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 208468 kb
Host smart-625bf90a-c4ff-46f1-9705-fcf90b9b5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318261483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2318261483
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1459180733
Short name T922
Test name
Test status
Simulation time 70692817 ps
CPU time 2.83 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:19 PM PDT 24
Peak memory 210064 kb
Host smart-142e8d69-5f71-4e05-9021-458dcfb69920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459180733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1459180733
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1229920567
Short name T444
Test name
Test status
Simulation time 10595241 ps
CPU time 0.81 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:29 PM PDT 24
Peak memory 205880 kb
Host smart-3165f821-2cee-41b9-a9b7-a7c18ae6c13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229920567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1229920567
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2451206463
Short name T326
Test name
Test status
Simulation time 68366137 ps
CPU time 2.97 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:26 PM PDT 24
Peak memory 222376 kb
Host smart-f418538d-4fa7-463b-a7fd-53cf1843431c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451206463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2451206463
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1981594779
Short name T313
Test name
Test status
Simulation time 54328255 ps
CPU time 2.57 seconds
Started Jun 28 04:44:24 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 214220 kb
Host smart-255e7f4b-fd9b-4cbd-940d-1618a2df8aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981594779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1981594779
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3258188737
Short name T374
Test name
Test status
Simulation time 54439234 ps
CPU time 2.26 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 214276 kb
Host smart-a6f21192-5af8-4a86-be3f-82e6e6afb9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258188737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3258188737
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2202241298
Short name T88
Test name
Test status
Simulation time 53375849 ps
CPU time 3.33 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 214548 kb
Host smart-5f6ed0c8-4c3f-4170-951b-b4e06a79cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202241298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2202241298
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.918694184
Short name T624
Test name
Test status
Simulation time 200097792 ps
CPU time 2.7 seconds
Started Jun 28 04:44:17 PM PDT 24
Finished Jun 28 04:44:23 PM PDT 24
Peak memory 209636 kb
Host smart-047db4e0-2494-4cf0-aa16-73fc99e50c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918694184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.918694184
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2933761580
Short name T349
Test name
Test status
Simulation time 286209433 ps
CPU time 6.02 seconds
Started Jun 28 04:44:17 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 218204 kb
Host smart-d4a57247-db28-4257-9655-87d4efcae651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933761580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2933761580
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1726319666
Short name T685
Test name
Test status
Simulation time 148781837 ps
CPU time 4.09 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:25 PM PDT 24
Peak memory 208560 kb
Host smart-d38366e9-111f-4e61-9836-f6d927307415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726319666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1726319666
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.49014691
Short name T258
Test name
Test status
Simulation time 219970447 ps
CPU time 2.7 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 208460 kb
Host smart-0503c660-23b0-498e-b2ec-d58e3218a67f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49014691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.49014691
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4157443429
Short name T886
Test name
Test status
Simulation time 1488625471 ps
CPU time 19.36 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:41 PM PDT 24
Peak memory 208336 kb
Host smart-69285fcf-c05d-44be-97af-65492d045472
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157443429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4157443429
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1976003330
Short name T837
Test name
Test status
Simulation time 343858742 ps
CPU time 6.89 seconds
Started Jun 28 04:44:26 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 206912 kb
Host smart-e17ff837-8fba-44fb-a47a-438ba69c51f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976003330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1976003330
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.355405186
Short name T657
Test name
Test status
Simulation time 3868611973 ps
CPU time 32.8 seconds
Started Jun 28 04:44:17 PM PDT 24
Finished Jun 28 04:44:54 PM PDT 24
Peak memory 209524 kb
Host smart-253d4594-4b58-42f9-8606-4edc4c5736e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355405186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.355405186
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2324169471
Short name T518
Test name
Test status
Simulation time 96899487 ps
CPU time 2.23 seconds
Started Jun 28 04:44:17 PM PDT 24
Finished Jun 28 04:44:23 PM PDT 24
Peak memory 206708 kb
Host smart-7ed97d13-7418-442e-931d-ab3216590dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324169471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2324169471
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2083771140
Short name T516
Test name
Test status
Simulation time 1208549953 ps
CPU time 13.3 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:36 PM PDT 24
Peak memory 215624 kb
Host smart-0fef4782-7b5f-4ce0-9ec2-31700dec7281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083771140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2083771140
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1023366263
Short name T719
Test name
Test status
Simulation time 77814203 ps
CPU time 3.83 seconds
Started Jun 28 04:44:20 PM PDT 24
Finished Jun 28 04:44:26 PM PDT 24
Peak memory 214328 kb
Host smart-90ec44f9-44e7-4adf-be3e-65fa6e365403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023366263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1023366263
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1929678791
Short name T378
Test name
Test status
Simulation time 48742983 ps
CPU time 1.63 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:23 PM PDT 24
Peak memory 209852 kb
Host smart-121d3076-a944-4917-b86b-9b6af0c5ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929678791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1929678791
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.352455310
Short name T800
Test name
Test status
Simulation time 19161262 ps
CPU time 0.83 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 205892 kb
Host smart-a8aaae21-67b5-4ac3-99b1-7fefa5870caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352455310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.352455310
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.4131704021
Short name T244
Test name
Test status
Simulation time 718678909 ps
CPU time 37.76 seconds
Started Jun 28 04:45:23 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 214464 kb
Host smart-69dcedb8-5449-4724-a036-7bfa5ca2f5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131704021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.4131704021
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3838659900
Short name T736
Test name
Test status
Simulation time 313504441 ps
CPU time 2.97 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 214408 kb
Host smart-1fc72c0b-6652-4d42-82f4-0bfec998bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838659900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3838659900
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.686161071
Short name T466
Test name
Test status
Simulation time 125992328 ps
CPU time 2.23 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 214224 kb
Host smart-4d576986-dbeb-4799-888f-5f97996259dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686161071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.686161071
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2029150957
Short name T638
Test name
Test status
Simulation time 243719941 ps
CPU time 3.69 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 214148 kb
Host smart-8323be3f-6efe-4b15-a86b-aa6c0f85140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029150957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2029150957
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.207519341
Short name T730
Test name
Test status
Simulation time 614016731 ps
CPU time 2.63 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 206248 kb
Host smart-ba9da29f-2d72-4e5a-b7ba-a74a72e36897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207519341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.207519341
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1209640796
Short name T874
Test name
Test status
Simulation time 1855409057 ps
CPU time 5.46 seconds
Started Jun 28 04:45:13 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 209172 kb
Host smart-e2069d91-45d5-485d-9015-cd5d35b284d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209640796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1209640796
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3525826352
Short name T20
Test name
Test status
Simulation time 106361973 ps
CPU time 2.79 seconds
Started Jun 28 04:45:17 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 208664 kb
Host smart-66460330-291f-482c-ad42-6defe05d95d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525826352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3525826352
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.571644205
Short name T18
Test name
Test status
Simulation time 1004604329 ps
CPU time 2.85 seconds
Started Jun 28 04:45:20 PM PDT 24
Finished Jun 28 04:45:23 PM PDT 24
Peak memory 207624 kb
Host smart-8b4583d3-0fcb-416d-947e-a1e702041b0f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571644205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.571644205
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1547658914
Short name T637
Test name
Test status
Simulation time 83963041 ps
CPU time 3.36 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 208908 kb
Host smart-3324de9d-d78f-4cfa-9aeb-9c3d7ae813a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547658914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1547658914
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4250456493
Short name T598
Test name
Test status
Simulation time 209516126 ps
CPU time 4.61 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 208740 kb
Host smart-9f1296d2-c94a-44bc-9395-f865f16bae2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250456493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4250456493
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1969364458
Short name T327
Test name
Test status
Simulation time 61276421 ps
CPU time 2.61 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 208112 kb
Host smart-7e8f1a8c-da2c-4d26-8e0b-584f09595e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969364458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1969364458
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2018248065
Short name T536
Test name
Test status
Simulation time 195236336 ps
CPU time 1.63 seconds
Started Jun 28 04:45:17 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 206960 kb
Host smart-101acbed-70c7-4626-9764-b73df85eb193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018248065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2018248065
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.396430263
Short name T314
Test name
Test status
Simulation time 362439711 ps
CPU time 4.44 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 214188 kb
Host smart-d15d35c3-681f-40a7-bfcd-77b701c06f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396430263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.396430263
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.529693199
Short name T399
Test name
Test status
Simulation time 133353956 ps
CPU time 1.5 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 210144 kb
Host smart-8ab31d26-754d-4a0a-9e1b-2a1e836df23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529693199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.529693199
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4166275431
Short name T16
Test name
Test status
Simulation time 30322420 ps
CPU time 0.71 seconds
Started Jun 28 04:45:20 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 206060 kb
Host smart-391eed05-232a-48ee-9205-3922e529bd14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166275431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4166275431
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3081561682
Short name T715
Test name
Test status
Simulation time 132356661 ps
CPU time 2.87 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 214224 kb
Host smart-ecb2c9aa-131a-47de-9bcf-fbac3b611ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081561682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3081561682
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2897965296
Short name T90
Test name
Test status
Simulation time 510849316 ps
CPU time 3.38 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 222188 kb
Host smart-ec81e38c-49e1-46a5-95aa-bc5ac45f4b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897965296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2897965296
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3295560030
Short name T783
Test name
Test status
Simulation time 413424156 ps
CPU time 3.62 seconds
Started Jun 28 04:45:19 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 217924 kb
Host smart-29b8ba07-845e-4cba-93b6-486631da6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295560030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3295560030
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2481718453
Short name T39
Test name
Test status
Simulation time 65673610 ps
CPU time 3.11 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 210300 kb
Host smart-6ce60475-5e34-454c-b56b-12958a72f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481718453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2481718453
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.761681100
Short name T278
Test name
Test status
Simulation time 6833938736 ps
CPU time 48.93 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 208548 kb
Host smart-37e6d471-e0ba-41e0-9e09-7a0351a6397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761681100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.761681100
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1391658098
Short name T793
Test name
Test status
Simulation time 188394811 ps
CPU time 5.6 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 207652 kb
Host smart-5f503d2e-5cdb-4062-98c4-511be85844c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391658098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1391658098
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1455341093
Short name T832
Test name
Test status
Simulation time 176597626 ps
CPU time 2.55 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 208568 kb
Host smart-42786372-39a3-49bb-8ba2-dc4173be98ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455341093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1455341093
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2271902071
Short name T238
Test name
Test status
Simulation time 523676108 ps
CPU time 4.68 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 214392 kb
Host smart-fbab863f-1de7-4170-b5d3-1f508191b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271902071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2271902071
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.939979294
Short name T484
Test name
Test status
Simulation time 128695596 ps
CPU time 3.29 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 208344 kb
Host smart-e05999df-eb98-4ce5-bdbe-258ac31a8f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939979294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.939979294
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3408756526
Short name T293
Test name
Test status
Simulation time 47986854 ps
CPU time 2.44 seconds
Started Jun 28 04:45:14 PM PDT 24
Finished Jun 28 04:45:18 PM PDT 24
Peak memory 209504 kb
Host smart-f3d6d785-6d4c-4213-8d25-839afd9477f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408756526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3408756526
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.214156873
Short name T389
Test name
Test status
Simulation time 3157934284 ps
CPU time 20.22 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 209168 kb
Host smart-1aba9e5f-cc7c-424c-976d-e2ffa51bd062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214156873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.214156873
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1134049255
Short name T663
Test name
Test status
Simulation time 385077233 ps
CPU time 2.86 seconds
Started Jun 28 04:45:17 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 210324 kb
Host smart-07514086-7458-454c-9f40-f8b66982631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134049255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1134049255
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1427865223
Short name T630
Test name
Test status
Simulation time 125607064 ps
CPU time 0.78 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 205948 kb
Host smart-beda0144-6986-4e57-b6f6-2fed6d3205ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427865223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1427865223
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2226231788
Short name T703
Test name
Test status
Simulation time 331546085 ps
CPU time 4.99 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:24 PM PDT 24
Peak memory 215680 kb
Host smart-16c6c38f-d03a-497a-b5e2-84246f47951b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226231788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2226231788
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.147255507
Short name T35
Test name
Test status
Simulation time 115978685 ps
CPU time 2.01 seconds
Started Jun 28 04:45:23 PM PDT 24
Finished Jun 28 04:45:26 PM PDT 24
Peak memory 210536 kb
Host smart-c86ac027-c8c4-475c-a9f7-85c5f845ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147255507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.147255507
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3876777256
Short name T273
Test name
Test status
Simulation time 39531147 ps
CPU time 2.64 seconds
Started Jun 28 04:45:16 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 214420 kb
Host smart-6c6f786d-ec24-45f2-811d-72d6b458d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876777256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3876777256
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1275592426
Short name T782
Test name
Test status
Simulation time 567391125 ps
CPU time 3.73 seconds
Started Jun 28 04:45:23 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 208960 kb
Host smart-8a4a8995-fefd-453e-9410-705a78ec49b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275592426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1275592426
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2113697781
Short name T716
Test name
Test status
Simulation time 160674953 ps
CPU time 2.07 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:27 PM PDT 24
Peak memory 206052 kb
Host smart-85c305d2-9d50-435d-a92d-453f292e7ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113697781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2113697781
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2017167838
Short name T460
Test name
Test status
Simulation time 86410219 ps
CPU time 2.84 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 206288 kb
Host smart-71ef5fe9-2d38-42ef-b60f-5a66863a818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017167838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2017167838
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4131765885
Short name T509
Test name
Test status
Simulation time 219677973 ps
CPU time 3.91 seconds
Started Jun 28 04:45:23 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 214296 kb
Host smart-a0554c8e-da80-46eb-984b-b4a928418d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131765885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4131765885
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3775022972
Short name T924
Test name
Test status
Simulation time 277418161 ps
CPU time 4.18 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 208136 kb
Host smart-db4e7f1f-cb60-48e5-95d8-4ee446712f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775022972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3775022972
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.4179679891
Short name T475
Test name
Test status
Simulation time 1810849460 ps
CPU time 18.15 seconds
Started Jun 28 04:45:23 PM PDT 24
Finished Jun 28 04:45:41 PM PDT 24
Peak memory 208388 kb
Host smart-496657c3-19c5-4f29-93d0-f0fc9d807914
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179679891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4179679891
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1534157842
Short name T263
Test name
Test status
Simulation time 36512060 ps
CPU time 2.21 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:27 PM PDT 24
Peak memory 206160 kb
Host smart-d0a81bd6-d900-4599-8fd7-3c2e9e9cbaf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534157842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1534157842
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4232866941
Short name T488
Test name
Test status
Simulation time 66595692 ps
CPU time 2.33 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:27 PM PDT 24
Peak memory 206748 kb
Host smart-970045f1-12a8-400c-8bd5-0d9350e388c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232866941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4232866941
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1109142786
Short name T242
Test name
Test status
Simulation time 341374181 ps
CPU time 4.27 seconds
Started Jun 28 04:45:15 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 218320 kb
Host smart-a23c10e9-cb54-4fba-8f48-bcc833ce46b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109142786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1109142786
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.300382396
Short name T473
Test name
Test status
Simulation time 112926532 ps
CPU time 2.5 seconds
Started Jun 28 04:45:22 PM PDT 24
Finished Jun 28 04:45:25 PM PDT 24
Peak memory 206944 kb
Host smart-1b44d0d2-f5b5-494e-be9c-6b80093b8934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300382396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.300382396
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1807643675
Short name T260
Test name
Test status
Simulation time 208059714 ps
CPU time 7.25 seconds
Started Jun 28 04:45:18 PM PDT 24
Finished Jun 28 04:45:26 PM PDT 24
Peak memory 209512 kb
Host smart-a321cb83-2d2c-4f7d-b7e7-514997fb9182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807643675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1807643675
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1124926692
Short name T578
Test name
Test status
Simulation time 163252839 ps
CPU time 2.33 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:27 PM PDT 24
Peak memory 210284 kb
Host smart-4543feb3-1fa0-4b7c-8a08-61bc41003e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124926692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1124926692
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1650874713
Short name T433
Test name
Test status
Simulation time 12219941 ps
CPU time 0.75 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:30 PM PDT 24
Peak memory 205940 kb
Host smart-4eb3bda2-fc16-4b3e-890e-739ae574372f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650874713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1650874713
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3673911752
Short name T406
Test name
Test status
Simulation time 129164549 ps
CPU time 2.51 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 222480 kb
Host smart-54bad540-596c-4e33-9078-ae049e4cfb61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673911752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3673911752
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2918942095
Short name T841
Test name
Test status
Simulation time 89443869 ps
CPU time 3.6 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 222832 kb
Host smart-b4880473-e03c-4777-9668-9c124a2eb829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918942095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2918942095
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2222037659
Short name T330
Test name
Test status
Simulation time 34125884 ps
CPU time 2.37 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:30 PM PDT 24
Peak memory 214316 kb
Host smart-ce4c84d8-9264-44aa-9962-42ca729b7a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222037659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2222037659
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3154172681
Short name T98
Test name
Test status
Simulation time 55064581 ps
CPU time 3.46 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 209584 kb
Host smart-b1d5feee-0249-4852-ae27-d863ec2fb971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154172681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3154172681
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1302471439
Short name T493
Test name
Test status
Simulation time 91616915 ps
CPU time 2.02 seconds
Started Jun 28 04:45:35 PM PDT 24
Finished Jun 28 04:45:38 PM PDT 24
Peak memory 214160 kb
Host smart-14310ced-f7a1-404d-8709-fd37fe2b0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302471439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1302471439
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2649159909
Short name T877
Test name
Test status
Simulation time 457709424 ps
CPU time 4.76 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:34 PM PDT 24
Peak memory 218920 kb
Host smart-ef92fbb0-4161-456c-be0b-a80196855c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649159909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2649159909
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4092706884
Short name T692
Test name
Test status
Simulation time 209281502 ps
CPU time 4 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:30 PM PDT 24
Peak memory 214324 kb
Host smart-24c290a6-3609-4499-8388-824ff65ade99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092706884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4092706884
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3652613646
Short name T453
Test name
Test status
Simulation time 48668702 ps
CPU time 2.67 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:34 PM PDT 24
Peak memory 206776 kb
Host smart-c82e5de3-3456-46e6-8cca-8645566ddcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652613646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3652613646
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.458487843
Short name T554
Test name
Test status
Simulation time 36391860 ps
CPU time 2.32 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 207040 kb
Host smart-bea4f4a5-9c05-4701-9a98-0a83d5906678
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458487843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.458487843
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2480776429
Short name T690
Test name
Test status
Simulation time 20087684 ps
CPU time 1.73 seconds
Started Jun 28 04:45:29 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 206976 kb
Host smart-43804560-7491-4a8f-a346-2b63afc120d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480776429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2480776429
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3567418118
Short name T227
Test name
Test status
Simulation time 1270382586 ps
CPU time 11.75 seconds
Started Jun 28 04:45:32 PM PDT 24
Finished Jun 28 04:45:44 PM PDT 24
Peak memory 208584 kb
Host smart-a06527fa-c7d9-4536-b593-cd6dd84ef034
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567418118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3567418118
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1970065677
Short name T676
Test name
Test status
Simulation time 85864659 ps
CPU time 1.94 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 207860 kb
Host smart-c0bc8b91-895c-49c8-84d6-b4240b03b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970065677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1970065677
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1541086050
Short name T803
Test name
Test status
Simulation time 262457208 ps
CPU time 8.87 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:36 PM PDT 24
Peak memory 208732 kb
Host smart-974b8354-2191-4037-b77a-ca6d1d06f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541086050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1541086050
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1626160847
Short name T549
Test name
Test status
Simulation time 417429446 ps
CPU time 8.4 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:38 PM PDT 24
Peak memory 221892 kb
Host smart-07df3b04-098d-460a-bdc5-c1999889487d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626160847 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1626160847
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4062266188
Short name T855
Test name
Test status
Simulation time 84346067 ps
CPU time 3.91 seconds
Started Jun 28 04:45:26 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 218092 kb
Host smart-e357e8d7-00f0-461f-a150-03bd8a65ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062266188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4062266188
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3342724161
Short name T710
Test name
Test status
Simulation time 82917778 ps
CPU time 2.77 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 210184 kb
Host smart-f7855071-62cb-4f4e-af69-d7f3fd5432f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342724161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3342724161
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1736866499
Short name T495
Test name
Test status
Simulation time 20134281 ps
CPU time 0.78 seconds
Started Jun 28 04:45:31 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 205948 kb
Host smart-ab2aeeb8-57c0-4d4c-ba40-853e69cbafb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736866499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1736866499
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3101891229
Short name T140
Test name
Test status
Simulation time 137270720 ps
CPU time 2.89 seconds
Started Jun 28 04:45:26 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 222432 kb
Host smart-bd92ebce-4c85-426c-86d4-93d7df82f945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101891229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3101891229
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1442173011
Short name T560
Test name
Test status
Simulation time 244570337 ps
CPU time 3.19 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 210092 kb
Host smart-ea482d0f-29e0-40de-9265-9b77a661ae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442173011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1442173011
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.104055679
Short name T567
Test name
Test status
Simulation time 41801581 ps
CPU time 1.84 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 216384 kb
Host smart-bddea475-56c4-46dc-98b0-64681d85a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104055679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.104055679
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.547391293
Short name T377
Test name
Test status
Simulation time 118018082 ps
CPU time 3.91 seconds
Started Jun 28 04:45:31 PM PDT 24
Finished Jun 28 04:45:35 PM PDT 24
Peak memory 214308 kb
Host smart-9310a59e-fd12-4c71-b96e-2c4620588173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547391293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.547391293
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1951603750
Short name T830
Test name
Test status
Simulation time 381054982 ps
CPU time 4.74 seconds
Started Jun 28 04:45:26 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 214392 kb
Host smart-a714f03e-43d1-4cb3-81b9-5d5563590f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951603750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1951603750
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3324645679
Short name T205
Test name
Test status
Simulation time 248428558 ps
CPU time 7.23 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:36 PM PDT 24
Peak memory 220200 kb
Host smart-e8eaaf5b-c586-4332-bad9-945a40ea2b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324645679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3324645679
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.227497531
Short name T712
Test name
Test status
Simulation time 526544581 ps
CPU time 7.19 seconds
Started Jun 28 04:45:24 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 208024 kb
Host smart-67b4407e-8c8c-43e5-aff4-ee289692237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227497531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.227497531
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.326854831
Short name T691
Test name
Test status
Simulation time 66612557 ps
CPU time 2.41 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:28 PM PDT 24
Peak memory 206892 kb
Host smart-182ef820-afe5-4bfd-9a53-e3471e065ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326854831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.326854831
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2157764493
Short name T625
Test name
Test status
Simulation time 588904486 ps
CPU time 3.91 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:33 PM PDT 24
Peak memory 206416 kb
Host smart-5cfd121a-53e4-48e9-8299-17943780b309
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157764493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2157764493
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2645666056
Short name T346
Test name
Test status
Simulation time 77309275 ps
CPU time 2.42 seconds
Started Jun 28 04:45:26 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 206940 kb
Host smart-9a1686a1-b121-4ff8-8fc3-b2f3badd8d92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645666056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2645666056
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3967156156
Short name T471
Test name
Test status
Simulation time 443793573 ps
CPU time 3.39 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 206848 kb
Host smart-f3fe3458-432d-44b6-b5df-2e8b785751f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967156156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3967156156
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.51241805
Short name T892
Test name
Test status
Simulation time 176315609 ps
CPU time 3.84 seconds
Started Jun 28 04:45:29 PM PDT 24
Finished Jun 28 04:45:34 PM PDT 24
Peak memory 208708 kb
Host smart-f2a9a621-1e5a-46c1-839f-1c86dd5873f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51241805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.51241805
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1386989399
Short name T897
Test name
Test status
Simulation time 418281711 ps
CPU time 8.49 seconds
Started Jun 28 04:45:40 PM PDT 24
Finished Jun 28 04:45:50 PM PDT 24
Peak memory 208328 kb
Host smart-d8837b8e-ebc1-4700-a1ec-929560e34296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386989399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1386989399
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1953236697
Short name T79
Test name
Test status
Simulation time 880277032 ps
CPU time 27.21 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 214388 kb
Host smart-6143c939-745f-4002-82b1-46f891d86f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953236697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1953236697
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.62877651
Short name T73
Test name
Test status
Simulation time 167580718 ps
CPU time 5.04 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:33 PM PDT 24
Peak memory 221700 kb
Host smart-218a0f37-de1c-4da1-80bd-38659cd10984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62877651 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.62877651
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2692569766
Short name T647
Test name
Test status
Simulation time 1057964714 ps
CPU time 13.03 seconds
Started Jun 28 04:45:25 PM PDT 24
Finished Jun 28 04:45:39 PM PDT 24
Peak memory 208776 kb
Host smart-8fa6ae58-257f-4fcb-bfbf-22184acd29b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692569766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2692569766
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2581149645
Short name T40
Test name
Test status
Simulation time 1118043670 ps
CPU time 3.74 seconds
Started Jun 28 04:45:31 PM PDT 24
Finished Jun 28 04:45:36 PM PDT 24
Peak memory 210388 kb
Host smart-7135a27a-7952-46e8-b0e2-9259478db2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581149645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2581149645
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3329714632
Short name T427
Test name
Test status
Simulation time 19808368 ps
CPU time 0.73 seconds
Started Jun 28 04:45:29 PM PDT 24
Finished Jun 28 04:45:30 PM PDT 24
Peak memory 205944 kb
Host smart-1288ab8d-6468-4321-acd7-633b03e11dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329714632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3329714632
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.369679105
Short name T766
Test name
Test status
Simulation time 536845210 ps
CPU time 4.68 seconds
Started Jun 28 04:45:31 PM PDT 24
Finished Jun 28 04:45:36 PM PDT 24
Peak memory 222372 kb
Host smart-bb13a3a0-ebb5-4f0d-9980-50bb30efa176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369679105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.369679105
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.372891208
Short name T622
Test name
Test status
Simulation time 373351170 ps
CPU time 4.56 seconds
Started Jun 28 04:45:35 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 208956 kb
Host smart-47f2f1fa-bba5-4d9b-8cc4-ae57cf204957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372891208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.372891208
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2509702177
Short name T845
Test name
Test status
Simulation time 3953265384 ps
CPU time 26.68 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 209188 kb
Host smart-e9d9a9f4-4f44-45ee-8fc6-8859e8bfa9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509702177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2509702177
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.83949328
Short name T790
Test name
Test status
Simulation time 66506998 ps
CPU time 2.55 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 214336 kb
Host smart-0790c948-b74f-4c3e-9d61-ea7f6fb47ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83949328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.83949328
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.32025024
Short name T42
Test name
Test status
Simulation time 51354566 ps
CPU time 3.13 seconds
Started Jun 28 04:45:26 PM PDT 24
Finished Jun 28 04:45:29 PM PDT 24
Peak memory 222520 kb
Host smart-f2eab615-7e37-49bf-b902-14be466fcc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32025024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.32025024
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2441141098
Short name T191
Test name
Test status
Simulation time 130173872 ps
CPU time 2.44 seconds
Started Jun 28 04:45:27 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 206652 kb
Host smart-07bef591-4de9-46ba-a0fc-17c52329fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441141098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2441141098
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2010052732
Short name T395
Test name
Test status
Simulation time 290144225 ps
CPU time 3.07 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:34 PM PDT 24
Peak memory 208676 kb
Host smart-c7b78636-1684-4f6d-8965-1623b2e4ed83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010052732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2010052732
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2508901769
Short name T828
Test name
Test status
Simulation time 183881423 ps
CPU time 4.11 seconds
Started Jun 28 04:45:29 PM PDT 24
Finished Jun 28 04:45:34 PM PDT 24
Peak memory 207952 kb
Host smart-891e6b16-7d16-404f-8470-3d054495300a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508901769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2508901769
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2676758293
Short name T440
Test name
Test status
Simulation time 134505302 ps
CPU time 1.8 seconds
Started Jun 28 04:45:29 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 206928 kb
Host smart-27f7e0ae-bc86-4f88-be46-92b961ca2f2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676758293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2676758293
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2152424746
Short name T677
Test name
Test status
Simulation time 280378329 ps
CPU time 9.81 seconds
Started Jun 28 04:45:40 PM PDT 24
Finished Jun 28 04:45:50 PM PDT 24
Peak memory 209828 kb
Host smart-c280deee-911f-4fd8-af98-8d22a6d3addf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152424746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2152424746
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1187902635
Short name T904
Test name
Test status
Simulation time 2325496555 ps
CPU time 21.53 seconds
Started Jun 28 04:45:32 PM PDT 24
Finished Jun 28 04:45:54 PM PDT 24
Peak memory 207032 kb
Host smart-9dc2e05a-df53-457d-a129-eec65e9d367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187902635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1187902635
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2230209464
Short name T537
Test name
Test status
Simulation time 120061540 ps
CPU time 8.16 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:39 PM PDT 24
Peak memory 222480 kb
Host smart-3edac396-03bf-4b93-82ee-ec56afcf1514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230209464 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2230209464
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.494858716
Short name T157
Test name
Test status
Simulation time 330289353 ps
CPU time 2.3 seconds
Started Jun 28 04:45:30 PM PDT 24
Finished Jun 28 04:45:34 PM PDT 24
Peak memory 209920 kb
Host smart-15d015fb-22e8-4c78-adcb-8df5d0177681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494858716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.494858716
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1636309491
Short name T513
Test name
Test status
Simulation time 14761539 ps
CPU time 0.92 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:44 PM PDT 24
Peak memory 206168 kb
Host smart-f85a57af-cd0b-4f11-bed4-40b477257b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636309491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1636309491
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2550426294
Short name T407
Test name
Test status
Simulation time 7042436678 ps
CPU time 95.34 seconds
Started Jun 28 04:45:37 PM PDT 24
Finished Jun 28 04:47:13 PM PDT 24
Peak memory 222540 kb
Host smart-09b0d961-ff4a-4861-9370-556f57a989d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550426294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2550426294
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1121340355
Short name T734
Test name
Test status
Simulation time 148665418 ps
CPU time 3.08 seconds
Started Jun 28 04:45:44 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 218452 kb
Host smart-cc9947d6-8f9b-4722-93e5-37bbec2e40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121340355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1121340355
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3509506097
Short name T764
Test name
Test status
Simulation time 101772824 ps
CPU time 3.36 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:43 PM PDT 24
Peak memory 214456 kb
Host smart-383ddf13-6049-440f-a534-43f34ec77cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509506097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3509506097
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1583631320
Short name T456
Test name
Test status
Simulation time 149358251 ps
CPU time 5.22 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:44 PM PDT 24
Peak memory 221948 kb
Host smart-e15a0251-883e-4db5-9508-4a2b2f3bf386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583631320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1583631320
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3738464553
Short name T58
Test name
Test status
Simulation time 168286830 ps
CPU time 2.56 seconds
Started Jun 28 04:45:37 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 222480 kb
Host smart-62372a53-83a9-4fea-947e-8b1c3b675883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738464553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3738464553
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3566447486
Short name T452
Test name
Test status
Simulation time 438392715 ps
CPU time 3.28 seconds
Started Jun 28 04:45:28 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 208328 kb
Host smart-4c6da79f-d6e5-4f4c-8e21-d2bbf6f9867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566447486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3566447486
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3278602136
Short name T316
Test name
Test status
Simulation time 142113748 ps
CPU time 5.05 seconds
Started Jun 28 04:45:36 PM PDT 24
Finished Jun 28 04:45:42 PM PDT 24
Peak memory 208736 kb
Host smart-077cb6ed-cf56-4a6e-9f3f-e221e69a570f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278602136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3278602136
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3837186782
Short name T749
Test name
Test status
Simulation time 25847906 ps
CPU time 2.03 seconds
Started Jun 28 04:45:29 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 208696 kb
Host smart-5ba81f1c-193c-405f-b18e-5c6eceb28df0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837186782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3837186782
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1823047083
Short name T747
Test name
Test status
Simulation time 138095468 ps
CPU time 3.57 seconds
Started Jun 28 04:45:37 PM PDT 24
Finished Jun 28 04:45:42 PM PDT 24
Peak memory 208348 kb
Host smart-052427cd-de6a-464f-8729-e840f3b8a5b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823047083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1823047083
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1832619586
Short name T714
Test name
Test status
Simulation time 96872204 ps
CPU time 2.81 seconds
Started Jun 28 04:45:38 PM PDT 24
Finished Jun 28 04:45:41 PM PDT 24
Peak memory 208784 kb
Host smart-ebf85ff9-e65e-48fa-be0c-6b99a4b91459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832619586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1832619586
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1310471195
Short name T461
Test name
Test status
Simulation time 299000405 ps
CPU time 5.67 seconds
Started Jun 28 04:45:37 PM PDT 24
Finished Jun 28 04:45:43 PM PDT 24
Peak memory 208308 kb
Host smart-20d3f4b7-1e5b-42b3-b6f2-a1db78db50b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310471195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1310471195
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1639041295
Short name T52
Test name
Test status
Simulation time 649496949 ps
CPU time 6.84 seconds
Started Jun 28 04:45:37 PM PDT 24
Finished Jun 28 04:45:45 PM PDT 24
Peak memory 216388 kb
Host smart-85937da2-d812-4832-b424-84b055471381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639041295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1639041295
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2318741184
Short name T662
Test name
Test status
Simulation time 2572407984 ps
CPU time 63.13 seconds
Started Jun 28 04:45:38 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 222564 kb
Host smart-4a2f8722-e9d9-4aca-9f4e-bd33d52200e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318741184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2318741184
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.831371862
Short name T610
Test name
Test status
Simulation time 25828626 ps
CPU time 0.86 seconds
Started Jun 28 04:45:41 PM PDT 24
Finished Jun 28 04:45:43 PM PDT 24
Peak memory 206064 kb
Host smart-be1df1a2-0e5c-42b7-8807-ff1f7942f14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831371862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.831371862
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1619475532
Short name T348
Test name
Test status
Simulation time 66737102 ps
CPU time 3.15 seconds
Started Jun 28 04:45:36 PM PDT 24
Finished Jun 28 04:45:39 PM PDT 24
Peak memory 221496 kb
Host smart-8023d70d-1937-4d6c-a749-d9bc52119209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619475532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1619475532
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2052582478
Short name T74
Test name
Test status
Simulation time 237246961 ps
CPU time 2.83 seconds
Started Jun 28 04:45:45 PM PDT 24
Finished Jun 28 04:45:49 PM PDT 24
Peak memory 214232 kb
Host smart-0c5acc8f-4427-4fee-9211-16678ef80132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052582478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2052582478
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2659078686
Short name T868
Test name
Test status
Simulation time 108506414 ps
CPU time 2.32 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:46 PM PDT 24
Peak memory 214460 kb
Host smart-3cc04bba-5b5e-481b-a909-bb79501a0cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659078686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2659078686
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1545288022
Short name T476
Test name
Test status
Simulation time 125709825 ps
CPU time 2.28 seconds
Started Jun 28 04:45:42 PM PDT 24
Finished Jun 28 04:45:44 PM PDT 24
Peak memory 214264 kb
Host smart-6176675a-452e-4301-8544-bb43f148771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545288022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1545288022
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4025403993
Short name T350
Test name
Test status
Simulation time 424438108 ps
CPU time 4.06 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 209952 kb
Host smart-c18d440b-a023-4a68-a8f4-89f5a87b06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025403993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4025403993
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.471236415
Short name T684
Test name
Test status
Simulation time 633830863 ps
CPU time 3.84 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:43 PM PDT 24
Peak memory 207924 kb
Host smart-2ce2cb06-0ef9-41d9-a1e6-159a3885c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471236415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.471236415
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4277553207
Short name T457
Test name
Test status
Simulation time 1450828353 ps
CPU time 11.96 seconds
Started Jun 28 04:45:34 PM PDT 24
Finished Jun 28 04:45:46 PM PDT 24
Peak memory 207016 kb
Host smart-575861df-0632-4f09-93e9-318689daaa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277553207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4277553207
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1599763547
Short name T489
Test name
Test status
Simulation time 266509364 ps
CPU time 4.47 seconds
Started Jun 28 04:45:44 PM PDT 24
Finished Jun 28 04:45:49 PM PDT 24
Peak memory 207340 kb
Host smart-0e238c59-094e-407b-8b9b-1a2a59138f07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599763547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1599763547
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1608407851
Short name T853
Test name
Test status
Simulation time 150174942 ps
CPU time 4.39 seconds
Started Jun 28 04:45:40 PM PDT 24
Finished Jun 28 04:45:45 PM PDT 24
Peak memory 208648 kb
Host smart-82cc61a1-5de8-4a94-946e-50f870d72a33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608407851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1608407851
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3366568969
Short name T295
Test name
Test status
Simulation time 230369429 ps
CPU time 3.91 seconds
Started Jun 28 04:45:36 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 206856 kb
Host smart-70aeef05-75b8-483f-9dc4-394719848271
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366568969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3366568969
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4076361778
Short name T271
Test name
Test status
Simulation time 71367839 ps
CPU time 2.08 seconds
Started Jun 28 04:45:38 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 208988 kb
Host smart-8d65f669-a8b5-4d5b-b2aa-2b2034e41f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076361778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4076361778
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3437423314
Short name T589
Test name
Test status
Simulation time 249047465 ps
CPU time 2.86 seconds
Started Jun 28 04:45:44 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 208732 kb
Host smart-ef6af843-7e3f-4549-b318-839519bbdaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437423314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3437423314
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2292348510
Short name T776
Test name
Test status
Simulation time 6907906275 ps
CPU time 150.24 seconds
Started Jun 28 04:45:42 PM PDT 24
Finished Jun 28 04:48:13 PM PDT 24
Peak memory 217112 kb
Host smart-739b325f-5a7a-4217-b0c6-f3facd1c1a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292348510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2292348510
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3140821377
Short name T491
Test name
Test status
Simulation time 3153399381 ps
CPU time 22.96 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 210412 kb
Host smart-69cb8153-b53d-4986-8829-1994aa7f0623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140821377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3140821377
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2832596818
Short name T483
Test name
Test status
Simulation time 172617443 ps
CPU time 2.23 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:42 PM PDT 24
Peak memory 208924 kb
Host smart-25176a66-4995-4e97-93f8-39495dbaff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832596818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2832596818
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2884298533
Short name T101
Test name
Test status
Simulation time 80909843 ps
CPU time 0.76 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:41 PM PDT 24
Peak memory 206048 kb
Host smart-c049f6c2-9ef1-489a-9309-426cde6321c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884298533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2884298533
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3410692525
Short name T744
Test name
Test status
Simulation time 174856314 ps
CPU time 3.49 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 222740 kb
Host smart-8ed02c3a-c3dd-4941-91fc-09b678246076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410692525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3410692525
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2834747379
Short name T639
Test name
Test status
Simulation time 103860753 ps
CPU time 1.65 seconds
Started Jun 28 04:45:38 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 209304 kb
Host smart-c9eff5f6-bb82-455a-b14a-f8a96c87b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834747379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2834747379
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3386755242
Short name T645
Test name
Test status
Simulation time 355183274 ps
CPU time 4.73 seconds
Started Jun 28 04:45:44 PM PDT 24
Finished Jun 28 04:45:49 PM PDT 24
Peak memory 215052 kb
Host smart-cf54d57e-daaf-4bfc-8a94-f77bc88b75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386755242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3386755242
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4153575657
Short name T306
Test name
Test status
Simulation time 57399988 ps
CPU time 2.26 seconds
Started Jun 28 04:45:45 PM PDT 24
Finished Jun 28 04:45:48 PM PDT 24
Peak memory 219140 kb
Host smart-3ad67f86-b44d-4fd3-9e98-52bb573ebb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153575657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4153575657
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1771712935
Short name T844
Test name
Test status
Simulation time 190969273 ps
CPU time 4.68 seconds
Started Jun 28 04:45:45 PM PDT 24
Finished Jun 28 04:45:51 PM PDT 24
Peak memory 218600 kb
Host smart-b1675af7-618a-4ecc-a8fe-1f9fcf7048f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771712935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1771712935
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4222099467
Short name T277
Test name
Test status
Simulation time 219147692 ps
CPU time 4.32 seconds
Started Jun 28 04:45:38 PM PDT 24
Finished Jun 28 04:45:43 PM PDT 24
Peak memory 207164 kb
Host smart-83244b9a-183a-466a-a336-b86ed1bd4e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222099467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4222099467
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2227034492
Short name T449
Test name
Test status
Simulation time 233980918 ps
CPU time 3.13 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:46 PM PDT 24
Peak memory 208292 kb
Host smart-beb002e3-a2ae-4826-83b3-aecacbaece92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227034492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2227034492
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1692090319
Short name T739
Test name
Test status
Simulation time 142031433 ps
CPU time 3.56 seconds
Started Jun 28 04:45:45 PM PDT 24
Finished Jun 28 04:45:49 PM PDT 24
Peak memory 208252 kb
Host smart-db8c501e-35ca-4bd2-84ee-066e97dd28af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692090319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1692090319
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.852255954
Short name T506
Test name
Test status
Simulation time 389527862 ps
CPU time 5.16 seconds
Started Jun 28 04:45:45 PM PDT 24
Finished Jun 28 04:45:51 PM PDT 24
Peak memory 207728 kb
Host smart-f9b41015-45e0-41a1-855e-e0d145b9a890
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852255954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.852255954
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3120072772
Short name T470
Test name
Test status
Simulation time 1531154686 ps
CPU time 4.05 seconds
Started Jun 28 04:45:40 PM PDT 24
Finished Jun 28 04:45:45 PM PDT 24
Peak memory 207116 kb
Host smart-880505dc-0ca4-4b7c-b468-adf282b7f0c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120072772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3120072772
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2874689178
Short name T106
Test name
Test status
Simulation time 434558831 ps
CPU time 3.69 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 208396 kb
Host smart-032c5643-4b8a-4774-bc4e-6f18536bf339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874689178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2874689178
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1588156226
Short name T738
Test name
Test status
Simulation time 388663857 ps
CPU time 3.86 seconds
Started Jun 28 04:45:43 PM PDT 24
Finished Jun 28 04:45:48 PM PDT 24
Peak memory 208420 kb
Host smart-9356260f-5df7-4057-96dc-c219a9a21175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588156226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1588156226
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3632803790
Short name T296
Test name
Test status
Simulation time 5778953447 ps
CPU time 51.58 seconds
Started Jun 28 04:45:41 PM PDT 24
Finished Jun 28 04:46:33 PM PDT 24
Peak memory 216344 kb
Host smart-ea3ab6d6-8c62-44a4-8d8c-0414cf6df1f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632803790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3632803790
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.874338587
Short name T105
Test name
Test status
Simulation time 582122307 ps
CPU time 24.04 seconds
Started Jun 28 04:45:45 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 222600 kb
Host smart-ce918ff7-328b-4f43-976d-fb467c46940c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874338587 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.874338587
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3540766304
Short name T564
Test name
Test status
Simulation time 288880087 ps
CPU time 7.66 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 208704 kb
Host smart-e7bd1ac8-add7-4ecd-a4ad-97ade6362f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540766304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3540766304
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3667317527
Short name T873
Test name
Test status
Simulation time 540421062 ps
CPU time 13.62 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:54 PM PDT 24
Peak memory 210964 kb
Host smart-b4223621-f92e-4c19-badc-31f1ce6c0708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667317527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3667317527
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2680785534
Short name T112
Test name
Test status
Simulation time 44849249 ps
CPU time 0.82 seconds
Started Jun 28 04:45:49 PM PDT 24
Finished Jun 28 04:45:50 PM PDT 24
Peak memory 205940 kb
Host smart-ef05701c-e07d-4451-9adb-1ba7598f690f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680785534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2680785534
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1438553378
Short name T245
Test name
Test status
Simulation time 40610633 ps
CPU time 3.06 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 214336 kb
Host smart-48a746ed-80d4-4bad-a546-166793d9ae68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438553378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1438553378
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2904595392
Short name T32
Test name
Test status
Simulation time 334438621 ps
CPU time 1.87 seconds
Started Jun 28 04:45:58 PM PDT 24
Finished Jun 28 04:46:00 PM PDT 24
Peak memory 215448 kb
Host smart-1d4402b2-ded7-4a32-a0b5-0813e6224149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904595392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2904595392
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2520467732
Short name T515
Test name
Test status
Simulation time 2301673458 ps
CPU time 23.71 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:23 PM PDT 24
Peak memory 208488 kb
Host smart-d2abbf7a-0f38-46d5-b141-4851a9deba15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520467732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2520467732
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1608907318
Short name T866
Test name
Test status
Simulation time 102522943 ps
CPU time 1.97 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:53 PM PDT 24
Peak memory 214620 kb
Host smart-12ed3001-9ce3-431f-8d7e-b1fb85174414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608907318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1608907318
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2571746795
Short name T699
Test name
Test status
Simulation time 269089807 ps
CPU time 3.66 seconds
Started Jun 28 04:45:58 PM PDT 24
Finished Jun 28 04:46:02 PM PDT 24
Peak memory 209032 kb
Host smart-c122efd3-2343-44b6-a68d-451636b13efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571746795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2571746795
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.549226116
Short name T269
Test name
Test status
Simulation time 53968482 ps
CPU time 3.15 seconds
Started Jun 28 04:45:54 PM PDT 24
Finished Jun 28 04:45:59 PM PDT 24
Peak memory 218244 kb
Host smart-9108b280-6eaf-4e37-87a5-2fec05e5e1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549226116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.549226116
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3621696111
Short name T81
Test name
Test status
Simulation time 172656715 ps
CPU time 4.34 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 208680 kb
Host smart-87c52292-07c6-4015-915e-c9109c709870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621696111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3621696111
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.361191336
Short name T812
Test name
Test status
Simulation time 309284934 ps
CPU time 2.41 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:45:57 PM PDT 24
Peak memory 206992 kb
Host smart-c010daf1-1c1c-443a-9a26-8dcf1835916d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361191336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.361191336
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3817803419
Short name T813
Test name
Test status
Simulation time 831357102 ps
CPU time 5.56 seconds
Started Jun 28 04:45:57 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 207828 kb
Host smart-ae34bc5f-5d1c-4f31-be42-1da720c049c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817803419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3817803419
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2546840691
Short name T236
Test name
Test status
Simulation time 1561706849 ps
CPU time 37.1 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:46:30 PM PDT 24
Peak memory 208528 kb
Host smart-d70a8c96-5a08-4353-a208-73f96dfc5cee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546840691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2546840691
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2018455268
Short name T906
Test name
Test status
Simulation time 496034741 ps
CPU time 4.25 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 215588 kb
Host smart-01c38ef0-08c4-4a3c-900d-3b6a006e61f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018455268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2018455268
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3738121764
Short name T530
Test name
Test status
Simulation time 664912538 ps
CPU time 3.86 seconds
Started Jun 28 04:45:39 PM PDT 24
Finished Jun 28 04:45:44 PM PDT 24
Peak memory 206948 kb
Host smart-ae69d4c7-c114-4091-9fed-e8193b9c533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738121764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3738121764
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2959931904
Short name T779
Test name
Test status
Simulation time 2590416354 ps
CPU time 8.16 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 218548 kb
Host smart-adbef062-9c3e-49a2-b427-d61b0271d3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959931904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2959931904
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3582341663
Short name T339
Test name
Test status
Simulation time 1043736571 ps
CPU time 18.86 seconds
Started Jun 28 04:45:58 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 222584 kb
Host smart-88e6cc61-f24e-4513-bbd6-cec5b9eb7431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582341663 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3582341663
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1104719808
Short name T917
Test name
Test status
Simulation time 99261648 ps
CPU time 2.81 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 218312 kb
Host smart-88dfcae3-dde1-46b6-a1cb-e1e71b8b2279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104719808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1104719808
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.646075334
Short name T619
Test name
Test status
Simulation time 53020539 ps
CPU time 2.36 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 209868 kb
Host smart-6e313983-521b-44ed-8e31-9eec4e24c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646075334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.646075334
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1672902607
Short name T570
Test name
Test status
Simulation time 21277541 ps
CPU time 0.8 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 205956 kb
Host smart-21946dd0-f6bb-43f5-af13-6f2462233aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672902607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1672902607
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3592618541
Short name T854
Test name
Test status
Simulation time 420851202 ps
CPU time 11.18 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 214260 kb
Host smart-483d2750-c9de-433f-8112-1ee2ea99bd11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592618541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3592618541
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3781834188
Short name T884
Test name
Test status
Simulation time 150531058 ps
CPU time 4.78 seconds
Started Jun 28 04:44:25 PM PDT 24
Finished Jun 28 04:44:30 PM PDT 24
Peak memory 220400 kb
Host smart-df9da221-8caf-41ff-9192-f08362aef0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781834188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3781834188
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3279786468
Short name T500
Test name
Test status
Simulation time 3544832246 ps
CPU time 6.2 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:44:30 PM PDT 24
Peak memory 218288 kb
Host smart-29bf4ecc-9b07-4c57-abc3-4d292ad772b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279786468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3279786468
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.222332158
Short name T86
Test name
Test status
Simulation time 337033552 ps
CPU time 2.95 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:31 PM PDT 24
Peak memory 214224 kb
Host smart-19da2f53-c854-49a1-a46e-de0d0ce86bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222332158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.222332158
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3381228364
Short name T546
Test name
Test status
Simulation time 150992043 ps
CPU time 2.91 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:44:36 PM PDT 24
Peak memory 222496 kb
Host smart-4d24eb5d-1395-407b-abb5-c912f6c58144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381228364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3381228364
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1235073948
Short name T607
Test name
Test status
Simulation time 323016914 ps
CPU time 2.46 seconds
Started Jun 28 04:44:26 PM PDT 24
Finished Jun 28 04:44:30 PM PDT 24
Peak memory 220112 kb
Host smart-da52aa43-9913-45f9-8baf-8fc61a0e4fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235073948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1235073948
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3127997546
Short name T367
Test name
Test status
Simulation time 3462317931 ps
CPU time 46.13 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:45:14 PM PDT 24
Peak memory 218312 kb
Host smart-3b885629-3c87-4aed-8e56-7af0d9ce7d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127997546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3127997546
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2006713826
Short name T104
Test name
Test status
Simulation time 531306922 ps
CPU time 6.33 seconds
Started Jun 28 04:44:26 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 234904 kb
Host smart-e82c91a8-00b8-4996-9048-15657dd5cfae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006713826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2006713826
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3731385365
Short name T791
Test name
Test status
Simulation time 1077618027 ps
CPU time 21.49 seconds
Started Jun 28 04:44:25 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 208364 kb
Host smart-3349dedc-3b11-4d8b-87c9-a5e04a7e5b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731385365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3731385365
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3280700976
Short name T533
Test name
Test status
Simulation time 161153112 ps
CPU time 4.89 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 208476 kb
Host smart-a249fb72-9523-4bd5-a538-b70335d581b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280700976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3280700976
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1101375098
Short name T706
Test name
Test status
Simulation time 351159842 ps
CPU time 7.55 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:38 PM PDT 24
Peak memory 208796 kb
Host smart-933d8bac-2296-4a60-ac0d-40ec981aac5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101375098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1101375098
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2072319764
Short name T651
Test name
Test status
Simulation time 36185310 ps
CPU time 2.55 seconds
Started Jun 28 04:44:25 PM PDT 24
Finished Jun 28 04:44:29 PM PDT 24
Peak memory 208248 kb
Host smart-17f24e50-3cd7-4f8a-b8d3-2794d393c218
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072319764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2072319764
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1073057746
Short name T517
Test name
Test status
Simulation time 52542348 ps
CPU time 2.46 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 208996 kb
Host smart-531fc2f1-a0a8-4de2-a293-2a7ca3f95615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073057746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1073057746
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.835347678
Short name T393
Test name
Test status
Simulation time 84748784 ps
CPU time 2.47 seconds
Started Jun 28 04:44:18 PM PDT 24
Finished Jun 28 04:44:24 PM PDT 24
Peak memory 206252 kb
Host smart-707da171-5f1c-4027-b91c-b4e6bf36a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835347678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.835347678
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1007970545
Short name T215
Test name
Test status
Simulation time 890811073 ps
CPU time 19.64 seconds
Started Jun 28 04:44:24 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 222296 kb
Host smart-e5e482a8-7d65-4edc-9c12-449eda64aae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007970545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1007970545
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.428245579
Short name T239
Test name
Test status
Simulation time 2165676463 ps
CPU time 71.74 seconds
Started Jun 28 04:44:26 PM PDT 24
Finished Jun 28 04:45:39 PM PDT 24
Peak memory 214312 kb
Host smart-9f830475-5798-4990-83c4-b72a500bc01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428245579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.428245579
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.194550124
Short name T429
Test name
Test status
Simulation time 27285008 ps
CPU time 1.54 seconds
Started Jun 28 04:44:24 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 209620 kb
Host smart-762d7438-8c75-4774-9f58-290374bdf17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194550124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.194550124
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.6932770
Short name T633
Test name
Test status
Simulation time 23054335 ps
CPU time 0.89 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:52 PM PDT 24
Peak memory 206052 kb
Host smart-ce3e82d4-26dd-456b-b46b-89d542d64e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6932770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.6932770
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2258011634
Short name T542
Test name
Test status
Simulation time 64781674 ps
CPU time 2.5 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:54 PM PDT 24
Peak memory 221680 kb
Host smart-532f9d72-dfbb-4437-88b0-2c693ff5b788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258011634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2258011634
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.327092988
Short name T522
Test name
Test status
Simulation time 179569851 ps
CPU time 2.25 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 208508 kb
Host smart-81814585-e7dc-4c34-9b21-a7e1688ee4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327092988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.327092988
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.319854309
Short name T912
Test name
Test status
Simulation time 105376753 ps
CPU time 3.63 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 214268 kb
Host smart-8de050cc-9b79-4ee8-9462-cd391679f415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319854309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.319854309
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2913724053
Short name T664
Test name
Test status
Simulation time 372849794 ps
CPU time 2.78 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:02 PM PDT 24
Peak memory 214336 kb
Host smart-158e6185-1c38-41a0-bde2-57b5bbdd966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913724053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2913724053
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.815844142
Short name T860
Test name
Test status
Simulation time 609392717 ps
CPU time 7.54 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:01 PM PDT 24
Peak memory 218340 kb
Host smart-0d9d9040-d076-4160-97a8-3c5e152bb413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815844142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.815844142
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2015223288
Short name T370
Test name
Test status
Simulation time 370306518 ps
CPU time 10.01 seconds
Started Jun 28 04:45:48 PM PDT 24
Finished Jun 28 04:45:59 PM PDT 24
Peak memory 208424 kb
Host smart-e76b0846-f670-4faa-8c1e-ae8516ec7df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015223288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2015223288
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.954911491
Short name T87
Test name
Test status
Simulation time 98435352 ps
CPU time 3.22 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 207992 kb
Host smart-ebf178a2-6318-4ee9-98c4-ebc47885595f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954911491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.954911491
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1457614332
Short name T458
Test name
Test status
Simulation time 234987293 ps
CPU time 3.28 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 206960 kb
Host smart-feb81ccd-e03a-4ef6-8d6c-e9a319d06583
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457614332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1457614332
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2417028106
Short name T869
Test name
Test status
Simulation time 571844019 ps
CPU time 4.77 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:46:00 PM PDT 24
Peak memory 207968 kb
Host smart-c9c0b8a0-5c05-4133-a320-87cc2eff49bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417028106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2417028106
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1193654180
Short name T259
Test name
Test status
Simulation time 105475321 ps
CPU time 2.9 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 215564 kb
Host smart-f19ae3ab-2afd-408c-a5c1-8145e66bab90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193654180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1193654180
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3617004711
Short name T882
Test name
Test status
Simulation time 110469816 ps
CPU time 2.43 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 206768 kb
Host smart-33829c0f-0495-43d2-80e1-29fc80b34661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617004711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3617004711
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3988442231
Short name T241
Test name
Test status
Simulation time 3129380101 ps
CPU time 21.98 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 222496 kb
Host smart-83b3d692-b70d-49b2-9ac1-707d9cb74ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988442231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3988442231
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1707748986
Short name T660
Test name
Test status
Simulation time 236921031 ps
CPU time 12.01 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 222568 kb
Host smart-a9a3acde-f3cf-4f5e-978a-1d68ceafd46b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707748986 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1707748986
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3792575458
Short name T472
Test name
Test status
Simulation time 697916085 ps
CPU time 9.23 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 210104 kb
Host smart-41bc7569-b2c5-4d82-9503-7608da098d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792575458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3792575458
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.569055908
Short name T708
Test name
Test status
Simulation time 1269444947 ps
CPU time 14.63 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 210892 kb
Host smart-b1bddec8-3fa6-41e1-a4e4-2de9b193a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569055908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.569055908
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.4106465017
Short name T643
Test name
Test status
Simulation time 12385337 ps
CPU time 0.75 seconds
Started Jun 28 04:45:56 PM PDT 24
Finished Jun 28 04:45:57 PM PDT 24
Peak memory 206084 kb
Host smart-4f2e9277-b5b3-496e-9634-3b00108743d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106465017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.4106465017
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3230506506
Short name T255
Test name
Test status
Simulation time 319160212 ps
CPU time 4.5 seconds
Started Jun 28 04:45:58 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 208948 kb
Host smart-a6ad3f9c-c346-4e42-85d7-5b8a025208ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230506506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3230506506
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1152510643
Short name T895
Test name
Test status
Simulation time 150496725 ps
CPU time 3.37 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:45:58 PM PDT 24
Peak memory 214328 kb
Host smart-9a6c281b-677a-46d4-9fb2-62bd6983bfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152510643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1152510643
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.621158518
Short name T808
Test name
Test status
Simulation time 261417168 ps
CPU time 5.87 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:11 PM PDT 24
Peak memory 208992 kb
Host smart-151c97be-c3c5-4526-90c7-e408aaf95599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621158518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.621158518
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.4246085473
Short name T41
Test name
Test status
Simulation time 233458002 ps
CPU time 3.16 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 214824 kb
Host smart-7a91d73c-b4e5-4071-978e-626233023c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246085473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4246085473
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3899753727
Short name T211
Test name
Test status
Simulation time 39198869 ps
CPU time 2.62 seconds
Started Jun 28 04:46:04 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 219760 kb
Host smart-8a13f97f-accb-4536-879b-282759bc80b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899753727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3899753727
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3049242985
Short name T511
Test name
Test status
Simulation time 63862683 ps
CPU time 3.95 seconds
Started Jun 28 04:45:49 PM PDT 24
Finished Jun 28 04:45:54 PM PDT 24
Peak memory 207400 kb
Host smart-dcbee9fd-8d68-4c93-9a90-b7333f909f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049242985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3049242985
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3718950015
Short name T640
Test name
Test status
Simulation time 326766705 ps
CPU time 6.99 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:46:02 PM PDT 24
Peak memory 208200 kb
Host smart-f1592494-ff88-4675-8727-bf80491fa8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718950015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3718950015
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3209592771
Short name T887
Test name
Test status
Simulation time 126129133 ps
CPU time 2.46 seconds
Started Jun 28 04:45:56 PM PDT 24
Finished Jun 28 04:45:59 PM PDT 24
Peak memory 206992 kb
Host smart-59eb37f3-1cce-4419-bd8e-a9e9e2d8f2f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209592771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3209592771
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3987843831
Short name T394
Test name
Test status
Simulation time 185586782 ps
CPU time 2.26 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 206876 kb
Host smart-8f94963c-30ab-44be-ba75-516353d0f85b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987843831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3987843831
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1873273958
Short name T486
Test name
Test status
Simulation time 2333738013 ps
CPU time 32.42 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 208240 kb
Host smart-99ef48ca-77b9-4484-b3c2-9bc7fef893e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873273958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1873273958
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.533208355
Short name T539
Test name
Test status
Simulation time 272808831 ps
CPU time 1.86 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:53 PM PDT 24
Peak memory 215696 kb
Host smart-f9ac7dea-7d05-498e-9349-644c953a1e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533208355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.533208355
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.383828398
Short name T400
Test name
Test status
Simulation time 539271499 ps
CPU time 3.7 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 207080 kb
Host smart-199930c1-6a3a-40e2-bc43-1ab6d68fde35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383828398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.383828398
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.4228335677
Short name T675
Test name
Test status
Simulation time 813749230 ps
CPU time 11.81 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 216276 kb
Host smart-ebc5bea8-74e3-443b-8c6c-1a7a08249596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228335677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.4228335677
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.130847528
Short name T669
Test name
Test status
Simulation time 18988090712 ps
CPU time 44.28 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 209792 kb
Host smart-9e2e3500-23d9-4326-a261-e7778da30b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130847528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.130847528
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3243480780
Short name T571
Test name
Test status
Simulation time 42309680 ps
CPU time 1.97 seconds
Started Jun 28 04:45:50 PM PDT 24
Finished Jun 28 04:45:53 PM PDT 24
Peak memory 209528 kb
Host smart-6f20d27b-4b01-4343-8d03-9c455ec689ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243480780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3243480780
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1878322436
Short name T888
Test name
Test status
Simulation time 16527323 ps
CPU time 0.8 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 205952 kb
Host smart-26cb5c75-b2c0-4754-8f01-f257e8fcba04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878322436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1878322436
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3424788088
Short name T129
Test name
Test status
Simulation time 51775714 ps
CPU time 3.75 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 214312 kb
Host smart-8137e5e8-90c5-4d1b-83ca-474d57f04f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424788088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3424788088
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1281864235
Short name T201
Test name
Test status
Simulation time 73783879 ps
CPU time 1.44 seconds
Started Jun 28 04:45:56 PM PDT 24
Finished Jun 28 04:45:58 PM PDT 24
Peak memory 220264 kb
Host smart-fdba4901-ede1-4d84-94fb-4bf5e6ab9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281864235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1281864235
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.479537837
Short name T528
Test name
Test status
Simulation time 96049654 ps
CPU time 2.77 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:04 PM PDT 24
Peak memory 208128 kb
Host smart-d080252f-de22-4878-937d-9422ff042a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479537837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.479537837
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.169191562
Short name T340
Test name
Test status
Simulation time 1433578574 ps
CPU time 18.6 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 219160 kb
Host smart-e175af7b-e619-43ea-abc2-3b654fcb4453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169191562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.169191562
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.326167059
Short name T849
Test name
Test status
Simulation time 1363866035 ps
CPU time 8.87 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:12 PM PDT 24
Peak memory 214356 kb
Host smart-bb83a8b6-b563-4c17-89bc-08e7ce96ff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326167059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.326167059
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2288273125
Short name T711
Test name
Test status
Simulation time 39487706 ps
CPU time 2.78 seconds
Started Jun 28 04:45:55 PM PDT 24
Finished Jun 28 04:45:59 PM PDT 24
Peak memory 222460 kb
Host smart-da68d0fb-9938-4989-9455-24257de5cf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288273125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2288273125
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.93507928
Short name T680
Test name
Test status
Simulation time 879489311 ps
CPU time 6.55 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:46:01 PM PDT 24
Peak memory 208016 kb
Host smart-255c0c8c-a017-4715-aa6d-a1664e7d0394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93507928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.93507928
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.967700763
Short name T799
Test name
Test status
Simulation time 350939977 ps
CPU time 5.53 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:00 PM PDT 24
Peak memory 208968 kb
Host smart-42bde5ae-686f-4ca1-bbfb-b101d1c13377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967700763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.967700763
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.817069371
Short name T548
Test name
Test status
Simulation time 70946423 ps
CPU time 2.25 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 207540 kb
Host smart-c0baca48-01fc-477d-be88-d28a62304faa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817069371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.817069371
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1827990799
Short name T659
Test name
Test status
Simulation time 61730469 ps
CPU time 2.97 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:45:57 PM PDT 24
Peak memory 208632 kb
Host smart-f141070d-0224-49e0-a48a-f4ddb68ab525
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827990799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1827990799
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2934706631
Short name T448
Test name
Test status
Simulation time 80895801 ps
CPU time 2.78 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:45:58 PM PDT 24
Peak memory 208896 kb
Host smart-6e409595-fd50-4d19-9472-eadd515ee881
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934706631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2934706631
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.493257466
Short name T396
Test name
Test status
Simulation time 377382195 ps
CPU time 7.41 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 215196 kb
Host smart-a5f16850-02d8-4a57-be1d-c35a4e104559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493257466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.493257466
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1225341384
Short name T871
Test name
Test status
Simulation time 1502453350 ps
CPU time 24.88 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 207760 kb
Host smart-15b7a478-5de0-4a1e-8c73-7f5bdb9b677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225341384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1225341384
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3666055127
Short name T283
Test name
Test status
Simulation time 1139946230 ps
CPU time 12.17 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 222500 kb
Host smart-05f070f8-1f8c-4d53-9b09-2883b1137e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666055127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3666055127
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3038130040
Short name T503
Test name
Test status
Simulation time 205448248 ps
CPU time 12.06 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 222688 kb
Host smart-f2de4119-da44-408d-80e0-7c579b26c7d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038130040 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3038130040
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3023615804
Short name T890
Test name
Test status
Simulation time 593027785 ps
CPU time 7.39 seconds
Started Jun 28 04:45:54 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 208692 kb
Host smart-af596638-1ab8-4862-adf3-c681853a7f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023615804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3023615804
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1256749212
Short name T49
Test name
Test status
Simulation time 83286611 ps
CPU time 2.91 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:45:57 PM PDT 24
Peak memory 210936 kb
Host smart-3372ad25-ead7-468b-8281-beba4c205008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256749212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1256749212
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.305555847
Short name T507
Test name
Test status
Simulation time 12958023 ps
CPU time 0.78 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:00 PM PDT 24
Peak memory 205956 kb
Host smart-626dd488-9786-4cd5-a9f6-1a45a443223e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305555847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.305555847
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1676144483
Short name T404
Test name
Test status
Simulation time 233210485 ps
CPU time 4.36 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 214852 kb
Host smart-2520a2aa-61fb-4689-8fd3-34a88e295b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676144483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1676144483
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1099413425
Short name T45
Test name
Test status
Simulation time 148034332 ps
CPU time 4.14 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:11 PM PDT 24
Peak memory 209052 kb
Host smart-2e904236-781b-44bf-80a7-8c651e0a8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099413425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1099413425
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2075969281
Short name T742
Test name
Test status
Simulation time 417151887 ps
CPU time 6.59 seconds
Started Jun 28 04:46:04 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 214216 kb
Host smart-25314764-15bd-4428-b584-8158203955d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075969281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2075969281
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1015181580
Short name T441
Test name
Test status
Simulation time 107657919 ps
CPU time 2.45 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:04 PM PDT 24
Peak memory 214176 kb
Host smart-dc69e0ff-c60a-468a-9076-054bb57f399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015181580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1015181580
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.922752525
Short name T358
Test name
Test status
Simulation time 89828764 ps
CPU time 2.35 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 215368 kb
Host smart-4a50dda8-a6e3-4768-8b38-280c143af0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922752525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.922752525
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3086061549
Short name T620
Test name
Test status
Simulation time 132406430 ps
CPU time 2.24 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 214216 kb
Host smart-bd7de148-9022-4ad9-8809-32e266d38602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086061549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3086061549
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.507365373
Short name T390
Test name
Test status
Simulation time 157848038 ps
CPU time 4.07 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:57 PM PDT 24
Peak memory 207684 kb
Host smart-596a6b93-341d-4925-bd0b-fa38af7204c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507365373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.507365373
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3538935492
Short name T899
Test name
Test status
Simulation time 191252104 ps
CPU time 2.42 seconds
Started Jun 28 04:45:52 PM PDT 24
Finished Jun 28 04:45:56 PM PDT 24
Peak memory 206884 kb
Host smart-37b24721-d222-4974-abd1-4015aba9ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538935492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3538935492
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1085605841
Short name T443
Test name
Test status
Simulation time 31877196 ps
CPU time 2.35 seconds
Started Jun 28 04:45:51 PM PDT 24
Finished Jun 28 04:45:55 PM PDT 24
Peak memory 206932 kb
Host smart-8f66cbd1-e463-4763-be90-5823127ca7cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085605841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1085605841
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2802137873
Short name T285
Test name
Test status
Simulation time 1609657630 ps
CPU time 16.32 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 208672 kb
Host smart-5643ba00-23e2-480c-824c-2110253e0fea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802137873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2802137873
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2996929802
Short name T195
Test name
Test status
Simulation time 101607705 ps
CPU time 3.98 seconds
Started Jun 28 04:45:53 PM PDT 24
Finished Jun 28 04:45:59 PM PDT 24
Peak memory 206764 kb
Host smart-13d6b8b6-b522-4ac0-bbc6-2ffb826ede7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996929802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2996929802
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1986703858
Short name T604
Test name
Test status
Simulation time 279158110 ps
CPU time 2.63 seconds
Started Jun 28 04:46:09 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 208664 kb
Host smart-a5023908-69a6-4910-a5fa-9148c9139279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986703858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1986703858
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.610723127
Short name T398
Test name
Test status
Simulation time 134627543 ps
CPU time 3.57 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 206676 kb
Host smart-5cea850b-8b04-4c18-8de3-a336e12f7c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610723127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.610723127
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2727452837
Short name T361
Test name
Test status
Simulation time 539403088 ps
CPU time 4.66 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 214220 kb
Host smart-3bbd0be1-82d3-491c-b1aa-448764130775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727452837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2727452837
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3002254950
Short name T642
Test name
Test status
Simulation time 150041079 ps
CPU time 2.42 seconds
Started Jun 28 04:45:59 PM PDT 24
Finished Jun 28 04:46:02 PM PDT 24
Peak memory 210048 kb
Host smart-e71621ac-65e5-4508-b588-6e59f3744e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002254950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3002254950
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1061063606
Short name T667
Test name
Test status
Simulation time 18284022 ps
CPU time 0.88 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 206048 kb
Host smart-6aa549e9-cb4d-49d4-9ba9-06c736d61df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061063606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1061063606
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.4045486701
Short name T126
Test name
Test status
Simulation time 139412898 ps
CPU time 2.82 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 214060 kb
Host smart-2c4cf668-2b93-44e5-92d1-1ad6bbd1de42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045486701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.4045486701
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.280810407
Short name T372
Test name
Test status
Simulation time 130216298 ps
CPU time 3.87 seconds
Started Jun 28 04:45:58 PM PDT 24
Finished Jun 28 04:46:03 PM PDT 24
Peak memory 207784 kb
Host smart-9d0fddb0-4d6b-4cee-b15d-dec887ffe3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280810407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.280810407
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2825136204
Short name T243
Test name
Test status
Simulation time 1189451001 ps
CPU time 5.5 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 208856 kb
Host smart-f826d1d5-3fd6-4e83-b587-01b2fb6a95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825136204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2825136204
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2622753069
Short name T408
Test name
Test status
Simulation time 96390800 ps
CPU time 4.46 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 220264 kb
Host smart-154bf423-cb4f-41a6-bcb4-699c486ef665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622753069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2622753069
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.357006803
Short name T299
Test name
Test status
Simulation time 180535746 ps
CPU time 4.11 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 209848 kb
Host smart-be09b75a-ecf4-46b9-ae47-9951126ee5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357006803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.357006803
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.145356461
Short name T172
Test name
Test status
Simulation time 65816836 ps
CPU time 1.72 seconds
Started Jun 28 04:46:06 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 206892 kb
Host smart-39fc0064-bbec-480b-8115-b1b6ccdef54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145356461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.145356461
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3481313243
Short name T342
Test name
Test status
Simulation time 154124678 ps
CPU time 3.03 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 208720 kb
Host smart-45356169-2a6e-4110-84fb-0a000473eb98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481313243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3481313243
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.830295684
Short name T445
Test name
Test status
Simulation time 166570018 ps
CPU time 4.99 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 208804 kb
Host smart-a2c042b8-f14c-41f3-8010-0500132a122e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830295684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.830295684
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1330601861
Short name T918
Test name
Test status
Simulation time 434758236 ps
CPU time 3.74 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:11 PM PDT 24
Peak memory 206836 kb
Host smart-783332c4-06ce-495c-8d1f-4da7e036d999
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330601861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1330601861
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3094275779
Short name T198
Test name
Test status
Simulation time 2816765921 ps
CPU time 29.54 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:32 PM PDT 24
Peak memory 222544 kb
Host smart-c89331bc-117a-4858-aad1-5133214315c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094275779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3094275779
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1454469937
Short name T3
Test name
Test status
Simulation time 1360991346 ps
CPU time 3.66 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 208480 kb
Host smart-5b1977ce-057f-4a21-8876-df84ef815608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454469937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1454469937
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3166205729
Short name T287
Test name
Test status
Simulation time 830088356 ps
CPU time 5.09 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 209680 kb
Host smart-b971484b-dea6-4c60-b3ca-75ddb4a85d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166205729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3166205729
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3257969474
Short name T61
Test name
Test status
Simulation time 393841723 ps
CPU time 2.59 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 210032 kb
Host smart-4609a980-72ab-4de8-8cf0-4cee865dd98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257969474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3257969474
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1322184077
Short name T688
Test name
Test status
Simulation time 30540764 ps
CPU time 0.75 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 206048 kb
Host smart-932a54a8-1fe6-45ca-b522-68efd1c3ca81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322184077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1322184077
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3176927308
Short name T318
Test name
Test status
Simulation time 245249316 ps
CPU time 4.74 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 215444 kb
Host smart-0a8c6b07-4602-43b7-8363-edd9f0a76978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176927308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3176927308
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1047233748
Short name T658
Test name
Test status
Simulation time 69544117 ps
CPU time 1.69 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 216540 kb
Host smart-ece48485-4a4c-4ac3-99c8-481df696d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047233748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1047233748
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.963650153
Short name T70
Test name
Test status
Simulation time 76826138 ps
CPU time 2.79 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 214320 kb
Host smart-2a75fad7-da81-451f-b3ea-963761a66bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963650153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.963650153
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2519228094
Short name T833
Test name
Test status
Simulation time 456526157 ps
CPU time 2.77 seconds
Started Jun 28 04:46:08 PM PDT 24
Finished Jun 28 04:46:11 PM PDT 24
Peak memory 214332 kb
Host smart-0eff2035-ba91-401b-bf4e-98b4c4fd719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519228094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2519228094
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2561383161
Short name T478
Test name
Test status
Simulation time 72747430 ps
CPU time 3.49 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 209780 kb
Host smart-a78c76d1-1969-49d0-802b-68912060fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561383161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2561383161
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2218246193
Short name T838
Test name
Test status
Simulation time 335147545 ps
CPU time 4.55 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 208188 kb
Host smart-7c78ba3b-3186-41dd-8442-0c6ff6339abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218246193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2218246193
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.650084592
Short name T435
Test name
Test status
Simulation time 772634640 ps
CPU time 5.45 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 208748 kb
Host smart-a7d2e8fd-be3d-450b-944b-84d5a2e71706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650084592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.650084592
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2219608430
Short name T455
Test name
Test status
Simulation time 36958860 ps
CPU time 2.73 seconds
Started Jun 28 04:46:06 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 208944 kb
Host smart-689d2ef9-d3dc-43e6-9f6b-1dd32746465f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219608430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2219608430
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3805940950
Short name T673
Test name
Test status
Simulation time 1499703328 ps
CPU time 27.85 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:30 PM PDT 24
Peak memory 209184 kb
Host smart-818bafca-ce1c-430e-aa5c-2cbec96b7a3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805940950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3805940950
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.53686802
Short name T196
Test name
Test status
Simulation time 31655311 ps
CPU time 2.39 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 207000 kb
Host smart-9151aee2-1435-4f5d-8ee2-1ca40d93867a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53686802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.53686802
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2453163867
Short name T916
Test name
Test status
Simulation time 130622863 ps
CPU time 1.94 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 209768 kb
Host smart-07d333d4-6f7f-4136-b61e-5e90a09740fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453163867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2453163867
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3573797037
Short name T82
Test name
Test status
Simulation time 43983084 ps
CPU time 2.23 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 208268 kb
Host smart-8d488068-803e-4a1c-a001-f24eb6067c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573797037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3573797037
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2153683063
Short name T290
Test name
Test status
Simulation time 2004516902 ps
CPU time 23.38 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 220760 kb
Host smart-24e5b7f3-795c-4565-9d80-ae304d3ec2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153683063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2153683063
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4186782539
Short name T861
Test name
Test status
Simulation time 113985309 ps
CPU time 4.23 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 208744 kb
Host smart-7b9ee82a-9b2e-4160-91f4-c3a83acd8364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186782539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4186782539
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2711848544
Short name T164
Test name
Test status
Simulation time 112984144 ps
CPU time 2.94 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 210424 kb
Host smart-2eb8cb25-9058-4121-a153-5df30274654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711848544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2711848544
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1013234554
Short name T698
Test name
Test status
Simulation time 45643228 ps
CPU time 0.87 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 206044 kb
Host smart-b2828942-e4cd-4ec3-95a8-46c9323f508b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013234554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1013234554
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2266896681
Short name T403
Test name
Test status
Simulation time 58718247 ps
CPU time 3.95 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 214496 kb
Host smart-92ba3852-647f-4c5f-bc99-1255643c6710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266896681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2266896681
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2138002714
Short name T878
Test name
Test status
Simulation time 731805247 ps
CPU time 4.09 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:06 PM PDT 24
Peak memory 220340 kb
Host smart-463007c3-25e5-4dc8-94dc-d2e381900a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138002714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2138002714
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2179905456
Short name T725
Test name
Test status
Simulation time 39443710 ps
CPU time 1.98 seconds
Started Jun 28 04:46:06 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 218320 kb
Host smart-7bf5919c-49da-4ddb-b527-a25e02841457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179905456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2179905456
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2838522487
Short name T97
Test name
Test status
Simulation time 1751737377 ps
CPU time 31.73 seconds
Started Jun 28 04:46:10 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 209804 kb
Host smart-381e827b-6d00-40ab-904d-11e1aad1fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838522487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2838522487
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2831131206
Short name T15
Test name
Test status
Simulation time 164827298 ps
CPU time 3.17 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 214368 kb
Host smart-bd4be73a-7fa6-4bbb-b801-6169d2dd755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831131206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2831131206
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.521116665
Short name T53
Test name
Test status
Simulation time 129550928 ps
CPU time 3.58 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 214236 kb
Host smart-0c1b93de-a7d3-4638-b7ef-524f282a481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521116665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.521116665
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.451183903
Short name T896
Test name
Test status
Simulation time 1332372931 ps
CPU time 23.35 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:27 PM PDT 24
Peak memory 209496 kb
Host smart-0efd0b6f-eb33-4d17-9ef5-2fe4cb034286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451183903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.451183903
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3983695443
Short name T85
Test name
Test status
Simulation time 405995655 ps
CPU time 6.83 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 208872 kb
Host smart-f49bb0a8-7ec3-4414-8cb7-605eda0680e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983695443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3983695443
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3143029818
Short name T430
Test name
Test status
Simulation time 312683425 ps
CPU time 4.59 seconds
Started Jun 28 04:46:11 PM PDT 24
Finished Jun 28 04:46:16 PM PDT 24
Peak memory 208604 kb
Host smart-d0109a81-6c20-4a6e-a57d-e47288f873f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143029818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3143029818
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3561130230
Short name T818
Test name
Test status
Simulation time 427972277 ps
CPU time 11.11 seconds
Started Jun 28 04:46:07 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 207972 kb
Host smart-9f28e082-7906-43fb-b7ed-ee24ab7b6bcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561130230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3561130230
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3648957787
Short name T661
Test name
Test status
Simulation time 926513890 ps
CPU time 8.29 seconds
Started Jun 28 04:46:01 PM PDT 24
Finished Jun 28 04:46:12 PM PDT 24
Peak memory 208096 kb
Host smart-6a2f95e7-4ba7-4786-8097-67baee9622cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648957787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3648957787
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.256264848
Short name T481
Test name
Test status
Simulation time 98620938 ps
CPU time 1.65 seconds
Started Jun 28 04:46:11 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 207148 kb
Host smart-d41e7179-268d-4d3e-8db3-0e8b864cc03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256264848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.256264848
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.222185600
Short name T644
Test name
Test status
Simulation time 253836892 ps
CPU time 2.58 seconds
Started Jun 28 04:46:00 PM PDT 24
Finished Jun 28 04:46:04 PM PDT 24
Peak memory 206716 kb
Host smart-b294b0c9-0dc4-46a6-8e5c-fd98ac00cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222185600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.222185600
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3371636277
Short name T819
Test name
Test status
Simulation time 223166734 ps
CPU time 6.31 seconds
Started Jun 28 04:46:11 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 215336 kb
Host smart-da97b4d6-0867-461f-8f4e-dd20becb5314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371636277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3371636277
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1414743564
Short name T335
Test name
Test status
Simulation time 202068117 ps
CPU time 8.32 seconds
Started Jun 28 04:46:07 PM PDT 24
Finished Jun 28 04:46:16 PM PDT 24
Peak memory 221432 kb
Host smart-8d60295a-9555-4300-8df6-a76ea00f6924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414743564 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1414743564
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.812272395
Short name T881
Test name
Test status
Simulation time 155119500 ps
CPU time 5.07 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 207524 kb
Host smart-e6b9cdf3-9c63-474e-abac-581a98a330e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812272395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.812272395
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.437226372
Short name T756
Test name
Test status
Simulation time 142224545 ps
CPU time 1.81 seconds
Started Jun 28 04:46:09 PM PDT 24
Finished Jun 28 04:46:12 PM PDT 24
Peak memory 209796 kb
Host smart-29f1831e-5265-4d05-af3f-ba901d93c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437226372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.437226372
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1157681391
Short name T421
Test name
Test status
Simulation time 13670235 ps
CPU time 0.9 seconds
Started Jun 28 04:46:19 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 206048 kb
Host smart-da8f8602-6ef2-44f6-9cfe-403804ebbc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157681391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1157681391
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.868405269
Short name T223
Test name
Test status
Simulation time 538663736 ps
CPU time 27.67 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 213956 kb
Host smart-b2cd9381-ce6b-42ec-956b-97190fb853c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868405269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.868405269
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1388944160
Short name T47
Test name
Test status
Simulation time 41100128 ps
CPU time 1.55 seconds
Started Jun 28 04:46:10 PM PDT 24
Finished Jun 28 04:46:12 PM PDT 24
Peak memory 219928 kb
Host smart-646b3230-afa6-4544-a35c-e2f39a8c469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388944160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1388944160
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1540431885
Short name T735
Test name
Test status
Simulation time 114845128 ps
CPU time 1.86 seconds
Started Jun 28 04:46:11 PM PDT 24
Finished Jun 28 04:46:14 PM PDT 24
Peak memory 208084 kb
Host smart-e69f4f4f-0d64-4587-b190-44c5f1b921fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540431885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1540431885
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1013753211
Short name T100
Test name
Test status
Simulation time 1143676172 ps
CPU time 7.7 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:14 PM PDT 24
Peak memory 220808 kb
Host smart-345323e5-d22a-45b4-b60a-9cb1f2e0e7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013753211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1013753211
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.426777070
Short name T817
Test name
Test status
Simulation time 592307371 ps
CPU time 4.78 seconds
Started Jun 28 04:46:05 PM PDT 24
Finished Jun 28 04:46:11 PM PDT 24
Peak memory 222504 kb
Host smart-d9123234-1764-471a-82a5-b1ea5b15b74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426777070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.426777070
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2614103748
Short name T584
Test name
Test status
Simulation time 87254580 ps
CPU time 2.67 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:07 PM PDT 24
Peak memory 215184 kb
Host smart-9f3be363-d4ea-493e-8e6e-4c3f5c2bbe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614103748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2614103748
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1791591611
Short name T84
Test name
Test status
Simulation time 396749964 ps
CPU time 4.57 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:09 PM PDT 24
Peak memory 219552 kb
Host smart-e6745cb1-b1a0-4c45-884b-f694c272f958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791591611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1791591611
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2035566921
Short name T338
Test name
Test status
Simulation time 64723905 ps
CPU time 2.46 seconds
Started Jun 28 04:46:10 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 208592 kb
Host smart-9c7cc7ae-5c5c-4a8c-b240-cc9fe8eb0f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035566921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2035566921
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3127580454
Short name T525
Test name
Test status
Simulation time 300879121 ps
CPU time 3.89 seconds
Started Jun 28 04:46:10 PM PDT 24
Finished Jun 28 04:46:15 PM PDT 24
Peak memory 208860 kb
Host smart-5c5e514b-dd3a-4927-b448-71e76451433c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127580454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3127580454
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1681806424
Short name T369
Test name
Test status
Simulation time 56209430 ps
CPU time 3.08 seconds
Started Jun 28 04:46:06 PM PDT 24
Finished Jun 28 04:46:11 PM PDT 24
Peak memory 206968 kb
Host smart-ef18b516-b2c1-48ad-b114-4790773b8e87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681806424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1681806424
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4004450341
Short name T577
Test name
Test status
Simulation time 142034239 ps
CPU time 3.33 seconds
Started Jun 28 04:46:10 PM PDT 24
Finished Jun 28 04:46:14 PM PDT 24
Peak memory 208564 kb
Host smart-40903564-a101-4968-a997-ebe844c200ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004450341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4004450341
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.80272079
Short name T469
Test name
Test status
Simulation time 368683494 ps
CPU time 2.71 seconds
Started Jun 28 04:46:04 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 218388 kb
Host smart-16d1705e-d9b3-407f-ade2-688d790a1dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80272079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.80272079
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3348641818
Short name T852
Test name
Test status
Simulation time 76510218 ps
CPU time 2.71 seconds
Started Jun 28 04:46:03 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 208304 kb
Host smart-717070b8-0b4b-4a6e-9507-b7884a634a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348641818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3348641818
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3856391576
Short name T834
Test name
Test status
Simulation time 1096464966 ps
CPU time 40.42 seconds
Started Jun 28 04:46:22 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 222480 kb
Host smart-887fc96e-78a2-4002-b2d3-af1d971a2d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856391576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3856391576
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.173533085
Short name T322
Test name
Test status
Simulation time 237584781 ps
CPU time 15.55 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:29 PM PDT 24
Peak memory 222708 kb
Host smart-08f743b5-1ec4-4dd9-9939-69585f1fae2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173533085 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.173533085
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4135156982
Short name T184
Test name
Test status
Simulation time 1086936506 ps
CPU time 8.58 seconds
Started Jun 28 04:46:09 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 218908 kb
Host smart-a71b81d3-5e2b-4e2a-b0a7-1d5fff179e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135156982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4135156982
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2096054012
Short name T784
Test name
Test status
Simulation time 587493601 ps
CPU time 16.23 seconds
Started Jun 28 04:46:02 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 210496 kb
Host smart-cec879b3-50a2-45e4-b4d4-066a890490dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096054012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2096054012
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3397481637
Short name T850
Test name
Test status
Simulation time 16825058 ps
CPU time 0.9 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 205940 kb
Host smart-ebe15e56-8fa5-4d73-92cd-bb56f5cdd3d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397481637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3397481637
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3938387533
Short name T413
Test name
Test status
Simulation time 455723489 ps
CPU time 13.26 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:29 PM PDT 24
Peak memory 215764 kb
Host smart-74ce872a-869e-442e-8d8c-c0cd6406e5c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938387533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3938387533
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3970967204
Short name T649
Test name
Test status
Simulation time 349391372 ps
CPU time 2.59 seconds
Started Jun 28 04:46:26 PM PDT 24
Finished Jun 28 04:46:29 PM PDT 24
Peak memory 209680 kb
Host smart-35378188-cef1-448e-8537-6fc8d9eef8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970967204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3970967204
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2043735073
Short name T701
Test name
Test status
Simulation time 527848743 ps
CPU time 4.43 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 214288 kb
Host smart-28dc8b81-e6d3-4d6e-8b0d-8975e01f9522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043735073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2043735073
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1446487680
Short name T94
Test name
Test status
Simulation time 129846186 ps
CPU time 5.44 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 219808 kb
Host smart-385b9857-7b69-4bba-9261-d52904d43a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446487680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1446487680
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2571142019
Short name T247
Test name
Test status
Simulation time 70902154 ps
CPU time 2.79 seconds
Started Jun 28 04:46:28 PM PDT 24
Finished Jun 28 04:46:32 PM PDT 24
Peak memory 214320 kb
Host smart-36698ec3-c5b7-4bab-a043-34843d9f4794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571142019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2571142019
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.177812541
Short name T220
Test name
Test status
Simulation time 742802127 ps
CPU time 5.9 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 220368 kb
Host smart-538336e8-6b7a-499d-882e-3230d8b36f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177812541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.177812541
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1889371635
Short name T741
Test name
Test status
Simulation time 104330108 ps
CPU time 4.82 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 209456 kb
Host smart-18c055d8-3aea-453a-b24f-369413b14e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889371635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1889371635
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2502635924
Short name T284
Test name
Test status
Simulation time 229095669 ps
CPU time 7.94 seconds
Started Jun 28 04:46:12 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 208436 kb
Host smart-a0f3a97b-b3b0-4d78-a13c-04c507227501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502635924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2502635924
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4010101959
Short name T534
Test name
Test status
Simulation time 234309563 ps
CPU time 5.52 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 208232 kb
Host smart-2844209f-ee45-4d99-a555-a8d9333669b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010101959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4010101959
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4274738682
Short name T492
Test name
Test status
Simulation time 727012230 ps
CPU time 4.98 seconds
Started Jun 28 04:46:12 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 208816 kb
Host smart-6934b9e4-a207-4096-a055-b557def095de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274738682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4274738682
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1465442825
Short name T787
Test name
Test status
Simulation time 129455751 ps
CPU time 3.39 seconds
Started Jun 28 04:46:21 PM PDT 24
Finished Jun 28 04:46:25 PM PDT 24
Peak memory 208524 kb
Host smart-5663ebd9-beeb-46d7-9595-6f438276c35a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465442825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1465442825
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2396730585
Short name T176
Test name
Test status
Simulation time 307207945 ps
CPU time 7.11 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 208928 kb
Host smart-303b8c61-f723-44de-a4f9-c076cc9d6c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396730585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2396730585
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1375671098
Short name T436
Test name
Test status
Simulation time 376509494 ps
CPU time 4.63 seconds
Started Jun 28 04:46:21 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 207028 kb
Host smart-efc41959-fbe3-4baf-83be-4a013c15c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375671098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1375671098
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1636628395
Short name T274
Test name
Test status
Simulation time 162737083 ps
CPU time 5.98 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 219072 kb
Host smart-54ac73c7-2b43-435f-8367-3b25157628e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636628395 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1636628395
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2091031023
Short name T494
Test name
Test status
Simulation time 46368989 ps
CPU time 3.1 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 214240 kb
Host smart-37a587bb-66e3-4b97-bc30-7cd4d72feaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091031023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2091031023
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.918704948
Short name T384
Test name
Test status
Simulation time 89922706 ps
CPU time 1.26 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:15 PM PDT 24
Peak memory 209968 kb
Host smart-f6e48d9d-4991-497b-87e6-6a50e3987a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918704948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.918704948
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.388311798
Short name T898
Test name
Test status
Simulation time 12301976 ps
CPU time 0.88 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:16 PM PDT 24
Peak memory 205932 kb
Host smart-a18793f8-516d-43e9-ada1-b7279d5132c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388311798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.388311798
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1825592643
Short name T226
Test name
Test status
Simulation time 574894873 ps
CPU time 7.81 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:23 PM PDT 24
Peak memory 215144 kb
Host smart-0380d254-a34b-42e4-89fa-d795b1273b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825592643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1825592643
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2177654573
Short name T34
Test name
Test status
Simulation time 252892821 ps
CPU time 3.67 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 214320 kb
Host smart-cc72a479-0132-450a-9087-53e048e75d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177654573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2177654573
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.579036663
Short name T836
Test name
Test status
Simulation time 356612262 ps
CPU time 1.84 seconds
Started Jun 28 04:46:26 PM PDT 24
Finished Jun 28 04:46:29 PM PDT 24
Peak memory 207716 kb
Host smart-f5509b17-3204-42b9-9367-ec58705fd9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579036663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.579036663
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3968286885
Short name T434
Test name
Test status
Simulation time 216438930 ps
CPU time 2.66 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 214200 kb
Host smart-2c82b6d3-defb-44f4-b87e-00f98d7fd216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968286885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3968286885
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2141171144
Short name T229
Test name
Test status
Simulation time 74619845 ps
CPU time 2.54 seconds
Started Jun 28 04:46:18 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 220956 kb
Host smart-6545928a-0c8f-40fc-b45f-22c5597f39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141171144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2141171144
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1331996040
Short name T775
Test name
Test status
Simulation time 176732034 ps
CPU time 4.33 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 214324 kb
Host smart-70809724-95d4-4de4-ae27-4fc272b67af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331996040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1331996040
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.632275318
Short name T189
Test name
Test status
Simulation time 43803051 ps
CPU time 2.95 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:17 PM PDT 24
Peak memory 210540 kb
Host smart-bd73a8c8-fdbc-4759-b93d-6252b3f04221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632275318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.632275318
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4130432019
Short name T814
Test name
Test status
Simulation time 144696394 ps
CPU time 4.5 seconds
Started Jun 28 04:46:12 PM PDT 24
Finished Jun 28 04:46:17 PM PDT 24
Peak memory 208808 kb
Host smart-c48da9d0-6f9f-4d0d-8b5b-02a4c6fb855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130432019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4130432019
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1383819440
Short name T702
Test name
Test status
Simulation time 93664141 ps
CPU time 3.9 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 208932 kb
Host smart-850f4474-fe22-4260-bc69-c0cf2f74e0be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383819440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1383819440
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3793029607
Short name T627
Test name
Test status
Simulation time 186127856 ps
CPU time 2.19 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 206868 kb
Host smart-41f3899e-f232-4d24-a11b-be44db2c0bac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793029607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3793029607
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2650999280
Short name T526
Test name
Test status
Simulation time 611039467 ps
CPU time 6.43 seconds
Started Jun 28 04:46:12 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 207928 kb
Host smart-0e8817cd-7cb6-40f8-a929-8f66737d0fbd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650999280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2650999280
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2844956100
Short name T594
Test name
Test status
Simulation time 610693847 ps
CPU time 3.36 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 218272 kb
Host smart-a3e26744-5534-425b-8127-b924fa7368e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844956100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2844956100
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1322974951
Short name T694
Test name
Test status
Simulation time 2117901217 ps
CPU time 13.92 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:27 PM PDT 24
Peak memory 208300 kb
Host smart-48dc6f26-a942-4cb5-9558-e60c199589af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322974951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1322974951
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3533119167
Short name T168
Test name
Test status
Simulation time 544909118 ps
CPU time 20.71 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:39 PM PDT 24
Peak memory 220964 kb
Host smart-44f9342b-ce3d-4ecb-aa96-04e1442b0877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533119167 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3533119167
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2610350010
Short name T190
Test name
Test status
Simulation time 36122395 ps
CPU time 1.78 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 207628 kb
Host smart-eb3696bb-8c98-45fe-bc8a-b76a7ff5e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610350010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2610350010
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.353184644
Short name T923
Test name
Test status
Simulation time 1188703631 ps
CPU time 7.09 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:23 PM PDT 24
Peak memory 210984 kb
Host smart-9ea9132c-5d51-48e7-b6ea-5ce3b13ae13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353184644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.353184644
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.64504067
Short name T431
Test name
Test status
Simulation time 13261286 ps
CPU time 0.83 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 205992 kb
Host smart-3f89b05f-8d2d-42dd-9e2b-28da2fbb2705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64504067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.64504067
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.944721467
Short name T328
Test name
Test status
Simulation time 305648771 ps
CPU time 4.53 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 215372 kb
Host smart-b9a0018e-910f-47d3-a2ff-774ef542d5cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944721467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.944721467
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2200766928
Short name T846
Test name
Test status
Simulation time 2459715986 ps
CPU time 23.58 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:56 PM PDT 24
Peak memory 221620 kb
Host smart-b2d1a597-cf1f-4155-9d2b-5e517b6b8fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200766928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2200766928
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4114555646
Short name T344
Test name
Test status
Simulation time 55447936 ps
CPU time 2.61 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 214292 kb
Host smart-d123656d-315f-4cf7-8372-a659037ed1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114555646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4114555646
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2307588417
Short name T761
Test name
Test status
Simulation time 114556427 ps
CPU time 4.89 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 214312 kb
Host smart-88e7ec2d-1bf1-453a-9aad-26ccf88b2245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307588417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2307588417
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2858363927
Short name T337
Test name
Test status
Simulation time 1589964358 ps
CPU time 4.43 seconds
Started Jun 28 04:44:32 PM PDT 24
Finished Jun 28 04:44:39 PM PDT 24
Peak memory 222412 kb
Host smart-3d4f1ff5-768e-4844-a904-28a55fcb5179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858363927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2858363927
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.3430486323
Short name T872
Test name
Test status
Simulation time 368206551 ps
CPU time 5.88 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:37 PM PDT 24
Peak memory 209612 kb
Host smart-5f889d72-c5a4-47a3-8c00-11c46a8c4d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430486323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3430486323
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.405809410
Short name T891
Test name
Test status
Simulation time 194698832 ps
CPU time 2.66 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 208384 kb
Host smart-7835eb62-3fb7-4e5e-8bd3-965072b15b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405809410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.405809410
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2072400850
Short name T623
Test name
Test status
Simulation time 335967661 ps
CPU time 3.23 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 209056 kb
Host smart-1f467437-9590-4eb6-bbbe-2f94103f6583
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072400850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2072400850
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.427809792
Short name T848
Test name
Test status
Simulation time 330047524 ps
CPU time 6.38 seconds
Started Jun 28 04:44:22 PM PDT 24
Finished Jun 28 04:44:30 PM PDT 24
Peak memory 208448 kb
Host smart-78e346b5-c055-466d-a113-4b4eb85fe38b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427809792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.427809792
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4175240363
Short name T582
Test name
Test status
Simulation time 145842994 ps
CPU time 2.23 seconds
Started Jun 28 04:44:32 PM PDT 24
Finished Jun 28 04:44:37 PM PDT 24
Peak memory 208528 kb
Host smart-e8d80fb9-bd18-412d-847f-1cb4a4b53501
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175240363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4175240363
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2049364042
Short name T552
Test name
Test status
Simulation time 483840466 ps
CPU time 2.82 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 214212 kb
Host smart-d9231dfa-c959-4348-9334-3d6762646f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049364042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2049364042
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2497576042
Short name T188
Test name
Test status
Simulation time 145467058 ps
CPU time 4.53 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:36 PM PDT 24
Peak memory 207216 kb
Host smart-c609127f-0695-4fcc-90e7-ea1116e6dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497576042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2497576042
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3579067483
Short name T315
Test name
Test status
Simulation time 414638403 ps
CPU time 13.14 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 215872 kb
Host smart-98d657dd-ae11-4185-80f3-945ed923d327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579067483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3579067483
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4091152224
Short name T514
Test name
Test status
Simulation time 1108750155 ps
CPU time 4.51 seconds
Started Jun 28 04:44:31 PM PDT 24
Finished Jun 28 04:44:38 PM PDT 24
Peak memory 218324 kb
Host smart-f60560af-7c61-4971-8ad6-cc2f99e998b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091152224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4091152224
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2609203566
Short name T629
Test name
Test status
Simulation time 277485019 ps
CPU time 1.93 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 210112 kb
Host smart-d20962b8-9ad2-4f1c-89d2-df52268c45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609203566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2609203566
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2906644225
Short name T822
Test name
Test status
Simulation time 49494285 ps
CPU time 0.75 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 206032 kb
Host smart-ea0f1980-85f2-4882-ad2e-3b8413962604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906644225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2906644225
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4262362507
Short name T222
Test name
Test status
Simulation time 216515318 ps
CPU time 10.97 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:25 PM PDT 24
Peak memory 222400 kb
Host smart-0d055ee2-00b6-4220-8d01-5cfb13c97c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262362507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4262362507
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.952444671
Short name T668
Test name
Test status
Simulation time 10821625324 ps
CPU time 18.79 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 209136 kb
Host smart-f1d1666a-7bb9-42c5-9d7d-b21089ac9e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952444671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.952444671
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1934039169
Short name T653
Test name
Test status
Simulation time 36070888 ps
CPU time 2.71 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 208968 kb
Host smart-02cd6763-9e91-43ce-b89b-ea24af6e6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934039169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1934039169
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.4251624801
Short name T305
Test name
Test status
Simulation time 118066630 ps
CPU time 2.91 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 214244 kb
Host smart-3cd4ff6d-0e39-4711-98c4-5ca01328900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251624801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4251624801
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2287608738
Short name T321
Test name
Test status
Simulation time 137106685 ps
CPU time 2.79 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 220240 kb
Host smart-1a10e8bb-f976-41ef-a5e1-43a2eefa3b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287608738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2287608738
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.143472662
Short name T717
Test name
Test status
Simulation time 332717347 ps
CPU time 4.54 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 207612 kb
Host smart-27a1eb4e-4720-4b4f-a1f7-4c08a2429857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143472662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.143472662
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3765099899
Short name T354
Test name
Test status
Simulation time 38424986 ps
CPU time 2.4 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 207180 kb
Host smart-6918c22b-0ffb-4090-8d46-05a2edc48157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765099899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3765099899
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2610823173
Short name T192
Test name
Test status
Simulation time 63274266 ps
CPU time 3.17 seconds
Started Jun 28 04:46:12 PM PDT 24
Finished Jun 28 04:46:15 PM PDT 24
Peak memory 209096 kb
Host smart-49aae899-cc60-410b-b2b5-3f17f7fc485d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610823173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2610823173
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.385835550
Short name T810
Test name
Test status
Simulation time 30023877 ps
CPU time 2.3 seconds
Started Jun 28 04:46:19 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 206892 kb
Host smart-68778e1c-56ea-42a3-98cb-58f124c73e56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385835550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.385835550
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1503986215
Short name T616
Test name
Test status
Simulation time 285294428 ps
CPU time 2.89 seconds
Started Jun 28 04:46:16 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 206188 kb
Host smart-2bf1bbae-4f92-4807-b2f2-8c4209ebc9b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503986215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1503986215
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1728865296
Short name T391
Test name
Test status
Simulation time 17843377 ps
CPU time 1.67 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:16 PM PDT 24
Peak memory 208104 kb
Host smart-499f22b4-7004-4491-b21c-bd76ab57e735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728865296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1728865296
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4173090929
Short name T580
Test name
Test status
Simulation time 206260014 ps
CPU time 2.35 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 206764 kb
Host smart-91aa1f54-5ba0-4c60-80c9-8c5a76ba9290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173090929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4173090929
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3682615377
Short name T57
Test name
Test status
Simulation time 2644171332 ps
CPU time 49.31 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:47:05 PM PDT 24
Peak memory 222480 kb
Host smart-e5340b1f-2df5-45db-a830-3845d57cc2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682615377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3682615377
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2052274357
Short name T655
Test name
Test status
Simulation time 150655048 ps
CPU time 6.48 seconds
Started Jun 28 04:46:13 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 218344 kb
Host smart-452cc800-9f55-47ea-8cf4-5b5d3ea443dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052274357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2052274357
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.254484472
Short name T182
Test name
Test status
Simulation time 114531429 ps
CPU time 2.48 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:18 PM PDT 24
Peak memory 209836 kb
Host smart-c61875fe-52a1-40a6-b0b9-aeea1aa1b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254484472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.254484472
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3475672361
Short name T419
Test name
Test status
Simulation time 44800305 ps
CPU time 0.86 seconds
Started Jun 28 04:46:24 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 205968 kb
Host smart-ae7a6b88-be2b-4603-8d3e-a46a0b86ed25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475672361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3475672361
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.640101771
Short name T36
Test name
Test status
Simulation time 594727431 ps
CPU time 1.83 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 222888 kb
Host smart-ac7908aa-a772-41a1-81f8-f9b5c4eb65af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640101771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.640101771
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3571502547
Short name T19
Test name
Test status
Simulation time 116665282 ps
CPU time 1.5 seconds
Started Jun 28 04:46:24 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 206908 kb
Host smart-c32bd099-e549-4c67-95bf-f7ea2c8a2db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571502547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3571502547
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1360820023
Short name T672
Test name
Test status
Simulation time 166073843 ps
CPU time 4.38 seconds
Started Jun 28 04:46:23 PM PDT 24
Finished Jun 28 04:46:28 PM PDT 24
Peak memory 222412 kb
Host smart-11e37fab-fa31-480b-ae36-f3e2b7d0f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360820023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1360820023
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2714130834
Short name T91
Test name
Test status
Simulation time 82731675 ps
CPU time 3.46 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:35 PM PDT 24
Peak memory 214188 kb
Host smart-f00431f7-447d-4afe-ba78-290431be3721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714130834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2714130834
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2295319989
Short name T130
Test name
Test status
Simulation time 433494849 ps
CPU time 5.01 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:23 PM PDT 24
Peak memory 209548 kb
Host smart-6d7b8a68-2c0e-4828-8400-3f18c751771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295319989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2295319989
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3096354439
Short name T246
Test name
Test status
Simulation time 121307056 ps
CPU time 5.54 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 210284 kb
Host smart-e702ef7b-efb1-4593-962a-a0b1b7e76d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096354439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3096354439
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3278265943
Short name T186
Test name
Test status
Simulation time 105986701 ps
CPU time 2.89 seconds
Started Jun 28 04:46:23 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 208076 kb
Host smart-5a19c9b9-65d2-4f71-bc9e-f56ca28fb581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278265943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3278265943
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3205919347
Short name T252
Test name
Test status
Simulation time 4325813911 ps
CPU time 31.17 seconds
Started Jun 28 04:46:24 PM PDT 24
Finished Jun 28 04:46:56 PM PDT 24
Peak memory 208588 kb
Host smart-18f018a5-8de4-4a89-88ad-c4cd916d7036
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205919347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3205919347
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1087519237
Short name T840
Test name
Test status
Simulation time 203412193 ps
CPU time 7.69 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 208320 kb
Host smart-20c701b5-0d49-4eeb-9860-41d98f7d722c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087519237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1087519237
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3823151413
Short name T713
Test name
Test status
Simulation time 93438946 ps
CPU time 2.7 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 206880 kb
Host smart-45802f9b-df35-4162-a4d5-7e0756e9634e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823151413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3823151413
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3010536538
Short name T437
Test name
Test status
Simulation time 104412859 ps
CPU time 1.8 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 208048 kb
Host smart-df42b3fd-b58d-4d19-acf7-7661a7da6001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010536538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3010536538
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4265891972
Short name T865
Test name
Test status
Simulation time 708503867 ps
CPU time 4.02 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 207788 kb
Host smart-46f3e679-3a5a-47a9-b6a8-e99a9eb65f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265891972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4265891972
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2921657228
Short name T650
Test name
Test status
Simulation time 693771799 ps
CPU time 16.24 seconds
Started Jun 28 04:46:21 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 216760 kb
Host smart-8543c965-56f9-4ca8-8aa4-bc9f274ccd7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921657228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2921657228
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1422283624
Short name T345
Test name
Test status
Simulation time 742776640 ps
CPU time 20.21 seconds
Started Jun 28 04:46:18 PM PDT 24
Finished Jun 28 04:46:39 PM PDT 24
Peak memory 208916 kb
Host smart-a5b088ed-74af-4669-bbf5-f0dad4b15831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422283624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1422283624
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3996247610
Short name T894
Test name
Test status
Simulation time 31634246 ps
CPU time 2.15 seconds
Started Jun 28 04:46:20 PM PDT 24
Finished Jun 28 04:46:23 PM PDT 24
Peak memory 210348 kb
Host smart-3c080f54-9ca6-4bd3-a4cd-a1b5cadee2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996247610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3996247610
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4004802590
Short name T438
Test name
Test status
Simulation time 11148057 ps
CPU time 0.71 seconds
Started Jun 28 04:46:19 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 205944 kb
Host smart-5252f55b-16a4-4198-8541-0ad7c32d59c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004802590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4004802590
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.4061500683
Short name T414
Test name
Test status
Simulation time 756847955 ps
CPU time 9.99 seconds
Started Jun 28 04:46:19 PM PDT 24
Finished Jun 28 04:46:30 PM PDT 24
Peak memory 215424 kb
Host smart-14f624d0-cf02-4aa5-aea5-22559647433d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061500683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.4061500683
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4251776012
Short name T789
Test name
Test status
Simulation time 62331060 ps
CPU time 2.84 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:35 PM PDT 24
Peak memory 208748 kb
Host smart-50a5ea2e-2af7-49ab-a094-21cf546d44d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251776012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4251776012
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2127548237
Short name T110
Test name
Test status
Simulation time 72260228 ps
CPU time 2.05 seconds
Started Jun 28 04:46:19 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 218072 kb
Host smart-6fd9faa8-311e-4c89-8703-2eaeeb36dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127548237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2127548237
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3790943394
Short name T99
Test name
Test status
Simulation time 52800299 ps
CPU time 3.18 seconds
Started Jun 28 04:46:20 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 209200 kb
Host smart-1a70a0dd-849d-427b-82f8-cc13927dc94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790943394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3790943394
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.916061067
Short name T230
Test name
Test status
Simulation time 218348152 ps
CPU time 3.03 seconds
Started Jun 28 04:46:30 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 214252 kb
Host smart-a1e274ae-708e-4e85-9460-4bfcbd81489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916061067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.916061067
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2989059392
Short name T200
Test name
Test status
Simulation time 363101649 ps
CPU time 2.27 seconds
Started Jun 28 04:46:19 PM PDT 24
Finished Jun 28 04:46:23 PM PDT 24
Peak memory 209288 kb
Host smart-301d5552-b11f-4727-9fe0-824b094a1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989059392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2989059392
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2171702906
Short name T621
Test name
Test status
Simulation time 362572926 ps
CPU time 4.46 seconds
Started Jun 28 04:46:29 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 218260 kb
Host smart-d5a4c72d-9681-44ed-98dc-5ccda23b4895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171702906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2171702906
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.812073179
Short name T425
Test name
Test status
Simulation time 95759844 ps
CPU time 3.33 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 206724 kb
Host smart-8d9f1809-f834-44fd-b199-3fd25504df3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812073179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.812073179
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2667680118
Short name T748
Test name
Test status
Simulation time 1183865723 ps
CPU time 6.83 seconds
Started Jun 28 04:46:27 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 208716 kb
Host smart-1fc91c0e-2c1e-4278-a38b-2dcbb97e12f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667680118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2667680118
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2122867704
Short name T919
Test name
Test status
Simulation time 315211203 ps
CPU time 3.4 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:21 PM PDT 24
Peak memory 206788 kb
Host smart-42d6f169-0d68-48b2-8a26-9a01d59e72ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122867704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2122867704
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.823402309
Short name T863
Test name
Test status
Simulation time 326705484 ps
CPU time 3.16 seconds
Started Jun 28 04:46:18 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 208520 kb
Host smart-e76a8ea4-87ef-4be7-9167-32109e119e88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823402309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.823402309
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2698054144
Short name T750
Test name
Test status
Simulation time 40144737 ps
CPU time 2.51 seconds
Started Jun 28 04:46:21 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 206944 kb
Host smart-d4605c6d-4ab4-4736-b7b1-636839c9a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698054144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2698054144
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.354515776
Short name T777
Test name
Test status
Simulation time 52334777 ps
CPU time 2.47 seconds
Started Jun 28 04:46:15 PM PDT 24
Finished Jun 28 04:46:19 PM PDT 24
Peak memory 208016 kb
Host smart-44cbb44d-40c0-47a4-a563-189e3bd79a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354515776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.354515776
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3814423155
Short name T820
Test name
Test status
Simulation time 3756320492 ps
CPU time 35.41 seconds
Started Jun 28 04:46:23 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 214924 kb
Host smart-c52e8d67-7d51-4513-98b0-51058269e1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814423155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3814423155
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1570946381
Short name T490
Test name
Test status
Simulation time 540975974 ps
CPU time 3.98 seconds
Started Jun 28 04:46:29 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 207448 kb
Host smart-a51fc9ab-7d3b-4b92-8945-fc2f472b51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570946381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1570946381
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2867249819
Short name T380
Test name
Test status
Simulation time 322365679 ps
CPU time 3.77 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:39 PM PDT 24
Peak memory 210408 kb
Host smart-c85b6131-db48-4ff2-8af5-b00a7d6218cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867249819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2867249819
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3728756480
Short name T903
Test name
Test status
Simulation time 16749270 ps
CPU time 0.74 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 206048 kb
Host smart-794f8ada-bb02-4332-a7a2-8b19f4e63162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728756480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3728756480
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2906911803
Short name T22
Test name
Test status
Simulation time 69143603 ps
CPU time 2.91 seconds
Started Jun 28 04:46:18 PM PDT 24
Finished Jun 28 04:46:22 PM PDT 24
Peak memory 209924 kb
Host smart-e6f2cede-6669-4767-bbc4-234e6c0dbd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906911803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2906911803
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3665790157
Short name T695
Test name
Test status
Simulation time 182210040 ps
CPU time 2.5 seconds
Started Jun 28 04:46:28 PM PDT 24
Finished Jun 28 04:46:31 PM PDT 24
Peak memory 209460 kb
Host smart-5af807a8-df05-4445-b2c7-a9990fd2e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665790157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3665790157
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.856303889
Short name T781
Test name
Test status
Simulation time 57376944 ps
CPU time 2.02 seconds
Started Jun 28 04:46:27 PM PDT 24
Finished Jun 28 04:46:29 PM PDT 24
Peak memory 214344 kb
Host smart-17615d78-94de-4c56-a925-8cecae265bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856303889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.856303889
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2538987516
Short name T309
Test name
Test status
Simulation time 205068352 ps
CPU time 3.71 seconds
Started Jun 28 04:46:14 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 214244 kb
Host smart-b458ee9d-c4f2-40fd-84a8-7bb7f66d1e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538987516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2538987516
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1281151051
Short name T216
Test name
Test status
Simulation time 40789476 ps
CPU time 2.67 seconds
Started Jun 28 04:46:27 PM PDT 24
Finished Jun 28 04:46:30 PM PDT 24
Peak memory 214324 kb
Host smart-5dd74781-e0ca-4566-8b0a-d0912ffea981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281151051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1281151051
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1858187173
Short name T487
Test name
Test status
Simulation time 642263508 ps
CPU time 3.83 seconds
Started Jun 28 04:46:28 PM PDT 24
Finished Jun 28 04:46:32 PM PDT 24
Peak memory 207028 kb
Host smart-41679697-4746-4837-9481-a71be9c87d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858187173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1858187173
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1069665206
Short name T802
Test name
Test status
Simulation time 343720113 ps
CPU time 3.73 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 208400 kb
Host smart-ec3f600f-eb18-41ea-a809-c6beb105fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069665206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1069665206
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2444702352
Short name T602
Test name
Test status
Simulation time 55851503 ps
CPU time 2.27 seconds
Started Jun 28 04:46:40 PM PDT 24
Finished Jun 28 04:46:43 PM PDT 24
Peak memory 208952 kb
Host smart-45688d4a-5d57-4969-bf68-8cfcad23f3bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444702352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2444702352
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2041157636
Short name T816
Test name
Test status
Simulation time 1175399968 ps
CPU time 8.81 seconds
Started Jun 28 04:46:17 PM PDT 24
Finished Jun 28 04:46:27 PM PDT 24
Peak memory 208604 kb
Host smart-23a30403-5699-402e-bdeb-8882a3ea26b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041157636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2041157636
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3130199150
Short name T80
Test name
Test status
Simulation time 221903366 ps
CPU time 4.94 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:39 PM PDT 24
Peak memory 208840 kb
Host smart-3deb75dd-d44d-424e-84f9-271ecb02b31d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130199150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3130199150
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1079505433
Short name T574
Test name
Test status
Simulation time 299934045 ps
CPU time 2.67 seconds
Started Jun 28 04:46:21 PM PDT 24
Finished Jun 28 04:46:24 PM PDT 24
Peak memory 218052 kb
Host smart-eda40c47-3440-42f0-84e3-37f4272abffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079505433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1079505433
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1217430241
Short name T614
Test name
Test status
Simulation time 104519699 ps
CPU time 2.55 seconds
Started Jun 28 04:46:26 PM PDT 24
Finished Jun 28 04:46:29 PM PDT 24
Peak memory 208564 kb
Host smart-4204a805-52ad-441e-9cbc-865a6c4e2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217430241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1217430241
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4287584873
Short name T311
Test name
Test status
Simulation time 178088254 ps
CPU time 7.51 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:43 PM PDT 24
Peak memory 210232 kb
Host smart-31678713-111d-43c4-9572-46122c80decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287584873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4287584873
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1322813802
Short name T600
Test name
Test status
Simulation time 57843427 ps
CPU time 1.87 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 209788 kb
Host smart-077dc7ff-3945-40d9-84fb-6bccfe96f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322813802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1322813802
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3851984174
Short name T879
Test name
Test status
Simulation time 39243834 ps
CPU time 0.72 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 206044 kb
Host smart-fed55fb3-2a10-4d6c-a66d-94d9c20b212a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851984174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3851984174
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2831612709
Short name T371
Test name
Test status
Simulation time 103990491 ps
CPU time 1.96 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 214360 kb
Host smart-b3efcd6c-b035-4d2a-a486-cc5a9ce19670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831612709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2831612709
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3863438821
Short name T206
Test name
Test status
Simulation time 159525931 ps
CPU time 3.66 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:40 PM PDT 24
Peak memory 221372 kb
Host smart-6048356d-723c-4d32-8d2c-a62b3a962e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863438821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3863438821
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4062364989
Short name T907
Test name
Test status
Simulation time 490872126 ps
CPU time 5.03 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 218524 kb
Host smart-7532e1bb-aff8-4a2b-bb07-94acdcee0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062364989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4062364989
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2552515092
Short name T373
Test name
Test status
Simulation time 239524875 ps
CPU time 2.31 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:52 PM PDT 24
Peak memory 214364 kb
Host smart-ca40dae9-7229-42fe-8c90-959e80084f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552515092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2552515092
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.358376480
Short name T754
Test name
Test status
Simulation time 2177074101 ps
CPU time 20.71 seconds
Started Jun 28 04:46:37 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 214360 kb
Host smart-ec6c8190-842d-400e-b6c8-d208a65847c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358376480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.358376480
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1882425062
Short name T208
Test name
Test status
Simulation time 95715090 ps
CPU time 2.77 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 214808 kb
Host smart-8b82d978-5bdd-436a-8339-c5a02bcfe120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882425062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1882425062
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1031603664
Short name T320
Test name
Test status
Simulation time 320196431 ps
CPU time 7.68 seconds
Started Jun 28 04:46:39 PM PDT 24
Finished Jun 28 04:46:47 PM PDT 24
Peak memory 218344 kb
Host smart-189c9e64-48f1-4fcd-8645-8b2c7d3fed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031603664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1031603664
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2785483338
Short name T596
Test name
Test status
Simulation time 548005064 ps
CPU time 3.56 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 206840 kb
Host smart-603e5741-ad3b-4e54-8a9e-c5518080c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785483338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2785483338
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3362562453
Short name T729
Test name
Test status
Simulation time 291683044 ps
CPU time 3.97 seconds
Started Jun 28 04:46:38 PM PDT 24
Finished Jun 28 04:46:43 PM PDT 24
Peak memory 206988 kb
Host smart-52b77ebf-5ed1-4389-8cc6-80a418d2bf60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362562453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3362562453
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1571716779
Short name T857
Test name
Test status
Simulation time 670480695 ps
CPU time 8.4 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 208980 kb
Host smart-b9b4a917-4f37-416b-83ee-35444b0c5023
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571716779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1571716779
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1099532114
Short name T697
Test name
Test status
Simulation time 2606491337 ps
CPU time 7.55 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:44 PM PDT 24
Peak memory 208820 kb
Host smart-d0e2fc12-3f09-46c2-bea0-07b13fd7c653
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099532114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1099532114
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.565005271
Short name T524
Test name
Test status
Simulation time 89164421 ps
CPU time 1.81 seconds
Started Jun 28 04:46:40 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 209056 kb
Host smart-054b8ae4-8cf0-47c3-bf93-4931a9fc0f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565005271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.565005271
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.143788230
Short name T870
Test name
Test status
Simulation time 109467869 ps
CPU time 2.61 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 208544 kb
Host smart-1c703dcd-d50c-45f3-8360-ee3b1ba04ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143788230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.143788230
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2395867678
Short name T210
Test name
Test status
Simulation time 287832749 ps
CPU time 9.46 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 214224 kb
Host smart-ac6691b2-839a-4308-b6c3-88ebaacb1b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395867678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2395867678
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1992942979
Short name T329
Test name
Test status
Simulation time 911130037 ps
CPU time 9.66 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 222528 kb
Host smart-0be14bda-e8da-4693-a75c-b74a557bf36e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992942979 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1992942979
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4057619162
Short name T183
Test name
Test status
Simulation time 399937720 ps
CPU time 4.91 seconds
Started Jun 28 04:46:30 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 207584 kb
Host smart-26fa09c6-e784-4ffd-8283-812043e26cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057619162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4057619162
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2329611194
Short name T617
Test name
Test status
Simulation time 65697637 ps
CPU time 1.7 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 210304 kb
Host smart-57f4e6a1-eb5b-4e60-91e5-451a7116966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329611194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2329611194
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3817545439
Short name T823
Test name
Test status
Simulation time 11134475 ps
CPU time 0.72 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 206060 kb
Host smart-51352adb-10ac-4d87-a0ac-e18ccf59979e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817545439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3817545439
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3879649810
Short name T353
Test name
Test status
Simulation time 183618707 ps
CPU time 6.66 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:47:03 PM PDT 24
Peak memory 214200 kb
Host smart-86adb2f2-1403-400a-ad5c-9e112f826d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3879649810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3879649810
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3076253527
Short name T519
Test name
Test status
Simulation time 444850226 ps
CPU time 2.26 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 222728 kb
Host smart-2f208476-d3c0-43ae-9d91-b07dbf2a7197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076253527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3076253527
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.930796505
Short name T724
Test name
Test status
Simulation time 438813550 ps
CPU time 10.76 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:47 PM PDT 24
Peak memory 218160 kb
Host smart-2c16b5cd-7601-4678-bf1a-6974bdfa9850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930796505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.930796505
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2655231108
Short name T92
Test name
Test status
Simulation time 135782422 ps
CPU time 6.3 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 214360 kb
Host smart-e24a7108-c53b-4c6b-bcd2-15c35af5716e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655231108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2655231108
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3150162606
Short name T89
Test name
Test status
Simulation time 944252686 ps
CPU time 4.8 seconds
Started Jun 28 04:46:26 PM PDT 24
Finished Jun 28 04:46:32 PM PDT 24
Peak memory 222228 kb
Host smart-fe60bb11-5a32-4fdf-91f4-96576b173934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150162606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3150162606
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.708670025
Short name T221
Test name
Test status
Simulation time 410785936 ps
CPU time 4.86 seconds
Started Jun 28 04:46:38 PM PDT 24
Finished Jun 28 04:46:44 PM PDT 24
Peak memory 222376 kb
Host smart-9b90cb9c-0abd-4810-8acb-96ab6686301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708670025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.708670025
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4183525594
Short name T418
Test name
Test status
Simulation time 135582873 ps
CPU time 2.58 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 207268 kb
Host smart-c66392ac-7f08-4995-bc98-4abca8500b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183525594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4183525594
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4002496778
Short name T446
Test name
Test status
Simulation time 63653447 ps
CPU time 2.58 seconds
Started Jun 28 04:46:43 PM PDT 24
Finished Jun 28 04:46:46 PM PDT 24
Peak memory 206120 kb
Host smart-091b4310-f65c-44aa-a2bd-ee2b42fe956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002496778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4002496778
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3824913415
Short name T497
Test name
Test status
Simulation time 66322254 ps
CPU time 3.23 seconds
Started Jun 28 04:46:38 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 209044 kb
Host smart-33ad08d9-4b5a-4494-b6fa-0e8d3d03ae67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824913415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3824913415
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3516038539
Short name T681
Test name
Test status
Simulation time 566255795 ps
CPU time 6.51 seconds
Started Jun 28 04:46:43 PM PDT 24
Finished Jun 28 04:46:50 PM PDT 24
Peak memory 208904 kb
Host smart-072c877b-c7ad-48de-bcd9-8744277babde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516038539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3516038539
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3774857641
Short name T485
Test name
Test status
Simulation time 33850942 ps
CPU time 1.64 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 206952 kb
Host smart-977afa49-327b-4e1f-9161-8acc43cfef52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774857641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3774857641
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3538720649
Short name T893
Test name
Test status
Simulation time 136010015 ps
CPU time 2.07 seconds
Started Jun 28 04:46:44 PM PDT 24
Finished Jun 28 04:46:47 PM PDT 24
Peak memory 208284 kb
Host smart-59276cec-fc63-4371-9c14-faf29298a263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538720649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3538720649
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2271263961
Short name T450
Test name
Test status
Simulation time 326153064 ps
CPU time 2.66 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:39 PM PDT 24
Peak memory 208136 kb
Host smart-329e5515-efb6-447b-945e-cf5bdf2093dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271263961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2271263961
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1204927660
Short name T123
Test name
Test status
Simulation time 379863303 ps
CPU time 15.05 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:48 PM PDT 24
Peak memory 222504 kb
Host smart-fe15327e-f67f-4972-a9cd-3f0a576286c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204927660 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1204927660
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3752824159
Short name T746
Test name
Test status
Simulation time 401688339 ps
CPU time 6.41 seconds
Started Jun 28 04:46:30 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 214228 kb
Host smart-c3a5d4ea-bc30-4c1c-85d2-1b64c1c5f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752824159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3752824159
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2050962877
Short name T386
Test name
Test status
Simulation time 71146901 ps
CPU time 2.4 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 210204 kb
Host smart-cdd377cd-4f2e-4600-bd50-32f4c4b10f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050962877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2050962877
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2155909933
Short name T462
Test name
Test status
Simulation time 12519198 ps
CPU time 0.86 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 205880 kb
Host smart-3ce6e68f-bb1b-4ef7-8162-5202b13a5584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155909933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2155909933
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1321707725
Short name T410
Test name
Test status
Simulation time 146750176 ps
CPU time 2.97 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:40 PM PDT 24
Peak memory 215328 kb
Host smart-4dee7de5-53e7-460f-a645-46c478d01f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321707725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1321707725
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.800522648
Short name T37
Test name
Test status
Simulation time 56157196 ps
CPU time 1.35 seconds
Started Jun 28 04:46:44 PM PDT 24
Finished Jun 28 04:46:46 PM PDT 24
Peak memory 214748 kb
Host smart-413dbce0-dfd6-41ba-a856-6f73afe44535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800522648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.800522648
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.432198174
Short name T709
Test name
Test status
Simulation time 77661236 ps
CPU time 1.7 seconds
Started Jun 28 04:46:28 PM PDT 24
Finished Jun 28 04:46:31 PM PDT 24
Peak memory 208128 kb
Host smart-ef609d61-0768-460f-9665-66b52b43ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432198174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.432198174
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1761991518
Short name T763
Test name
Test status
Simulation time 32130904 ps
CPU time 2.6 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 214252 kb
Host smart-0f5f598a-6150-4ad8-8a32-ff2331c87b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761991518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1761991518
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.465877966
Short name T671
Test name
Test status
Simulation time 213683141 ps
CPU time 3.01 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 214140 kb
Host smart-36e4b996-8315-4352-ad5b-1637f7cb769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465877966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.465877966
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1912977098
Short name T728
Test name
Test status
Simulation time 193716954 ps
CPU time 2.77 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:40 PM PDT 24
Peak memory 220244 kb
Host smart-3020f9d1-161b-4b21-8836-abbe7583e0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912977098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1912977098
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1943946554
Short name T254
Test name
Test status
Simulation time 114173529 ps
CPU time 4.14 seconds
Started Jun 28 04:46:32 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 214344 kb
Host smart-b6127e3d-b3af-4595-9ceb-c48dc15e8f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943946554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1943946554
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2593013339
Short name T656
Test name
Test status
Simulation time 1588926461 ps
CPU time 10.58 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:47:08 PM PDT 24
Peak memory 207980 kb
Host smart-0a5fbe11-5cf1-4afe-8e6d-2a63be491cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593013339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2593013339
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1271247885
Short name T504
Test name
Test status
Simulation time 72666519 ps
CPU time 1.76 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:44 PM PDT 24
Peak memory 206820 kb
Host smart-33fbd011-5d88-47b6-a6a6-501a87ef6f06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271247885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1271247885
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3239925604
Short name T566
Test name
Test status
Simulation time 405072521 ps
CPU time 5.11 seconds
Started Jun 28 04:46:36 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 208484 kb
Host smart-02adadbd-6908-4452-b39a-a35e3be32273
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239925604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3239925604
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2739716279
Short name T704
Test name
Test status
Simulation time 257691092 ps
CPU time 3.19 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 206788 kb
Host smart-86575491-e07d-4d96-b07c-914cb05471d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739716279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2739716279
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3889857042
Short name T454
Test name
Test status
Simulation time 194605900 ps
CPU time 3.32 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 214296 kb
Host smart-fa34d74b-a3e1-4f0d-8fe1-434a70528988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889857042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3889857042
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1811004020
Short name T420
Test name
Test status
Simulation time 6334591975 ps
CPU time 31.09 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:47:07 PM PDT 24
Peak memory 208400 kb
Host smart-fd147ce3-8d95-4fcf-92ec-0147601fb224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811004020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1811004020
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1764345463
Short name T325
Test name
Test status
Simulation time 2103768596 ps
CPU time 9.8 seconds
Started Jun 28 04:46:42 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 216008 kb
Host smart-6a9a39f3-aded-4fc5-9cff-af1538ae7d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764345463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1764345463
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2660001730
Short name T167
Test name
Test status
Simulation time 261791850 ps
CPU time 9.79 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:45 PM PDT 24
Peak memory 217984 kb
Host smart-3fa51c79-3745-445f-a6d0-ee70dc88e0e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660001730 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2660001730
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2933684414
Short name T679
Test name
Test status
Simulation time 362097683 ps
CPU time 5.9 seconds
Started Jun 28 04:46:46 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 207652 kb
Host smart-89f22eea-25ac-4951-93af-6b9ff36372a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933684414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2933684414
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1622643851
Short name T561
Test name
Test status
Simulation time 47003740 ps
CPU time 1.46 seconds
Started Jun 28 04:46:38 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 209500 kb
Host smart-97969fd4-0ba8-440b-9b93-e28a1baaeb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622643851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1622643851
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.196238516
Short name T422
Test name
Test status
Simulation time 13245551 ps
CPU time 0.75 seconds
Started Jun 28 04:46:51 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 206032 kb
Host smart-be9f273a-049a-41a0-bb45-6301c5349ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196238516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.196238516
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1552989300
Short name T405
Test name
Test status
Simulation time 182748706 ps
CPU time 10.16 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:47 PM PDT 24
Peak memory 214344 kb
Host smart-eec7afa5-effe-4286-84d2-aa3211b990f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552989300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1552989300
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1184437857
Short name T670
Test name
Test status
Simulation time 887217507 ps
CPU time 23.45 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:47:20 PM PDT 24
Peak memory 214692 kb
Host smart-d49edcd1-980c-4b57-8c3b-038259fee894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184437857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1184437857
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2070451568
Short name T700
Test name
Test status
Simulation time 382732187 ps
CPU time 10.14 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:10 PM PDT 24
Peak memory 208868 kb
Host smart-8533ebb4-8b46-4220-b6c2-f22d41f0e60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070451568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2070451568
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1296867596
Short name T302
Test name
Test status
Simulation time 142147830 ps
CPU time 1.95 seconds
Started Jun 28 04:46:44 PM PDT 24
Finished Jun 28 04:46:47 PM PDT 24
Peak memory 214328 kb
Host smart-918baa4b-7337-4cc1-893b-85d96d182e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296867596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1296867596
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1330866888
Short name T375
Test name
Test status
Simulation time 379146910 ps
CPU time 4.38 seconds
Started Jun 28 04:46:50 PM PDT 24
Finished Jun 28 04:46:56 PM PDT 24
Peak memory 214276 kb
Host smart-8ce154db-a5cd-472c-8661-72934c2e321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330866888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1330866888
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.713247418
Short name T212
Test name
Test status
Simulation time 71116411 ps
CPU time 3.57 seconds
Started Jun 28 04:46:45 PM PDT 24
Finished Jun 28 04:46:49 PM PDT 24
Peak memory 209336 kb
Host smart-d74e3acd-2b77-477d-81d9-6c8e66e7435e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713247418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.713247418
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3621282713
Short name T856
Test name
Test status
Simulation time 87995955 ps
CPU time 3.91 seconds
Started Jun 28 04:46:42 PM PDT 24
Finished Jun 28 04:46:47 PM PDT 24
Peak memory 218124 kb
Host smart-484895a0-6a2a-4497-a391-897b9fce80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621282713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3621282713
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1812519319
Short name T601
Test name
Test status
Simulation time 251676218 ps
CPU time 3.21 seconds
Started Jun 28 04:46:38 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 208684 kb
Host smart-47848187-00ac-47ef-9a27-435add5c8b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812519319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1812519319
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2530761387
Short name T298
Test name
Test status
Simulation time 418698038 ps
CPU time 4.12 seconds
Started Jun 28 04:46:45 PM PDT 24
Finished Jun 28 04:46:49 PM PDT 24
Peak memory 206944 kb
Host smart-f4a245ca-818c-44b2-9315-ff2921d8091b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530761387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2530761387
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3164530254
Short name T862
Test name
Test status
Simulation time 110463929 ps
CPU time 4.03 seconds
Started Jun 28 04:46:28 PM PDT 24
Finished Jun 28 04:46:32 PM PDT 24
Peak memory 208180 kb
Host smart-42df8bbf-1161-47ae-81c5-8347e61f401e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164530254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3164530254
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2265342624
Short name T778
Test name
Test status
Simulation time 522477615 ps
CPU time 4.19 seconds
Started Jun 28 04:46:31 PM PDT 24
Finished Jun 28 04:46:36 PM PDT 24
Peak memory 206916 kb
Host smart-4939bda0-a16d-4e06-81b6-56c37229f194
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265342624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2265342624
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2282119599
Short name T474
Test name
Test status
Simulation time 1313398165 ps
CPU time 5.43 seconds
Started Jun 28 04:46:35 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 208292 kb
Host smart-33e15511-fd21-4de9-a547-5b35cfef088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282119599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2282119599
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.521565480
Short name T611
Test name
Test status
Simulation time 6713690038 ps
CPU time 49.87 seconds
Started Jun 28 04:46:37 PM PDT 24
Finished Jun 28 04:47:29 PM PDT 24
Peak memory 208460 kb
Host smart-77dc873f-2eb4-4d0f-839d-a6f6e1ec2d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521565480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.521565480
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1453173577
Short name T177
Test name
Test status
Simulation time 449805150 ps
CPU time 17.21 seconds
Started Jun 28 04:46:43 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 222292 kb
Host smart-dda58e16-1e17-454d-8c11-fa1476f2c62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453173577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1453173577
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1072023592
Short name T60
Test name
Test status
Simulation time 145469801 ps
CPU time 9.95 seconds
Started Jun 28 04:46:42 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 222620 kb
Host smart-7a3507c1-ba9e-4914-96d9-46f5201682b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072023592 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1072023592
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.867358408
Short name T502
Test name
Test status
Simulation time 1042733909 ps
CPU time 23.84 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:47:19 PM PDT 24
Peak memory 209696 kb
Host smart-2753cf3a-66f2-4138-afdf-8c8c28ebb9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867358408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.867358408
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.179790027
Short name T737
Test name
Test status
Simulation time 40171381 ps
CPU time 1.58 seconds
Started Jun 28 04:46:40 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 209832 kb
Host smart-f01e84b6-8552-4431-81ba-62c6e021bcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179790027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.179790027
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2799589553
Short name T465
Test name
Test status
Simulation time 35596175 ps
CPU time 0.79 seconds
Started Jun 28 04:46:40 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 205928 kb
Host smart-64bdfe55-fde3-4716-b3c3-cc061b1a93d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799589553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2799589553
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.742158923
Short name T831
Test name
Test status
Simulation time 100734072 ps
CPU time 3.35 seconds
Started Jun 28 04:46:37 PM PDT 24
Finished Jun 28 04:46:42 PM PDT 24
Peak memory 223028 kb
Host smart-40e8d7ef-71c7-4a35-a85f-1b92a49d3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742158923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.742158923
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1645801642
Short name T521
Test name
Test status
Simulation time 646660518 ps
CPU time 11.16 seconds
Started Jun 28 04:46:43 PM PDT 24
Finished Jun 28 04:46:55 PM PDT 24
Peak memory 210540 kb
Host smart-d4e6322b-db38-47e0-9b8b-63f8e1150444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645801642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1645801642
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.149108986
Short name T232
Test name
Test status
Simulation time 170557772 ps
CPU time 1.84 seconds
Started Jun 28 04:46:43 PM PDT 24
Finished Jun 28 04:46:46 PM PDT 24
Peak memory 214684 kb
Host smart-ea3d4b2a-5b09-46ad-9f96-e0edcedf8cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149108986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.149108986
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.488083582
Short name T762
Test name
Test status
Simulation time 53608465 ps
CPU time 2.37 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:01 PM PDT 24
Peak memory 222420 kb
Host smart-78279171-358e-4389-8be4-051aa7d8aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488083582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.488083582
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2490603839
Short name T538
Test name
Test status
Simulation time 50336160 ps
CPU time 2.88 seconds
Started Jun 28 04:46:50 PM PDT 24
Finished Jun 28 04:46:54 PM PDT 24
Peak memory 209520 kb
Host smart-70980983-32b3-4694-a5ea-c4ecf28f0ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490603839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2490603839
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3683007606
Short name T821
Test name
Test status
Simulation time 34873041 ps
CPU time 2.77 seconds
Started Jun 28 04:46:46 PM PDT 24
Finished Jun 28 04:46:49 PM PDT 24
Peak memory 207732 kb
Host smart-0e7fe9cb-8c97-42a6-a5e1-551be1aa4c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683007606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3683007606
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4250136705
Short name T250
Test name
Test status
Simulation time 78604899 ps
CPU time 3.59 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:54 PM PDT 24
Peak memory 208312 kb
Host smart-11bc5b8b-2a7c-4787-b6c6-6e7ea805fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250136705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4250136705
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2937567855
Short name T806
Test name
Test status
Simulation time 183243920 ps
CPU time 5.64 seconds
Started Jun 28 04:46:43 PM PDT 24
Finished Jun 28 04:46:50 PM PDT 24
Peak memory 207940 kb
Host smart-8b79105a-01d4-4b69-a33c-050d697a1618
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937567855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2937567855
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1580838042
Short name T562
Test name
Test status
Simulation time 2796109924 ps
CPU time 5.01 seconds
Started Jun 28 04:46:45 PM PDT 24
Finished Jun 28 04:46:51 PM PDT 24
Peak memory 208040 kb
Host smart-0a387377-ef7a-48c0-9fad-b129b590c665
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580838042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1580838042
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1587627951
Short name T696
Test name
Test status
Simulation time 33435035 ps
CPU time 2.4 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 207000 kb
Host smart-aab56965-715e-43f6-b5c5-63dc39ef715e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587627951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1587627951
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3318598866
Short name T901
Test name
Test status
Simulation time 141337601 ps
CPU time 2 seconds
Started Jun 28 04:46:46 PM PDT 24
Finished Jun 28 04:46:49 PM PDT 24
Peak memory 214336 kb
Host smart-8db45d23-2da1-4499-8ceb-efb498e365c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318598866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3318598866
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2830353528
Short name T479
Test name
Test status
Simulation time 670326818 ps
CPU time 2.48 seconds
Started Jun 28 04:46:45 PM PDT 24
Finished Jun 28 04:46:48 PM PDT 24
Peak memory 206768 kb
Host smart-c815f249-5e01-43ba-8a20-b182ee34f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830353528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2830353528
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1481259764
Short name T788
Test name
Test status
Simulation time 2714991295 ps
CPU time 60.7 seconds
Started Jun 28 04:46:42 PM PDT 24
Finished Jun 28 04:47:44 PM PDT 24
Peak memory 220220 kb
Host smart-45729c58-8858-4b7d-b18f-c5586a30dc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481259764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1481259764
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1975558018
Short name T54
Test name
Test status
Simulation time 2131726089 ps
CPU time 14.64 seconds
Started Jun 28 04:46:50 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 222624 kb
Host smart-136ea3ca-85e9-4a55-bc63-b71a681770ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975558018 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1975558018
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2632359271
Short name T597
Test name
Test status
Simulation time 897952559 ps
CPU time 4.43 seconds
Started Jun 28 04:46:48 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 207272 kb
Host smart-4806560e-2204-4462-a754-6d96050192e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632359271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2632359271
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4256230984
Short name T605
Test name
Test status
Simulation time 105786472 ps
CPU time 2.16 seconds
Started Jun 28 04:46:45 PM PDT 24
Finished Jun 28 04:46:48 PM PDT 24
Peak memory 210064 kb
Host smart-bb58db56-a99e-4ecd-8175-9ec7d99e7fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256230984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4256230984
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4269524578
Short name T760
Test name
Test status
Simulation time 18666308 ps
CPU time 0.95 seconds
Started Jun 28 04:46:57 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 206060 kb
Host smart-05dee93b-490b-4074-aa55-ff88df192124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269524578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4269524578
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.20308745
Short name T324
Test name
Test status
Simulation time 399800751 ps
CPU time 11.22 seconds
Started Jun 28 04:46:49 PM PDT 24
Finished Jun 28 04:47:02 PM PDT 24
Peak memory 214928 kb
Host smart-3de89c05-69fe-4f93-b6ff-101cea6b1f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20308745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.20308745
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2415645943
Short name T71
Test name
Test status
Simulation time 162123511 ps
CPU time 1.53 seconds
Started Jun 28 04:46:34 PM PDT 24
Finished Jun 28 04:46:37 PM PDT 24
Peak memory 208388 kb
Host smart-d69fff1d-4785-452a-9b51-6bb0b90e26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415645943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2415645943
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3947940736
Short name T889
Test name
Test status
Simulation time 41916763 ps
CPU time 1.74 seconds
Started Jun 28 04:46:50 PM PDT 24
Finished Jun 28 04:46:53 PM PDT 24
Peak memory 214224 kb
Host smart-8d735ac3-e522-49ef-886b-dfb9d0671442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947940736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3947940736
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1321707550
Short name T583
Test name
Test status
Simulation time 249957800 ps
CPU time 4.46 seconds
Started Jun 28 04:46:47 PM PDT 24
Finished Jun 28 04:46:52 PM PDT 24
Peak memory 207196 kb
Host smart-ed40c13d-6190-4c72-8a72-0099890650f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321707550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1321707550
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2343113395
Short name T480
Test name
Test status
Simulation time 2239353486 ps
CPU time 17.1 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:16 PM PDT 24
Peak memory 208692 kb
Host smart-270c1095-1e64-4268-9d1a-a3798dfe07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343113395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2343113395
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2937704973
Short name T599
Test name
Test status
Simulation time 113137269 ps
CPU time 2.23 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 206656 kb
Host smart-4e0d2f44-cc96-4be0-b12f-cb054498908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937704973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2937704973
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.135412208
Short name T796
Test name
Test status
Simulation time 332691623 ps
CPU time 4.35 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:04 PM PDT 24
Peak memory 208620 kb
Host smart-adb619a1-828d-4a1e-afa5-94c7c550c809
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135412208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.135412208
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3523013630
Short name T193
Test name
Test status
Simulation time 85837720 ps
CPU time 4.05 seconds
Started Jun 28 04:46:53 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 209276 kb
Host smart-95973330-18a6-457c-980d-17a4ca8ac382
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523013630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3523013630
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2327861302
Short name T759
Test name
Test status
Simulation time 58137679 ps
CPU time 3.33 seconds
Started Jun 28 04:46:39 PM PDT 24
Finished Jun 28 04:46:43 PM PDT 24
Peak memory 208476 kb
Host smart-45ace142-54e0-465d-9815-61baeef4aca2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327861302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2327861302
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2445087857
Short name T343
Test name
Test status
Simulation time 652141254 ps
CPU time 2.97 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 218196 kb
Host smart-416fbf34-151c-4daf-b9d0-425b25d17c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445087857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2445087857
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.713816041
Short name T920
Test name
Test status
Simulation time 149748946 ps
CPU time 2.16 seconds
Started Jun 28 04:46:55 PM PDT 24
Finished Jun 28 04:47:00 PM PDT 24
Peak memory 206560 kb
Host smart-1d310ce2-13b5-494b-8fbb-620ae83168cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713816041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.713816041
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1556008363
Short name T885
Test name
Test status
Simulation time 206957139 ps
CPU time 12.7 seconds
Started Jun 28 04:46:52 PM PDT 24
Finished Jun 28 04:47:06 PM PDT 24
Peak memory 222664 kb
Host smart-e32a2792-4500-419f-b6cd-fb1b5815afa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556008363 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1556008363
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1589621863
Short name T520
Test name
Test status
Simulation time 595393458 ps
CPU time 6.07 seconds
Started Jun 28 04:46:33 PM PDT 24
Finished Jun 28 04:46:41 PM PDT 24
Peak memory 207444 kb
Host smart-9d8669fe-c533-4729-8814-925cda7d1ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589621863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1589621863
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.167300754
Short name T572
Test name
Test status
Simulation time 289117386 ps
CPU time 2.55 seconds
Started Jun 28 04:46:54 PM PDT 24
Finished Jun 28 04:46:59 PM PDT 24
Peak memory 209784 kb
Host smart-521ac70b-eb37-41fd-98ba-955fdae4acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167300754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.167300754
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1535139449
Short name T772
Test name
Test status
Simulation time 44963064 ps
CPU time 0.9 seconds
Started Jun 28 04:44:31 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 205932 kb
Host smart-fbc1359c-04b5-4da3-b836-016338ed9dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535139449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1535139449
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.436202248
Short name T21
Test name
Test status
Simulation time 245726892 ps
CPU time 4.96 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:44:38 PM PDT 24
Peak memory 219640 kb
Host smart-64629dec-123b-4bf2-adb4-f64830d59390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436202248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.436202248
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2300915376
Short name T780
Test name
Test status
Simulation time 362484664 ps
CPU time 2.51 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:31 PM PDT 24
Peak memory 219740 kb
Host smart-074ddbe8-85ac-462f-92e3-513746b99ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300915376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2300915376
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.460166216
Short name T914
Test name
Test status
Simulation time 38629849 ps
CPU time 2.55 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 218536 kb
Host smart-6432370e-bf83-4e20-a067-10492b22e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460166216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.460166216
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2557959457
Short name T563
Test name
Test status
Simulation time 107419078 ps
CPU time 4.72 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:44:38 PM PDT 24
Peak memory 214148 kb
Host smart-bef4c25d-87cf-4d13-8631-46598f1d0465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557959457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2557959457
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1139760347
Short name T880
Test name
Test status
Simulation time 348473349 ps
CPU time 2.24 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 215160 kb
Host smart-c7732057-1a5d-4f0e-b3ec-b925806ff252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139760347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1139760347
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2537217126
Short name T811
Test name
Test status
Simulation time 239783304 ps
CPU time 5.11 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 214308 kb
Host smart-69e70a36-4daf-4813-be0d-4bf80e5425a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537217126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2537217126
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1436568200
Short name T839
Test name
Test status
Simulation time 161414830 ps
CPU time 2.73 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 206768 kb
Host smart-ecdc4a46-8bc0-4d08-9151-ebc2eb31ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436568200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1436568200
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.416223911
Short name T689
Test name
Test status
Simulation time 229721215 ps
CPU time 2.84 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:31 PM PDT 24
Peak memory 206960 kb
Host smart-20a87971-cf51-4d99-a8ce-c9829f7d44ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416223911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.416223911
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2886208314
Short name T575
Test name
Test status
Simulation time 214922362 ps
CPU time 2.75 seconds
Started Jun 28 04:44:27 PM PDT 24
Finished Jun 28 04:44:32 PM PDT 24
Peak memory 206800 kb
Host smart-aa20b22b-0f7e-4765-9bd2-5d1e1ee44176
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886208314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2886208314
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3767890091
Short name T773
Test name
Test status
Simulation time 141057430 ps
CPU time 3.56 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:35 PM PDT 24
Peak memory 208568 kb
Host smart-d1a3727d-e9d6-49c6-b7fe-75cbb6a75f02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767890091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3767890091
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.936453804
Short name T875
Test name
Test status
Simulation time 294210692 ps
CPU time 3.76 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 208564 kb
Host smart-6d0fbc65-a8e5-4da1-b3b0-eb496b4e61d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936453804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.936453804
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3808851121
Short name T590
Test name
Test status
Simulation time 188147387 ps
CPU time 2.72 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 208204 kb
Host smart-2441dc22-a6c2-4d1c-b5d0-64e19843fffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808851121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3808851121
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1931241214
Short name T859
Test name
Test status
Simulation time 907675701 ps
CPU time 12.58 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 222548 kb
Host smart-c72c4a51-38d8-4cf4-83a3-a20c4b9cd5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931241214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1931241214
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3745273584
Short name T652
Test name
Test status
Simulation time 4125360592 ps
CPU time 12.79 seconds
Started Jun 28 04:44:29 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 210368 kb
Host smart-35091dc3-7f0d-4a1d-8752-59b4b8f95cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745273584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3745273584
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2857503563
Short name T535
Test name
Test status
Simulation time 94715938 ps
CPU time 2.43 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 210240 kb
Host smart-46ddd54d-0ee0-4a2e-a130-94529a883b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857503563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2857503563
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1610504001
Short name T442
Test name
Test status
Simulation time 109399013 ps
CPU time 0.8 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:41 PM PDT 24
Peak memory 205940 kb
Host smart-915569f2-1dbc-4668-8d93-9986c2dfdefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610504001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1610504001
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4032014777
Short name T10
Test name
Test status
Simulation time 60052796 ps
CPU time 3.25 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 209004 kb
Host smart-7e0e0317-a951-4ccb-a828-6e4c0d9705f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032014777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4032014777
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3770265898
Short name T678
Test name
Test status
Simulation time 135435176 ps
CPU time 2.09 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:43 PM PDT 24
Peak memory 218204 kb
Host smart-7160a391-4c14-4f8e-9f50-4a7cbdbcf249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770265898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3770265898
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.640413490
Short name T641
Test name
Test status
Simulation time 29032312 ps
CPU time 2.31 seconds
Started Jun 28 04:44:44 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 215028 kb
Host smart-c6194c22-57d5-4ff6-90fa-4ef11f2f4360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640413490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.640413490
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2879941312
Short name T265
Test name
Test status
Simulation time 47104546 ps
CPU time 1.98 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 214256 kb
Host smart-dd32704d-d812-4d04-b5c6-48a7ac7868e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879941312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2879941312
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1795780692
Short name T202
Test name
Test status
Simulation time 81937517 ps
CPU time 3.04 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 214212 kb
Host smart-7ddc9548-4427-406f-af81-9c076dae5ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795780692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1795780692
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1236180227
Short name T334
Test name
Test status
Simulation time 264923537 ps
CPU time 6.86 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:37 PM PDT 24
Peak memory 218036 kb
Host smart-42074072-ccf9-423b-b8b0-cee54568f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236180227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1236180227
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1848995957
Short name T632
Test name
Test status
Simulation time 193489979 ps
CPU time 2.86 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:33 PM PDT 24
Peak memory 208604 kb
Host smart-39732a59-1ade-45eb-8ca6-c20dc789e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848995957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1848995957
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.487112228
Short name T666
Test name
Test status
Simulation time 137336852 ps
CPU time 2.71 seconds
Started Jun 28 04:44:28 PM PDT 24
Finished Jun 28 04:44:34 PM PDT 24
Peak memory 208904 kb
Host smart-3400c44e-1411-44d7-ac8a-96cfe4bc2351
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487112228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.487112228
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3839595756
Short name T508
Test name
Test status
Simulation time 634536045 ps
CPU time 4.32 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:44:38 PM PDT 24
Peak memory 206828 kb
Host smart-b394beed-f445-4f02-b036-d5588a146504
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839595756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3839595756
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1245948298
Short name T529
Test name
Test status
Simulation time 1084758177 ps
CPU time 25.3 seconds
Started Jun 28 04:44:30 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 208256 kb
Host smart-8fdf7fb5-8bd7-4e40-bf71-94baddcf3c6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245948298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1245948298
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3828119602
Short name T463
Test name
Test status
Simulation time 419391572 ps
CPU time 2.67 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 214164 kb
Host smart-49027194-2a1d-45ff-83db-ea22a40fb9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828119602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3828119602
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2831262168
Short name T592
Test name
Test status
Simulation time 42414732 ps
CPU time 2.27 seconds
Started Jun 28 04:44:31 PM PDT 24
Finished Jun 28 04:44:36 PM PDT 24
Peak memory 206816 kb
Host smart-3b3d1da0-af36-4a92-8ae5-856720036c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831262168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2831262168
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.168027835
Short name T905
Test name
Test status
Simulation time 195768604 ps
CPU time 8.23 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 222404 kb
Host smart-e96444f6-fcce-4f6b-921f-fc0b90da9521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168027835 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.168027835
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.167034004
Short name T858
Test name
Test status
Simulation time 90572090 ps
CPU time 3.97 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:47 PM PDT 24
Peak memory 218160 kb
Host smart-5860897e-f965-4dbd-9a98-83549bb53c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167034004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.167034004
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3311972973
Short name T464
Test name
Test status
Simulation time 48935617 ps
CPU time 2.93 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 210616 kb
Host smart-6e5d36ad-5ec1-4480-8297-b7fbdd24c683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311972973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3311972973
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2650268933
Short name T102
Test name
Test status
Simulation time 48140923 ps
CPU time 0.72 seconds
Started Jun 28 04:44:43 PM PDT 24
Finished Jun 28 04:44:47 PM PDT 24
Peak memory 206048 kb
Host smart-3f6e3673-7d6c-4616-9c1c-e0347438914b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650268933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2650268933
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3451001093
Short name T411
Test name
Test status
Simulation time 216587609 ps
CPU time 4.02 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 214460 kb
Host smart-af2a9d26-a5b8-4b39-b348-2c1db998ccbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3451001093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3451001093
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2983552651
Short name T355
Test name
Test status
Simulation time 280753080 ps
CPU time 3.29 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 209724 kb
Host smart-ada8bec8-4553-41e5-acbc-ad8305a41ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983552651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2983552651
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3769627190
Short name T745
Test name
Test status
Simulation time 324587699 ps
CPU time 13.2 seconds
Started Jun 28 04:44:43 PM PDT 24
Finished Jun 28 04:44:59 PM PDT 24
Peak memory 214312 kb
Host smart-968eb361-0326-47c9-9cbe-fda06d344b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769627190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3769627190
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.955117576
Short name T44
Test name
Test status
Simulation time 48578581 ps
CPU time 2.76 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 222372 kb
Host smart-b80ad933-26e4-4017-b249-0efd02a59681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955117576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.955117576
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3578324142
Short name T721
Test name
Test status
Simulation time 461400384 ps
CPU time 5.19 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 218216 kb
Host smart-de57240f-a068-42f2-8318-d40bfa21a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578324142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3578324142
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3531828972
Short name T648
Test name
Test status
Simulation time 423407119 ps
CPU time 5.99 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:49 PM PDT 24
Peak memory 214248 kb
Host smart-f5d75a5b-b2c2-4c18-afd0-22b40aabfbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531828972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3531828972
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4221343474
Short name T631
Test name
Test status
Simulation time 1023883180 ps
CPU time 3.26 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:43 PM PDT 24
Peak memory 208612 kb
Host smart-24793ac9-0181-47e5-bddf-269076cd2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221343474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4221343474
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.166399349
Short name T545
Test name
Test status
Simulation time 80519686 ps
CPU time 2.85 seconds
Started Jun 28 04:44:44 PM PDT 24
Finished Jun 28 04:44:49 PM PDT 24
Peak memory 206964 kb
Host smart-2007407f-3d33-4e7f-b38f-ea55ee5b5be5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166399349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.166399349
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4059256125
Short name T397
Test name
Test status
Simulation time 135395635 ps
CPU time 2.32 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 206832 kb
Host smart-3e76eb8c-8483-4dcd-9581-aa62e16592ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059256125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4059256125
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4264784929
Short name T286
Test name
Test status
Simulation time 895752681 ps
CPU time 5.58 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 208420 kb
Host smart-3adcb0fe-defc-432d-8d68-c0404ddb8d92
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264784929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4264784929
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.273227149
Short name T467
Test name
Test status
Simulation time 67722363 ps
CPU time 1.59 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 207136 kb
Host smart-f9e966cb-545b-4b8e-bf5f-4763981325d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273227149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.273227149
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3647229229
Short name T591
Test name
Test status
Simulation time 72784415 ps
CPU time 3.09 seconds
Started Jun 28 04:44:42 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 208256 kb
Host smart-ea43121d-01ae-4699-befb-86f7a408567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647229229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3647229229
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1131173828
Short name T178
Test name
Test status
Simulation time 800017703 ps
CPU time 30.78 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:45:14 PM PDT 24
Peak memory 220340 kb
Host smart-41e9e298-d2e9-47b7-aa7f-456f95739b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131173828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1131173828
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1809251187
Short name T276
Test name
Test status
Simulation time 2555512208 ps
CPU time 58.65 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:45:40 PM PDT 24
Peak memory 218376 kb
Host smart-928e2cf3-1385-49f6-b725-9a41420b648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809251187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1809251187
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2180255270
Short name T477
Test name
Test status
Simulation time 42814577 ps
CPU time 0.73 seconds
Started Jun 28 04:44:42 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 205944 kb
Host smart-e7eb2ba8-36ee-42d0-8ad9-762db0488aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180255270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2180255270
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.340337331
Short name T686
Test name
Test status
Simulation time 38265996 ps
CPU time 2.07 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 208792 kb
Host smart-2e531178-3a23-4805-a498-ca8eefb98c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340337331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.340337331
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3367881688
Short name T66
Test name
Test status
Simulation time 5021194101 ps
CPU time 11.97 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:44:53 PM PDT 24
Peak memory 218372 kb
Host smart-fa4e5b2f-44fe-4599-b488-02d428cb2cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367881688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3367881688
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3315845406
Short name T727
Test name
Test status
Simulation time 61671903 ps
CPU time 2.31 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 209540 kb
Host smart-855144f8-e1b7-47d2-ae83-6518fbb2a371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315845406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3315845406
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3596855462
Short name T765
Test name
Test status
Simulation time 94464130 ps
CPU time 2.04 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 214276 kb
Host smart-66a8b3c1-b2a5-4c13-bf5c-5880e03e12ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596855462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3596855462
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_random.3595175034
Short name T197
Test name
Test status
Simulation time 44451314 ps
CPU time 3.16 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 214208 kb
Host smart-97035978-1094-499c-b0ef-1b17bafb0ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595175034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3595175034
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.907900533
Short name T723
Test name
Test status
Simulation time 43716961 ps
CPU time 2.49 seconds
Started Jun 28 04:44:43 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 208448 kb
Host smart-db108044-de1e-43dc-9af8-3b0c6d45a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907900533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.907900533
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2704292556
Short name T829
Test name
Test status
Simulation time 84422871 ps
CPU time 3.9 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:47 PM PDT 24
Peak memory 208736 kb
Host smart-88bda40f-fa76-4b2e-9ee6-7413a14aada7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704292556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2704292556
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1986769242
Short name T194
Test name
Test status
Simulation time 217983674 ps
CPU time 3.31 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 206984 kb
Host smart-d9345dee-7b99-4cdc-bb95-5df0ea419302
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986769242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1986769242
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4106242187
Short name T459
Test name
Test status
Simulation time 160559586 ps
CPU time 4.54 seconds
Started Jun 28 04:44:44 PM PDT 24
Finished Jun 28 04:44:51 PM PDT 24
Peak memory 208020 kb
Host smart-5bcb153e-0516-49ae-870a-d4578836c0ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106242187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4106242187
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2481014329
Short name T319
Test name
Test status
Simulation time 202984461 ps
CPU time 2.17 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 214300 kb
Host smart-61f2e090-0549-4228-b54b-11ee62b3b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481014329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2481014329
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.93940519
Short name T576
Test name
Test status
Simulation time 56858279 ps
CPU time 1.77 seconds
Started Jun 28 04:44:42 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 206540 kb
Host smart-a40bd2c2-d349-4766-a10a-43f8c93f5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93940519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.93940519
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3083929459
Short name T181
Test name
Test status
Simulation time 5449074529 ps
CPU time 43.14 seconds
Started Jun 28 04:44:39 PM PDT 24
Finished Jun 28 04:45:23 PM PDT 24
Peak memory 222648 kb
Host smart-69ff8573-a79c-46ae-bd23-0035ce168af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083929459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3083929459
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1633232108
Short name T30
Test name
Test status
Simulation time 166267705 ps
CPU time 3.29 seconds
Started Jun 28 04:44:38 PM PDT 24
Finished Jun 28 04:44:42 PM PDT 24
Peak memory 207184 kb
Host smart-6524ec55-4b21-4b67-be69-640b525f9e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633232108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1633232108
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2409291114
Short name T593
Test name
Test status
Simulation time 186863212 ps
CPU time 2.96 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 210472 kb
Host smart-00eee3dd-71ef-4a0f-beeb-6b2bf92bde85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409291114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2409291114
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2648532048
Short name T769
Test name
Test status
Simulation time 52534564 ps
CPU time 0.87 seconds
Started Jun 28 04:44:56 PM PDT 24
Finished Jun 28 04:44:58 PM PDT 24
Peak memory 205876 kb
Host smart-bf8fa596-f7f8-4d6c-878d-bf34b368ad5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648532048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2648532048
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1247912763
Short name T415
Test name
Test status
Simulation time 32711646 ps
CPU time 2.58 seconds
Started Jun 28 04:44:43 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 215192 kb
Host smart-80492e94-e707-49c6-8b04-c0606ff5a52b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247912763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1247912763
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1869481083
Short name T209
Test name
Test status
Simulation time 37330396 ps
CPU time 1.87 seconds
Started Jun 28 04:44:57 PM PDT 24
Finished Jun 28 04:45:01 PM PDT 24
Peak memory 219676 kb
Host smart-15646346-c6ca-4da3-893c-60c98e8a3668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869481083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1869481083
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3501542225
Short name T628
Test name
Test status
Simulation time 1806890949 ps
CPU time 14.71 seconds
Started Jun 28 04:44:42 PM PDT 24
Finished Jun 28 04:45:00 PM PDT 24
Peak memory 209544 kb
Host smart-67696e49-0b55-4e67-bbc0-72d0b8837bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501542225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3501542225
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.516830708
Short name T720
Test name
Test status
Simulation time 316283972 ps
CPU time 2.68 seconds
Started Jun 28 04:44:56 PM PDT 24
Finished Jun 28 04:45:00 PM PDT 24
Peak memory 214360 kb
Host smart-a7355f2d-862c-44b6-a40f-b3aa422256cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516830708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.516830708
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2804338065
Short name T234
Test name
Test status
Simulation time 172186170 ps
CPU time 2.41 seconds
Started Jun 28 04:44:56 PM PDT 24
Finished Jun 28 04:44:59 PM PDT 24
Peak memory 214264 kb
Host smart-355195bb-3e78-4b4e-890f-b9bffb65b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804338065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2804338065
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1221801833
Short name T615
Test name
Test status
Simulation time 902488539 ps
CPU time 4.38 seconds
Started Jun 28 04:44:38 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 209948 kb
Host smart-11c51032-6ba1-4cf9-b009-d0c455cb9598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221801833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1221801833
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.4019056334
Short name T527
Test name
Test status
Simulation time 351543198 ps
CPU time 3.74 seconds
Started Jun 28 04:44:43 PM PDT 24
Finished Jun 28 04:44:49 PM PDT 24
Peak memory 207680 kb
Host smart-a262cd81-48b5-45c9-8e04-185033138c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019056334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.4019056334
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.836193204
Short name T256
Test name
Test status
Simulation time 1795050233 ps
CPU time 6.51 seconds
Started Jun 28 04:44:42 PM PDT 24
Finished Jun 28 04:44:51 PM PDT 24
Peak memory 206652 kb
Host smart-9e0b7e52-f943-4bcc-a666-26bdd9f48038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836193204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.836193204
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3811592028
Short name T757
Test name
Test status
Simulation time 147808957 ps
CPU time 4.24 seconds
Started Jun 28 04:44:41 PM PDT 24
Finished Jun 28 04:44:47 PM PDT 24
Peak memory 208148 kb
Host smart-0f5ee183-904b-4642-81c8-9f4b2510f0a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811592028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3811592028
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2338010954
Short name T312
Test name
Test status
Simulation time 305334856 ps
CPU time 4.25 seconds
Started Jun 28 04:44:43 PM PDT 24
Finished Jun 28 04:44:50 PM PDT 24
Peak memory 208816 kb
Host smart-d3b27266-132d-40a6-92a1-d4338d8f4294
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338010954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2338010954
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.52491395
Short name T451
Test name
Test status
Simulation time 21411031790 ps
CPU time 49.96 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:45:32 PM PDT 24
Peak memory 208984 kb
Host smart-c1332bcd-3578-4eb3-bc5e-108bb4ade588
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52491395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.52491395
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2077469105
Short name T543
Test name
Test status
Simulation time 630641884 ps
CPU time 4.47 seconds
Started Jun 28 04:44:58 PM PDT 24
Finished Jun 28 04:45:04 PM PDT 24
Peak memory 209512 kb
Host smart-73545106-649a-4ac7-91ac-0404a437d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077469105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2077469105
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3181143818
Short name T544
Test name
Test status
Simulation time 23188462 ps
CPU time 1.63 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:43 PM PDT 24
Peak memory 206928 kb
Host smart-7e5ad3da-2ad4-4ab4-9c73-747c14e7142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181143818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3181143818
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.922546653
Short name T122
Test name
Test status
Simulation time 1225289763 ps
CPU time 21.44 seconds
Started Jun 28 04:44:55 PM PDT 24
Finished Jun 28 04:45:17 PM PDT 24
Peak memory 222616 kb
Host smart-333739d6-d697-40ca-b493-a472466df67b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922546653 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.922546653
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1006660389
Short name T482
Test name
Test status
Simulation time 61815743 ps
CPU time 2.72 seconds
Started Jun 28 04:44:40 PM PDT 24
Finished Jun 28 04:44:45 PM PDT 24
Peak memory 208076 kb
Host smart-3c17e25d-1198-4b5b-9aac-5f420d33bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006660389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1006660389
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.123934653
Short name T50
Test name
Test status
Simulation time 410796757 ps
CPU time 2.59 seconds
Started Jun 28 04:44:53 PM PDT 24
Finished Jun 28 04:44:56 PM PDT 24
Peak memory 210248 kb
Host smart-19a968c7-0a64-4c7e-beb6-a536a5f89109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123934653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.123934653
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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