Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.37	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	49	13	36	73.47

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	0	5	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	12	23	65.71	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	47	1			T40	1		T25	1		T22	1
auto[OpGenId]	14	1			T65	1		T30	1		T210	1
auto[OpGenSwOut]	15	1			T49	1		T51	1		T63	1
auto[OpGenHwOut]	22	1			T27	1		T100	1		T6	1
auto[OpDisable]	1	1			T211	1		-	-		-	-

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1686	1			T43	4		T52	4		T27	1
auto[StInit]	91	1			T49	1		T22	1		T100	1
auto[StCreatorRootKey]	59	1			T53	1		T7	1		T63	2
auto[StOwnerIntKey]	39	1			T4	1		T17	1		T57	1
auto[StOwnerKey]	40	1			T40	1		T25	1		T19	1
auto[StDisabled]	451	1			T17	9		T43	9		T52	13
auto[StInvalid]	50	1			T1	1		T14	1		T32	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3400

1

T1

2

T2

1

T3

1

auto[1]

99

1

T40

1

T25

1

T49

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1677	1			T43	4		T52	4		T6	2
auto[StReset]	auto[1]	9	1			T27	1		T148	1		T30	1
auto[StInit]	auto[0]	43	1			T83	1		T20	1		T113	1
auto[StInit]	auto[1]	48	1			T49	1		T22	1		T100	1
auto[StCreatorRootKey]	auto[0]	40	1			T53	1		T63	2		T21	1
auto[StCreatorRootKey]	auto[1]	19	1			T7	1		T35	1		T8	1
auto[StOwnerIntKey]	auto[0]	31	1			T4	1		T17	1		T57	1
auto[StOwnerIntKey]	auto[1]	8	1			T193	1		T212	1		T213	1
auto[StOwnerKey]	auto[0]	32	1			T19	1		T34	1		T37	1
auto[StOwnerKey]	auto[1]	8	1			T40	1		T25	1		T214	1
auto[StDisabled]	auto[0]	444	1			T17	9		T43	9		T52	13
auto[StDisabled]	auto[1]	7	1			T215	1		T216	1		T217	1
auto[StInvalid]	auto[0]	50	1			T1	1		T14	1		T32	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	12	23	65.71	12

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T46	1		T47	1		T218	1
auto[StReset]	auto[OpGenId]	1	1			T30	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	2	1			T27	1		T148	1		-	-
auto[StInit]	auto[OpAdvance]	22	1			T22	1		T9	1		T145	1
auto[StInit]	auto[OpGenId]	3	1			T65	1		T219	1		T151	1
auto[StInit]	auto[OpGenSwOut]	12	1			T49	1		T51	1		T63	1
auto[StInit]	auto[OpGenHwOut]	10	1			T100	1		T6	1		T206	1
auto[StInit]	auto[OpDisable]	1	1			T211	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T41	1		T217	1		T220	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T221	1		T222	1		T223	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	1	1			T72	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	7	1			T7	1		T35	1		T8	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T193	1		T212	1		T224	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T213	1		T225	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T226	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	3	1			T40	1		T25	1		T214	1
auto[StOwnerKey]	auto[OpGenId]	3	1			T227	1		T223	1		T228	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T229	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T230	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T216	1		T217	1		T158	1
auto[StDisabled]	auto[OpGenId]	2	1			T210	1		T231	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T215	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T232	1		-	-		-	-