Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4739

1

T1

1

T3

1

T4

3

auto[1]

539

1

T3

5

T17

3

T18

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4739

1

T1

1

T3

1

T4

3

auto[1]

539

1

T3

5

T17

3

T18

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4688

1

T1

1

T3

4

T4

3

auto[1]

590

1

T3

2

T16

4

T17

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4688

1

T1

1

T3

4

T4

3

auto[1]

590

1

T3

2

T16

4

T17

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T5	3		T14	1		T17	2
auto[OpGenId]	1091	1			T3	3		T4	2		T14	6
auto[OpGenSwOut]	1144	1			T1	1		T5	1		T17	9
auto[OpGenHwOut]	2560	1			T3	3		T4	1		T5	1
auto[OpDisable]	56	1			T43	1		T61	1		T52	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T5	3		T14	1		T17	2
auto[OpGenId]	1091	1			T3	3		T4	2		T14	6
auto[OpGenSwOut]	1144	1			T1	1		T5	1		T17	9
auto[OpGenHwOut]	2560	1			T3	3		T4	1		T5	1
auto[OpDisable]	56	1			T43	1		T61	1		T52	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4682

1

T1

1

T3

6

T4

3

auto[1]

596

1

T5

1

T17

2

T38

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4682

1

T1

1

T3

6

T4

3

auto[1]

596

1

T5

1

T17

2

T38

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5031

1

T1

1

T3

6

T4

3

auto[1]

247

1

T87

6

T118

16

T134

15

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1854	1			T1	1		T3	3		T4	2
auto[1]	714	1			T4	1		T5	1		T17	4
auto[2]	698	1			T3	2		T14	4		T16	2
auto[3]	657	1			T3	1		T5	1		T14	2
auto[4]	363	1			T17	4		T18	1		T32	1
auto[5]	315	1			T16	1		T17	4		T104	1
auto[6]	326	1			T18	1		T31	1		T44	1
auto[7]	351	1			T17	1		T38	1		T86	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1355	1			T16	1		T17	9		T18	2
clear_one[1]	714	1			T4	1		T5	1		T17	4
clear_one[2]	698	1			T3	2		T14	4		T16	2
clear_one[3]	657	1			T3	1		T5	1		T14	2
clear_none	1854	1			T1	1		T3	3		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	945	1			T14	4		T17	8		T18	1
auto[StInit]	648	1			T3	1		T4	1		T5	1
auto[StCreatorRootKey]	603	1			T3	1		T4	1		T5	1
auto[StOwnerIntKey]	510	1			T3	1		T4	1		T16	1
auto[StOwnerKey]	479	1			T3	1		T16	1		T17	2
auto[StDisabled]	1831	1			T3	2		T5	3		T16	4
auto[StInvalid]	262	1			T1	1		T14	4		T32	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	945	1			T14	4		T17	8		T18	1
auto[StInit]	648	1			T3	1		T4	1		T5	1
auto[StCreatorRootKey]	603	1			T3	1		T4	1		T5	1
auto[StOwnerIntKey]	510	1			T3	1		T4	1		T16	1
auto[StOwnerKey]	479	1			T3	1		T16	1		T17	2
auto[StDisabled]	1831	1			T3	2		T5	3		T16	4
auto[StInvalid]	262	1			T1	1		T14	4		T32	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T233	2		T234	1		T235	1
auto[0]	auto[StReset]	auto[OpGenId]	140	1			T14	2		T17	1		T43	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	167	1			T17	2		T88	1		T43	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	246	1			T17	3		T18	1		T31	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T5	1		T134	1		T64	1
auto[0]	auto[StInit]	auto[OpGenId]	85	1			T4	1		T24	1		T89	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	99	1			T23	1		T197	1		T52	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	189	1			T3	1		T16	1		T86	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T134	1		T236	1		T127	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	51	1			T3	1		T17	1		T52	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	62	1			T87	1		T196	1		T134	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	86	1			T43	1		T52	1		T53	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T33	1		T137	1		T237	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T4	1		T61	1		T202	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	34	1			T87	2		T52	2		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	67	1			T3	1		T17	1		T18	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T136	1		T46	1		T238	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T66	1		T239	1		T137	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	29	1			T6	1		T240	1		T123	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T17	1		T38	1		T43	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T5	1		T38	1		T52	2
auto[0]	auto[StDisabled]	auto[OpGenId]	79	1			T17	2		T43	1		T52	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T43	1		T241	1		T64	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T5	1		T16	2		T204	1
auto[0]	auto[StDisabled]	auto[OpDisable]	13	1			T52	1		T242	1		T206	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T243	1		T244	1		T97	1
auto[0]	auto[StInvalid]	auto[OpGenId]	23	1			T44	1		T245	2		T246	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T1	1		T45	1		T104	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	26	1			T32	1		T45	1		T90	1
auto[1]	auto[StReset]	auto[OpGenId]	18	1			T43	1		T89	1		T104	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T52	1		T82	1		T28	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	46	1			T43	1		T247	2		T248	1
auto[1]	auto[StInit]	auto[OpAdvance]	2	1			T249	1		T250	1		-	-
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T88	1		T251	1		T252	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	10	1			T6	1		T253	1		T254	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	20	1			T79	1		T255	1		T256	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T118	2		T206	1		T158	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T92	1		T52	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T5	1		T24	1		T200	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T4	1		T247	1		T258	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T43	1		T259	1		T260	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T17	1		T81	1		T240	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T24	1		T52	1		T118	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T261	1		T262	1		T263	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T264	1		T265	1		T74	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	18	1			T40	1		T64	1		T240	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T134	3		T236	1		T206	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T24	1		T204	1		T118	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T266	1		T6	1		T267	1
auto[1]	auto[StDisabled]	auto[OpGenId]	60	1			T17	1		T43	1		T135	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T17	1		T38	1		T50	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T17	1		T18	2		T52	1
auto[1]	auto[StDisabled]	auto[OpDisable]	12	1			T43	1		T52	1		T268	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T245	1		T269	1		T270	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T90	1		T271	1		T243	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T243	1		T272	1		T273	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T44	1		T274	1		T275	1
auto[2]	auto[StReset]	auto[OpGenId]	13	1			T14	1		T43	1		T6	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T276	1		T135	1		T275	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	38	1			T89	1		T208	1		T148	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T23	1		T251	1		T214	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T31	1		T79	1		T277	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	14	1			T33	1		T278	1		T8	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T17	1		T208	1		T279	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T17	1		T80	1		T280	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T52	1		T199	1		T118	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T86	1		T43	2		T34	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T16	1		T17	1		T18	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T281	1		T229	1		T282	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	26	1			T6	1		T64	1		T240	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T29	1		T267	1		T217	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T16	1		T204	1		T208	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T118	1		T283	1		T221	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T200	1		T52	1		T284	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T6	1		T285	1		T286	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T3	1		T43	2		T258	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T92	1		T118	4		T287	1
auto[2]	auto[StDisabled]	auto[OpGenId]	47	1			T3	1		T118	3		T6	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T17	1		T87	1		T43	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T17	1		T18	1		T88	1
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T255	1		T288	1		T286	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T14	1		T289	1		T290	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T14	1		T104	1		T291	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T32	1		T292	2		T275	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T14	1		T293	1		T294	2
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T14	1		T43	1		T6	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	11	1			T89	1		T66	1		T206	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	52	1			T247	1		T295	1		T279	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T259	1		T296	1		T297	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T43	1		T92	1		T79	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T17	1		T23	1		T298	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	17	1			T93	1		T299	1		T295	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T286	1		T300	1		T230	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T63	1		T301	1		T217	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T302	1		T80	1		T303	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T304	1		T208	1		T305	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T8	1		T46	1		T221	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T31	1		T25	1		T93	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T127	1		T47	1		T221	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T86	1		T306	1		T129	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T87	1		T127	1		T307	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	17	1			T19	1		T259	1		T29	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T216	1		T46	1		T308	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T18	1		T208	1		T209	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	33	1			T5	1		T134	4		T202	1
auto[3]	auto[StDisabled]	auto[OpGenId]	49	1			T3	1		T38	1		T52	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T17	2		T43	1		T134	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T16	2		T43	1		T304	1
auto[3]	auto[StDisabled]	auto[OpDisable]	4	1			T309	1		T310	1		T182	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T246	1		T293	1		T275	1
auto[3]	auto[StInvalid]	auto[OpGenId]	13	1			T14	1		T276	1		T33	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T33	1		T292	1		T272	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T104	1		T90	1		T246	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T17	1		T219	1		T214	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T17	1		T27	1		T199	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T43	1		T276	1		T304	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T311	1		T312	1		T313	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T311	1		T314	1		T307	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T23	1		T315	1		T127	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T316	1		T317	1		T318	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T135	1		T47	1		T319	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T296	1		T216	1		T320	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T284	1		T311	1		T286	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T316	1		T321	1		T263	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T138	1		T322	2		T323	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T17	1		T193	1		T324	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T322	1		T325	1		T326	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T135	1		T327	1		T328	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T329	1		T330	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T17	1		T52	2		T46	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T6	1		T280	1		T331	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T86	1		T332	1		T333	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	23	1			T6	1		T191	1		T46	1
auto[4]	auto[StDisabled]	auto[OpGenId]	15	1			T52	1		T334	1		T303	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T88	1		T260	1		T219	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	91	1			T18	1		T52	1		T209	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T6	1		T191	1		T253	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T32	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T335	1		T336	1		T290	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T337	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T45	1		T275	1		T273	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T268	1		T137	1		T338	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T221	1		T339	1		T340	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	20	1			T247	1		T279	1		T341	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T260	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T81	1		T268	1		T158	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	2	1			T64	1		T342	1		-	-
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T209	1		T34	1		T343	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T137	1		T127	1		T217	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T202	1		T344	1		T345	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T99	1		T98	1		T74	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T346	1		T248	1		T347	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T17	1		T66	1		T297	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T137	1		T206	1		T348	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T199	1		T82	1		T284	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T248	1		T349	1		T350	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T351	1		T46	1		T352	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	8	1			T191	1		T216	1		T217	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T202	1		T353	1		T354	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T16	1		T205	1		T299	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T355	1		T192	1		T356	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T17	1		T52	1		T135	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	12	1			T17	1		T357	1		T233	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T17	1		T52	1		T204	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T229	1		T358	1		T359	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T104	1		T90	1		T338	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T84	2		T245	1		T360	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T289	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T246	1		T269	1		T338	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T50	1		T203	1		T79	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	5	1			T361	1		T72	1		T181	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	21	1			T208	1		T328	1		T343	1
auto[6]	auto[StInit]	auto[OpAdvance]	6	1			T79	1		T354	1		T362	1
auto[6]	auto[StInit]	auto[OpGenId]	2	1			T363	1		T364	1		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	11	1			T6	1		T96	1		T365	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T18	1		T304	1		T263	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T366	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T203	1		T353	1		T206	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T8	1		T285	1		T47	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T52	1		T204	1		T367	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T89	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T203	1		T368	1		T369	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T370	1		T351	1		T206	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T205	1		T209	1		T279	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T371	1		T339	1		T48	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T372	1		T369	1		T373	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T95	1		T206	1		T369	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T247	1		T374	1		T375	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	5	1			T376	1		T307	1		T377	1
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T94	1		T284	1		T378	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	17	1			T94	1		T311	1		T379	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T31	1		T204	1		T304	1
auto[6]	auto[StDisabled]	auto[OpDisable]	1	1			T380	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T274	1		T84	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T292	1		T54	1		T381	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T291	1		T244	1		T382	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T44	1		T245	1		T97	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T27	1		T71	1		T383	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T43	1		T8	1		T47	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	23	1			T209	1		T384	1		T111	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T385	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T206	1		T194	1		T386	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T387	1		T194	1		T180	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T247	1		T85	1		T388	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T354	1		T389	1		T390	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T93	1		T66	1		T63	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T385	3		T217	1		T48	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T391	1		T374	1		T262	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T392	1		T393	1		T394	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T158	1		T395	1		T339	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T191	1		T219	1		T396	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T304	1		T85	1		T258	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T241	1		T397	2		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T43	1		T191	1		T377	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T368	1		T158	1		T386	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T261	1		T316	1		T327	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	17	1			T38	1		T87	1		T43	1
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T86	1		T99	1		T398	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T87	2		T52	1		T346	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T17	1		T87	1		T205	2
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T61	1		T70	1		T331	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T274	1		T269	1		T270	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T269	1		T399	1		T400	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T276	1		T401	1		T402	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T91	1		T54	1		T403	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1355

1

T16

1

T17

9

T18

2

clear_one[1]

auto[0]

auto[0]

auto[0]

419

1

T4

1

T5

1

T17

3

clear_one[1]

auto[0]

auto[0]

auto[1]

121

1

T40

1

T43

1

T92

1

clear_one[1]

auto[0]

auto[1]

auto[0]

130

1

T17

1

T43

1

T208

1

clear_one[1]

auto[0]

auto[1]

auto[1]

44

1

T38

1

T52

2

T134

3

clear_one[2]

auto[0]

auto[0]

auto[0]

386

1

T14

4

T16

2

T17

2

clear_one[2]

auto[0]

auto[0]

auto[1]

158

1

T17

1

T43

3

T52

1

clear_one[2]

auto[1]

auto[0]

auto[0]

120

1

T3

2

T17

2

T18

2

clear_one[2]

auto[1]

auto[0]

auto[1]

34

1

T88

1

T92

3

T355

1

clear_one[3]

auto[0]

auto[0]

auto[0]

379

1

T5

1

T14

2

T17

2

clear_one[3]

auto[0]

auto[1]

auto[0]

115

1

T16

2

T17

1

T43

1

clear_one[3]

auto[1]

auto[0]

auto[0]

114

1

T3

1

T18

1

T31

1

clear_one[3]

auto[1]

auto[1]

auto[0]

49

1

T87

1

T52

1

T129

2

clear_none

auto[0]

auto[0]

auto[0]

1307

1

T1

1

T3

1

T4

2

clear_none

auto[0]

auto[0]

auto[1]

143

1

T5

1

T17

1

T87

1

clear_none

auto[0]

auto[1]

auto[0]

142

1

T16

2

T17

1

T208

1

clear_none

auto[0]

auto[1]

auto[1]

40

1

T87

2

T43

1

T52

2

clear_none

auto[1]

auto[0]

auto[0]

126

1

T17

1

T18

1

T38

1

clear_none

auto[1]

auto[0]

auto[1]

26

1

T88

1

T129

1

T355

1

clear_none

auto[1]

auto[1]

auto[0]

40

1

T3

2

T52

1

T134

3

clear_none

auto[1]

auto[1]

auto[1]

30

1

T38

1

T87

1

T52

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1285	1			T16	1		T17	9		T18	2
clear_all	auto[1]	70	1			T87	3		T135	2		T241	1
clear_one[1]	auto[0]	683	1			T4	1		T5	1		T17	4
clear_one[1]	auto[1]	31	1			T118	2		T134	2		T137	3
clear_one[2]	auto[0]	655	1			T3	2		T14	4		T16	2
clear_one[2]	auto[1]	43	1			T118	11		T134	1		T137	1
clear_one[3]	auto[0]	633	1			T3	1		T5	1		T14	2
clear_one[3]	auto[1]	24	1			T134	6		T404	2		T311	4
clear_none	auto[0]	1775	1			T1	1		T3	3		T4	2
clear_none	auto[1]	79	1			T87	3		T118	3		T134	6