Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11163

1

T1

2

T3

8

T4

2

auto[Attestation]

7804

1

T3

17

T4

6

T5

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2746	1			T1	1		T3	4		T4	2
auto[Aes]	3376	1			T3	3		T4	2		T5	1
auto[Kmac]	3470	1			T1	1		T3	5		T4	1
auto[Otbn]	3389	1			T3	2		T5	2		T14	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7772	1			T1	2		T3	8		T4	3
auto[OpGenId]	5986	1			T3	11		T4	3		T5	1
auto[OpGenSwOut]	6031	1			T3	4		T4	2		T5	4
auto[OpGenHwOut]	6950	1			T1	2		T3	10		T4	3
auto[OpDisable]	127	1			T17	1		T31	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10697

1

T1

1

T3

17

T4

8

auto[OpDoneFail]

16169

1

T1

3

T3

16

T4

3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6425	1			T1	1		T3	1		T4	1
auto[StInit]	3836	1			T1	3		T3	6		T4	4
auto[StCreatorRootKey]	3156	1			T3	6		T4	2		T5	4
auto[StOwnerIntKey]	2862	1			T3	3		T4	4		T5	2
auto[StOwnerKey]	2517	1			T3	6		T5	1		T15	2
auto[StDisabled]	8070	1			T3	11		T5	5		T15	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	304	1			T17	4		T195	3		T43	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T23	1		T196	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	97	1			T86	1		T92	2		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	88	1			T17	1		T38	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	69	1			T43	1		T89	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	205	1			T15	1		T17	2		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	316	1			T15	1		T17	9		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T17	1		T197	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	73	1			T5	1		T195	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T87	2		T43	1		T52	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	70	1			T43	2		T92	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	218	1			T17	2		T38	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	334	1			T15	1		T17	5		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	108	1			T17	1		T24	2		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T200	1		T43	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T31	1		T92	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	68	1			T3	1		T89	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	212	1			T17	3		T38	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	328	1			T17	5		T31	1		T195	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	112	1			T15	1		T17	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T43	1		T92	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T195	1		T52	2		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	53	1			T3	1		T86	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	230	1			T5	1		T17	2		T87	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	86	1			T43	1		T6	2		T63	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T23	1		T24	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T5	1		T17	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T5	1		T24	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	66	1			T3	1		T17	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T15	1		T17	2		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	83	1			T43	1		T33	1		T6	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T17	1		T43	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	90	1			T196	1		T43	3		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T4	2		T17	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	52	1			T17	1		T201	1		T134	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	216	1			T3	1		T87	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	109	1			T17	1		T43	3		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T17	1		T23	2		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	68	1			T17	1		T38	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T17	1		T196	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	71	1			T17	1		T43	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	227	1			T17	4		T38	1		T88	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T17	1		T43	3		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T17	1		T23	2		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T133	1		T24	1		T52	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T17	1		T197	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T17	1		T195	1		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T17	1		T38	1		T43	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	272	1			T14	1		T17	2		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	91	1			T1	1		T14	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T17	1		T86	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	50	1			T3	1		T17	2		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	44	1			T24	1		T40	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	165	1			T3	1		T86	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	465	1			T14	1		T17	1		T18	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T17	1		T23	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	114	1			T18	1		T52	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	87	1			T86	1		T87	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T18	1		T38	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	308	1			T17	3		T18	1		T88	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	433	1			T14	1		T17	1		T197	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T16	1		T17	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T133	3		T88	1		T197	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	97	1			T16	1		T33	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	287	1			T16	3		T17	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	436	1			T14	3		T17	2		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	131	1			T31	1		T24	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T87	1		T52	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T86	1		T87	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	87	1			T17	1		T38	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	286	1			T5	1		T31	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	70	1			T43	1		T80	1		T8	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	115	1			T4	1		T17	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	55	1			T4	1		T38	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T196	1		T203	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T3	1		T86	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	196	1			T17	1		T88	2		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T43	4		T8	2		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T18	1		T89	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	105	1			T3	1		T17	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	94	1			T17	1		T18	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	88	1			T24	1		T43	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	266	1			T3	1		T17	3		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	45	1			T43	2		T33	1		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	122	1			T3	1		T17	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T3	2		T17	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T16	1		T17	1		T196	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	98	1			T207	1		T208	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T16	1		T17	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	56	1			T43	3		T33	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	105	1			T3	1		T31	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T38	1		T43	2		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T88	1		T196	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	108	1			T33	1		T209	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	283	1			T17	1		T87	1		T88	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	227	1			T17	1		T38	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	640	1			T15	1		T17	6		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	200	1			T5	1		T87	2		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	658	1			T15	1		T17	12		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	232	1			T3	1		T31	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	675	1			T15	1		T17	9		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	183	1			T3	1		T86	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	694	1			T5	1		T15	1		T17	8
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	198	1			T3	1		T17	2		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	417	1			T5	2		T15	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	213	1			T4	2		T17	2		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	411	1			T3	1		T17	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T17	2		T38	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	463	1			T17	7		T23	2		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T17	2		T133	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	416	1			T17	3		T23	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	159	1			T3	1		T17	3		T86	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	550	1			T1	1		T3	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T18	2		T38	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	908	1			T14	1		T17	5		T18	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	278	1			T16	2		T133	3		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	860	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T17	1		T38	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	874	1			T5	1		T14	3		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	157	1			T3	1		T4	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	398	1			T4	1		T17	2		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	268	1			T3	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	452	1			T3	1		T17	4		T18	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	290	1			T3	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	476	1			T3	1		T16	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T38	1		T88	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	468	1			T3	1		T17	1		T31	1