Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32785

1

T1

34

T3

35

T4

11

auto[1]

282

1

T38

3

T87

5

T118

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32794	1			T1	34		T3	35		T4	11
auto[134217728:268435455]	7	1			T138	1		T429	1		T312	2
auto[268435456:402653183]	16	1			T118	1		T134	1		T135	1
auto[402653184:536870911]	10	1			T137	1		T392	1		T322	1
auto[536870912:671088639]	15	1			T134	1		T241	2		T138	1
auto[671088640:805306367]	7	1			T241	1		T385	1		T404	1
auto[805306368:939524095]	7	1			T137	1		T385	1		T416	1
auto[939524096:1073741823]	4	1			T38	1		T311	1		T419	1
auto[1073741824:1207959551]	12	1			T135	1		T241	1		T419	1
auto[1207959552:1342177279]	5	1			T136	1		T297	1		T429	1
auto[1342177280:1476395007]	6	1			T87	1		T237	1		T416	1
auto[1476395008:1610612735]	6	1			T136	1		T419	1		T429	1
auto[1610612736:1744830463]	10	1			T233	1		T369	2		T419	1
auto[1744830464:1879048191]	10	1			T404	1		T416	1		T260	1
auto[1879048192:2013265919]	7	1			T118	1		T136	1		T430	1
auto[2013265920:2147483647]	16	1			T87	1		T241	2		T237	1
auto[2147483648:2281701375]	8	1			T87	2		T416	1		T297	1
auto[2281701376:2415919103]	6	1			T137	1		T404	2		T416	1
auto[2415919104:2550136831]	9	1			T87	1		T134	1		T138	1
auto[2550136832:2684354559]	12	1			T404	1		T322	1		T430	1
auto[2684354560:2818572287]	7	1			T134	1		T241	1		T417	1
auto[2818572288:2952790015]	7	1			T404	1		T416	1		T431	2
auto[2952790016:3087007743]	8	1			T392	1		T404	1		T431	2
auto[3087007744:3221225471]	8	1			T134	1		T392	1		T311	1
auto[3221225472:3355443199]	7	1			T322	1		T297	3		T420	1
auto[3355443200:3489660927]	9	1			T134	2		T385	1		T322	1
auto[3489660928:3623878655]	5	1			T138	1		T418	1		T432	1
auto[3623878656:3758096383]	6	1			T118	1		T241	1		T404	1
auto[3758096384:3892314111]	11	1			T134	1		T376	1		T322	1
auto[3892314112:4026531839]	13	1			T134	3		T385	1		T376	1
auto[4026531840:4160749567]	12	1			T38	2		T137	1		T385	1
auto[4160749568:4294967295]	7	1			T118	3		T322	1		T416	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	30	34	53.12	30

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[2415919104:2550136831]]	[auto[0]]	--	--	18
[auto[2684354560:2818572287] - auto[4160749568:4294967295]]	[auto[0]]	--	--	12

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32784	1			T1	34		T3	35		T4	11
auto[0:134217727]	auto[1]	10	1			T134	1		T241	1		T138	1
auto[134217728:268435455]	auto[1]	7	1			T138	1		T429	1		T312	2
auto[268435456:402653183]	auto[1]	16	1			T118	1		T134	1		T135	1
auto[402653184:536870911]	auto[1]	10	1			T137	1		T392	1		T322	1
auto[536870912:671088639]	auto[1]	15	1			T134	1		T241	2		T138	1
auto[671088640:805306367]	auto[1]	7	1			T241	1		T385	1		T404	1
auto[805306368:939524095]	auto[1]	7	1			T137	1		T385	1		T416	1
auto[939524096:1073741823]	auto[1]	4	1			T38	1		T311	1		T419	1
auto[1073741824:1207959551]	auto[1]	12	1			T135	1		T241	1		T419	1
auto[1207959552:1342177279]	auto[1]	5	1			T136	1		T297	1		T429	1
auto[1342177280:1476395007]	auto[1]	6	1			T87	1		T237	1		T416	1
auto[1476395008:1610612735]	auto[1]	6	1			T136	1		T419	1		T429	1
auto[1610612736:1744830463]	auto[1]	10	1			T233	1		T369	2		T419	1
auto[1744830464:1879048191]	auto[1]	10	1			T404	1		T416	1		T260	1
auto[1879048192:2013265919]	auto[1]	7	1			T118	1		T136	1		T430	1
auto[2013265920:2147483647]	auto[1]	16	1			T87	1		T241	2		T237	1
auto[2147483648:2281701375]	auto[1]	8	1			T87	2		T416	1		T297	1
auto[2281701376:2415919103]	auto[1]	6	1			T137	1		T404	2		T416	1
auto[2415919104:2550136831]	auto[1]	9	1			T87	1		T134	1		T138	1
auto[2550136832:2684354559]	auto[0]	1	1			T314	1		-	-		-	-
auto[2550136832:2684354559]	auto[1]	11	1			T404	1		T322	1		T430	1
auto[2684354560:2818572287]	auto[1]	7	1			T134	1		T241	1		T417	1
auto[2818572288:2952790015]	auto[1]	7	1			T404	1		T416	1		T431	2
auto[2952790016:3087007743]	auto[1]	8	1			T392	1		T404	1		T431	2
auto[3087007744:3221225471]	auto[1]	8	1			T134	1		T392	1		T311	1
auto[3221225472:3355443199]	auto[1]	7	1			T322	1		T297	3		T420	1
auto[3355443200:3489660927]	auto[1]	9	1			T134	2		T385	1		T322	1
auto[3489660928:3623878655]	auto[1]	5	1			T138	1		T418	1		T432	1
auto[3623878656:3758096383]	auto[1]	6	1			T118	1		T241	1		T404	1
auto[3758096384:3892314111]	auto[1]	11	1			T134	1		T376	1		T322	1
auto[3892314112:4026531839]	auto[1]	13	1			T134	3		T385	1		T376	1
auto[4026531840:4160749567]	auto[1]	12	1			T38	2		T137	1		T385	1
auto[4160749568:4294967295]	auto[1]	7	1			T118	3		T322	1		T416	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1625

1

T1

1

T3

1

T4

1

auto[1]

1789

1

T1

2

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T5	1		T38	1		T24	1
auto[134217728:268435455]	104	1			T32	1		T86	1		T45	1
auto[268435456:402653183]	102	1			T276	1		T91	1		T33	1
auto[402653184:536870911]	113	1			T86	1		T45	1		T43	1
auto[536870912:671088639]	99	1			T17	1		T38	1		T104	1
auto[671088640:805306367]	113	1			T5	1		T133	1		T87	1
auto[805306368:939524095]	93	1			T17	1		T32	1		T88	1
auto[939524096:1073741823]	116	1			T17	1		T87	1		T52	1
auto[1073741824:1207959551]	94	1			T17	1		T23	1		T44	1
auto[1207959552:1342177279]	118	1			T1	1		T5	1		T92	1
auto[1342177280:1476395007]	116	1			T4	1		T14	1		T23	1
auto[1476395008:1610612735]	104	1			T14	1		T17	2		T88	1
auto[1610612736:1744830463]	113	1			T1	1		T3	1		T104	1
auto[1744830464:1879048191]	117	1			T17	2		T23	1		T43	1
auto[1879048192:2013265919]	97	1			T4	1		T31	1		T43	1
auto[2013265920:2147483647]	102	1			T17	2		T92	1		T276	1
auto[2147483648:2281701375]	94	1			T17	3		T92	1		T90	1
auto[2281701376:2415919103]	91	1			T5	1		T14	1		T17	1
auto[2415919104:2550136831]	96	1			T3	1		T17	1		T32	1
auto[2550136832:2684354559]	111	1			T43	2		T203	1		T202	1
auto[2684354560:2818572287]	120	1			T14	1		T17	2		T24	1
auto[2818572288:2952790015]	106	1			T3	1		T14	1		T23	1
auto[2952790016:3087007743]	119	1			T5	2		T17	1		T38	1
auto[3087007744:3221225471]	99	1			T17	1		T32	1		T88	1
auto[3221225472:3355443199]	109	1			T44	1		T104	1		T52	2
auto[3355443200:3489660927]	105	1			T17	1		T40	1		T92	1
auto[3489660928:3623878655]	111	1			T14	1		T17	1		T88	1
auto[3623878656:3758096383]	94	1			T86	2		T52	1		T199	1
auto[3758096384:3892314111]	129	1			T1	1		T17	1		T23	1
auto[3892314112:4026531839]	103	1			T5	1		T17	1		T43	1
auto[4026531840:4160749567]	116	1			T14	1		T17	1		T43	2
auto[4160749568:4294967295]	113	1			T17	1		T23	1		T133	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T38	1		T93	1		T6	1
auto[0:134217727]	auto[1]	44	1			T5	1		T24	1		T43	1
auto[134217728:268435455]	auto[0]	45	1			T45	1		T104	1		T90	1
auto[134217728:268435455]	auto[1]	59	1			T32	1		T86	1		T40	2
auto[268435456:402653183]	auto[0]	45	1			T276	1		T91	1		T33	1
auto[268435456:402653183]	auto[1]	57	1			T52	1		T291	1		T334	1
auto[402653184:536870911]	auto[0]	46	1			T86	1		T104	1		T50	1
auto[402653184:536870911]	auto[1]	67	1			T45	1		T43	1		T90	1
auto[536870912:671088639]	auto[0]	46	1			T38	1		T104	1		T33	1
auto[536870912:671088639]	auto[1]	53	1			T17	1		T33	2		T52	1
auto[671088640:805306367]	auto[0]	55	1			T133	1		T89	1		T90	1
auto[671088640:805306367]	auto[1]	58	1			T5	1		T87	1		T45	1
auto[805306368:939524095]	auto[0]	47	1			T17	1		T32	1		T91	1
auto[805306368:939524095]	auto[1]	46	1			T88	1		T50	1		T6	2
auto[939524096:1073741823]	auto[0]	56	1			T17	1		T87	1		T53	1
auto[939524096:1073741823]	auto[1]	60	1			T52	1		T6	1		T79	2
auto[1073741824:1207959551]	auto[0]	46	1			T17	1		T23	1		T24	1
auto[1073741824:1207959551]	auto[1]	48	1			T44	1		T25	1		T34	1
auto[1207959552:1342177279]	auto[0]	59	1			T92	1		T90	1		T33	1
auto[1207959552:1342177279]	auto[1]	59	1			T1	1		T5	1		T199	1
auto[1342177280:1476395007]	auto[0]	54	1			T14	1		T89	1		T61	1
auto[1342177280:1476395007]	auto[1]	62	1			T4	1		T23	1		T197	1
auto[1476395008:1610612735]	auto[0]	54	1			T17	1		T88	1		T52	2
auto[1476395008:1610612735]	auto[1]	50	1			T14	1		T17	1		T89	1
auto[1610612736:1744830463]	auto[0]	53	1			T33	1		T60	1		T246	1
auto[1610612736:1744830463]	auto[1]	60	1			T1	1		T3	1		T104	1
auto[1744830464:1879048191]	auto[0]	58	1			T17	2		T23	1		T118	1
auto[1744830464:1879048191]	auto[1]	59	1			T43	1		T25	1		T203	1
auto[1879048192:2013265919]	auto[0]	47	1			T4	1		T31	1		T414	1
auto[1879048192:2013265919]	auto[1]	50	1			T43	1		T49	1		T80	1
auto[2013265920:2147483647]	auto[0]	39	1			T17	1		T92	1		T276	1
auto[2013265920:2147483647]	auto[1]	63	1			T17	1		T91	1		T93	1
auto[2147483648:2281701375]	auto[0]	53	1			T17	2		T90	1		T27	1
auto[2147483648:2281701375]	auto[1]	41	1			T17	1		T92	1		T414	1
auto[2281701376:2415919103]	auto[0]	38	1			T14	1		T17	1		T355	1
auto[2281701376:2415919103]	auto[1]	53	1			T5	1		T23	1		T43	1
auto[2415919104:2550136831]	auto[0]	44	1			T17	1		T38	1		T89	1
auto[2415919104:2550136831]	auto[1]	52	1			T3	1		T32	1		T45	1
auto[2550136832:2684354559]	auto[0]	52	1			T43	1		T203	1		T6	2
auto[2550136832:2684354559]	auto[1]	59	1			T43	1		T202	1		T82	1
auto[2684354560:2818572287]	auto[0]	65	1			T14	1		T17	1		T24	1
auto[2684354560:2818572287]	auto[1]	55	1			T17	1		T276	1		T52	1
auto[2818572288:2952790015]	auto[0]	38	1			T3	1		T14	1		T23	1
auto[2818572288:2952790015]	auto[1]	68	1			T61	1		T52	2		T93	2
auto[2952790016:3087007743]	auto[0]	57	1			T38	1		T49	1		T34	1
auto[2952790016:3087007743]	auto[1]	62	1			T5	2		T17	1		T40	1
auto[3087007744:3221225471]	auto[0]	51	1			T43	1		T91	1		T302	1
auto[3087007744:3221225471]	auto[1]	48	1			T17	1		T32	1		T88	1
auto[3221225472:3355443199]	auto[0]	56	1			T104	1		T52	1		T199	1
auto[3221225472:3355443199]	auto[1]	53	1			T44	1		T52	1		T57	1
auto[3355443200:3489660927]	auto[0]	46	1			T17	1		T89	1		T90	1
auto[3355443200:3489660927]	auto[1]	59	1			T40	1		T92	1		T52	1
auto[3489660928:3623878655]	auto[0]	59	1			T14	1		T17	1		T196	1
auto[3489660928:3623878655]	auto[1]	52	1			T88	1		T276	1		T33	1
auto[3623878656:3758096383]	auto[0]	46	1			T86	2		T60	1		T433	1
auto[3623878656:3758096383]	auto[1]	48	1			T52	1		T199	1		T80	1
auto[3758096384:3892314111]	auto[0]	54	1			T1	1		T17	1		T23	1
auto[3758096384:3892314111]	auto[1]	75	1			T45	1		T43	1		T89	1
auto[3892314112:4026531839]	auto[0]	49	1			T43	1		T61	1		T52	1
auto[3892314112:4026531839]	auto[1]	54	1			T5	1		T17	1		T49	1
auto[4026531840:4160749567]	auto[0]	54	1			T14	1		T17	1		T90	1
auto[4026531840:4160749567]	auto[1]	62	1			T43	2		T104	1		T276	1
auto[4160749568:4294967295]	auto[0]	60	1			T23	1		T135	1		T280	1
auto[4160749568:4294967295]	auto[1]	53	1			T17	1		T133	1		T45	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1604

1

T1

1

T3

1

T4

1

auto[1]

1809

1

T1

2

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T414	1		T91	1		T52	2
auto[134217728:268435455]	111	1			T17	1		T23	1		T43	1
auto[268435456:402653183]	102	1			T17	1		T133	1		T88	1
auto[402653184:536870911]	102	1			T5	1		T17	1		T23	1
auto[536870912:671088639]	105	1			T17	1		T23	1		T43	1
auto[671088640:805306367]	94	1			T14	1		T17	1		T133	1
auto[805306368:939524095]	134	1			T14	2		T17	2		T45	1
auto[939524096:1073741823]	107	1			T5	2		T44	1		T24	1
auto[1073741824:1207959551]	100	1			T17	1		T23	1		T87	1
auto[1207959552:1342177279]	100	1			T4	1		T5	1		T14	1
auto[1342177280:1476395007]	106	1			T1	1		T5	1		T17	1
auto[1476395008:1610612735]	115	1			T3	1		T17	1		T50	1
auto[1610612736:1744830463]	129	1			T14	1		T17	1		T196	1
auto[1744830464:1879048191]	108	1			T4	1		T38	1		T43	1
auto[1879048192:2013265919]	99	1			T5	1		T32	1		T31	1
auto[2013265920:2147483647]	86	1			T86	1		T45	1		T40	1
auto[2147483648:2281701375]	94	1			T17	2		T43	1		T89	1
auto[2281701376:2415919103]	99	1			T3	1		T17	1		T38	1
auto[2415919104:2550136831]	104	1			T1	1		T14	1		T17	1
auto[2550136832:2684354559]	115	1			T32	1		T87	1		T25	1
auto[2684354560:2818572287]	115	1			T17	1		T33	1		T52	2
auto[2818572288:2952790015]	97	1			T17	1		T88	1		T43	1
auto[2952790016:3087007743]	106	1			T88	1		T40	1		T43	2
auto[3087007744:3221225471]	95	1			T17	1		T43	1		T92	1
auto[3221225472:3355443199]	113	1			T3	1		T17	1		T32	1
auto[3355443200:3489660927]	97	1			T17	1		T32	1		T23	1
auto[3489660928:3623878655]	112	1			T1	1		T43	3		T33	1
auto[3623878656:3758096383]	110	1			T23	1		T24	1		T40	1
auto[3758096384:3892314111]	136	1			T104	1		T302	1		T27	1
auto[3892314112:4026531839]	114	1			T5	1		T14	1		T17	2
auto[4026531840:4160749567]	104	1			T17	1		T45	1		T90	1
auto[4160749568:4294967295]	93	1			T17	1		T86	1		T61	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T91	1		T118	1		T51	1
auto[0:134217727]	auto[1]	57	1			T414	1		T52	2		T79	1
auto[134217728:268435455]	auto[0]	50	1			T17	1		T43	1		T203	1
auto[134217728:268435455]	auto[1]	61	1			T23	1		T79	1		T84	1
auto[268435456:402653183]	auto[0]	47	1			T17	1		T24	1		T52	1
auto[268435456:402653183]	auto[1]	55	1			T133	1		T88	1		T52	3
auto[402653184:536870911]	auto[0]	49	1			T23	1		T104	1		T52	1
auto[402653184:536870911]	auto[1]	53	1			T5	1		T17	1		T43	1
auto[536870912:671088639]	auto[0]	54	1			T23	1		T61	1		T276	1
auto[536870912:671088639]	auto[1]	51	1			T17	1		T43	1		T93	1
auto[671088640:805306367]	auto[0]	46	1			T14	1		T17	1		T133	1
auto[671088640:805306367]	auto[1]	48	1			T52	1		T135	1		T6	1
auto[805306368:939524095]	auto[0]	52	1			T14	2		T17	1		T45	1
auto[805306368:939524095]	auto[1]	82	1			T17	1		T134	1		T6	2
auto[939524096:1073741823]	auto[0]	51	1			T5	1		T414	1		T52	1
auto[939524096:1073741823]	auto[1]	56	1			T5	1		T44	1		T24	1
auto[1073741824:1207959551]	auto[0]	42	1			T87	1		T57	1		T7	1
auto[1073741824:1207959551]	auto[1]	58	1			T17	1		T23	1		T44	1
auto[1207959552:1342177279]	auto[0]	41	1			T4	1		T14	1		T276	1
auto[1207959552:1342177279]	auto[1]	59	1			T5	1		T17	1		T197	1
auto[1342177280:1476395007]	auto[0]	49	1			T17	1		T23	1		T27	1
auto[1342177280:1476395007]	auto[1]	57	1			T1	1		T5	1		T86	1
auto[1476395008:1610612735]	auto[0]	58	1			T17	1		T50	1		T135	1
auto[1476395008:1610612735]	auto[1]	57	1			T3	1		T203	1		T135	1
auto[1610612736:1744830463]	auto[0]	62	1			T14	1		T17	1		T196	1
auto[1610612736:1744830463]	auto[1]	67	1			T89	1		T33	1		T6	1
auto[1744830464:1879048191]	auto[0]	48	1			T38	1		T90	1		T199	1
auto[1744830464:1879048191]	auto[1]	60	1			T4	1		T43	1		T61	1
auto[1879048192:2013265919]	auto[0]	41	1			T31	1		T38	1		T104	1
auto[1879048192:2013265919]	auto[1]	58	1			T5	1		T32	1		T52	2
auto[2013265920:2147483647]	auto[0]	40	1			T86	1		T89	1		T90	1
auto[2013265920:2147483647]	auto[1]	46	1			T45	1		T40	1		T49	1
auto[2147483648:2281701375]	auto[0]	47	1			T43	1		T89	1		T104	1
auto[2147483648:2281701375]	auto[1]	47	1			T17	2		T25	1		T33	1
auto[2281701376:2415919103]	auto[0]	50	1			T17	1		T34	1		T135	1
auto[2281701376:2415919103]	auto[1]	49	1			T3	1		T38	1		T104	1
auto[2415919104:2550136831]	auto[0]	47	1			T14	1		T17	1		T86	1
auto[2415919104:2550136831]	auto[1]	57	1			T1	1		T276	1		T52	1
auto[2550136832:2684354559]	auto[0]	49	1			T64	1		T341	1		T236	1
auto[2550136832:2684354559]	auto[1]	66	1			T32	1		T87	1		T25	1
auto[2684354560:2818572287]	auto[0]	55	1			T202	1		T242	1		T433	1
auto[2684354560:2818572287]	auto[1]	60	1			T17	1		T33	1		T52	2
auto[2818572288:2952790015]	auto[0]	46	1			T17	1		T60	1		T7	1
auto[2818572288:2952790015]	auto[1]	51	1			T88	1		T43	1		T90	1
auto[2952790016:3087007743]	auto[0]	45	1			T40	1		T89	2		T203	1
auto[2952790016:3087007743]	auto[1]	61	1			T88	1		T43	2		T25	1
auto[3087007744:3221225471]	auto[0]	49	1			T17	1		T92	1		T49	1
auto[3087007744:3221225471]	auto[1]	46	1			T43	1		T52	1		T242	1
auto[3221225472:3355443199]	auto[0]	53	1			T3	1		T32	1		T302	1
auto[3221225472:3355443199]	auto[1]	60	1			T17	1		T43	1		T89	1
auto[3355443200:3489660927]	auto[0]	48	1			T17	1		T23	1		T38	1
auto[3355443200:3489660927]	auto[1]	49	1			T32	1		T45	1		T40	1
auto[3489660928:3623878655]	auto[0]	51	1			T1	1		T43	2		T6	1
auto[3489660928:3623878655]	auto[1]	61	1			T43	1		T33	1		T199	1
auto[3623878656:3758096383]	auto[0]	62	1			T23	1		T24	1		T90	1
auto[3623878656:3758096383]	auto[1]	48	1			T40	1		T92	1		T52	1
auto[3758096384:3892314111]	auto[0]	59	1			T104	1		T27	1		T274	1
auto[3758096384:3892314111]	auto[1]	77	1			T302	1		T82	1		T148	1
auto[3892314112:4026531839]	auto[0]	57	1			T14	1		T17	2		T49	1
auto[3892314112:4026531839]	auto[1]	57	1			T5	1		T33	2		T52	1
auto[4026531840:4160749567]	auto[0]	52	1			T17	1		T90	1		T33	1
auto[4026531840:4160749567]	auto[1]	52	1			T45	1		T50	1		T52	1
auto[4160749568:4294967295]	auto[0]	50	1			T50	1		T81	1		T433	1
auto[4160749568:4294967295]	auto[1]	43	1			T17	1		T86	1		T61	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1605

1

T1

1

T3

1

T4

1

auto[1]

1808

1

T1

2

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T17	1		T88	1		T197	1
auto[134217728:268435455]	87	1			T133	1		T89	2		T90	1
auto[268435456:402653183]	102	1			T14	3		T17	2		T23	1
auto[402653184:536870911]	103	1			T23	1		T89	1		T276	1
auto[536870912:671088639]	109	1			T32	1		T87	1		T43	1
auto[671088640:805306367]	97	1			T5	1		T14	1		T17	1
auto[805306368:939524095]	101	1			T45	1		T276	1		T52	2
auto[939524096:1073741823]	118	1			T43	1		T50	1		T52	2
auto[1073741824:1207959551]	102	1			T1	1		T3	1		T14	1
auto[1207959552:1342177279]	107	1			T88	1		T40	1		T92	1
auto[1342177280:1476395007]	125	1			T31	1		T43	1		T104	1
auto[1476395008:1610612735]	100	1			T3	1		T5	2		T52	1
auto[1610612736:1744830463]	112	1			T17	2		T43	1		T89	1
auto[1744830464:1879048191]	117	1			T1	1		T17	1		T86	2
auto[1879048192:2013265919]	109	1			T17	1		T38	1		T86	1
auto[2013265920:2147483647]	112	1			T17	3		T24	1		T43	1
auto[2147483648:2281701375]	115	1			T5	1		T17	1		T32	1
auto[2281701376:2415919103]	103	1			T3	1		T17	1		T133	1
auto[2415919104:2550136831]	112	1			T32	1		T43	1		T89	1
auto[2550136832:2684354559]	126	1			T1	1		T17	3		T45	1
auto[2684354560:2818572287]	86	1			T17	1		T196	1		T43	1
auto[2818572288:2952790015]	105	1			T5	1		T17	1		T50	1
auto[2952790016:3087007743]	120	1			T5	1		T23	1		T45	2
auto[3087007744:3221225471]	93	1			T17	1		T43	1		T50	1
auto[3221225472:3355443199]	125	1			T4	1		T23	1		T38	1
auto[3355443200:3489660927]	102	1			T14	1		T17	1		T88	1
auto[3489660928:3623878655]	112	1			T5	1		T14	1		T17	2
auto[3623878656:3758096383]	101	1			T4	1		T45	1		T43	1
auto[3758096384:3892314111]	88	1			T88	1		T45	1		T199	1
auto[3892314112:4026531839]	124	1			T17	1		T38	1		T44	1
auto[4026531840:4160749567]	108	1			T17	2		T23	1		T38	1
auto[4160749568:4294967295]	94	1			T32	1		T44	1		T90	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T17	1		T88	1		T197	1
auto[0:134217727]	auto[1]	51	1			T24	1		T40	1		T93	1
auto[134217728:268435455]	auto[0]	42	1			T89	2		T90	1		T203	1
auto[134217728:268435455]	auto[1]	45	1			T133	1		T33	1		T6	1
auto[268435456:402653183]	auto[0]	57	1			T14	3		T17	1		T90	1
auto[268435456:402653183]	auto[1]	45	1			T17	1		T23	1		T84	1
auto[402653184:536870911]	auto[0]	54	1			T276	1		T91	1		T118	1
auto[402653184:536870911]	auto[1]	49	1			T23	1		T89	1		T52	1
auto[536870912:671088639]	auto[0]	54	1			T32	1		T87	1		T90	1
auto[536870912:671088639]	auto[1]	55	1			T43	1		T414	1		T52	1
auto[671088640:805306367]	auto[0]	47	1			T14	1		T17	1		T23	2
auto[671088640:805306367]	auto[1]	50	1			T5	1		T88	1		T40	1
auto[805306368:939524095]	auto[0]	46	1			T52	1		T57	1		T242	1
auto[805306368:939524095]	auto[1]	55	1			T45	1		T276	1		T52	1
auto[939524096:1073741823]	auto[0]	56	1			T50	1		T57	1		T82	1
auto[939524096:1073741823]	auto[1]	62	1			T43	1		T52	2		T80	1
auto[1073741824:1207959551]	auto[0]	38	1			T14	1		T274	1		T60	1
auto[1073741824:1207959551]	auto[1]	64	1			T1	1		T3	1		T40	1
auto[1207959552:1342177279]	auto[0]	49	1			T88	1		T40	1		T92	1
auto[1207959552:1342177279]	auto[1]	58	1			T203	1		T79	1		T84	1
auto[1342177280:1476395007]	auto[0]	59	1			T43	1		T104	1		T53	1
auto[1342177280:1476395007]	auto[1]	66	1			T31	1		T276	1		T91	1
auto[1476395008:1610612735]	auto[0]	50	1			T266	1		T6	2		T69	1
auto[1476395008:1610612735]	auto[1]	50	1			T3	1		T5	2		T52	1
auto[1610612736:1744830463]	auto[0]	60	1			T17	2		T302	1		T6	2
auto[1610612736:1744830463]	auto[1]	52	1			T43	1		T89	1		T33	1
auto[1744830464:1879048191]	auto[0]	56	1			T86	1		T89	1		T90	2
auto[1744830464:1879048191]	auto[1]	61	1			T1	1		T17	1		T86	1
auto[1879048192:2013265919]	auto[0]	55	1			T86	1		T43	1		T91	1
auto[1879048192:2013265919]	auto[1]	54	1			T17	1		T38	1		T87	1
auto[2013265920:2147483647]	auto[0]	55	1			T17	2		T92	1		T33	1
auto[2013265920:2147483647]	auto[1]	57	1			T17	1		T24	1		T43	1
auto[2147483648:2281701375]	auto[0]	50	1			T24	1		T100	1		T6	1
auto[2147483648:2281701375]	auto[1]	65	1			T5	1		T17	1		T32	1
auto[2281701376:2415919103]	auto[0]	42	1			T3	1		T17	1		T133	1
auto[2281701376:2415919103]	auto[1]	61	1			T79	1		T84	1		T245	1
auto[2415919104:2550136831]	auto[0]	51	1			T89	1		T27	1		T6	1
auto[2415919104:2550136831]	auto[1]	61	1			T32	1		T43	1		T25	2
auto[2550136832:2684354559]	auto[0]	58	1			T1	1		T17	2		T61	1
auto[2550136832:2684354559]	auto[1]	68	1			T17	1		T45	1		T43	1
auto[2684354560:2818572287]	auto[0]	35	1			T196	1		T100	1		T6	1
auto[2684354560:2818572287]	auto[1]	51	1			T17	1		T43	1		T52	1
auto[2818572288:2952790015]	auto[0]	48	1			T50	1		T203	1		T291	1
auto[2818572288:2952790015]	auto[1]	57	1			T5	1		T17	1		T302	1
auto[2952790016:3087007743]	auto[0]	51	1			T104	1		T49	1		T355	1
auto[2952790016:3087007743]	auto[1]	69	1			T5	1		T23	1		T45	2
auto[3087007744:3221225471]	auto[0]	35	1			T43	1		T52	1		T22	1
auto[3087007744:3221225471]	auto[1]	58	1			T17	1		T50	1		T134	1
auto[3221225472:3355443199]	auto[0]	63	1			T4	1		T23	1		T38	1
auto[3221225472:3355443199]	auto[1]	62	1			T89	1		T52	1		T6	1
auto[3355443200:3489660927]	auto[0]	51	1			T14	1		T43	1		T80	1
auto[3355443200:3489660927]	auto[1]	51	1			T17	1		T88	1		T92	1
auto[3489660928:3623878655]	auto[0]	46	1			T14	1		T17	1		T433	1
auto[3489660928:3623878655]	auto[1]	66	1			T5	1		T17	1		T276	1
auto[3623878656:3758096383]	auto[0]	53	1			T90	1		T414	1		T50	1
auto[3623878656:3758096383]	auto[1]	48	1			T4	1		T45	1		T43	1
auto[3758096384:3892314111]	auto[0]	41	1			T199	1		T6	1		T81	1
auto[3758096384:3892314111]	auto[1]	47	1			T88	1		T45	1		T118	1
auto[3892314112:4026531839]	auto[0]	63	1			T17	1		T38	1		T49	1
auto[3892314112:4026531839]	auto[1]	61	1			T44	1		T49	1		T203	1
auto[4026531840:4160749567]	auto[0]	57	1			T17	2		T23	1		T92	1
auto[4026531840:4160749567]	auto[1]	51	1			T38	1		T86	1		T43	1
auto[4160749568:4294967295]	auto[0]	36	1			T90	1		T49	1		T274	1
auto[4160749568:4294967295]	auto[1]	58	1			T32	1		T44	1		T91	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T1

1

T3

1

T14

7

auto[1]

1805

1

T1

2

T3

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T23	1		T89	1		T104	1
auto[134217728:268435455]	110	1			T1	1		T43	1		T52	1
auto[268435456:402653183]	105	1			T5	2		T14	1		T17	2
auto[402653184:536870911]	116	1			T133	1		T45	1		T50	2
auto[536870912:671088639]	106	1			T14	1		T23	1		T87	1
auto[671088640:805306367]	116	1			T32	1		T88	1		T52	1
auto[805306368:939524095]	102	1			T17	1		T104	1		T50	1
auto[939524096:1073741823]	110	1			T17	2		T104	1		T52	2
auto[1073741824:1207959551]	93	1			T88	1		T24	1		T61	1
auto[1207959552:1342177279]	108	1			T1	1		T17	1		T23	1
auto[1342177280:1476395007]	98	1			T17	1		T32	1		T23	2
auto[1476395008:1610612735]	120	1			T4	1		T17	1		T89	1
auto[1610612736:1744830463]	108	1			T17	1		T88	1		T90	1
auto[1744830464:1879048191]	111	1			T1	1		T3	1		T4	1
auto[1879048192:2013265919]	102	1			T43	1		T92	1		T89	1
auto[2013265920:2147483647]	112	1			T86	2		T43	1		T134	1
auto[2147483648:2281701375]	118	1			T17	3		T38	1		T45	1
auto[2281701376:2415919103]	90	1			T90	1		T93	1		T6	1
auto[2415919104:2550136831]	104	1			T14	1		T17	1		T86	1
auto[2550136832:2684354559]	98	1			T5	1		T45	1		T43	1
auto[2684354560:2818572287]	125	1			T40	1		T90	1		T49	1
auto[2818572288:2952790015]	99	1			T197	1		T25	1		T50	1
auto[2952790016:3087007743]	113	1			T3	1		T17	2		T23	1
auto[3087007744:3221225471]	104	1			T14	1		T17	2		T33	1
auto[3221225472:3355443199]	102	1			T43	1		T89	1		T91	1
auto[3355443200:3489660927]	96	1			T5	1		T17	1		T32	1
auto[3489660928:3623878655]	98	1			T5	1		T17	1		T88	1
auto[3623878656:3758096383]	118	1			T17	3		T23	1		T38	1
auto[3758096384:3892314111]	110	1			T3	1		T14	1		T17	1
auto[3892314112:4026531839]	107	1			T5	1		T14	1		T17	1
auto[4026531840:4160749567]	101	1			T5	1		T17	1		T32	1
auto[4160749568:4294967295]	103	1			T14	1		T44	2		T92	1