Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4602

1

T5

14

T14

10

T17

32

auto[1]

2224

1

T1

6

T3

6

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	224	1			T17	4		T25	2		T50	2
auto[134217728:268435455]	208	1			T5	4		T14	4		T17	2
auto[268435456:402653183]	190	1			T1	2		T5	2		T14	2
auto[402653184:536870911]	210	1			T32	2		T86	2		T44	2
auto[536870912:671088639]	214	1			T43	2		T84	2		T355	2
auto[671088640:805306367]	188	1			T4	2		T92	2		T276	4
auto[805306368:939524095]	220	1			T5	2		T17	2		T133	2
auto[939524096:1073741823]	250	1			T17	4		T45	4		T92	2
auto[1073741824:1207959551]	174	1			T14	2		T104	2		T90	2
auto[1207959552:1342177279]	182	1			T89	2		T49	4		T33	2
auto[1342177280:1476395007]	240	1			T1	2		T17	2		T32	2
auto[1476395008:1610612735]	238	1			T23	2		T88	2		T43	2
auto[1610612736:1744830463]	230	1			T24	2		T104	2		T135	2
auto[1744830464:1879048191]	190	1			T86	2		T88	4		T90	2
auto[1879048192:2013265919]	224	1			T3	2		T17	2		T43	2
auto[2013265920:2147483647]	226	1			T17	4		T23	2		T87	2
auto[2147483648:2281701375]	234	1			T5	2		T14	2		T52	4
auto[2281701376:2415919103]	202	1			T104	2		T52	4		T100	2
auto[2415919104:2550136831]	216	1			T3	2		T43	2		T61	4
auto[2550136832:2684354559]	228	1			T3	2		T14	2		T17	8
auto[2684354560:2818572287]	220	1			T17	2		T196	2		T118	2
auto[2818572288:2952790015]	250	1			T31	2		T38	2		T133	2
auto[2952790016:3087007743]	214	1			T17	2		T38	2		T86	2
auto[3087007744:3221225471]	220	1			T4	2		T17	4		T23	2
auto[3221225472:3355443199]	192	1			T5	2		T17	2		T38	2
auto[3355443200:3489660927]	216	1			T17	2		T23	4		T44	2
auto[3489660928:3623878655]	224	1			T14	2		T17	2		T86	2
auto[3623878656:3758096383]	182	1			T45	2		T61	2		T22	2
auto[3758096384:3892314111]	184	1			T32	4		T92	2		T33	2
auto[3892314112:4026531839]	228	1			T5	2		T17	2		T23	2
auto[4026531840:4160749567]	176	1			T17	2		T45	2		T52	2
auto[4160749568:4294967295]	232	1			T1	2		T17	4		T89	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	140	1			T17	2		T25	2		T203	2
auto[0:134217727]	auto[1]	84	1			T17	2		T50	2		T203	2
auto[134217728:268435455]	auto[0]	144	1			T5	4		T14	4		T38	2
auto[134217728:268435455]	auto[1]	64	1			T17	2		T52	2		T134	2
auto[268435456:402653183]	auto[0]	132	1			T5	2		T14	2		T40	2
auto[268435456:402653183]	auto[1]	58	1			T1	2		T91	2		T6	2
auto[402653184:536870911]	auto[0]	152	1			T86	2		T44	2		T89	2
auto[402653184:536870911]	auto[1]	58	1			T32	2		T27	2		T434	2
auto[536870912:671088639]	auto[0]	152	1			T43	2		T99	2		T341	2
auto[536870912:671088639]	auto[1]	62	1			T84	2		T355	2		T63	2
auto[671088640:805306367]	auto[0]	124	1			T276	2		T91	2		T33	2
auto[671088640:805306367]	auto[1]	64	1			T4	2		T92	2		T276	2
auto[805306368:939524095]	auto[0]	156	1			T5	2		T133	2		T40	2
auto[805306368:939524095]	auto[1]	64	1			T17	2		T202	2		T82	2
auto[939524096:1073741823]	auto[0]	168	1			T17	4		T45	4		T92	2
auto[939524096:1073741823]	auto[1]	82	1			T202	2		T6	2		T82	2
auto[1073741824:1207959551]	auto[0]	124	1			T14	2		T104	2		T90	2
auto[1073741824:1207959551]	auto[1]	50	1			T79	2		T291	2		T331	2
auto[1207959552:1342177279]	auto[0]	118	1			T49	4		T52	2		T118	2
auto[1207959552:1342177279]	auto[1]	64	1			T89	2		T33	2		T52	2
auto[1342177280:1476395007]	auto[0]	162	1			T17	2		T32	2		T23	2
auto[1342177280:1476395007]	auto[1]	78	1			T1	2		T50	2		T52	2
auto[1476395008:1610612735]	auto[0]	142	1			T23	2		T88	2		T276	2
auto[1476395008:1610612735]	auto[1]	96	1			T43	2		T414	2		T33	2
auto[1610612736:1744830463]	auto[0]	158	1			T104	2		T135	2		T6	2
auto[1610612736:1744830463]	auto[1]	72	1			T24	2		T274	2		T80	2
auto[1744830464:1879048191]	auto[0]	128	1			T86	2		T88	4		T90	2
auto[1744830464:1879048191]	auto[1]	62	1			T50	2		T62	2		T289	2
auto[1879048192:2013265919]	auto[0]	134	1			T17	2		T43	2		T414	2
auto[1879048192:2013265919]	auto[1]	90	1			T3	2		T266	2		T280	2
auto[2013265920:2147483647]	auto[0]	158	1			T17	2		T87	2		T88	2
auto[2013265920:2147483647]	auto[1]	68	1			T17	2		T23	2		T43	2
auto[2147483648:2281701375]	auto[0]	168	1			T5	2		T52	4		T7	2
auto[2147483648:2281701375]	auto[1]	66	1			T14	2		T80	2		T84	4
auto[2281701376:2415919103]	auto[0]	136	1			T52	2		T6	4		T79	2
auto[2281701376:2415919103]	auto[1]	66	1			T104	2		T52	2		T100	2
auto[2415919104:2550136831]	auto[0]	158	1			T43	2		T61	2		T25	2
auto[2415919104:2550136831]	auto[1]	58	1			T3	2		T61	2		T280	2
auto[2550136832:2684354559]	auto[0]	134	1			T14	2		T17	8		T118	2
auto[2550136832:2684354559]	auto[1]	94	1			T3	2		T87	2		T52	2
auto[2684354560:2818572287]	auto[0]	146	1			T17	2		T118	2		T6	6
auto[2684354560:2818572287]	auto[1]	74	1			T196	2		T245	4		T293	2
auto[2818572288:2952790015]	auto[0]	176	1			T31	2		T38	2		T43	2
auto[2818572288:2952790015]	auto[1]	74	1			T133	2		T88	2		T197	2
auto[2952790016:3087007743]	auto[0]	154	1			T86	2		T24	2		T45	2
auto[2952790016:3087007743]	auto[1]	60	1			T17	2		T38	2		T43	2
auto[3087007744:3221225471]	auto[0]	154	1			T17	4		T23	2		T90	2
auto[3087007744:3221225471]	auto[1]	66	1			T4	2		T43	2		T52	2
auto[3221225472:3355443199]	auto[0]	120	1			T5	2		T17	2		T104	2
auto[3221225472:3355443199]	auto[1]	72	1			T38	2		T43	2		T92	2
auto[3355443200:3489660927]	auto[0]	130	1			T23	4		T44	2		T40	2
auto[3355443200:3489660927]	auto[1]	86	1			T17	2		T43	2		T52	2
auto[3489660928:3623878655]	auto[0]	158	1			T17	2		T86	2		T45	2
auto[3489660928:3623878655]	auto[1]	66	1			T14	2		T341	2		T66	4
auto[3623878656:3758096383]	auto[0]	126	1			T45	2		T61	2		T7	2
auto[3623878656:3758096383]	auto[1]	56	1			T22	2		T93	2		T135	2
auto[3758096384:3892314111]	auto[0]	124	1			T32	4		T92	2		T33	2
auto[3758096384:3892314111]	auto[1]	60	1			T57	2		T292	2		T242	2
auto[3892314112:4026531839]	auto[0]	148	1			T5	2		T17	2		T23	2
auto[3892314112:4026531839]	auto[1]	80	1			T24	2		T104	2		T52	4
auto[4026531840:4160749567]	auto[0]	114	1			T45	2		T82	2		T137	2
auto[4026531840:4160749567]	auto[1]	62	1			T17	2		T52	2		T64	2
auto[4160749568:4294967295]	auto[0]	164	1			T89	2		T90	2		T53	2
auto[4160749568:4294967295]	auto[1]	68	1			T1	2		T17	4		T25	2