Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2991

1

T1

3

T3

3

T4

2

auto[1]

282

1

T38

3

T87

5

T118

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T17	2		T43	1		T92	1
auto[134217728:268435455]	98	1			T5	1		T23	1		T104	1
auto[268435456:402653183]	88	1			T3	1		T17	1		T89	1
auto[402653184:536870911]	119	1			T17	2		T23	1		T86	1
auto[536870912:671088639]	109	1			T1	1		T88	1		T45	1
auto[671088640:805306367]	102	1			T4	1		T38	1		T88	1
auto[805306368:939524095]	87	1			T17	1		T104	1		T33	1
auto[939524096:1073741823]	89	1			T1	1		T14	1		T87	1
auto[1073741824:1207959551]	113	1			T14	1		T17	2		T23	1
auto[1207959552:1342177279]	109	1			T17	1		T38	1		T87	1
auto[1342177280:1476395007]	99	1			T38	1		T89	1		T104	2
auto[1476395008:1610612735]	102	1			T87	2		T40	1		T92	2
auto[1610612736:1744830463]	115	1			T32	2		T23	1		T43	1
auto[1744830464:1879048191]	105	1			T31	1		T45	1		T90	1
auto[1879048192:2013265919]	122	1			T38	1		T44	1		T90	1
auto[2013265920:2147483647]	99	1			T3	1		T17	1		T86	2
auto[2147483648:2281701375]	110	1			T4	1		T17	1		T43	2
auto[2281701376:2415919103]	105	1			T86	1		T44	1		T88	1
auto[2415919104:2550136831]	111	1			T1	1		T3	1		T17	1
auto[2550136832:2684354559]	100	1			T133	1		T89	1		T90	1
auto[2684354560:2818572287]	110	1			T17	2		T91	1		T33	2
auto[2818572288:2952790015]	89	1			T14	2		T23	1		T24	1
auto[2952790016:3087007743]	112	1			T14	1		T17	2		T87	1
auto[3087007744:3221225471]	88	1			T5	1		T17	1		T32	1
auto[3221225472:3355443199]	109	1			T14	1		T196	1		T24	1
auto[3355443200:3489660927]	93	1			T5	1		T14	1		T17	1
auto[3489660928:3623878655]	92	1			T32	1		T23	1		T52	1
auto[3623878656:3758096383]	98	1			T5	1		T38	1		T89	1
auto[3758096384:3892314111]	103	1			T5	2		T23	1		T38	1
auto[3892314112:4026531839]	88	1			T88	1		T135	1		T202	1
auto[4026531840:4160749567]	100	1			T5	1		T17	1		T88	1
auto[4160749568:4294967295]	108	1			T17	1		T40	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	90	1			T17	2		T43	1		T92	1
auto[0:134217727]	auto[1]	11	1			T118	1		T134	1		T135	1
auto[134217728:268435455]	auto[0]	87	1			T5	1		T23	1		T104	1
auto[134217728:268435455]	auto[1]	11	1			T137	1		T385	1		T311	1
auto[268435456:402653183]	auto[0]	79	1			T3	1		T17	1		T89	1
auto[268435456:402653183]	auto[1]	9	1			T134	1		T416	1		T417	1
auto[402653184:536870911]	auto[0]	110	1			T17	2		T23	1		T86	1
auto[402653184:536870911]	auto[1]	9	1			T241	1		T137	2		T322	1
auto[536870912:671088639]	auto[0]	101	1			T1	1		T88	1		T45	1
auto[536870912:671088639]	auto[1]	8	1			T118	1		T237	1		T311	1
auto[671088640:805306367]	auto[0]	96	1			T4	1		T38	1		T88	1
auto[671088640:805306367]	auto[1]	6	1			T237	1		T260	1		T431	1
auto[805306368:939524095]	auto[0]	80	1			T17	1		T104	1		T33	1
auto[805306368:939524095]	auto[1]	7	1			T134	1		T416	1		T431	1
auto[939524096:1073741823]	auto[0]	81	1			T1	1		T14	1		T87	1
auto[939524096:1073741823]	auto[1]	8	1			T416	1		T417	2		T419	1
auto[1073741824:1207959551]	auto[0]	98	1			T14	1		T17	2		T23	1
auto[1073741824:1207959551]	auto[1]	15	1			T241	1		T385	1		T311	3
auto[1207959552:1342177279]	auto[0]	98	1			T17	1		T38	1		T45	1
auto[1207959552:1342177279]	auto[1]	11	1			T87	1		T233	1		T138	1
auto[1342177280:1476395007]	auto[0]	93	1			T38	1		T89	1		T104	2
auto[1342177280:1476395007]	auto[1]	6	1			T385	1		T431	1		T283	2
auto[1476395008:1610612735]	auto[0]	93	1			T87	1		T40	1		T92	2
auto[1476395008:1610612735]	auto[1]	9	1			T87	1		T134	1		T385	1
auto[1610612736:1744830463]	auto[0]	107	1			T32	2		T23	1		T43	1
auto[1610612736:1744830463]	auto[1]	8	1			T134	1		T138	1		T322	1
auto[1744830464:1879048191]	auto[0]	99	1			T31	1		T45	1		T90	1
auto[1744830464:1879048191]	auto[1]	6	1			T241	1		T138	1		T322	1
auto[1879048192:2013265919]	auto[0]	115	1			T44	1		T90	1		T52	1
auto[1879048192:2013265919]	auto[1]	7	1			T38	1		T237	1		T322	1
auto[2013265920:2147483647]	auto[0]	89	1			T3	1		T17	1		T86	2
auto[2013265920:2147483647]	auto[1]	10	1			T118	2		T404	2		T417	1
auto[2147483648:2281701375]	auto[0]	95	1			T4	1		T17	1		T43	2
auto[2147483648:2281701375]	auto[1]	15	1			T134	1		T241	2		T137	1
auto[2281701376:2415919103]	auto[0]	97	1			T86	1		T44	1		T88	1
auto[2281701376:2415919103]	auto[1]	8	1			T134	2		T136	1		T385	1
auto[2415919104:2550136831]	auto[0]	102	1			T1	1		T3	1		T17	1
auto[2415919104:2550136831]	auto[1]	9	1			T87	1		T241	1		T137	1
auto[2550136832:2684354559]	auto[0]	91	1			T133	1		T89	1		T90	1
auto[2550136832:2684354559]	auto[1]	9	1			T134	1		T297	1		T369	1
auto[2684354560:2818572287]	auto[0]	104	1			T17	2		T91	1		T33	2
auto[2684354560:2818572287]	auto[1]	6	1			T135	1		T417	2		T419	1
auto[2818572288:2952790015]	auto[0]	82	1			T14	2		T23	1		T24	1
auto[2818572288:2952790015]	auto[1]	7	1			T404	3		T419	1		T429	2
auto[2952790016:3087007743]	auto[0]	105	1			T14	1		T17	2		T276	1
auto[2952790016:3087007743]	auto[1]	7	1			T87	1		T416	1		T283	1
auto[3087007744:3221225471]	auto[0]	80	1			T5	1		T17	1		T32	1
auto[3087007744:3221225471]	auto[1]	8	1			T118	1		T385	1		T322	1
auto[3221225472:3355443199]	auto[0]	99	1			T14	1		T196	1		T24	1
auto[3221225472:3355443199]	auto[1]	10	1			T118	1		T134	3		T404	1
auto[3355443200:3489660927]	auto[0]	87	1			T5	1		T14	1		T17	1
auto[3355443200:3489660927]	auto[1]	6	1			T87	1		T237	1		T385	1
auto[3489660928:3623878655]	auto[0]	86	1			T32	1		T23	1		T52	1
auto[3489660928:3623878655]	auto[1]	6	1			T136	1		T138	1		T385	1
auto[3623878656:3758096383]	auto[0]	88	1			T5	1		T89	1		T104	1
auto[3623878656:3758096383]	auto[1]	10	1			T38	1		T118	1		T134	1
auto[3758096384:3892314111]	auto[0]	94	1			T5	2		T23	1		T89	1
auto[3758096384:3892314111]	auto[1]	9	1			T38	1		T134	1		T138	2
auto[3892314112:4026531839]	auto[0]	75	1			T88	1		T202	1		T6	2
auto[3892314112:4026531839]	auto[1]	13	1			T135	1		T241	1		T138	1
auto[4026531840:4160749567]	auto[0]	93	1			T5	1		T17	1		T88	1
auto[4026531840:4160749567]	auto[1]	7	1			T118	1		T134	2		T137	1
auto[4160749568:4294967295]	auto[0]	97	1			T17	1		T40	1		T43	1
auto[4160749568:4294967295]	auto[1]	11	1			T134	1		T431	1		T419	1