Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2994

1

T1

3

T3

3

T4

2

auto[1]

285

1

T87

6

T118

8

T134

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T17	1		T86	1		T87	1
auto[134217728:268435455]	102	1			T24	1		T43	1		T134	1
auto[268435456:402653183]	94	1			T1	1		T14	1		T38	1
auto[402653184:536870911]	93	1			T23	1		T38	1		T414	1
auto[536870912:671088639]	100	1			T1	1		T4	1		T90	2
auto[671088640:805306367]	115	1			T3	1		T5	1		T87	1
auto[805306368:939524095]	113	1			T5	1		T17	1		T32	1
auto[939524096:1073741823]	90	1			T1	1		T14	1		T23	3
auto[1073741824:1207959551]	103	1			T14	1		T17	1		T87	1
auto[1207959552:1342177279]	111	1			T87	1		T45	1		T90	2
auto[1342177280:1476395007]	109	1			T32	2		T86	1		T87	1
auto[1476395008:1610612735]	94	1			T87	1		T44	1		T43	1
auto[1610612736:1744830463]	105	1			T5	1		T17	1		T133	1
auto[1744830464:1879048191]	104	1			T5	1		T17	1		T86	1
auto[1879048192:2013265919]	103	1			T23	1		T38	1		T302	1
auto[2013265920:2147483647]	116	1			T17	1		T90	1		T118	1
auto[2147483648:2281701375]	101	1			T23	1		T45	1		T40	1
auto[2281701376:2415919103]	97	1			T17	1		T104	1		T90	1
auto[2415919104:2550136831]	100	1			T4	1		T5	1		T17	3
auto[2550136832:2684354559]	116	1			T3	1		T92	1		T104	2
auto[2684354560:2818572287]	100	1			T89	2		T33	1		T93	1
auto[2818572288:2952790015]	99	1			T3	1		T24	1		T89	1
auto[2952790016:3087007743]	105	1			T14	1		T38	1		T88	1
auto[3087007744:3221225471]	104	1			T5	1		T17	1		T87	1
auto[3221225472:3355443199]	94	1			T14	1		T43	1		T104	1
auto[3355443200:3489660927]	108	1			T17	1		T86	1		T89	1
auto[3489660928:3623878655]	98	1			T17	2		T44	1		T45	1
auto[3623878656:3758096383]	103	1			T5	1		T88	1		T43	1
auto[3758096384:3892314111]	121	1			T17	3		T31	1		T52	1
auto[3892314112:4026531839]	88	1			T32	1		T23	1		T133	1
auto[4026531840:4160749567]	97	1			T14	1		T17	1		T92	1
auto[4160749568:4294967295]	85	1			T14	1		T17	2		T45	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	98	1			T17	1		T86	1		T88	1
auto[0:134217727]	auto[1]	13	1			T87	1		T134	1		T241	1
auto[134217728:268435455]	auto[0]	85	1			T24	1		T43	1		T80	1
auto[134217728:268435455]	auto[1]	17	1			T134	1		T241	1		T136	1
auto[268435456:402653183]	auto[0]	85	1			T1	1		T14	1		T38	1
auto[268435456:402653183]	auto[1]	9	1			T87	1		T118	1		T137	1
auto[402653184:536870911]	auto[0]	85	1			T23	1		T38	1		T414	1
auto[402653184:536870911]	auto[1]	8	1			T241	1		T392	1		T416	1
auto[536870912:671088639]	auto[0]	93	1			T1	1		T4	1		T90	2
auto[536870912:671088639]	auto[1]	7	1			T134	2		T241	1		T237	1
auto[671088640:805306367]	auto[0]	103	1			T3	1		T5	1		T43	1
auto[671088640:805306367]	auto[1]	12	1			T87	1		T134	1		T404	1
auto[805306368:939524095]	auto[0]	106	1			T5	1		T17	1		T32	1
auto[805306368:939524095]	auto[1]	7	1			T134	1		T241	2		T417	1
auto[939524096:1073741823]	auto[0]	86	1			T1	1		T14	1		T23	3
auto[939524096:1073741823]	auto[1]	4	1			T134	1		T416	1		T419	1
auto[1073741824:1207959551]	auto[0]	97	1			T14	1		T17	1		T87	1
auto[1073741824:1207959551]	auto[1]	6	1			T241	1		T322	2		T297	1
auto[1207959552:1342177279]	auto[0]	97	1			T45	1		T90	2		T91	1
auto[1207959552:1342177279]	auto[1]	14	1			T87	1		T134	1		T241	1
auto[1342177280:1476395007]	auto[0]	100	1			T32	2		T86	1		T43	1
auto[1342177280:1476395007]	auto[1]	9	1			T87	1		T404	1		T311	1
auto[1476395008:1610612735]	auto[0]	89	1			T87	1		T44	1		T43	1
auto[1476395008:1610612735]	auto[1]	5	1			T404	1		T417	1		T419	1
auto[1610612736:1744830463]	auto[0]	96	1			T5	1		T17	1		T133	1
auto[1610612736:1744830463]	auto[1]	9	1			T136	1		T237	1		T418	1
auto[1744830464:1879048191]	auto[0]	94	1			T5	1		T17	1		T86	1
auto[1744830464:1879048191]	auto[1]	10	1			T237	1		T311	1		T260	1
auto[1879048192:2013265919]	auto[0]	98	1			T23	1		T38	1		T302	1
auto[1879048192:2013265919]	auto[1]	5	1			T135	1		T444	1		T352	1
auto[2013265920:2147483647]	auto[0]	112	1			T17	1		T90	1		T118	1
auto[2013265920:2147483647]	auto[1]	4	1			T137	1		T322	1		T419	1
auto[2147483648:2281701375]	auto[0]	92	1			T23	1		T45	1		T40	1
auto[2147483648:2281701375]	auto[1]	9	1			T118	1		T135	1		T311	1
auto[2281701376:2415919103]	auto[0]	91	1			T17	1		T104	1		T90	1
auto[2281701376:2415919103]	auto[1]	6	1			T135	1		T297	1		T444	1
auto[2415919104:2550136831]	auto[0]	95	1			T4	1		T5	1		T17	3
auto[2415919104:2550136831]	auto[1]	5	1			T118	1		T134	1		T369	2
auto[2550136832:2684354559]	auto[0]	107	1			T3	1		T92	1		T104	2
auto[2550136832:2684354559]	auto[1]	9	1			T138	1		T416	1		T297	1
auto[2684354560:2818572287]	auto[0]	90	1			T89	2		T33	1		T93	1
auto[2684354560:2818572287]	auto[1]	10	1			T137	1		T311	2		T416	1
auto[2818572288:2952790015]	auto[0]	91	1			T3	1		T24	1		T89	1
auto[2818572288:2952790015]	auto[1]	8	1			T118	1		T311	1		T444	1
auto[2952790016:3087007743]	auto[0]	97	1			T14	1		T38	1		T88	1
auto[2952790016:3087007743]	auto[1]	8	1			T134	1		T135	1		T137	1
auto[3087007744:3221225471]	auto[0]	92	1			T5	1		T17	1		T45	1
auto[3087007744:3221225471]	auto[1]	12	1			T87	1		T134	1		T241	1
auto[3221225472:3355443199]	auto[0]	82	1			T14	1		T43	1		T104	1
auto[3221225472:3355443199]	auto[1]	12	1			T118	1		T134	1		T241	1
auto[3355443200:3489660927]	auto[0]	100	1			T17	1		T86	1		T89	1
auto[3355443200:3489660927]	auto[1]	8	1			T134	1		T135	1		T322	1
auto[3489660928:3623878655]	auto[0]	88	1			T17	2		T44	1		T45	1
auto[3489660928:3623878655]	auto[1]	10	1			T376	1		T322	1		T297	1
auto[3623878656:3758096383]	auto[0]	94	1			T5	1		T88	1		T43	1
auto[3623878656:3758096383]	auto[1]	9	1			T136	1		T137	1		T404	1
auto[3758096384:3892314111]	auto[0]	112	1			T17	3		T31	1		T52	1
auto[3758096384:3892314111]	auto[1]	9	1			T138	1		T237	1		T385	1
auto[3892314112:4026531839]	auto[0]	79	1			T32	1		T23	1		T133	1
auto[3892314112:4026531839]	auto[1]	9	1			T118	1		T385	2		T416	2
auto[4026531840:4160749567]	auto[0]	84	1			T14	1		T17	1		T92	1
auto[4026531840:4160749567]	auto[1]	13	1			T241	2		T322	2		T416	1
auto[4160749568:4294967295]	auto[0]	76	1			T14	1		T17	2		T45	1
auto[4160749568:4294967295]	auto[1]	9	1			T118	2		T322	1		T416	2