Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7071

1

T1

8

T3

6

T4

4

auto[1]

286

1

T38

3

T87

9

T118

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2932	1			T1	4		T3	2		T4	1
auto[134217728:268435455]	175	1			T17	2		T133	1		T87	1
auto[268435456:402653183]	169	1			T1	1		T17	3		T38	1
auto[402653184:536870911]	138	1			T1	1		T14	1		T17	1
auto[536870912:671088639]	166	1			T17	1		T38	1		T197	1
auto[671088640:805306367]	123	1			T17	2		T32	1		T24	1
auto[805306368:939524095]	137	1			T14	1		T87	1		T89	2
auto[939524096:1073741823]	162	1			T133	1		T87	1		T196	1
auto[1073741824:1207959551]	122	1			T1	1		T4	1		T5	1
auto[1207959552:1342177279]	136	1			T4	1		T17	1		T88	1
auto[1342177280:1476395007]	129	1			T14	1		T24	1		T45	1
auto[1476395008:1610612735]	140	1			T3	1		T14	1		T17	1
auto[1610612736:1744830463]	142	1			T14	1		T23	1		T38	1
auto[1744830464:1879048191]	170	1			T3	1		T14	1		T17	1
auto[1879048192:2013265919]	153	1			T3	1		T5	1		T17	1
auto[2013265920:2147483647]	133	1			T31	1		T87	1		T24	1
auto[2147483648:2281701375]	127	1			T5	1		T38	1		T87	1
auto[2281701376:2415919103]	150	1			T4	1		T14	2		T38	1
auto[2415919104:2550136831]	127	1			T17	2		T32	1		T45	1
auto[2550136832:2684354559]	130	1			T17	1		T32	1		T23	1
auto[2684354560:2818572287]	133	1			T88	1		T24	1		T43	1
auto[2818572288:2952790015]	151	1			T5	1		T44	1		T45	2
auto[2952790016:3087007743]	113	1			T38	1		T86	1		T45	1
auto[3087007744:3221225471]	151	1			T14	1		T32	1		T87	1
auto[3221225472:3355443199]	135	1			T3	1		T5	1		T17	2
auto[3355443200:3489660927]	143	1			T88	1		T104	1		T90	1
auto[3489660928:3623878655]	127	1			T17	1		T23	1		T86	1
auto[3623878656:3758096383]	150	1			T17	3		T23	1		T90	1
auto[3758096384:3892314111]	153	1			T17	3		T88	2		T196	1
auto[3892314112:4026531839]	135	1			T1	1		T5	2		T14	1
auto[4026531840:4160749567]	157	1			T17	1		T32	1		T23	1
auto[4160749568:4294967295]	148	1			T5	2		T14	1		T17	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2921	1			T1	4		T3	2		T4	1
auto[0:134217727]	auto[1]	11	1			T87	1		T118	1		T404	1
auto[134217728:268435455]	auto[0]	166	1			T17	2		T133	1		T87	1
auto[134217728:268435455]	auto[1]	9	1			T137	1		T138	1		T311	1
auto[268435456:402653183]	auto[0]	158	1			T1	1		T17	3		T86	1
auto[268435456:402653183]	auto[1]	11	1			T38	1		T87	1		T118	2
auto[402653184:536870911]	auto[0]	129	1			T1	1		T14	1		T17	1
auto[402653184:536870911]	auto[1]	9	1			T118	1		T134	1		T385	1
auto[536870912:671088639]	auto[0]	154	1			T17	1		T197	1		T33	2
auto[536870912:671088639]	auto[1]	12	1			T38	1		T118	1		T135	1
auto[671088640:805306367]	auto[0]	115	1			T17	2		T32	1		T24	1
auto[671088640:805306367]	auto[1]	8	1			T135	1		T237	1		T311	1
auto[805306368:939524095]	auto[0]	126	1			T14	1		T89	2		T61	1
auto[805306368:939524095]	auto[1]	11	1			T87	1		T311	1		T322	1
auto[939524096:1073741823]	auto[0]	147	1			T133	1		T196	1		T24	2
auto[939524096:1073741823]	auto[1]	15	1			T87	1		T134	1		T135	3
auto[1073741824:1207959551]	auto[0]	112	1			T1	1		T4	1		T5	1
auto[1073741824:1207959551]	auto[1]	10	1			T137	1		T392	2		T385	1
auto[1207959552:1342177279]	auto[0]	124	1			T4	1		T17	1		T88	1
auto[1207959552:1342177279]	auto[1]	12	1			T134	3		T416	2		T417	1
auto[1342177280:1476395007]	auto[0]	123	1			T14	1		T24	1		T45	1
auto[1342177280:1476395007]	auto[1]	6	1			T135	1		T322	1		T297	1
auto[1476395008:1610612735]	auto[0]	128	1			T3	1		T14	1		T17	1
auto[1476395008:1610612735]	auto[1]	12	1			T87	1		T135	1		T322	1
auto[1610612736:1744830463]	auto[0]	136	1			T14	1		T23	1		T38	1
auto[1610612736:1744830463]	auto[1]	6	1			T237	1		T283	1		T419	2
auto[1744830464:1879048191]	auto[0]	162	1			T3	1		T14	1		T17	1
auto[1744830464:1879048191]	auto[1]	8	1			T118	1		T241	1		T404	1
auto[1879048192:2013265919]	auto[0]	144	1			T3	1		T5	1		T17	1
auto[1879048192:2013265919]	auto[1]	9	1			T135	1		T385	1		T417	1
auto[2013265920:2147483647]	auto[0]	127	1			T31	1		T87	1		T24	1
auto[2013265920:2147483647]	auto[1]	6	1			T241	1		T416	1		T369	1
auto[2147483648:2281701375]	auto[0]	119	1			T5	1		T38	1		T43	1
auto[2147483648:2281701375]	auto[1]	8	1			T87	1		T138	1		T431	2
auto[2281701376:2415919103]	auto[0]	137	1			T4	1		T14	2		T38	1
auto[2281701376:2415919103]	auto[1]	13	1			T87	1		T118	1		T241	1
auto[2415919104:2550136831]	auto[0]	113	1			T17	2		T32	1		T45	1
auto[2415919104:2550136831]	auto[1]	14	1			T135	1		T241	1		T385	1
auto[2550136832:2684354559]	auto[0]	127	1			T17	1		T32	1		T23	1
auto[2550136832:2684354559]	auto[1]	3	1			T322	1		T417	1		T435	1
auto[2684354560:2818572287]	auto[0]	122	1			T88	1		T24	1		T43	1
auto[2684354560:2818572287]	auto[1]	11	1			T138	1		T311	1		T322	1
auto[2818572288:2952790015]	auto[0]	144	1			T5	1		T44	1		T45	2
auto[2818572288:2952790015]	auto[1]	7	1			T134	1		T392	1		T385	2
auto[2952790016:3087007743]	auto[0]	108	1			T38	1		T86	1		T45	1
auto[2952790016:3087007743]	auto[1]	5	1			T233	1		T237	1		T376	1
auto[3087007744:3221225471]	auto[0]	143	1			T14	1		T32	1		T44	1
auto[3087007744:3221225471]	auto[1]	8	1			T87	1		T118	1		T137	1
auto[3221225472:3355443199]	auto[0]	122	1			T3	1		T5	1		T17	2
auto[3221225472:3355443199]	auto[1]	13	1			T38	1		T118	1		T136	1
auto[3355443200:3489660927]	auto[0]	137	1			T88	1		T104	1		T90	1
auto[3355443200:3489660927]	auto[1]	6	1			T138	1		T431	1		T419	1
auto[3489660928:3623878655]	auto[0]	124	1			T17	1		T23	1		T86	1
auto[3489660928:3623878655]	auto[1]	3	1			T136	1		T417	1		T436	1
auto[3623878656:3758096383]	auto[0]	136	1			T17	3		T23	1		T90	1
auto[3623878656:3758096383]	auto[1]	14	1			T134	1		T135	1		T376	1
auto[3758096384:3892314111]	auto[0]	146	1			T17	3		T88	2		T196	1
auto[3758096384:3892314111]	auto[1]	7	1			T118	1		T385	1		T404	1
auto[3892314112:4026531839]	auto[0]	129	1			T1	1		T5	2		T14	1
auto[3892314112:4026531839]	auto[1]	6	1			T87	1		T118	1		T404	2
auto[4026531840:4160749567]	auto[0]	152	1			T17	1		T32	1		T23	1
auto[4026531840:4160749567]	auto[1]	5	1			T135	1		T417	1		T419	1
auto[4160749568:4294967295]	auto[0]	140	1			T5	2		T14	1		T17	2
auto[4160749568:4294967295]	auto[1]	8	1			T134	1		T237	1		T385	1