Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.04 98.11 98.66 100.00 99.02 98.41 91.32


Total test records in report: 1083
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T1008 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.149029241 Jun 29 04:39:32 PM PDT 24 Jun 29 04:39:35 PM PDT 24 507637602 ps
T1009 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3900757452 Jun 29 04:39:32 PM PDT 24 Jun 29 04:39:42 PM PDT 24 1614661686 ps
T1010 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.469095407 Jun 29 04:39:31 PM PDT 24 Jun 29 04:39:33 PM PDT 24 15366068 ps
T1011 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.733681931 Jun 29 04:39:49 PM PDT 24 Jun 29 04:39:51 PM PDT 24 34377453 ps
T1012 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1629357 Jun 29 04:39:20 PM PDT 24 Jun 29 04:39:22 PM PDT 24 30588148 ps
T156 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3763606962 Jun 29 04:38:48 PM PDT 24 Jun 29 04:38:55 PM PDT 24 541817543 ps
T1013 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3760617108 Jun 29 04:39:38 PM PDT 24 Jun 29 04:39:39 PM PDT 24 31633795 ps
T1014 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1332495265 Jun 29 04:39:23 PM PDT 24 Jun 29 04:39:26 PM PDT 24 406740036 ps
T1015 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3315993507 Jun 29 04:39:31 PM PDT 24 Jun 29 04:39:35 PM PDT 24 98158591 ps
T178 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.262066759 Jun 29 04:39:34 PM PDT 24 Jun 29 04:39:40 PM PDT 24 925859681 ps
T1016 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3722698081 Jun 29 04:39:08 PM PDT 24 Jun 29 04:39:10 PM PDT 24 165564087 ps
T1017 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3610875872 Jun 29 04:39:12 PM PDT 24 Jun 29 04:39:14 PM PDT 24 22919074 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1792981662 Jun 29 04:38:48 PM PDT 24 Jun 29 04:38:51 PM PDT 24 344233522 ps
T1019 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2959408362 Jun 29 04:39:29 PM PDT 24 Jun 29 04:39:39 PM PDT 24 537559843 ps
T1020 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4156660283 Jun 29 04:39:38 PM PDT 24 Jun 29 04:39:39 PM PDT 24 29744181 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2537740215 Jun 29 04:38:41 PM PDT 24 Jun 29 04:38:47 PM PDT 24 440811257 ps
T1022 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3302025004 Jun 29 04:38:42 PM PDT 24 Jun 29 04:38:46 PM PDT 24 225284114 ps
T1023 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1206586095 Jun 29 04:39:21 PM PDT 24 Jun 29 04:39:22 PM PDT 24 23834870 ps
T1024 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3345416042 Jun 29 04:38:42 PM PDT 24 Jun 29 04:38:43 PM PDT 24 54350293 ps
T1025 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2158100801 Jun 29 04:39:07 PM PDT 24 Jun 29 04:39:09 PM PDT 24 73719753 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1785635549 Jun 29 04:39:06 PM PDT 24 Jun 29 04:39:07 PM PDT 24 27756185 ps
T1027 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.464891410 Jun 29 04:39:31 PM PDT 24 Jun 29 04:39:34 PM PDT 24 363813032 ps
T1028 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3001302274 Jun 29 04:38:49 PM PDT 24 Jun 29 04:38:51 PM PDT 24 62775114 ps
T1029 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2011505256 Jun 29 04:39:07 PM PDT 24 Jun 29 04:39:09 PM PDT 24 42426139 ps
T1030 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3841696750 Jun 29 04:39:21 PM PDT 24 Jun 29 04:39:25 PM PDT 24 223074862 ps
T1031 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.656250480 Jun 29 04:39:16 PM PDT 24 Jun 29 04:39:21 PM PDT 24 104479617 ps
T161 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.46193699 Jun 29 04:38:34 PM PDT 24 Jun 29 04:38:45 PM PDT 24 1124898943 ps
T172 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1140503388 Jun 29 04:38:41 PM PDT 24 Jun 29 04:38:44 PM PDT 24 261530745 ps
T1032 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3261009727 Jun 29 04:39:35 PM PDT 24 Jun 29 04:39:39 PM PDT 24 271031355 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4289314837 Jun 29 04:38:34 PM PDT 24 Jun 29 04:38:41 PM PDT 24 895791594 ps
T1034 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3547403708 Jun 29 04:39:07 PM PDT 24 Jun 29 04:39:11 PM PDT 24 97963677 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1177820158 Jun 29 04:38:35 PM PDT 24 Jun 29 04:38:37 PM PDT 24 29824193 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2676894855 Jun 29 04:38:48 PM PDT 24 Jun 29 04:38:50 PM PDT 24 54551200 ps
T174 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3553970389 Jun 29 04:38:56 PM PDT 24 Jun 29 04:39:02 PM PDT 24 353851305 ps
T1037 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2568009181 Jun 29 04:39:30 PM PDT 24 Jun 29 04:39:34 PM PDT 24 560289917 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.805382800 Jun 29 04:38:51 PM PDT 24 Jun 29 04:38:55 PM PDT 24 1700879030 ps
T1039 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2081052453 Jun 29 04:38:55 PM PDT 24 Jun 29 04:39:21 PM PDT 24 3553970921 ps
T1040 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1451937491 Jun 29 04:39:07 PM PDT 24 Jun 29 04:39:09 PM PDT 24 19740411 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2997854703 Jun 29 04:38:40 PM PDT 24 Jun 29 04:38:41 PM PDT 24 26554607 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1193678431 Jun 29 04:38:48 PM PDT 24 Jun 29 04:38:49 PM PDT 24 12777671 ps
T1043 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4292404184 Jun 29 04:39:31 PM PDT 24 Jun 29 04:39:33 PM PDT 24 52138498 ps
T157 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2955917750 Jun 29 04:39:12 PM PDT 24 Jun 29 04:39:16 PM PDT 24 186661872 ps
T1044 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3945553952 Jun 29 04:39:32 PM PDT 24 Jun 29 04:39:37 PM PDT 24 200674622 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2170636607 Jun 29 04:39:12 PM PDT 24 Jun 29 04:39:14 PM PDT 24 308084405 ps
T1046 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.714220667 Jun 29 04:39:22 PM PDT 24 Jun 29 04:39:24 PM PDT 24 84003064 ps
T1047 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1012314552 Jun 29 04:39:36 PM PDT 24 Jun 29 04:39:38 PM PDT 24 35626931 ps
T1048 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.880729391 Jun 29 04:39:28 PM PDT 24 Jun 29 04:39:31 PM PDT 24 1160255769 ps
T1049 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1633529215 Jun 29 04:38:57 PM PDT 24 Jun 29 04:38:59 PM PDT 24 69909475 ps
T1050 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2937797283 Jun 29 04:38:55 PM PDT 24 Jun 29 04:38:59 PM PDT 24 184074155 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3155157878 Jun 29 04:39:14 PM PDT 24 Jun 29 04:39:15 PM PDT 24 18229923 ps
T1052 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2798507486 Jun 29 04:39:20 PM PDT 24 Jun 29 04:39:24 PM PDT 24 268731258 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3677803395 Jun 29 04:38:49 PM PDT 24 Jun 29 04:39:04 PM PDT 24 1564799472 ps
T1054 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3382927670 Jun 29 04:38:40 PM PDT 24 Jun 29 04:38:53 PM PDT 24 1042008089 ps
T176 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2680829116 Jun 29 04:39:22 PM PDT 24 Jun 29 04:39:26 PM PDT 24 216729303 ps
T1055 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4131524408 Jun 29 04:39:32 PM PDT 24 Jun 29 04:39:33 PM PDT 24 23615710 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2776098465 Jun 29 04:39:21 PM PDT 24 Jun 29 04:39:24 PM PDT 24 185735700 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2588168489 Jun 29 04:38:40 PM PDT 24 Jun 29 04:38:41 PM PDT 24 15932026 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4035521464 Jun 29 04:38:42 PM PDT 24 Jun 29 04:38:45 PM PDT 24 58464577 ps
T1059 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.425575303 Jun 29 04:39:37 PM PDT 24 Jun 29 04:39:38 PM PDT 24 46459496 ps
T1060 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1621976420 Jun 29 04:39:30 PM PDT 24 Jun 29 04:39:31 PM PDT 24 15649698 ps
T1061 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2640817691 Jun 29 04:38:39 PM PDT 24 Jun 29 04:38:42 PM PDT 24 180714780 ps
T1062 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1378920087 Jun 29 04:39:07 PM PDT 24 Jun 29 04:39:13 PM PDT 24 149672619 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1014426760 Jun 29 04:39:28 PM PDT 24 Jun 29 04:39:30 PM PDT 24 11947762 ps
T1064 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2376232421 Jun 29 04:39:15 PM PDT 24 Jun 29 04:39:20 PM PDT 24 571426708 ps
T1065 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3373568199 Jun 29 04:38:49 PM PDT 24 Jun 29 04:38:50 PM PDT 24 23456536 ps
T1066 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3847647472 Jun 29 04:39:21 PM PDT 24 Jun 29 04:39:26 PM PDT 24 330681415 ps
T1067 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1190655788 Jun 29 04:39:37 PM PDT 24 Jun 29 04:39:38 PM PDT 24 9313223 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.157141163 Jun 29 04:39:20 PM PDT 24 Jun 29 04:39:25 PM PDT 24 73146951 ps
T1069 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1495323158 Jun 29 04:39:37 PM PDT 24 Jun 29 04:39:39 PM PDT 24 40608537 ps
T1070 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1677164017 Jun 29 04:39:15 PM PDT 24 Jun 29 04:39:16 PM PDT 24 22672871 ps
T1071 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.764194007 Jun 29 04:39:31 PM PDT 24 Jun 29 04:39:33 PM PDT 24 27941284 ps
T1072 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2164403232 Jun 29 04:38:48 PM PDT 24 Jun 29 04:38:54 PM PDT 24 606001015 ps
T1073 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3192254093 Jun 29 04:39:37 PM PDT 24 Jun 29 04:39:39 PM PDT 24 51821809 ps
T1074 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1438242345 Jun 29 04:38:39 PM PDT 24 Jun 29 04:38:41 PM PDT 24 62433534 ps
T1075 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1982166120 Jun 29 04:39:21 PM PDT 24 Jun 29 04:39:22 PM PDT 24 18216072 ps
T1076 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3952073742 Jun 29 04:38:47 PM PDT 24 Jun 29 04:38:59 PM PDT 24 253980812 ps
T1077 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.813227893 Jun 29 04:38:39 PM PDT 24 Jun 29 04:38:41 PM PDT 24 29569404 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.167845463 Jun 29 04:38:57 PM PDT 24 Jun 29 04:39:01 PM PDT 24 83995235 ps
T1079 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.522677275 Jun 29 04:39:39 PM PDT 24 Jun 29 04:39:40 PM PDT 24 15621602 ps
T1080 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1549557642 Jun 29 04:39:07 PM PDT 24 Jun 29 04:39:08 PM PDT 24 20350409 ps
T1081 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3494310872 Jun 29 04:38:41 PM PDT 24 Jun 29 04:38:51 PM PDT 24 807466655 ps
T1082 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3127950340 Jun 29 04:39:37 PM PDT 24 Jun 29 04:39:38 PM PDT 24 33356123 ps
T1083 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2046831647 Jun 29 04:38:49 PM PDT 24 Jun 29 04:38:53 PM PDT 24 1072981769 ps

Test location /workspace/coverage/default/47.keymgr_stress_all.172730949
Short name T17
Test name
Test status
Simulation time 395994028 ps
CPU time 20.48 seconds
Started Jun 29 04:44:08 PM PDT 24
Finished Jun 29 04:44:30 PM PDT 24
Peak memory 215468 kb
Host smart-35753327-ecaa-474e-a82b-090e548acb38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172730949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.172730949
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2065590465
Short name T6
Test name
Test status
Simulation time 1649802952 ps
CPU time 49.63 seconds
Started Jun 29 04:43:41 PM PDT 24
Finished Jun 29 04:44:31 PM PDT 24
Peak memory 214520 kb
Host smart-9907c2cc-8a88-47fd-b3ec-ce7bfd1a83f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065590465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2065590465
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3220030477
Short name T66
Test name
Test status
Simulation time 2351365562 ps
CPU time 22.47 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:54 PM PDT 24
Peak memory 222676 kb
Host smart-80f3e2a7-90a6-4572-a2bb-1846aa8be22b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220030477 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3220030477
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3909772436
Short name T12
Test name
Test status
Simulation time 928281862 ps
CPU time 6.71 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:59 PM PDT 24
Peak memory 231072 kb
Host smart-26feb8f6-c18b-446c-986d-5b0fd1be45d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909772436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3909772436
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3106187598
Short name T52
Test name
Test status
Simulation time 61532183941 ps
CPU time 178.75 seconds
Started Jun 29 04:43:41 PM PDT 24
Finished Jun 29 04:46:40 PM PDT 24
Peak memory 218108 kb
Host smart-cb96c942-e237-4526-beae-e2ce834ebb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106187598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3106187598
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.538839714
Short name T32
Test name
Test status
Simulation time 73589866 ps
CPU time 1.67 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:05 PM PDT 24
Peak memory 214260 kb
Host smart-6cc85c62-e0a6-46c8-9614-527379b9691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538839714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.538839714
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3384730649
Short name T63
Test name
Test status
Simulation time 586856763 ps
CPU time 22.9 seconds
Started Jun 29 04:44:23 PM PDT 24
Finished Jun 29 04:44:47 PM PDT 24
Peak memory 222516 kb
Host smart-9868b575-c605-47e3-89ac-5c3915bc7f54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384730649 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3384730649
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3764068254
Short name T134
Test name
Test status
Simulation time 3613390999 ps
CPU time 93.49 seconds
Started Jun 29 04:43:47 PM PDT 24
Finished Jun 29 04:45:21 PM PDT 24
Peak memory 222224 kb
Host smart-8d115d18-7f1e-46af-a9e7-7433a4f0ca59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764068254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3764068254
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3998530419
Short name T8
Test name
Test status
Simulation time 720464402 ps
CPU time 10.17 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:55 PM PDT 24
Peak memory 215844 kb
Host smart-a2767228-2118-4581-80fa-2fd81022d081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998530419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3998530419
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3393061712
Short name T115
Test name
Test status
Simulation time 492978058 ps
CPU time 6.81 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:27 PM PDT 24
Peak memory 214036 kb
Host smart-11287a0d-ff0d-4c2a-afd9-a4a709d6e3a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393061712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3393061712
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1211056826
Short name T9
Test name
Test status
Simulation time 154747822 ps
CPU time 3.91 seconds
Started Jun 29 04:41:21 PM PDT 24
Finished Jun 29 04:41:26 PM PDT 24
Peak memory 222804 kb
Host smart-360918ee-3518-4bcc-8be6-2598e35980fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211056826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1211056826
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3790800856
Short name T89
Test name
Test status
Simulation time 213367890 ps
CPU time 4.98 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 222444 kb
Host smart-38e80506-a000-44d6-a854-9d484a105656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790800856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3790800856
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3207192002
Short name T206
Test name
Test status
Simulation time 10402428915 ps
CPU time 113.68 seconds
Started Jun 29 04:42:30 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 215076 kb
Host smart-909557ac-71ed-4c75-bf8b-ae79ba64ad9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207192002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3207192002
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1900305034
Short name T419
Test name
Test status
Simulation time 227371850 ps
CPU time 12.53 seconds
Started Jun 29 04:43:36 PM PDT 24
Finished Jun 29 04:43:48 PM PDT 24
Peak memory 214332 kb
Host smart-9b75d1ad-92b8-49d8-8fb5-270bc9de6c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900305034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1900305034
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2189279881
Short name T33
Test name
Test status
Simulation time 381814952 ps
CPU time 4.61 seconds
Started Jun 29 04:41:44 PM PDT 24
Finished Jun 29 04:41:49 PM PDT 24
Peak memory 214272 kb
Host smart-1f6e2671-a4f8-4678-a07b-83021526ab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189279881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2189279881
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1628537375
Short name T118
Test name
Test status
Simulation time 1428701981 ps
CPU time 9.39 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:07 PM PDT 24
Peak memory 215824 kb
Host smart-7587d6e9-9719-403a-b3dd-035c5e2a1634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628537375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1628537375
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.222165211
Short name T87
Test name
Test status
Simulation time 143066941 ps
CPU time 4.12 seconds
Started Jun 29 04:44:11 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 214236 kb
Host smart-3e26de85-c9d1-49c9-b346-e3ed96dff1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222165211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.222165211
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1134133017
Short name T43
Test name
Test status
Simulation time 1410100516 ps
CPU time 27.43 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 221680 kb
Host smart-523ad548-8826-4e68-b92d-6c97d3d59090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134133017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1134133017
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3204860007
Short name T135
Test name
Test status
Simulation time 429332196 ps
CPU time 6.63 seconds
Started Jun 29 04:41:46 PM PDT 24
Finished Jun 29 04:41:53 PM PDT 24
Peak memory 215444 kb
Host smart-2662ae54-304a-4bd6-a761-fe59b93adfcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204860007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3204860007
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2845093066
Short name T175
Test name
Test status
Simulation time 157043386 ps
CPU time 2.21 seconds
Started Jun 29 04:42:37 PM PDT 24
Finished Jun 29 04:42:40 PM PDT 24
Peak memory 210592 kb
Host smart-bffbbe83-1f6a-4fdf-84d3-a91acd9fcd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845093066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2845093066
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3956363985
Short name T312
Test name
Test status
Simulation time 526783653 ps
CPU time 7.49 seconds
Started Jun 29 04:42:15 PM PDT 24
Finished Jun 29 04:42:23 PM PDT 24
Peak memory 215476 kb
Host smart-84c5bdfa-9d61-4a78-9316-d1da50968877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956363985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3956363985
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.711141213
Short name T158
Test name
Test status
Simulation time 1257828102 ps
CPU time 24.26 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:29 PM PDT 24
Peak memory 223724 kb
Host smart-d04c2a32-b47b-493b-a021-bf7162df0983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711141213 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.711141213
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1529491980
Short name T21
Test name
Test status
Simulation time 34144738 ps
CPU time 1.95 seconds
Started Jun 29 04:43:00 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 217004 kb
Host smart-b52ffc15-9f2d-42bd-9264-d48142629baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529491980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1529491980
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3657534182
Short name T34
Test name
Test status
Simulation time 510003748 ps
CPU time 5.98 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:51 PM PDT 24
Peak memory 209376 kb
Host smart-be7d6b50-b087-448f-8e4a-8a1c34fd0157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657534182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3657534182
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.540167189
Short name T946
Test name
Test status
Simulation time 159547227 ps
CPU time 2.92 seconds
Started Jun 29 04:39:23 PM PDT 24
Finished Jun 29 04:39:26 PM PDT 24
Peak memory 214040 kb
Host smart-108ca502-627e-48d7-a5f5-8415c36e01d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540167189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.540167189
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.467818768
Short name T4
Test name
Test status
Simulation time 140971923 ps
CPU time 2.66 seconds
Started Jun 29 04:41:44 PM PDT 24
Finished Jun 29 04:41:47 PM PDT 24
Peak memory 218252 kb
Host smart-f73b1b92-bff4-4872-b904-1cc32161351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467818768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.467818768
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2338668953
Short name T404
Test name
Test status
Simulation time 215090071 ps
CPU time 6.6 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 215364 kb
Host smart-fa969112-c304-4f41-b4fa-37f930f4492a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338668953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2338668953
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3552174281
Short name T46
Test name
Test status
Simulation time 2783416452 ps
CPU time 57.85 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:45:09 PM PDT 24
Peak memory 222556 kb
Host smart-673cae1f-2012-4de2-b71d-bb216f81df09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552174281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3552174281
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.342600195
Short name T27
Test name
Test status
Simulation time 89162592 ps
CPU time 2.66 seconds
Started Jun 29 04:41:52 PM PDT 24
Finished Jun 29 04:41:55 PM PDT 24
Peak memory 214396 kb
Host smart-8d904a8c-5264-4fc1-bc20-e1286a35bd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342600195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.342600195
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.375539091
Short name T448
Test name
Test status
Simulation time 78219148 ps
CPU time 0.89 seconds
Started Jun 29 04:41:20 PM PDT 24
Finished Jun 29 04:41:21 PM PDT 24
Peak memory 206100 kb
Host smart-723e7ec9-7389-4c2e-b98e-f8da371e9ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375539091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.375539091
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1906078466
Short name T98
Test name
Test status
Simulation time 475149024 ps
CPU time 4.04 seconds
Started Jun 29 04:42:56 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 214316 kb
Host smart-e5c746d6-eeae-4ed3-b762-38b915da7ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906078466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1906078466
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1226586887
Short name T137
Test name
Test status
Simulation time 916787043 ps
CPU time 4.91 seconds
Started Jun 29 04:41:26 PM PDT 24
Finished Jun 29 04:41:31 PM PDT 24
Peak memory 215664 kb
Host smart-05df9837-d6c1-45ac-b105-1d3c179de09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226586887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1226586887
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.362913706
Short name T138
Test name
Test status
Simulation time 3811197194 ps
CPU time 43.23 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:42 PM PDT 24
Peak memory 214360 kb
Host smart-24778c8f-7914-41f6-b4ba-1b18e7ca641a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362913706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.362913706
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1073297145
Short name T322
Test name
Test status
Simulation time 535272802 ps
CPU time 14.39 seconds
Started Jun 29 04:42:38 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 214332 kb
Host smart-c15485a4-78ae-4dee-ab2a-1828cdf25a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073297145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1073297145
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3297976695
Short name T104
Test name
Test status
Simulation time 88899358 ps
CPU time 2.12 seconds
Started Jun 29 04:43:08 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 206148 kb
Host smart-2f26e89f-59d1-4811-9c6f-a1155b6dbb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297976695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3297976695
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4029948976
Short name T24
Test name
Test status
Simulation time 48220296 ps
CPU time 3.23 seconds
Started Jun 29 04:41:46 PM PDT 24
Finished Jun 29 04:41:50 PM PDT 24
Peak memory 209760 kb
Host smart-f0cdb781-f931-419c-bb47-1391d98e98aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029948976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4029948976
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3815802341
Short name T223
Test name
Test status
Simulation time 1917028904 ps
CPU time 56.01 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:43:05 PM PDT 24
Peak memory 216300 kb
Host smart-933e284c-4f12-48ab-9cdf-634e6a70eb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815802341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3815802341
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1540912309
Short name T159
Test name
Test status
Simulation time 1384326737 ps
CPU time 7.2 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:23 PM PDT 24
Peak memory 213584 kb
Host smart-5e41cfca-32e6-4ad6-91d1-3d5b42a7e5a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540912309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1540912309
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.349411606
Short name T79
Test name
Test status
Simulation time 114794869 ps
CPU time 3.77 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:44 PM PDT 24
Peak memory 219972 kb
Host smart-4d7aec49-1dcc-4a1f-a5d2-781eedbeaeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349411606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.349411606
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3371037424
Short name T269
Test name
Test status
Simulation time 118103741 ps
CPU time 2.29 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 214416 kb
Host smart-c6b6c8a1-2f5f-4a7b-a40c-d8da4a1a6b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371037424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3371037424
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2347514137
Short name T214
Test name
Test status
Simulation time 1258277334 ps
CPU time 46.39 seconds
Started Jun 29 04:43:55 PM PDT 24
Finished Jun 29 04:44:42 PM PDT 24
Peak memory 216448 kb
Host smart-245425b8-6685-4311-a43c-11e14ec4379f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347514137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2347514137
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3472465947
Short name T393
Test name
Test status
Simulation time 2354766556 ps
CPU time 34.05 seconds
Started Jun 29 04:44:17 PM PDT 24
Finished Jun 29 04:44:52 PM PDT 24
Peak memory 214504 kb
Host smart-dd4bbc88-ab2b-4fd9-9a32-d9e81175b664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472465947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3472465947
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.46193699
Short name T161
Test name
Test status
Simulation time 1124898943 ps
CPU time 11.51 seconds
Started Jun 29 04:38:34 PM PDT 24
Finished Jun 29 04:38:45 PM PDT 24
Peak memory 216044 kb
Host smart-a100bd4a-1f26-4c76-b055-69c8266f41d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46193699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.46193699
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1549952670
Short name T53
Test name
Test status
Simulation time 237134397 ps
CPU time 2.24 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:47 PM PDT 24
Peak memory 222620 kb
Host smart-c92a010e-bbbc-4374-a721-9c84c4fc6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549952670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1549952670
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.878395351
Short name T20
Test name
Test status
Simulation time 94425612 ps
CPU time 2.8 seconds
Started Jun 29 04:42:37 PM PDT 24
Finished Jun 29 04:42:41 PM PDT 24
Peak memory 222820 kb
Host smart-6a554ab1-8bdc-460c-8309-99ea493b99ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878395351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.878395351
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1528328721
Short name T283
Test name
Test status
Simulation time 3944831784 ps
CPU time 53.66 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 216260 kb
Host smart-c6008425-e5b3-45c7-9c8e-24703c69653b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528328721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1528328721
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4102221118
Short name T291
Test name
Test status
Simulation time 107370252 ps
CPU time 2.16 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 214228 kb
Host smart-e82c6d70-1888-4219-8535-ac6c1e68ed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102221118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4102221118
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2798689651
Short name T219
Test name
Test status
Simulation time 7305908092 ps
CPU time 220.49 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:47:51 PM PDT 24
Peak memory 216720 kb
Host smart-025a19b1-475c-4408-806a-1e06ed86290c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798689651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2798689651
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2950812793
Short name T229
Test name
Test status
Simulation time 492218548 ps
CPU time 24.61 seconds
Started Jun 29 04:42:41 PM PDT 24
Finished Jun 29 04:43:06 PM PDT 24
Peak memory 222440 kb
Host smart-92143fd6-b54c-49d9-8e46-31b1a1809d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950812793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2950812793
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2114428696
Short name T221
Test name
Test status
Simulation time 15467959125 ps
CPU time 91.75 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:44:38 PM PDT 24
Peak memory 222596 kb
Host smart-e70a7150-12b1-4105-a85d-f6a7e6bb5dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114428696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2114428696
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2412832847
Short name T136
Test name
Test status
Simulation time 269324436 ps
CPU time 4.37 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 214364 kb
Host smart-debb8b3d-46a3-443c-a88b-94c3460ab61d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412832847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2412832847
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1612108183
Short name T241
Test name
Test status
Simulation time 1963477053 ps
CPU time 14.88 seconds
Started Jun 29 04:44:24 PM PDT 24
Finished Jun 29 04:44:39 PM PDT 24
Peak memory 215192 kb
Host smart-392babf6-7e4b-4eb2-b985-cfd6d97fc2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612108183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1612108183
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3216102298
Short name T152
Test name
Test status
Simulation time 154575023 ps
CPU time 3.92 seconds
Started Jun 29 04:43:05 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 218256 kb
Host smart-8eefae4c-d2d3-464f-8942-0d33bae37eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216102298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3216102298
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3315893905
Short name T146
Test name
Test status
Simulation time 82769830 ps
CPU time 3.08 seconds
Started Jun 29 04:43:28 PM PDT 24
Finished Jun 29 04:43:32 PM PDT 24
Peak memory 217680 kb
Host smart-46580119-eaba-4ff2-ab4f-14b53d13f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315893905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3315893905
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1403962820
Short name T247
Test name
Test status
Simulation time 69192694 ps
CPU time 3.59 seconds
Started Jun 29 04:42:38 PM PDT 24
Finished Jun 29 04:42:42 PM PDT 24
Peak memory 208704 kb
Host smart-701954cc-a4c1-46fe-9d91-f260381279ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403962820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1403962820
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_random.2029979539
Short name T202
Test name
Test status
Simulation time 348961377 ps
CPU time 3.79 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 209464 kb
Host smart-bab885b5-89c2-4320-8279-f8f9e51c27a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029979539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2029979539
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1693646072
Short name T192
Test name
Test status
Simulation time 2162888487 ps
CPU time 41.31 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 220124 kb
Host smart-dd6567fb-986b-4931-8572-8a17aa9bac56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693646072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1693646072
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.508015929
Short name T243
Test name
Test status
Simulation time 548691661 ps
CPU time 5.21 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 220032 kb
Host smart-4f1661ae-de95-45d5-880a-fc6803ca58c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508015929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.508015929
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1644036603
Short name T113
Test name
Test status
Simulation time 42459155 ps
CPU time 1.63 seconds
Started Jun 29 04:41:35 PM PDT 24
Finished Jun 29 04:41:37 PM PDT 24
Peak memory 210328 kb
Host smart-ee1a68d2-c76b-432f-85b7-1227616f6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644036603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1644036603
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.193142948
Short name T164
Test name
Test status
Simulation time 134534474 ps
CPU time 2.62 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 213540 kb
Host smart-2ad9564f-d700-4581-955d-24d1177e2708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193142948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.193142948
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1993691874
Short name T166
Test name
Test status
Simulation time 848698291 ps
CPU time 9.05 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:41 PM PDT 24
Peak memory 214980 kb
Host smart-64a09c03-c0a9-4cf6-b20f-84dabf9ac1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993691874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1993691874
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2955917750
Short name T157
Test name
Test status
Simulation time 186661872 ps
CPU time 3.63 seconds
Started Jun 29 04:39:12 PM PDT 24
Finished Jun 29 04:39:16 PM PDT 24
Peak memory 214948 kb
Host smart-ef4429ae-644a-48b3-8438-8b2e92e8c1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955917750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2955917750
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2939674729
Short name T100
Test name
Test status
Simulation time 138519428 ps
CPU time 4.87 seconds
Started Jun 29 04:43:09 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 217000 kb
Host smart-16d10240-e3d8-4d33-a7b6-ada0a05ce5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939674729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2939674729
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4283949976
Short name T150
Test name
Test status
Simulation time 229464530 ps
CPU time 3.72 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:08 PM PDT 24
Peak memory 216424 kb
Host smart-65f2b547-9193-4477-97d3-f31fced07392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283949976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4283949976
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.458258484
Short name T304
Test name
Test status
Simulation time 216578353 ps
CPU time 3.16 seconds
Started Jun 29 04:41:26 PM PDT 24
Finished Jun 29 04:41:29 PM PDT 24
Peak memory 207340 kb
Host smart-8c05aece-6679-4e65-8312-62b9d70a64c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458258484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.458258484
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1497801135
Short name T311
Test name
Test status
Simulation time 864164080 ps
CPU time 15.14 seconds
Started Jun 29 04:42:15 PM PDT 24
Finished Jun 29 04:42:31 PM PDT 24
Peak memory 215252 kb
Host smart-6f7d0b59-f3f5-420d-b533-e8dd5f36173d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497801135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1497801135
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_random.2693519840
Short name T86
Test name
Test status
Simulation time 297277551 ps
CPU time 4.33 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 208204 kb
Host smart-0712d94f-2e2c-437e-a665-3b4d2883dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693519840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2693519840
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3747189144
Short name T250
Test name
Test status
Simulation time 1014546012 ps
CPU time 12.49 seconds
Started Jun 29 04:42:31 PM PDT 24
Finished Jun 29 04:42:44 PM PDT 24
Peak memory 214396 kb
Host smart-5b007e2c-55ba-4cb4-ad35-67fb0fe97b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747189144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3747189144
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.626043914
Short name T336
Test name
Test status
Simulation time 87964009 ps
CPU time 3.57 seconds
Started Jun 29 04:42:39 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 214724 kb
Host smart-ab11b0fe-0eb9-429e-87a6-78624998a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626043914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.626043914
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4008595561
Short name T289
Test name
Test status
Simulation time 307490764 ps
CPU time 2.92 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 206288 kb
Host smart-ac8709d2-2ffe-44a2-a986-b4edd2f9b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008595561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4008595561
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3156890525
Short name T233
Test name
Test status
Simulation time 271330185 ps
CPU time 2.43 seconds
Started Jun 29 04:44:12 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 214220 kb
Host smart-bd7b949f-7b16-49da-a827-ac50f6029011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156890525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3156890525
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3560116509
Short name T149
Test name
Test status
Simulation time 737658510 ps
CPU time 9.81 seconds
Started Jun 29 04:42:33 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 217712 kb
Host smart-39244c4e-cafa-40a0-9724-a6c9be1015c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560116509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3560116509
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3996211685
Short name T147
Test name
Test status
Simulation time 302479038 ps
CPU time 8.27 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:57 PM PDT 24
Peak memory 222576 kb
Host smart-85e87c58-ac05-4c2d-9894-a5e4534a3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996211685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3996211685
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3399342985
Short name T151
Test name
Test status
Simulation time 123919798 ps
CPU time 3.31 seconds
Started Jun 29 04:43:11 PM PDT 24
Finished Jun 29 04:43:15 PM PDT 24
Peak memory 216960 kb
Host smart-3008b52e-7a9b-4006-a3e6-8ba11a40347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399342985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3399342985
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2872377516
Short name T260
Test name
Test status
Simulation time 44742791 ps
CPU time 3.16 seconds
Started Jun 29 04:41:18 PM PDT 24
Finished Jun 29 04:41:22 PM PDT 24
Peak memory 214472 kb
Host smart-e0e3d4fd-cd9a-4dbe-8fce-75f8e189168f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872377516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2872377516
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.885055655
Short name T486
Test name
Test status
Simulation time 140795492 ps
CPU time 2.18 seconds
Started Jun 29 04:41:26 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 210144 kb
Host smart-ced30b00-1ff0-48f7-b106-1df61c448423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885055655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.885055655
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.868211634
Short name T349
Test name
Test status
Simulation time 2674386929 ps
CPU time 25.99 seconds
Started Jun 29 04:42:27 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 208540 kb
Host smart-312b1a57-777e-4076-994e-3825b1557e03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868211634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.868211634
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_random.974444113
Short name T389
Test name
Test status
Simulation time 455286504 ps
CPU time 6.77 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:39 PM PDT 24
Peak memory 218312 kb
Host smart-6efbd1bb-bca3-43be-891d-363fd1eb98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974444113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.974444113
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3383239934
Short name T211
Test name
Test status
Simulation time 340810943 ps
CPU time 10.62 seconds
Started Jun 29 04:42:34 PM PDT 24
Finished Jun 29 04:42:45 PM PDT 24
Peak memory 222616 kb
Host smart-3c7d589b-ce54-4e8b-8402-d89b4318f3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383239934 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3383239934
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.686462916
Short name T54
Test name
Test status
Simulation time 379469617 ps
CPU time 2.46 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 222380 kb
Host smart-9967857a-e651-4e22-bd50-21b5edc1dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686462916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.686462916
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.172816687
Short name T23
Test name
Test status
Simulation time 177409509 ps
CPU time 5.5 seconds
Started Jun 29 04:41:37 PM PDT 24
Finished Jun 29 04:41:43 PM PDT 24
Peak memory 219036 kb
Host smart-1b611abd-d020-4a54-9c95-87abcf343a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172816687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.172816687
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2834811659
Short name T330
Test name
Test status
Simulation time 520893416 ps
CPU time 16.87 seconds
Started Jun 29 04:43:00 PM PDT 24
Finished Jun 29 04:43:17 PM PDT 24
Peak memory 222632 kb
Host smart-4a960bed-d733-4b58-904c-ff60d9f20451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834811659 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2834811659
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4140093205
Short name T70
Test name
Test status
Simulation time 249349289 ps
CPU time 3.15 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 214220 kb
Host smart-50c9db75-35ae-451c-bdab-5ab8714b4882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140093205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4140093205
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3722158831
Short name T245
Test name
Test status
Simulation time 936723911 ps
CPU time 3.85 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 214260 kb
Host smart-82a111c8-2156-4b10-92bf-d2d77606c779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722158831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3722158831
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.113740828
Short name T380
Test name
Test status
Simulation time 115203299 ps
CPU time 5.12 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 210208 kb
Host smart-d1746281-40aa-4e76-ab76-03ffc1875084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113740828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.113740828
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1140503388
Short name T172
Test name
Test status
Simulation time 261530745 ps
CPU time 2.79 seconds
Started Jun 29 04:38:41 PM PDT 24
Finished Jun 29 04:38:44 PM PDT 24
Peak memory 213644 kb
Host smart-2d049c07-808f-45de-b9a6-51790f4bfc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140503388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1140503388
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4215825892
Short name T168
Test name
Test status
Simulation time 876853561 ps
CPU time 7.7 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:29 PM PDT 24
Peak memory 213596 kb
Host smart-5e37999a-b4c2-459b-9a6e-598acd83d5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215825892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4215825892
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2680829116
Short name T176
Test name
Test status
Simulation time 216729303 ps
CPU time 3.28 seconds
Started Jun 29 04:39:22 PM PDT 24
Finished Jun 29 04:39:26 PM PDT 24
Peak memory 205420 kb
Host smart-600097fd-b588-4517-b155-442301cfa232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680829116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2680829116
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3553970389
Short name T174
Test name
Test status
Simulation time 353851305 ps
CPU time 4.82 seconds
Started Jun 29 04:38:56 PM PDT 24
Finished Jun 29 04:39:02 PM PDT 24
Peak memory 213608 kb
Host smart-4f4b1c1a-b7db-44dc-b8bc-d25e473ca617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553970389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3553970389
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1818612889
Short name T163
Test name
Test status
Simulation time 1149125095 ps
CPU time 5.75 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:12 PM PDT 24
Peak memory 213620 kb
Host smart-c08687e5-3ac0-4bb5-9edd-14b1f58adaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818612889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1818612889
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.820675038
Short name T39
Test name
Test status
Simulation time 1768927736 ps
CPU time 10.62 seconds
Started Jun 29 04:41:37 PM PDT 24
Finished Jun 29 04:41:48 PM PDT 24
Peak memory 238012 kb
Host smart-b7bf9f84-0210-46bc-a25f-abe16831fa04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820675038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.820675038
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2354222848
Short name T145
Test name
Test status
Simulation time 39967420 ps
CPU time 2.1 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 217320 kb
Host smart-bd07430e-91f0-44e4-9695-4d1f95faeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354222848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2354222848
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1276441707
Short name T812
Test name
Test status
Simulation time 209590021 ps
CPU time 2.76 seconds
Started Jun 29 04:41:18 PM PDT 24
Finished Jun 29 04:41:21 PM PDT 24
Peak memory 218584 kb
Host smart-f72b7c5c-bb98-44c1-934c-e3661e2f6908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276441707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1276441707
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_random.259319862
Short name T266
Test name
Test status
Simulation time 59377346 ps
CPU time 2.86 seconds
Started Jun 29 04:41:23 PM PDT 24
Finished Jun 29 04:41:26 PM PDT 24
Peak memory 207448 kb
Host smart-3d51fe3e-f0e9-42ad-beb4-4d88ae4d1a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259319862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.259319862
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3067384548
Short name T213
Test name
Test status
Simulation time 236440929 ps
CPU time 5.89 seconds
Started Jun 29 04:41:27 PM PDT 24
Finished Jun 29 04:41:34 PM PDT 24
Peak memory 222208 kb
Host smart-2ae78986-7879-4424-b049-39fb97b4e8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067384548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3067384548
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.484174610
Short name T730
Test name
Test status
Simulation time 4306503274 ps
CPU time 19.14 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:45 PM PDT 24
Peak memory 214372 kb
Host smart-9afface1-3597-48a9-bc32-d705aee569da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484174610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.484174610
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1279431876
Short name T215
Test name
Test status
Simulation time 300216979 ps
CPU time 3.98 seconds
Started Jun 29 04:41:27 PM PDT 24
Finished Jun 29 04:41:32 PM PDT 24
Peak memory 207560 kb
Host smart-8daf047e-3c14-41d6-879e-7a100ac730d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279431876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1279431876
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1492175835
Short name T364
Test name
Test status
Simulation time 391431822 ps
CPU time 24.2 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:50 PM PDT 24
Peak memory 222504 kb
Host smart-7bb8fd4b-f5c8-4ced-a154-6e1dd90a7dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492175835 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1492175835
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2569890091
Short name T230
Test name
Test status
Simulation time 39518710 ps
CPU time 2.24 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 222136 kb
Host smart-4437ac7b-8b80-4f40-960c-4f6cae65d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569890091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2569890091
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1874760866
Short name T802
Test name
Test status
Simulation time 198699048 ps
CPU time 2.66 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 214432 kb
Host smart-b7ba9570-a15b-4357-b664-6f9015957378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874760866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1874760866
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3735601448
Short name T402
Test name
Test status
Simulation time 145427304 ps
CPU time 3.44 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 214224 kb
Host smart-226b195b-cf42-483e-bb03-2d913573ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735601448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3735601448
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1247990719
Short name T368
Test name
Test status
Simulation time 130660424 ps
CPU time 2.51 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 207036 kb
Host smart-724e0f5d-7f60-4c7a-be01-bd10043764de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247990719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1247990719
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4220048257
Short name T618
Test name
Test status
Simulation time 156868411 ps
CPU time 5.41 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 214208 kb
Host smart-963ae59c-5dc6-4b76-a7fd-b8989f367dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220048257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4220048257
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3523364070
Short name T385
Test name
Test status
Simulation time 530759713 ps
CPU time 7.82 seconds
Started Jun 29 04:42:25 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 214648 kb
Host smart-db143672-4bf4-420e-8a01-7195de798b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523364070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3523364070
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3193970436
Short name T232
Test name
Test status
Simulation time 203381259 ps
CPU time 3.55 seconds
Started Jun 29 04:42:34 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 214336 kb
Host smart-0ea2804d-9c52-4d86-9693-646762391285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193970436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3193970436
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1536385613
Short name T226
Test name
Test status
Simulation time 71100237 ps
CPU time 2.89 seconds
Started Jun 29 04:42:34 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 209096 kb
Host smart-7841cfa5-1177-468d-b915-19ca89421be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536385613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1536385613
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.275949479
Short name T64
Test name
Test status
Simulation time 322132953 ps
CPU time 10.34 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 222540 kb
Host smart-a36a3f93-a92b-4cc7-ba5e-8460eca2451d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275949479 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.275949479
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.870672450
Short name T397
Test name
Test status
Simulation time 636213734 ps
CPU time 9.05 seconds
Started Jun 29 04:41:29 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 222484 kb
Host smart-0746966e-1bc0-4b6d-a4ff-a311c440e30d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870672450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.870672450
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.64222852
Short name T352
Test name
Test status
Simulation time 369510089 ps
CPU time 3.59 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 214340 kb
Host smart-63d9adfb-0227-439a-a52a-f073811734a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64222852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.64222852
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3565278327
Short name T274
Test name
Test status
Simulation time 96593258 ps
CPU time 3.5 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 222440 kb
Host smart-f9785242-ee94-45ed-a985-f13a0f278ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565278327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3565278327
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3766500430
Short name T205
Test name
Test status
Simulation time 42802153 ps
CPU time 2.49 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 207188 kb
Host smart-40f56148-fef4-40c5-91d1-78ff46b8c3a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766500430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3766500430
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1621331927
Short name T237
Test name
Test status
Simulation time 93545439 ps
CPU time 3.68 seconds
Started Jun 29 04:42:56 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 214344 kb
Host smart-78140936-8247-4581-ab63-358771111fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621331927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1621331927
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.233635152
Short name T210
Test name
Test status
Simulation time 40493236 ps
CPU time 3.47 seconds
Started Jun 29 04:43:00 PM PDT 24
Finished Jun 29 04:43:03 PM PDT 24
Peak memory 208888 kb
Host smart-b2f37977-fae0-4d56-9bf3-2c20074444c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233635152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.233635152
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1775136400
Short name T314
Test name
Test status
Simulation time 114540095 ps
CPU time 2.7 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 214872 kb
Host smart-08ac0af5-ee39-446d-b3c4-cfbbb21120ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775136400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1775136400
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2978669337
Short name T366
Test name
Test status
Simulation time 132026870 ps
CPU time 3.81 seconds
Started Jun 29 04:43:09 PM PDT 24
Finished Jun 29 04:43:13 PM PDT 24
Peak memory 222228 kb
Host smart-041cdcad-5965-4a38-9973-ef8ec0f3672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978669337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2978669337
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3302979555
Short name T337
Test name
Test status
Simulation time 176997857 ps
CPU time 3.05 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 219588 kb
Host smart-a17f1e8a-7a0d-4e86-ad4c-3c21fc997897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302979555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3302979555
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.431198263
Short name T30
Test name
Test status
Simulation time 48993682 ps
CPU time 2.52 seconds
Started Jun 29 04:43:49 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 222728 kb
Host smart-0fc7b762-b7da-4f4c-acd8-6f5168ace5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431198263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.431198263
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4286495857
Short name T72
Test name
Test status
Simulation time 4878678459 ps
CPU time 49.49 seconds
Started Jun 29 04:41:58 PM PDT 24
Finished Jun 29 04:42:48 PM PDT 24
Peak memory 222540 kb
Host smart-5e5d60e6-c109-4cd2-a8a5-430950a5399f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286495857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4286495857
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1344231460
Short name T186
Test name
Test status
Simulation time 224553370 ps
CPU time 6.94 seconds
Started Jun 29 04:38:39 PM PDT 24
Finished Jun 29 04:38:46 PM PDT 24
Peak memory 205544 kb
Host smart-f3cf26c1-f4ac-4aa5-93d9-edbbb5305277
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344231460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
344231460
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3382927670
Short name T1054
Test name
Test status
Simulation time 1042008089 ps
CPU time 12.21 seconds
Started Jun 29 04:38:40 PM PDT 24
Finished Jun 29 04:38:53 PM PDT 24
Peak memory 205388 kb
Host smart-9115b831-0844-43bd-b485-ad38512d0793
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382927670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
382927670
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.237023196
Short name T189
Test name
Test status
Simulation time 142156492 ps
CPU time 1.16 seconds
Started Jun 29 04:38:39 PM PDT 24
Finished Jun 29 04:38:40 PM PDT 24
Peak memory 205320 kb
Host smart-9930756c-efbe-453a-8dd2-732ebd2c0873
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237023196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.237023196
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1438242345
Short name T1074
Test name
Test status
Simulation time 62433534 ps
CPU time 1.48 seconds
Started Jun 29 04:38:39 PM PDT 24
Finished Jun 29 04:38:41 PM PDT 24
Peak memory 213672 kb
Host smart-2692095f-7547-4724-9e0d-f88ff20bd4b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438242345 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1438242345
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.813227893
Short name T1077
Test name
Test status
Simulation time 29569404 ps
CPU time 1.13 seconds
Started Jun 29 04:38:39 PM PDT 24
Finished Jun 29 04:38:41 PM PDT 24
Peak memory 205412 kb
Host smart-8ece12fe-6848-4fe0-8189-0f99baea7bef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813227893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.813227893
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2588168489
Short name T1057
Test name
Test status
Simulation time 15932026 ps
CPU time 0.87 seconds
Started Jun 29 04:38:40 PM PDT 24
Finished Jun 29 04:38:41 PM PDT 24
Peak memory 205536 kb
Host smart-e740a4f9-bccb-4233-b7c7-0b2515050185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588168489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2588168489
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4035521464
Short name T1058
Test name
Test status
Simulation time 58464577 ps
CPU time 1.76 seconds
Started Jun 29 04:38:42 PM PDT 24
Finished Jun 29 04:38:45 PM PDT 24
Peak memory 205412 kb
Host smart-61175920-6412-4a2b-8ea2-92a6a44f2eed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035521464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4035521464
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.79772148
Short name T117
Test name
Test status
Simulation time 67687093 ps
CPU time 1.49 seconds
Started Jun 29 04:38:35 PM PDT 24
Finished Jun 29 04:38:36 PM PDT 24
Peak memory 213984 kb
Host smart-91957e04-d96a-4f9a-b773-1ab2cc97bace
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79772148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_
reg_errors.79772148
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4289314837
Short name T1033
Test name
Test status
Simulation time 895791594 ps
CPU time 6.05 seconds
Started Jun 29 04:38:34 PM PDT 24
Finished Jun 29 04:38:41 PM PDT 24
Peak memory 213644 kb
Host smart-414afc99-1407-41b0-b99f-a78aa04facc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289314837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.4289314837
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1177820158
Short name T1035
Test name
Test status
Simulation time 29824193 ps
CPU time 1.85 seconds
Started Jun 29 04:38:35 PM PDT 24
Finished Jun 29 04:38:37 PM PDT 24
Peak memory 213608 kb
Host smart-a4b6e95d-0206-4934-b6ec-148a8f641905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177820158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1177820158
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3494310872
Short name T1081
Test name
Test status
Simulation time 807466655 ps
CPU time 8.91 seconds
Started Jun 29 04:38:41 PM PDT 24
Finished Jun 29 04:38:51 PM PDT 24
Peak memory 205488 kb
Host smart-36451bf7-22d1-4a00-ab30-fb71f5aeeeff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494310872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
494310872
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1143233165
Short name T979
Test name
Test status
Simulation time 3453338557 ps
CPU time 15.54 seconds
Started Jun 29 04:38:40 PM PDT 24
Finished Jun 29 04:38:56 PM PDT 24
Peak memory 205456 kb
Host smart-b3948a39-5d88-4672-9457-539c411a681c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143233165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
143233165
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2820603911
Short name T1005
Test name
Test status
Simulation time 118784282 ps
CPU time 1.41 seconds
Started Jun 29 04:38:41 PM PDT 24
Finished Jun 29 04:38:43 PM PDT 24
Peak memory 205476 kb
Host smart-9a290170-58e4-45f9-a7bb-aa6d2f3a729f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820603911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
820603911
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2519329989
Short name T971
Test name
Test status
Simulation time 18429589 ps
CPU time 1.48 seconds
Started Jun 29 04:38:41 PM PDT 24
Finished Jun 29 04:38:43 PM PDT 24
Peak memory 213704 kb
Host smart-42ecd60d-a305-409e-af60-5dae6c60f294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519329989 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2519329989
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3201410593
Short name T141
Test name
Test status
Simulation time 30313891 ps
CPU time 1.21 seconds
Started Jun 29 04:38:41 PM PDT 24
Finished Jun 29 04:38:43 PM PDT 24
Peak memory 205408 kb
Host smart-8fc6e18d-f08e-4193-bcf9-7f91534606d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201410593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3201410593
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2997854703
Short name T1041
Test name
Test status
Simulation time 26554607 ps
CPU time 0.86 seconds
Started Jun 29 04:38:40 PM PDT 24
Finished Jun 29 04:38:41 PM PDT 24
Peak memory 205272 kb
Host smart-4f3d85fe-4631-4042-bbce-c45b3fa33e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997854703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2997854703
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3302025004
Short name T1022
Test name
Test status
Simulation time 225284114 ps
CPU time 2.96 seconds
Started Jun 29 04:38:42 PM PDT 24
Finished Jun 29 04:38:46 PM PDT 24
Peak memory 205716 kb
Host smart-5a960804-6b04-4aa8-88c7-c76d926b65fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302025004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3302025004
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3345416042
Short name T1024
Test name
Test status
Simulation time 54350293 ps
CPU time 1.57 seconds
Started Jun 29 04:38:42 PM PDT 24
Finished Jun 29 04:38:43 PM PDT 24
Peak memory 213908 kb
Host smart-922603b8-62bd-45a5-afd4-8e55cdd44921
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345416042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3345416042
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2537740215
Short name T1021
Test name
Test status
Simulation time 440811257 ps
CPU time 6.57 seconds
Started Jun 29 04:38:41 PM PDT 24
Finished Jun 29 04:38:47 PM PDT 24
Peak memory 214004 kb
Host smart-6eeeed3e-c0b2-4bca-a742-9d8e72a7df06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537740215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2537740215
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1442254321
Short name T965
Test name
Test status
Simulation time 108811512 ps
CPU time 3.82 seconds
Started Jun 29 04:38:39 PM PDT 24
Finished Jun 29 04:38:43 PM PDT 24
Peak memory 213672 kb
Host smart-3f973707-8931-4a2d-a46b-96e745ffdce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442254321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1442254321
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1495733148
Short name T956
Test name
Test status
Simulation time 220776339 ps
CPU time 2.14 seconds
Started Jun 29 04:39:16 PM PDT 24
Finished Jun 29 04:39:19 PM PDT 24
Peak memory 213652 kb
Host smart-e3641678-7323-4516-80f3-486f65187378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495733148 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1495733148
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1595137029
Short name T963
Test name
Test status
Simulation time 49065759 ps
CPU time 1.07 seconds
Started Jun 29 04:39:13 PM PDT 24
Finished Jun 29 04:39:15 PM PDT 24
Peak memory 205412 kb
Host smart-8a4517e1-63b0-468a-8d13-2cacda1bf7f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595137029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1595137029
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.349774115
Short name T931
Test name
Test status
Simulation time 34553117 ps
CPU time 0.87 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:16 PM PDT 24
Peak memory 205384 kb
Host smart-5f455ea9-a559-4fce-b00a-55d7690bb789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349774115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.349774115
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3610875872
Short name T1017
Test name
Test status
Simulation time 22919074 ps
CPU time 1.69 seconds
Started Jun 29 04:39:12 PM PDT 24
Finished Jun 29 04:39:14 PM PDT 24
Peak memory 205360 kb
Host smart-aaf22c29-6cc2-4eac-a8ab-d8f13eab99a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610875872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3610875872
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.656250480
Short name T1031
Test name
Test status
Simulation time 104479617 ps
CPU time 3.99 seconds
Started Jun 29 04:39:16 PM PDT 24
Finished Jun 29 04:39:21 PM PDT 24
Peak memory 213760 kb
Host smart-6a94a013-5c3d-40c6-8165-53eb5dfb1e24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656250480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.656250480
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3092545446
Short name T954
Test name
Test status
Simulation time 344721902 ps
CPU time 4.87 seconds
Started Jun 29 04:39:16 PM PDT 24
Finished Jun 29 04:39:21 PM PDT 24
Peak memory 213872 kb
Host smart-5ab414f4-66ab-40d4-bcda-13ab8a50ce9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092545446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3092545446
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2450397853
Short name T962
Test name
Test status
Simulation time 73554097 ps
CPU time 2.12 seconds
Started Jun 29 04:39:14 PM PDT 24
Finished Jun 29 04:39:17 PM PDT 24
Peak memory 216912 kb
Host smart-44f66856-4e47-43ed-b01b-9b7cd97eec98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450397853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2450397853
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2093693744
Short name T982
Test name
Test status
Simulation time 133034216 ps
CPU time 3.63 seconds
Started Jun 29 04:39:16 PM PDT 24
Finished Jun 29 04:39:20 PM PDT 24
Peak memory 213616 kb
Host smart-59e9b7bc-83d4-468f-aeb5-111bdcec949e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093693744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2093693744
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.751701164
Short name T160
Test name
Test status
Simulation time 84687966 ps
CPU time 1.71 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:17 PM PDT 24
Peak memory 216516 kb
Host smart-ce288480-176b-4ce7-9697-ae133edecb90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751701164 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.751701164
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4289870763
Short name T999
Test name
Test status
Simulation time 37606019 ps
CPU time 0.96 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:16 PM PDT 24
Peak memory 205428 kb
Host smart-d6d01a0c-160a-461a-a48b-eb0fad193945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289870763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4289870763
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4152990402
Short name T1004
Test name
Test status
Simulation time 69867956 ps
CPU time 0.7 seconds
Started Jun 29 04:39:16 PM PDT 24
Finished Jun 29 04:39:17 PM PDT 24
Peak memory 205276 kb
Host smart-45668105-b93c-4fef-8fed-5bf85281df75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152990402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4152990402
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3504559344
Short name T958
Test name
Test status
Simulation time 188715423 ps
CPU time 1.83 seconds
Started Jun 29 04:39:14 PM PDT 24
Finished Jun 29 04:39:16 PM PDT 24
Peak memory 205404 kb
Host smart-548a1e93-1078-4a53-ae9f-1c3c63f0a416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504559344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3504559344
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3343368055
Short name T995
Test name
Test status
Simulation time 145628859 ps
CPU time 3 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:18 PM PDT 24
Peak memory 213860 kb
Host smart-28008b56-ffee-4bb2-aaaf-56002660c029
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343368055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3343368055
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.955896115
Short name T960
Test name
Test status
Simulation time 203417232 ps
CPU time 9.16 seconds
Started Jun 29 04:39:13 PM PDT 24
Finished Jun 29 04:39:22 PM PDT 24
Peak memory 214004 kb
Host smart-6991366f-262f-4626-94e7-51a6d85754ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955896115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.955896115
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2376232421
Short name T1064
Test name
Test status
Simulation time 571426708 ps
CPU time 4.77 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:20 PM PDT 24
Peak memory 215752 kb
Host smart-4c653f6f-372d-4674-af60-a64a21d62423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376232421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2376232421
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2444922712
Short name T968
Test name
Test status
Simulation time 172296120 ps
CPU time 2.19 seconds
Started Jun 29 04:39:22 PM PDT 24
Finished Jun 29 04:39:25 PM PDT 24
Peak memory 213672 kb
Host smart-ff2dc820-e8ab-427a-b493-bce9958a7c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444922712 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2444922712
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3862186991
Short name T977
Test name
Test status
Simulation time 73926814 ps
CPU time 0.97 seconds
Started Jun 29 04:39:23 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 205180 kb
Host smart-3144a2dd-ecce-4cb1-9342-aacaed716ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862186991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3862186991
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3573418194
Short name T927
Test name
Test status
Simulation time 84641737 ps
CPU time 0.86 seconds
Started Jun 29 04:39:22 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 205380 kb
Host smart-ab698417-91ec-482b-93e0-c6cf660cce8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573418194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3573418194
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2303823856
Short name T974
Test name
Test status
Simulation time 110138456 ps
CPU time 1.89 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:22 PM PDT 24
Peak memory 205552 kb
Host smart-b855a90f-7c84-4dff-ab64-d90de4a03ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303823856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2303823856
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1207710411
Short name T119
Test name
Test status
Simulation time 540425933 ps
CPU time 4.05 seconds
Started Jun 29 04:39:24 PM PDT 24
Finished Jun 29 04:39:28 PM PDT 24
Peak memory 213924 kb
Host smart-179f74d6-8d36-4c9e-924d-43cc86979d60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207710411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1207710411
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.157141163
Short name T1068
Test name
Test status
Simulation time 73146951 ps
CPU time 4.51 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:25 PM PDT 24
Peak memory 213832 kb
Host smart-15cb1273-c03d-4b03-9308-46f96e80a136
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157141163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.157141163
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1332495265
Short name T1014
Test name
Test status
Simulation time 406740036 ps
CPU time 3.14 seconds
Started Jun 29 04:39:23 PM PDT 24
Finished Jun 29 04:39:26 PM PDT 24
Peak memory 213656 kb
Host smart-4b5fbf10-4d75-412d-8040-bac6943f6160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332495265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1332495265
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1527608829
Short name T926
Test name
Test status
Simulation time 42609142 ps
CPU time 1.82 seconds
Started Jun 29 04:39:23 PM PDT 24
Finished Jun 29 04:39:25 PM PDT 24
Peak memory 213720 kb
Host smart-375a6d5b-871b-4d80-b507-7eb43e7f8f72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527608829 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1527608829
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1629357
Short name T1012
Test name
Test status
Simulation time 30588148 ps
CPU time 0.95 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:22 PM PDT 24
Peak memory 205356 kb
Host smart-d490999d-2966-4a35-9e33-de28cc1dfc1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1629357
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3623848713
Short name T938
Test name
Test status
Simulation time 12325218 ps
CPU time 0.73 seconds
Started Jun 29 04:39:22 PM PDT 24
Finished Jun 29 04:39:23 PM PDT 24
Peak memory 205244 kb
Host smart-50999ba1-6cf2-409b-9c4e-c975b7c76bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623848713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3623848713
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.714220667
Short name T1046
Test name
Test status
Simulation time 84003064 ps
CPU time 1.98 seconds
Started Jun 29 04:39:22 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 205512 kb
Host smart-69cc2ab1-695d-49e9-b413-4d20f773239c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714220667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.714220667
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2798507486
Short name T1052
Test name
Test status
Simulation time 268731258 ps
CPU time 3.46 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 213732 kb
Host smart-23bf1e19-517e-4d32-b861-71607dea56a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798507486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2798507486
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3530794861
Short name T923
Test name
Test status
Simulation time 45234782 ps
CPU time 1.8 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 213668 kb
Host smart-d629c26b-e43f-447e-a68c-65cdb4babea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530794861 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3530794861
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3471634534
Short name T1006
Test name
Test status
Simulation time 133100106 ps
CPU time 1.23 seconds
Started Jun 29 04:39:22 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 205312 kb
Host smart-1d6edc03-2f18-458e-9d2d-0cd9fafaf50d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471634534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3471634534
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2466983052
Short name T967
Test name
Test status
Simulation time 48027786 ps
CPU time 0.74 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:23 PM PDT 24
Peak memory 205196 kb
Host smart-f0fdf5e5-c33e-4396-a6d7-0756fe649e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466983052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2466983052
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2776098465
Short name T1056
Test name
Test status
Simulation time 185735700 ps
CPU time 1.58 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 205816 kb
Host smart-375fb287-2a45-44ba-8b86-e52f4fbcbcd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776098465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2776098465
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3841696750
Short name T1030
Test name
Test status
Simulation time 223074862 ps
CPU time 2.6 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:25 PM PDT 24
Peak memory 213804 kb
Host smart-52a51621-1312-494e-83cb-a5c0a2c00f17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841696750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3841696750
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.104902125
Short name T1002
Test name
Test status
Simulation time 290567863 ps
CPU time 8.32 seconds
Started Jun 29 04:39:23 PM PDT 24
Finished Jun 29 04:39:32 PM PDT 24
Peak memory 213956 kb
Host smart-b72b572e-06bf-414b-8ff5-6e212589907a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104902125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.104902125
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3760471459
Short name T188
Test name
Test status
Simulation time 218667055 ps
CPU time 1.8 seconds
Started Jun 29 04:39:24 PM PDT 24
Finished Jun 29 04:39:26 PM PDT 24
Peak memory 213716 kb
Host smart-9cbabc81-29fa-4d65-8352-008d9ca36e37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760471459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3760471459
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1066095282
Short name T155
Test name
Test status
Simulation time 79093430 ps
CPU time 1.19 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:22 PM PDT 24
Peak memory 205528 kb
Host smart-35c08b69-b13c-4029-8fb8-8c25a6c23f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066095282 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1066095282
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1982166120
Short name T1075
Test name
Test status
Simulation time 18216072 ps
CPU time 1.2 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:22 PM PDT 24
Peak memory 205492 kb
Host smart-f0a8658d-5f76-4839-81bd-53180ceb37cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982166120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1982166120
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1206586095
Short name T1023
Test name
Test status
Simulation time 23834870 ps
CPU time 0.73 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:22 PM PDT 24
Peak memory 205380 kb
Host smart-a3503962-1168-4848-aeb6-98c8d6159f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206586095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1206586095
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3770835158
Short name T143
Test name
Test status
Simulation time 207706638 ps
CPU time 3.83 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:25 PM PDT 24
Peak memory 205552 kb
Host smart-b08e939f-df93-461e-a906-261d1b224c1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770835158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3770835158
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.347010998
Short name T940
Test name
Test status
Simulation time 50561562 ps
CPU time 2.22 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 214008 kb
Host smart-bf524bb4-b075-4c46-876e-353e26b3c052
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347010998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.347010998
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3847647472
Short name T1066
Test name
Test status
Simulation time 330681415 ps
CPU time 4.76 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:26 PM PDT 24
Peak memory 219976 kb
Host smart-78d89a5e-433d-444c-b3d4-cd8aa68ccc92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847647472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3847647472
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2713860044
Short name T925
Test name
Test status
Simulation time 87521625 ps
CPU time 2.01 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:23 PM PDT 24
Peak memory 213708 kb
Host smart-0d158e7c-aebe-4506-a01c-bdabdb1411be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713860044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2713860044
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4105969210
Short name T169
Test name
Test status
Simulation time 56139194 ps
CPU time 2.94 seconds
Started Jun 29 04:39:20 PM PDT 24
Finished Jun 29 04:39:24 PM PDT 24
Peak memory 213696 kb
Host smart-a845dcfd-ca01-4ca0-9672-7f80903976d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105969210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4105969210
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3332285599
Short name T980
Test name
Test status
Simulation time 192450108 ps
CPU time 2.12 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 213764 kb
Host smart-5619a45d-a52f-4db0-a222-5a24b5d25709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332285599 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3332285599
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1014426760
Short name T1063
Test name
Test status
Simulation time 11947762 ps
CPU time 0.9 seconds
Started Jun 29 04:39:28 PM PDT 24
Finished Jun 29 04:39:30 PM PDT 24
Peak memory 205432 kb
Host smart-b08c93e2-7774-4c6b-a2ea-f8851035d776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014426760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1014426760
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1886552908
Short name T985
Test name
Test status
Simulation time 59676837 ps
CPU time 0.71 seconds
Started Jun 29 04:39:28 PM PDT 24
Finished Jun 29 04:39:29 PM PDT 24
Peak memory 205380 kb
Host smart-3d5d4dd0-d9e3-4cbe-9c36-adc3fc5f717d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886552908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1886552908
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1738393925
Short name T1003
Test name
Test status
Simulation time 44567386 ps
CPU time 1.4 seconds
Started Jun 29 04:39:30 PM PDT 24
Finished Jun 29 04:39:32 PM PDT 24
Peak memory 205524 kb
Host smart-ca9a68c9-b65b-46dd-aa5d-6a2cefe46e8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738393925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1738393925
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2078498013
Short name T120
Test name
Test status
Simulation time 511003346 ps
CPU time 2.85 seconds
Started Jun 29 04:39:21 PM PDT 24
Finished Jun 29 04:39:25 PM PDT 24
Peak memory 213832 kb
Host smart-e1a8eb7d-cb0b-4c65-a42e-bf6cbb37b3fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078498013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2078498013
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3900757452
Short name T1009
Test name
Test status
Simulation time 1614661686 ps
CPU time 9.79 seconds
Started Jun 29 04:39:32 PM PDT 24
Finished Jun 29 04:39:42 PM PDT 24
Peak memory 214044 kb
Host smart-744c03e1-4c19-40f4-8ba1-61bdf2e75d56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900757452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3900757452
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1354457339
Short name T961
Test name
Test status
Simulation time 797347437 ps
CPU time 4.08 seconds
Started Jun 29 04:39:29 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 213728 kb
Host smart-bc064b9a-7381-4e52-b07f-9242cfd58794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354457339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1354457339
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2880561864
Short name T993
Test name
Test status
Simulation time 54423443 ps
CPU time 1.61 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 205564 kb
Host smart-5d08db13-8295-4099-8953-1609d4e3f1a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880561864 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2880561864
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.764194007
Short name T1071
Test name
Test status
Simulation time 27941284 ps
CPU time 1.55 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 205436 kb
Host smart-6a30711b-1e2a-48b1-8535-dfe0d2fc7356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764194007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.764194007
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4131524408
Short name T1055
Test name
Test status
Simulation time 23615710 ps
CPU time 0.7 seconds
Started Jun 29 04:39:32 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 205276 kb
Host smart-9b0b98d2-77df-40a9-a78c-bcbde5e5b1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131524408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4131524408
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3386916631
Short name T140
Test name
Test status
Simulation time 134480337 ps
CPU time 2.28 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 213556 kb
Host smart-52c8a058-b70a-4dae-9382-6865abc2915c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386916631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3386916631
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.464891410
Short name T1027
Test name
Test status
Simulation time 363813032 ps
CPU time 2.56 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 214008 kb
Host smart-375bf909-4a42-4d93-aeed-e7d01ef811ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464891410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.464891410
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4165717664
Short name T114
Test name
Test status
Simulation time 303441713 ps
CPU time 7.11 seconds
Started Jun 29 04:39:29 PM PDT 24
Finished Jun 29 04:39:37 PM PDT 24
Peak memory 213828 kb
Host smart-676a4bf6-b4f6-4548-96b9-b9fa48680819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165717664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4165717664
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2568009181
Short name T1037
Test name
Test status
Simulation time 560289917 ps
CPU time 3.28 seconds
Started Jun 29 04:39:30 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 213800 kb
Host smart-d477c096-9ee2-4d75-8597-316a37caea9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568009181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2568009181
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2775244872
Short name T165
Test name
Test status
Simulation time 94822312 ps
CPU time 4.38 seconds
Started Jun 29 04:39:35 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205376 kb
Host smart-7ae91f10-3991-4750-be0e-729646482603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775244872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2775244872
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.316101332
Short name T929
Test name
Test status
Simulation time 81265075 ps
CPU time 1.46 seconds
Started Jun 29 04:39:32 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 213684 kb
Host smart-fe8f859e-6ba4-4d9f-9e7b-76b1ed3bc2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316101332 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.316101332
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1341217122
Short name T964
Test name
Test status
Simulation time 14974942 ps
CPU time 0.99 seconds
Started Jun 29 04:39:34 PM PDT 24
Finished Jun 29 04:39:36 PM PDT 24
Peak memory 205328 kb
Host smart-277a172a-1a55-4bdd-afeb-3669e4f04e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341217122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1341217122
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.469095407
Short name T1010
Test name
Test status
Simulation time 15366068 ps
CPU time 0.77 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 205172 kb
Host smart-7a6cda67-35a2-4c5b-8568-5e446db9dd21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469095407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.469095407
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.880729391
Short name T1048
Test name
Test status
Simulation time 1160255769 ps
CPU time 2.46 seconds
Started Jun 29 04:39:28 PM PDT 24
Finished Jun 29 04:39:31 PM PDT 24
Peak memory 205428 kb
Host smart-5869067c-80b4-4692-996c-4185c031a862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880729391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.880729391
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3261009727
Short name T1032
Test name
Test status
Simulation time 271031355 ps
CPU time 4.3 seconds
Started Jun 29 04:39:35 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 213832 kb
Host smart-17fcf2ff-43bf-418e-85e2-382d895bedaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261009727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3261009727
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1317229821
Short name T989
Test name
Test status
Simulation time 967639999 ps
CPU time 9.76 seconds
Started Jun 29 04:39:29 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 213928 kb
Host smart-3b0fcdb0-1b60-4ad5-9e82-a939644d55d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317229821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1317229821
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3315993507
Short name T1015
Test name
Test status
Simulation time 98158591 ps
CPU time 3.13 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:35 PM PDT 24
Peak memory 213656 kb
Host smart-28c0921b-6dc3-4490-bed1-c04f8157af11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315993507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3315993507
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3945553952
Short name T1044
Test name
Test status
Simulation time 200674622 ps
CPU time 4.43 seconds
Started Jun 29 04:39:32 PM PDT 24
Finished Jun 29 04:39:37 PM PDT 24
Peak memory 213696 kb
Host smart-34fc18bf-734e-4c42-b790-70012c82d4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945553952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3945553952
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.672312816
Short name T937
Test name
Test status
Simulation time 36620550 ps
CPU time 2.89 seconds
Started Jun 29 04:39:29 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 213760 kb
Host smart-47e66282-d898-4496-a818-ebe2a4e8c143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672312816 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.672312816
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.517908920
Short name T943
Test name
Test status
Simulation time 23325653 ps
CPU time 1.43 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 205404 kb
Host smart-281004a2-f9d6-460b-b6bc-b4fde16ce3ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517908920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.517908920
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4292404184
Short name T1043
Test name
Test status
Simulation time 52138498 ps
CPU time 0.88 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:33 PM PDT 24
Peak memory 205392 kb
Host smart-ac9f5df5-b601-42a2-abe4-ac7002b9b204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292404184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4292404184
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.149029241
Short name T1008
Test name
Test status
Simulation time 507637602 ps
CPU time 2.6 seconds
Started Jun 29 04:39:32 PM PDT 24
Finished Jun 29 04:39:35 PM PDT 24
Peak memory 205320 kb
Host smart-2515f152-3cf6-41a6-b546-e0faf5d95931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149029241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.149029241
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1085703318
Short name T947
Test name
Test status
Simulation time 98512762 ps
CPU time 2.06 seconds
Started Jun 29 04:39:31 PM PDT 24
Finished Jun 29 04:39:34 PM PDT 24
Peak memory 213956 kb
Host smart-dbbebf09-9f83-4cd8-b70f-509ec032e53a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085703318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1085703318
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2959408362
Short name T1019
Test name
Test status
Simulation time 537559843 ps
CPU time 9.93 seconds
Started Jun 29 04:39:29 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 220932 kb
Host smart-9f5d640d-3608-423f-a65f-be20f6ea79aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959408362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2959408362
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2422923517
Short name T933
Test name
Test status
Simulation time 255363208 ps
CPU time 2.51 seconds
Started Jun 29 04:39:33 PM PDT 24
Finished Jun 29 04:39:36 PM PDT 24
Peak memory 214172 kb
Host smart-c9a8ef36-5751-4cf4-b2de-40fb05f9b8af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422923517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2422923517
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.262066759
Short name T178
Test name
Test status
Simulation time 925859681 ps
CPU time 5.06 seconds
Started Jun 29 04:39:34 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 213588 kb
Host smart-f94992da-02e5-4cea-b3b6-6584da21a3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262066759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.262066759
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1113531178
Short name T983
Test name
Test status
Simulation time 68031415 ps
CPU time 4.32 seconds
Started Jun 29 04:38:47 PM PDT 24
Finished Jun 29 04:38:52 PM PDT 24
Peak memory 205512 kb
Host smart-b5d1fa03-1aa5-41c9-a051-86083e3c3f0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113531178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
113531178
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3952073742
Short name T1076
Test name
Test status
Simulation time 253980812 ps
CPU time 11.77 seconds
Started Jun 29 04:38:47 PM PDT 24
Finished Jun 29 04:38:59 PM PDT 24
Peak memory 205328 kb
Host smart-a5d092a6-7227-4b2c-8b64-c0ea7c9f5bf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952073742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
952073742
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.453964953
Short name T957
Test name
Test status
Simulation time 58650090 ps
CPU time 1.19 seconds
Started Jun 29 04:38:47 PM PDT 24
Finished Jun 29 04:38:48 PM PDT 24
Peak memory 213692 kb
Host smart-cbbb3642-65ed-4d1c-9092-6c81b39ac019
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453964953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.453964953
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.500338089
Short name T998
Test name
Test status
Simulation time 96868108 ps
CPU time 1.76 seconds
Started Jun 29 04:38:47 PM PDT 24
Finished Jun 29 04:38:49 PM PDT 24
Peak memory 213636 kb
Host smart-9468b6f0-afde-4d9d-971c-56f1df747a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500338089 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.500338089
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1934874349
Short name T415
Test name
Test status
Simulation time 24822434 ps
CPU time 1.44 seconds
Started Jun 29 04:38:47 PM PDT 24
Finished Jun 29 04:38:49 PM PDT 24
Peak memory 205316 kb
Host smart-4721af2f-10c9-4cdf-8381-8f0d7d1b53af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934874349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1934874349
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1193678431
Short name T1042
Test name
Test status
Simulation time 12777671 ps
CPU time 0.77 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:38:49 PM PDT 24
Peak memory 205252 kb
Host smart-1616a889-2136-45dc-9048-91469c867fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193678431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1193678431
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.305146745
Short name T942
Test name
Test status
Simulation time 96003371 ps
CPU time 1.79 seconds
Started Jun 29 04:38:51 PM PDT 24
Finished Jun 29 04:38:53 PM PDT 24
Peak memory 205488 kb
Host smart-ea6e123f-274a-441d-8dc8-9246686a9e94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305146745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.305146745
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2640817691
Short name T1061
Test name
Test status
Simulation time 180714780 ps
CPU time 2.71 seconds
Started Jun 29 04:38:39 PM PDT 24
Finished Jun 29 04:38:42 PM PDT 24
Peak memory 213904 kb
Host smart-cfc428c9-9988-484b-bd4c-78262193b251
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640817691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2640817691
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2152134083
Short name T955
Test name
Test status
Simulation time 3657546475 ps
CPU time 10.77 seconds
Started Jun 29 04:38:50 PM PDT 24
Finished Jun 29 04:39:01 PM PDT 24
Peak memory 214160 kb
Host smart-36b0ca89-db26-47aa-8f9e-9463d9e9ff79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152134083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2152134083
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3001302274
Short name T1028
Test name
Test status
Simulation time 62775114 ps
CPU time 1.69 seconds
Started Jun 29 04:38:49 PM PDT 24
Finished Jun 29 04:38:51 PM PDT 24
Peak memory 213800 kb
Host smart-07b56d99-f362-441e-8ae9-b3fcb82ff133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001302274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3001302274
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3763606962
Short name T156
Test name
Test status
Simulation time 541817543 ps
CPU time 6.08 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:38:55 PM PDT 24
Peak memory 213696 kb
Host smart-2585bc45-4f38-40e9-9abd-4d3dee25899d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763606962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3763606962
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1613583289
Short name T948
Test name
Test status
Simulation time 175826052 ps
CPU time 0.83 seconds
Started Jun 29 04:39:34 PM PDT 24
Finished Jun 29 04:39:35 PM PDT 24
Peak memory 205284 kb
Host smart-c8e1907e-3277-417b-a1e7-b1dad6b4cdf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613583289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1613583289
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1621976420
Short name T1060
Test name
Test status
Simulation time 15649698 ps
CPU time 0.76 seconds
Started Jun 29 04:39:30 PM PDT 24
Finished Jun 29 04:39:31 PM PDT 24
Peak memory 205272 kb
Host smart-b5e17258-fd9e-46c8-a2ca-b85249211c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621976420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1621976420
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.643390766
Short name T972
Test name
Test status
Simulation time 10445413 ps
CPU time 0.72 seconds
Started Jun 29 04:39:34 PM PDT 24
Finished Jun 29 04:39:35 PM PDT 24
Peak memory 205284 kb
Host smart-dba7afa9-768c-4d12-9212-14c7ca452673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643390766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.643390766
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2841410564
Short name T951
Test name
Test status
Simulation time 32194114 ps
CPU time 0.68 seconds
Started Jun 29 04:39:29 PM PDT 24
Finished Jun 29 04:39:30 PM PDT 24
Peak memory 205348 kb
Host smart-c87f19be-f754-4837-8378-b074f77cc475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841410564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2841410564
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3760617108
Short name T1013
Test name
Test status
Simulation time 31633795 ps
CPU time 0.81 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205276 kb
Host smart-bca9230e-4c67-4154-90c2-af7406f2248e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760617108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3760617108
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1344241441
Short name T990
Test name
Test status
Simulation time 26007091 ps
CPU time 0.78 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 205304 kb
Host smart-a1c7ec71-4501-40ea-8471-31b49052f78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344241441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1344241441
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.818849385
Short name T924
Test name
Test status
Simulation time 41413833 ps
CPU time 0.79 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 205312 kb
Host smart-2dc9552c-8fa4-4f74-be9f-eee37edb2b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818849385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.818849385
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.225729765
Short name T973
Test name
Test status
Simulation time 27314180 ps
CPU time 0.72 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:38 PM PDT 24
Peak memory 205276 kb
Host smart-8ff4593e-32ea-404b-a1c3-a97f45780a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225729765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.225729765
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2755058798
Short name T996
Test name
Test status
Simulation time 15989473 ps
CPU time 0.93 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205344 kb
Host smart-84405e96-bb3d-4b3a-ab96-2787ca548338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755058798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2755058798
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3192254093
Short name T1073
Test name
Test status
Simulation time 51821809 ps
CPU time 0.7 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205308 kb
Host smart-84be3ec0-a17c-4b33-874b-a346a8bf5b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192254093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3192254093
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3677803395
Short name T1053
Test name
Test status
Simulation time 1564799472 ps
CPU time 14.33 seconds
Started Jun 29 04:38:49 PM PDT 24
Finished Jun 29 04:39:04 PM PDT 24
Peak memory 205284 kb
Host smart-e37dc5ce-0854-4fd6-82a6-fbc28b1013a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677803395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
677803395
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2164403232
Short name T1072
Test name
Test status
Simulation time 606001015 ps
CPU time 6.12 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:38:54 PM PDT 24
Peak memory 205296 kb
Host smart-b68219a4-a96f-4137-ab73-d9aec68304ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164403232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
164403232
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3373568199
Short name T1065
Test name
Test status
Simulation time 23456536 ps
CPU time 0.93 seconds
Started Jun 29 04:38:49 PM PDT 24
Finished Jun 29 04:38:50 PM PDT 24
Peak memory 205428 kb
Host smart-cb33a67f-e01e-4b9b-bc56-97f6f600b46b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373568199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
373568199
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2676894855
Short name T1036
Test name
Test status
Simulation time 54551200 ps
CPU time 1.82 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:38:50 PM PDT 24
Peak memory 217756 kb
Host smart-9fb44b5d-7205-467d-8cba-5ac23291e94d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676894855 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2676894855
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2891252612
Short name T970
Test name
Test status
Simulation time 16206069 ps
CPU time 1.08 seconds
Started Jun 29 04:38:47 PM PDT 24
Finished Jun 29 04:38:48 PM PDT 24
Peak memory 205372 kb
Host smart-6fa7af8b-91c6-431c-bc5c-5e6282f56149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891252612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2891252612
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3797930175
Short name T934
Test name
Test status
Simulation time 16371635 ps
CPU time 0.75 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:38:49 PM PDT 24
Peak memory 205380 kb
Host smart-7015e6cc-01a5-49ae-bf99-cdadfcdf207c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797930175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3797930175
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1792981662
Short name T1018
Test name
Test status
Simulation time 344233522 ps
CPU time 2.03 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:38:51 PM PDT 24
Peak memory 205544 kb
Host smart-4a857a5c-ee00-471f-803c-76c8c80a8349
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792981662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1792981662
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2417955234
Short name T122
Test name
Test status
Simulation time 51902386 ps
CPU time 2.14 seconds
Started Jun 29 04:38:49 PM PDT 24
Finished Jun 29 04:38:51 PM PDT 24
Peak memory 213800 kb
Host smart-05e5d176-43db-475f-8763-06a089076fce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417955234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2417955234
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1973487407
Short name T976
Test name
Test status
Simulation time 376487591 ps
CPU time 7.03 seconds
Started Jun 29 04:38:51 PM PDT 24
Finished Jun 29 04:38:59 PM PDT 24
Peak memory 214052 kb
Host smart-26ec70c6-9719-4c64-b629-5705165d08cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973487407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1973487407
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.805382800
Short name T1038
Test name
Test status
Simulation time 1700879030 ps
CPU time 3.96 seconds
Started Jun 29 04:38:51 PM PDT 24
Finished Jun 29 04:38:55 PM PDT 24
Peak memory 213632 kb
Host smart-1fff3abe-7a08-44aa-bf2e-ea3a8c0ff7c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805382800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.805382800
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1691452677
Short name T170
Test name
Test status
Simulation time 592332641 ps
CPU time 11.32 seconds
Started Jun 29 04:38:48 PM PDT 24
Finished Jun 29 04:39:00 PM PDT 24
Peak memory 213560 kb
Host smart-40f520a1-e8fe-40bd-b1ae-7dd72fdb04b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691452677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1691452677
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2763127033
Short name T959
Test name
Test status
Simulation time 11489139 ps
CPU time 0.68 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:38 PM PDT 24
Peak memory 205204 kb
Host smart-35eafad0-5238-4c12-b2bf-a4b8992c74c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763127033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2763127033
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2660520664
Short name T997
Test name
Test status
Simulation time 18032843 ps
CPU time 0.86 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 205328 kb
Host smart-e2df6086-bfe6-4f85-a0b2-8ac0684c5172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660520664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2660520664
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3956208059
Short name T920
Test name
Test status
Simulation time 19305375 ps
CPU time 0.83 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:39:50 PM PDT 24
Peak memory 205376 kb
Host smart-29005f82-b638-4d39-b12b-95a024cad5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956208059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3956208059
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3127950340
Short name T1082
Test name
Test status
Simulation time 33356123 ps
CPU time 0.87 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:38 PM PDT 24
Peak memory 205344 kb
Host smart-cc5c02a4-4aa5-4c2b-bc05-18a863ac233c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127950340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3127950340
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2984111382
Short name T949
Test name
Test status
Simulation time 17277322 ps
CPU time 0.75 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205196 kb
Host smart-4f34ca63-29e2-4518-89f3-f7e91bd6bdfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984111382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2984111382
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.339494310
Short name T1000
Test name
Test status
Simulation time 36644585 ps
CPU time 0.68 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205208 kb
Host smart-d11d82a0-e231-4bf0-9f52-01eb1cd88994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339494310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.339494310
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2921003244
Short name T987
Test name
Test status
Simulation time 51264331 ps
CPU time 0.77 seconds
Started Jun 29 04:39:41 PM PDT 24
Finished Jun 29 04:39:43 PM PDT 24
Peak memory 205360 kb
Host smart-e30c9c40-7f99-442a-87a9-2fd720f207ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921003244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2921003244
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.522677275
Short name T1079
Test name
Test status
Simulation time 15621602 ps
CPU time 0.77 seconds
Started Jun 29 04:39:39 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 205256 kb
Host smart-15c51a8e-8729-4b18-a515-77581bf4ef74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522677275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.522677275
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.425575303
Short name T1059
Test name
Test status
Simulation time 46459496 ps
CPU time 0.75 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:38 PM PDT 24
Peak memory 205276 kb
Host smart-ec58e2ef-2037-44db-a132-25ffe8e3e9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425575303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.425575303
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3462259473
Short name T1001
Test name
Test status
Simulation time 8191848 ps
CPU time 0.82 seconds
Started Jun 29 04:39:41 PM PDT 24
Finished Jun 29 04:39:43 PM PDT 24
Peak memory 205360 kb
Host smart-4e5f1d3e-74e4-490b-aaa4-9a470554142f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462259473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3462259473
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3364348348
Short name T950
Test name
Test status
Simulation time 69506457 ps
CPU time 5.04 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:39:02 PM PDT 24
Peak memory 205552 kb
Host smart-ceff5015-52ca-489f-96ee-f761d7750bf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364348348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
364348348
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2081052453
Short name T1039
Test name
Test status
Simulation time 3553970921 ps
CPU time 25.05 seconds
Started Jun 29 04:38:55 PM PDT 24
Finished Jun 29 04:39:21 PM PDT 24
Peak memory 205460 kb
Host smart-10c09598-89e5-4545-b87c-71b017351ab8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081052453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
081052453
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.317658812
Short name T935
Test name
Test status
Simulation time 16367866 ps
CPU time 1.1 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:38:59 PM PDT 24
Peak memory 205480 kb
Host smart-5bd82848-0790-42e1-8df4-a3ca01b60213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317658812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.317658812
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3874155567
Short name T930
Test name
Test status
Simulation time 98134052 ps
CPU time 1.08 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:38:58 PM PDT 24
Peak memory 205312 kb
Host smart-952214af-7e21-4dd0-b755-8ca29bb68563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874155567 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3874155567
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3693023471
Short name T144
Test name
Test status
Simulation time 24802814 ps
CPU time 0.9 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:38:58 PM PDT 24
Peak memory 205392 kb
Host smart-67790c31-bd97-442b-9fbf-185489138bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693023471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3693023471
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3068061694
Short name T922
Test name
Test status
Simulation time 10286092 ps
CPU time 0.82 seconds
Started Jun 29 04:38:56 PM PDT 24
Finished Jun 29 04:38:57 PM PDT 24
Peak memory 205388 kb
Host smart-ae5fec93-1f7a-4d14-8298-03f5cc1e59da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068061694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3068061694
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1932091594
Short name T1007
Test name
Test status
Simulation time 45966204 ps
CPU time 2.29 seconds
Started Jun 29 04:38:56 PM PDT 24
Finished Jun 29 04:38:58 PM PDT 24
Peak memory 205468 kb
Host smart-8d8d44e3-b16b-4ed8-a003-f80d2f5715dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932091594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1932091594
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2046831647
Short name T1083
Test name
Test status
Simulation time 1072981769 ps
CPU time 3.5 seconds
Started Jun 29 04:38:49 PM PDT 24
Finished Jun 29 04:38:53 PM PDT 24
Peak memory 214004 kb
Host smart-eb2ff617-5863-49c7-84bb-9276ab8b5ae3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046831647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2046831647
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.167845463
Short name T1078
Test name
Test status
Simulation time 83995235 ps
CPU time 3.75 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:39:01 PM PDT 24
Peak memory 213884 kb
Host smart-10bbc571-2e65-4249-ae0e-e0f13b412333
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167845463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.167845463
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3061971405
Short name T187
Test name
Test status
Simulation time 56193907 ps
CPU time 1.86 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:38:59 PM PDT 24
Peak memory 221884 kb
Host smart-c4dd5f4e-eb74-421b-8859-60cc5b8ddb10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061971405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3061971405
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.733681931
Short name T1011
Test name
Test status
Simulation time 34377453 ps
CPU time 0.79 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:39:51 PM PDT 24
Peak memory 205308 kb
Host smart-26ce77e6-9a76-4d9b-8b07-58aa7af82894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733681931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.733681931
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1878155019
Short name T932
Test name
Test status
Simulation time 112308908 ps
CPU time 0.86 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:39:50 PM PDT 24
Peak memory 205376 kb
Host smart-9ce922c3-90cd-4dd2-9e71-4ea3c8c443a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878155019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1878155019
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.190823255
Short name T936
Test name
Test status
Simulation time 25636012 ps
CPU time 0.75 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 205284 kb
Host smart-9d25bb0f-8d49-46fa-9b16-faf8fa63b600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190823255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.190823255
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1440181562
Short name T975
Test name
Test status
Simulation time 11540363 ps
CPU time 0.69 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:39:51 PM PDT 24
Peak memory 205380 kb
Host smart-0df9a75c-19dd-4d3a-8e92-29f83dfc5f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440181562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1440181562
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4156660283
Short name T1020
Test name
Test status
Simulation time 29744181 ps
CPU time 0.77 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205192 kb
Host smart-c4e7f529-7e64-44ff-abdb-a518a54d17f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156660283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4156660283
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1495323158
Short name T1069
Test name
Test status
Simulation time 40608537 ps
CPU time 0.77 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:39 PM PDT 24
Peak memory 205196 kb
Host smart-8aeff712-b25d-440d-ab05-3c32ebf6e1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495323158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1495323158
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1012314552
Short name T1047
Test name
Test status
Simulation time 35626931 ps
CPU time 0.82 seconds
Started Jun 29 04:39:36 PM PDT 24
Finished Jun 29 04:39:38 PM PDT 24
Peak memory 205168 kb
Host smart-f1fb1af9-8c8f-4fee-a7b4-b49c38108a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012314552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1012314552
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1190655788
Short name T1067
Test name
Test status
Simulation time 9313223 ps
CPU time 0.72 seconds
Started Jun 29 04:39:37 PM PDT 24
Finished Jun 29 04:39:38 PM PDT 24
Peak memory 205308 kb
Host smart-420dae4d-a679-4d0d-8d0d-cf40234c047c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190655788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1190655788
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1822281889
Short name T986
Test name
Test status
Simulation time 11300953 ps
CPU time 0.71 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:40 PM PDT 24
Peak memory 205192 kb
Host smart-e5873022-3631-41fa-8efc-00edb04d0383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822281889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1822281889
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3612690378
Short name T921
Test name
Test status
Simulation time 18801626 ps
CPU time 0.82 seconds
Started Jun 29 04:39:41 PM PDT 24
Finished Jun 29 04:39:42 PM PDT 24
Peak memory 205280 kb
Host smart-bcbd3f66-5105-40dc-8aa1-bd3fbaca04c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612690378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3612690378
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2011505256
Short name T1029
Test name
Test status
Simulation time 42426139 ps
CPU time 1.57 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 213660 kb
Host smart-32dda902-6066-4a37-9299-4a9233898e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011505256 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2011505256
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1549557642
Short name T1080
Test name
Test status
Simulation time 20350409 ps
CPU time 0.9 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:08 PM PDT 24
Peak memory 205324 kb
Host smart-22fdff69-142d-4bcb-a454-0c60462258c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549557642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1549557642
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.753180006
Short name T966
Test name
Test status
Simulation time 45509256 ps
CPU time 0.84 seconds
Started Jun 29 04:38:55 PM PDT 24
Finished Jun 29 04:38:56 PM PDT 24
Peak memory 205280 kb
Host smart-29edd64a-8f25-4008-9c31-76e63bcc3f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753180006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.753180006
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3296402738
Short name T142
Test name
Test status
Simulation time 350779273 ps
CPU time 1.99 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 205412 kb
Host smart-bec8edb7-c2d6-422d-ad20-c07e49469d13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296402738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3296402738
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1633529215
Short name T1049
Test name
Test status
Simulation time 69909475 ps
CPU time 1.43 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:38:59 PM PDT 24
Peak memory 213976 kb
Host smart-a04a0ae6-eba9-4314-8b9d-c99cee9fa9e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633529215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1633529215
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2937797283
Short name T1050
Test name
Test status
Simulation time 184074155 ps
CPU time 4.1 seconds
Started Jun 29 04:38:55 PM PDT 24
Finished Jun 29 04:38:59 PM PDT 24
Peak memory 213812 kb
Host smart-13bb5024-9166-41ef-922d-462930273130
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937797283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2937797283
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1569922460
Short name T184
Test name
Test status
Simulation time 174964938 ps
CPU time 5.57 seconds
Started Jun 29 04:38:58 PM PDT 24
Finished Jun 29 04:39:04 PM PDT 24
Peak memory 213712 kb
Host smart-89c31478-1938-42c8-a051-8d45b4d38e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569922460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1569922460
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.820277607
Short name T173
Test name
Test status
Simulation time 98620079 ps
CPU time 5.56 seconds
Started Jun 29 04:38:57 PM PDT 24
Finished Jun 29 04:39:03 PM PDT 24
Peak memory 213588 kb
Host smart-2a2b6a57-aa3d-4c23-9457-2c6e9dbb5c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820277607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
820277607
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.921680998
Short name T939
Test name
Test status
Simulation time 695407160 ps
CPU time 1.91 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:10 PM PDT 24
Peak memory 213764 kb
Host smart-a195af03-e240-4f19-8d36-28097c7a6e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921680998 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.921680998
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1451937491
Short name T1040
Test name
Test status
Simulation time 19740411 ps
CPU time 1.07 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 205328 kb
Host smart-83c272a9-0ea3-4746-9418-d6066c883871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451937491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1451937491
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3274818251
Short name T994
Test name
Test status
Simulation time 61121765 ps
CPU time 0.83 seconds
Started Jun 29 04:39:05 PM PDT 24
Finished Jun 29 04:39:07 PM PDT 24
Peak memory 205284 kb
Host smart-303aaf25-296c-40e2-bc8d-ebf9730761cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274818251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3274818251
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2879829906
Short name T991
Test name
Test status
Simulation time 48462888 ps
CPU time 2.23 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:10 PM PDT 24
Peak memory 205472 kb
Host smart-65f5dda3-b932-409f-b03b-8bfaa0bdb828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879829906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2879829906
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3722698081
Short name T1016
Test name
Test status
Simulation time 165564087 ps
CPU time 2.1 seconds
Started Jun 29 04:39:08 PM PDT 24
Finished Jun 29 04:39:10 PM PDT 24
Peak memory 214032 kb
Host smart-2c7c059f-8565-47d1-9876-fc7355f543d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722698081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3722698081
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.411837733
Short name T978
Test name
Test status
Simulation time 639648111 ps
CPU time 6.76 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:13 PM PDT 24
Peak memory 214060 kb
Host smart-7b8f76c8-763e-4764-b3ac-471722a21590
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411837733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.411837733
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1952707377
Short name T928
Test name
Test status
Simulation time 177275385 ps
CPU time 3.89 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:11 PM PDT 24
Peak memory 213628 kb
Host smart-ba9fbc5f-c1f1-4d66-9703-b4b264f30bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952707377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1952707377
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2158100801
Short name T1025
Test name
Test status
Simulation time 73719753 ps
CPU time 2.25 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 213680 kb
Host smart-f2395ec9-e3a2-4722-afb5-e9b9af2cfe90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158100801 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2158100801
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.139259105
Short name T981
Test name
Test status
Simulation time 25633470 ps
CPU time 1.12 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:07 PM PDT 24
Peak memory 205488 kb
Host smart-73a2681e-8ac5-4650-ab2c-dff519546c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139259105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.139259105
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2016439344
Short name T984
Test name
Test status
Simulation time 13922584 ps
CPU time 0.91 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 205444 kb
Host smart-67c7b944-6720-4839-a0df-d32b5b644e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016439344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2016439344
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.23684708
Short name T945
Test name
Test status
Simulation time 85746362 ps
CPU time 1.59 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:08 PM PDT 24
Peak memory 205472 kb
Host smart-4a06db42-6260-41b8-8b97-e9bb07395c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same
_csr_outstanding.23684708
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3547403708
Short name T1034
Test name
Test status
Simulation time 97963677 ps
CPU time 3.08 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:11 PM PDT 24
Peak memory 213908 kb
Host smart-ddf61355-64ff-465c-9842-d0cbba1e9bd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547403708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3547403708
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3083605916
Short name T116
Test name
Test status
Simulation time 82400167 ps
CPU time 3.39 seconds
Started Jun 29 04:39:05 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 219912 kb
Host smart-d93dd77d-8ac4-4c82-bb34-da9c6f995b23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083605916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3083605916
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1378920087
Short name T1062
Test name
Test status
Simulation time 149672619 ps
CPU time 5.2 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:13 PM PDT 24
Peak memory 216840 kb
Host smart-32bf3233-5d0b-4e30-87cc-bfb8ceca72fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378920087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1378920087
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2306196317
Short name T167
Test name
Test status
Simulation time 152421351 ps
CPU time 4.02 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:10 PM PDT 24
Peak memory 213696 kb
Host smart-9404d536-2b50-4b52-8a87-b6da8bc2398b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306196317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2306196317
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3284489175
Short name T988
Test name
Test status
Simulation time 83946808 ps
CPU time 1.73 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:09 PM PDT 24
Peak memory 213800 kb
Host smart-13cf0a5b-3dcb-4591-aead-d2575187818d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284489175 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3284489175
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2918791213
Short name T969
Test name
Test status
Simulation time 44712138 ps
CPU time 1.25 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:08 PM PDT 24
Peak memory 205456 kb
Host smart-ccd67450-d2bb-42e2-9a2d-b4e69ef363de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918791213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2918791213
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1785635549
Short name T1026
Test name
Test status
Simulation time 27756185 ps
CPU time 0.84 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:07 PM PDT 24
Peak memory 205252 kb
Host smart-9a3d8b82-094f-46b2-b2b0-754d727dfb7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785635549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1785635549
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2860028619
Short name T952
Test name
Test status
Simulation time 231985344 ps
CPU time 2.57 seconds
Started Jun 29 04:39:08 PM PDT 24
Finished Jun 29 04:39:11 PM PDT 24
Peak memory 213696 kb
Host smart-7a936cef-6c65-4010-b134-5e0defbcda4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860028619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2860028619
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3725372374
Short name T992
Test name
Test status
Simulation time 84591617 ps
CPU time 1.96 seconds
Started Jun 29 04:39:05 PM PDT 24
Finished Jun 29 04:39:07 PM PDT 24
Peak memory 213932 kb
Host smart-057d6f7e-6d13-476e-97b4-51b55437c155
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725372374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3725372374
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2921367723
Short name T944
Test name
Test status
Simulation time 361055976 ps
CPU time 4.91 seconds
Started Jun 29 04:39:06 PM PDT 24
Finished Jun 29 04:39:12 PM PDT 24
Peak memory 214008 kb
Host smart-deeb2b8d-b154-455b-b2f8-70d1ae491334
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921367723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2921367723
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4217545168
Short name T953
Test name
Test status
Simulation time 92079390 ps
CPU time 3.37 seconds
Started Jun 29 04:39:08 PM PDT 24
Finished Jun 29 04:39:12 PM PDT 24
Peak memory 213716 kb
Host smart-03e39dc9-783b-4448-aec2-b30af9c868e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217545168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4217545168
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4093386648
Short name T408
Test name
Test status
Simulation time 680423432 ps
CPU time 5.17 seconds
Started Jun 29 04:39:07 PM PDT 24
Finished Jun 29 04:39:13 PM PDT 24
Peak memory 215080 kb
Host smart-0c0e17dd-c11c-4787-98f2-2ce249dc3d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093386648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4093386648
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1886881867
Short name T941
Test name
Test status
Simulation time 88204551 ps
CPU time 1.21 seconds
Started Jun 29 04:39:12 PM PDT 24
Finished Jun 29 04:39:14 PM PDT 24
Peak memory 205428 kb
Host smart-68ff1a05-4a55-4a8c-b594-ba9637233b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886881867 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1886881867
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3155157878
Short name T1051
Test name
Test status
Simulation time 18229923 ps
CPU time 0.89 seconds
Started Jun 29 04:39:14 PM PDT 24
Finished Jun 29 04:39:15 PM PDT 24
Peak memory 205292 kb
Host smart-495f5189-1293-45cd-a4f6-97f461fd76d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155157878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3155157878
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1677164017
Short name T1070
Test name
Test status
Simulation time 22672871 ps
CPU time 0.71 seconds
Started Jun 29 04:39:15 PM PDT 24
Finished Jun 29 04:39:16 PM PDT 24
Peak memory 205296 kb
Host smart-5270b791-a69f-4f31-9ebd-1ed8c67beee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677164017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1677164017
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1570446018
Short name T139
Test name
Test status
Simulation time 83801813 ps
CPU time 1.71 seconds
Started Jun 29 04:39:12 PM PDT 24
Finished Jun 29 04:39:14 PM PDT 24
Peak memory 205472 kb
Host smart-c6e21720-0b1b-495a-9e1c-ffafb8fb0f9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570446018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1570446018
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2170636607
Short name T1045
Test name
Test status
Simulation time 308084405 ps
CPU time 1.55 seconds
Started Jun 29 04:39:12 PM PDT 24
Finished Jun 29 04:39:14 PM PDT 24
Peak memory 213884 kb
Host smart-60748d4f-8151-47f8-8179-3e0e5d37581b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170636607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2170636607
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2952212385
Short name T121
Test name
Test status
Simulation time 388870220 ps
CPU time 9.63 seconds
Started Jun 29 04:39:16 PM PDT 24
Finished Jun 29 04:39:27 PM PDT 24
Peak memory 213628 kb
Host smart-e8e59ce5-8c1f-4745-a6dc-5494fd00af35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952212385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2952212385
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1786157465
Short name T185
Test name
Test status
Simulation time 151840327 ps
CPU time 3.39 seconds
Started Jun 29 04:39:14 PM PDT 24
Finished Jun 29 04:39:18 PM PDT 24
Peak memory 221840 kb
Host smart-f0f482d2-1a37-4e59-8c9c-100054ff7f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786157465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1786157465
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1476540249
Short name T406
Test name
Test status
Simulation time 248091845 ps
CPU time 3.62 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 209476 kb
Host smart-b6237bcc-d4a6-4d41-a7e2-e3b8baee34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476540249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1476540249
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3215447973
Short name T273
Test name
Test status
Simulation time 1155821441 ps
CPU time 5.27 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:25 PM PDT 24
Peak memory 222428 kb
Host smart-e9ed7f97-c9b7-4934-8756-c4092d6d1414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215447973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3215447973
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.84074570
Short name T60
Test name
Test status
Simulation time 1340582924 ps
CPU time 9.76 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:29 PM PDT 24
Peak memory 209512 kb
Host smart-9fe298f2-431e-4fd7-9ccd-d0f21cb5eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84074570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.84074570
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4203625173
Short name T11
Test name
Test status
Simulation time 1424698428 ps
CPU time 9.42 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:29 PM PDT 24
Peak memory 233316 kb
Host smart-c99d805e-896b-4b7e-9c92-ac9f9c64b741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203625173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4203625173
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2295689972
Short name T370
Test name
Test status
Simulation time 107048137 ps
CPU time 2.98 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 208536 kb
Host smart-52eb5207-55ee-4451-a311-f13b7625b006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295689972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2295689972
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1877403587
Short name T471
Test name
Test status
Simulation time 47991031 ps
CPU time 2.73 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:22 PM PDT 24
Peak memory 207392 kb
Host smart-5e475e3a-da81-4fc8-abd6-8ff0d6b3e1ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877403587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1877403587
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2771305053
Short name T498
Test name
Test status
Simulation time 211901285 ps
CPU time 5.75 seconds
Started Jun 29 04:41:21 PM PDT 24
Finished Jun 29 04:41:27 PM PDT 24
Peak memory 208512 kb
Host smart-9eba2c79-5df5-41a0-abee-2e40a3e8e8b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771305053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2771305053
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1322071337
Short name T506
Test name
Test status
Simulation time 349071401 ps
CPU time 5.68 seconds
Started Jun 29 04:41:20 PM PDT 24
Finished Jun 29 04:41:26 PM PDT 24
Peak memory 208004 kb
Host smart-80cc9a9f-7c31-464b-900b-06f8c4214460
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322071337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1322071337
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.993161932
Short name T698
Test name
Test status
Simulation time 91127708 ps
CPU time 3.21 seconds
Started Jun 29 04:41:17 PM PDT 24
Finished Jun 29 04:41:21 PM PDT 24
Peak memory 208308 kb
Host smart-207382a9-3703-4c22-99ed-34f0d5852f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993161932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.993161932
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3845309412
Short name T475
Test name
Test status
Simulation time 53956640 ps
CPU time 2.47 seconds
Started Jun 29 04:41:18 PM PDT 24
Finished Jun 29 04:41:21 PM PDT 24
Peak memory 208388 kb
Host smart-80579b82-35d5-4654-b72b-5a01ebdc4419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845309412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3845309412
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3228757476
Short name T193
Test name
Test status
Simulation time 666714722 ps
CPU time 24.99 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:45 PM PDT 24
Peak memory 221036 kb
Host smart-11a913ba-f8dc-4cb6-b927-c4b7ee890ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228757476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3228757476
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2264517668
Short name T829
Test name
Test status
Simulation time 1553459341 ps
CPU time 16.72 seconds
Started Jun 29 04:41:20 PM PDT 24
Finished Jun 29 04:41:37 PM PDT 24
Peak memory 222764 kb
Host smart-ffdadede-f3ce-4abe-9bad-82c16dfb813d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264517668 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2264517668
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.4194757340
Short name T88
Test name
Test status
Simulation time 44421653 ps
CPU time 2.89 seconds
Started Jun 29 04:41:20 PM PDT 24
Finished Jun 29 04:41:24 PM PDT 24
Peak memory 210236 kb
Host smart-dc098885-e0cc-4d98-be06-b0c21582f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194757340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4194757340
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4133500214
Short name T132
Test name
Test status
Simulation time 52082039 ps
CPU time 2.45 seconds
Started Jun 29 04:41:17 PM PDT 24
Finished Jun 29 04:41:20 PM PDT 24
Peak memory 209788 kb
Host smart-c80faf4f-9e09-43f8-a95e-c12707069529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133500214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4133500214
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1005281128
Short name T750
Test name
Test status
Simulation time 9035057 ps
CPU time 0.7 seconds
Started Jun 29 04:41:28 PM PDT 24
Finished Jun 29 04:41:29 PM PDT 24
Peak memory 205920 kb
Host smart-7cb9b644-ed54-42b3-a574-4316329fc92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005281128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1005281128
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3487838822
Short name T91
Test name
Test status
Simulation time 93317372 ps
CPU time 2.01 seconds
Started Jun 29 04:41:29 PM PDT 24
Finished Jun 29 04:41:31 PM PDT 24
Peak memory 214968 kb
Host smart-fc061412-2475-4410-ba61-a6631ec6504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487838822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3487838822
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2679826419
Short name T400
Test name
Test status
Simulation time 1110329186 ps
CPU time 3.37 seconds
Started Jun 29 04:41:27 PM PDT 24
Finished Jun 29 04:41:31 PM PDT 24
Peak memory 213640 kb
Host smart-593a40c9-723a-4f2f-9f56-e4f9218594a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679826419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2679826419
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.2807052722
Short name T239
Test name
Test status
Simulation time 639004401 ps
CPU time 3.37 seconds
Started Jun 29 04:41:26 PM PDT 24
Finished Jun 29 04:41:30 PM PDT 24
Peak memory 207904 kb
Host smart-c602af86-94fd-4c91-a1f4-f97955499a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807052722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2807052722
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3198865946
Short name T105
Test name
Test status
Simulation time 550491963 ps
CPU time 8.17 seconds
Started Jun 29 04:41:28 PM PDT 24
Finished Jun 29 04:41:37 PM PDT 24
Peak memory 231172 kb
Host smart-1baadcf7-f273-4b39-a397-0075dd4652af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198865946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3198865946
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3413827932
Short name T907
Test name
Test status
Simulation time 75342553 ps
CPU time 2.7 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:22 PM PDT 24
Peak memory 208716 kb
Host smart-534a6fef-7436-419c-904b-9224850fdd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413827932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3413827932
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2818223050
Short name T911
Test name
Test status
Simulation time 235860400 ps
CPU time 4.34 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:30 PM PDT 24
Peak memory 208732 kb
Host smart-a722587e-1db3-4d78-a94b-398ea825cf48
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818223050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2818223050
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.568837933
Short name T470
Test name
Test status
Simulation time 480525091 ps
CPU time 2.52 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 206776 kb
Host smart-253d9671-0bce-4bf3-8968-ed6778f98676
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568837933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.568837933
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2823628945
Short name T236
Test name
Test status
Simulation time 521000310 ps
CPU time 4.26 seconds
Started Jun 29 04:41:32 PM PDT 24
Finished Jun 29 04:41:37 PM PDT 24
Peak memory 215544 kb
Host smart-678ab69d-970f-4f3f-b4f8-31566f0849d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823628945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2823628945
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2157960691
Short name T551
Test name
Test status
Simulation time 459262928 ps
CPU time 3.08 seconds
Started Jun 29 04:41:20 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 206656 kb
Host smart-7762bcfc-577f-46a3-befd-c2b04afa4e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157960691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2157960691
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1688347170
Short name T217
Test name
Test status
Simulation time 284846245 ps
CPU time 15.24 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 222460 kb
Host smart-4b6c2871-81b4-4e57-a1a4-5ca562106fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688347170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1688347170
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3586037008
Short name T795
Test name
Test status
Simulation time 498993825 ps
CPU time 6.4 seconds
Started Jun 29 04:41:32 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 207940 kb
Host smart-cf75fd13-9931-4dde-aa62-1653bc1b4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586037008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3586037008
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2666056410
Short name T558
Test name
Test status
Simulation time 48639806 ps
CPU time 0.75 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:12 PM PDT 24
Peak memory 206072 kb
Host smart-3ea4c2b8-e460-4d5e-ae73-034ce1ebaa15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666056410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2666056410
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4291936042
Short name T796
Test name
Test status
Simulation time 148253135 ps
CPU time 2.95 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 215188 kb
Host smart-f88fbe2a-36f9-4dbe-97ae-f0fb33af235c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291936042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4291936042
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3940805706
Short name T22
Test name
Test status
Simulation time 553496505 ps
CPU time 3.99 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:15 PM PDT 24
Peak memory 209720 kb
Host smart-e712111c-5c44-4b85-992d-ff790841bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940805706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3940805706
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3904456778
Short name T331
Test name
Test status
Simulation time 65613203 ps
CPU time 2.84 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:13 PM PDT 24
Peak memory 209380 kb
Host smart-8ac1f386-37ab-4218-b9e3-f589b7aa59f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904456778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3904456778
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.126991267
Short name T719
Test name
Test status
Simulation time 95388511 ps
CPU time 4.84 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 208916 kb
Host smart-b73a3c40-6f0b-44c6-aa24-34d2cbfed7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126991267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.126991267
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1188004564
Short name T811
Test name
Test status
Simulation time 137800455 ps
CPU time 4.5 seconds
Started Jun 29 04:42:11 PM PDT 24
Finished Jun 29 04:42:16 PM PDT 24
Peak memory 214092 kb
Host smart-b9e80de5-c36c-4efc-aeb7-14c43a144ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188004564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1188004564
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3187206087
Short name T814
Test name
Test status
Simulation time 160515334 ps
CPU time 2.34 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:13 PM PDT 24
Peak memory 207220 kb
Host smart-11661998-c17e-4a2b-abc0-35b481639fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187206087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3187206087
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4189003091
Short name T377
Test name
Test status
Simulation time 3090186645 ps
CPU time 39.59 seconds
Started Jun 29 04:42:11 PM PDT 24
Finished Jun 29 04:42:51 PM PDT 24
Peak memory 208032 kb
Host smart-f1b17dc9-677b-44e7-a248-6d7bb0486334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189003091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4189003091
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2505390021
Short name T585
Test name
Test status
Simulation time 4000159057 ps
CPU time 27.22 seconds
Started Jun 29 04:42:09 PM PDT 24
Finished Jun 29 04:42:37 PM PDT 24
Peak memory 208320 kb
Host smart-7e4d6ed1-6876-4f6b-b010-7bab77717d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505390021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2505390021
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3576102355
Short name T428
Test name
Test status
Simulation time 35775486 ps
CPU time 2.41 seconds
Started Jun 29 04:42:12 PM PDT 24
Finished Jun 29 04:42:15 PM PDT 24
Peak memory 208624 kb
Host smart-58c8eb94-5f33-486d-bb27-141275270193
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576102355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3576102355
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1829155144
Short name T871
Test name
Test status
Simulation time 73750512 ps
CPU time 3.03 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 206980 kb
Host smart-ec61f634-c53f-4c80-a2a6-0cd03a0877bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829155144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1829155144
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3138495704
Short name T711
Test name
Test status
Simulation time 856322126 ps
CPU time 4.45 seconds
Started Jun 29 04:42:07 PM PDT 24
Finished Jun 29 04:42:11 PM PDT 24
Peak memory 208040 kb
Host smart-891f1651-1fc5-4f94-a1d0-990879918778
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138495704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3138495704
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3426165022
Short name T607
Test name
Test status
Simulation time 293238727 ps
CPU time 3.21 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:21 PM PDT 24
Peak memory 209352 kb
Host smart-a0485d70-5640-4877-9837-c9c654e60e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426165022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3426165022
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1138971529
Short name T524
Test name
Test status
Simulation time 213894509 ps
CPU time 2.53 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:11 PM PDT 24
Peak memory 208848 kb
Host smart-5f0f5ab1-a6e9-46c9-8f4f-75646dbc07ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138971529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1138971529
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1931198743
Short name T280
Test name
Test status
Simulation time 1138062722 ps
CPU time 8.87 seconds
Started Jun 29 04:42:09 PM PDT 24
Finished Jun 29 04:42:18 PM PDT 24
Peak memory 214316 kb
Host smart-5d08e440-c109-48af-8448-420f75693e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931198743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1931198743
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1463875507
Short name T735
Test name
Test status
Simulation time 1371018558 ps
CPU time 17.82 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:27 PM PDT 24
Peak memory 210856 kb
Host smart-c8b82e99-e87f-4f34-ad60-603aeaac710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463875507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1463875507
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1633472964
Short name T518
Test name
Test status
Simulation time 21562688 ps
CPU time 0.74 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:19 PM PDT 24
Peak memory 206052 kb
Host smart-35de31da-aba7-4ef2-bf3f-57a7c4fe8aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633472964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1633472964
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2124742931
Short name T788
Test name
Test status
Simulation time 37806899 ps
CPU time 2.97 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:23 PM PDT 24
Peak memory 215288 kb
Host smart-64344206-4972-4c96-9644-4cd7effa7668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2124742931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2124742931
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1459588937
Short name T268
Test name
Test status
Simulation time 115136819 ps
CPU time 3.47 seconds
Started Jun 29 04:42:21 PM PDT 24
Finished Jun 29 04:42:25 PM PDT 24
Peak memory 219596 kb
Host smart-ccee035c-24d2-4abb-875b-bfbc10164778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459588937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1459588937
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3627096664
Short name T661
Test name
Test status
Simulation time 32564464 ps
CPU time 2.19 seconds
Started Jun 29 04:42:13 PM PDT 24
Finished Jun 29 04:42:16 PM PDT 24
Peak memory 214388 kb
Host smart-378b1578-ca7c-4757-980b-be733bd2761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627096664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3627096664
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3933580308
Short name T7
Test name
Test status
Simulation time 98307442 ps
CPU time 3.6 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 220200 kb
Host smart-8d02bd89-222a-4144-bd93-25d88e7e8cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933580308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3933580308
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1145872394
Short name T703
Test name
Test status
Simulation time 602128254 ps
CPU time 3.98 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:23 PM PDT 24
Peak memory 214352 kb
Host smart-3166ec60-65fa-4ec0-a695-eb0d49acfc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145872394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1145872394
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3880742128
Short name T387
Test name
Test status
Simulation time 360381665 ps
CPU time 5.05 seconds
Started Jun 29 04:42:21 PM PDT 24
Finished Jun 29 04:42:26 PM PDT 24
Peak memory 208540 kb
Host smart-31bb0fd6-a4bd-4d3d-aaa1-2e3851e1b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880742128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3880742128
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4188418948
Short name T594
Test name
Test status
Simulation time 111474051 ps
CPU time 2.4 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:20 PM PDT 24
Peak memory 206972 kb
Host smart-19757d69-f722-4805-84ca-1d3322923678
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188418948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4188418948
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3754376332
Short name T208
Test name
Test status
Simulation time 609231598 ps
CPU time 12.76 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 208928 kb
Host smart-ac295380-78d5-451e-9c49-8847cf7e490c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754376332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3754376332
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1668197301
Short name T785
Test name
Test status
Simulation time 92583767 ps
CPU time 2.12 seconds
Started Jun 29 04:42:15 PM PDT 24
Finished Jun 29 04:42:17 PM PDT 24
Peak memory 208800 kb
Host smart-b5150580-5f02-48de-9a5c-937d0de6bb37
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668197301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1668197301
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4187175635
Short name T544
Test name
Test status
Simulation time 34519357 ps
CPU time 1.97 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 222444 kb
Host smart-fb883528-1a4f-4c5c-b184-0f905d3bd460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187175635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4187175635
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2062725156
Short name T484
Test name
Test status
Simulation time 231345982 ps
CPU time 2.22 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:20 PM PDT 24
Peak memory 206676 kb
Host smart-46482e39-ecaa-48b9-b266-f2f9c99c21ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062725156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2062725156
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.965378221
Short name T216
Test name
Test status
Simulation time 2027345407 ps
CPU time 29.48 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:46 PM PDT 24
Peak memory 222500 kb
Host smart-4644fdb6-ce50-45dd-bdb8-bc9ee3e92ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965378221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.965378221
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3944378562
Short name T725
Test name
Test status
Simulation time 1931834032 ps
CPU time 4.74 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:21 PM PDT 24
Peak memory 219660 kb
Host smart-e51d16a3-5a3f-4e42-8e9a-0809313efb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944378562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3944378562
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.444596175
Short name T768
Test name
Test status
Simulation time 201032745 ps
CPU time 3.8 seconds
Started Jun 29 04:42:15 PM PDT 24
Finished Jun 29 04:42:20 PM PDT 24
Peak memory 210160 kb
Host smart-9c332c5a-df05-41e3-b4f9-3c6376e42b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444596175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.444596175
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.121785752
Short name T520
Test name
Test status
Simulation time 17388538 ps
CPU time 0.81 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:20 PM PDT 24
Peak memory 206056 kb
Host smart-2853e127-4389-43fe-a273-0fbad4f9639b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121785752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.121785752
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1461878773
Short name T810
Test name
Test status
Simulation time 98344016 ps
CPU time 2.76 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 214392 kb
Host smart-2fd8c8e0-18ec-4858-8886-9377054a62c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461878773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1461878773
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3871560816
Short name T882
Test name
Test status
Simulation time 183188247 ps
CPU time 2.73 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:19 PM PDT 24
Peak memory 208628 kb
Host smart-77242e58-6b0c-49ed-82e3-095f519f854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871560816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3871560816
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.181191895
Short name T862
Test name
Test status
Simulation time 700614192 ps
CPU time 2.64 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:19 PM PDT 24
Peak memory 214236 kb
Host smart-ac26b0b1-4b68-4e15-8926-49de1a8d0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181191895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.181191895
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.163157595
Short name T601
Test name
Test status
Simulation time 148621553 ps
CPU time 2.13 seconds
Started Jun 29 04:42:15 PM PDT 24
Finished Jun 29 04:42:18 PM PDT 24
Peak memory 214400 kb
Host smart-4419fa62-f856-473f-8a11-4c178bd0a1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163157595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.163157595
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1216141505
Short name T850
Test name
Test status
Simulation time 157841310 ps
CPU time 2.74 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 207244 kb
Host smart-1ff5a37a-b101-4ab5-ae0a-fa91d2f02ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216141505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1216141505
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4166662190
Short name T857
Test name
Test status
Simulation time 542339686 ps
CPU time 4.36 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 208848 kb
Host smart-08837c2b-7dde-4145-87f2-d00f2cd69e41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166662190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4166662190
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2878958790
Short name T522
Test name
Test status
Simulation time 328211277 ps
CPU time 3.15 seconds
Started Jun 29 04:42:21 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 207012 kb
Host smart-65055c4b-3dd2-4b8c-b886-06c10b3c7404
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878958790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2878958790
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1911092741
Short name T831
Test name
Test status
Simulation time 1087885713 ps
CPU time 33.93 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:51 PM PDT 24
Peak memory 207996 kb
Host smart-174d955c-16e7-4bb2-b8a7-31b2a60a0009
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911092741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1911092741
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2171800684
Short name T482
Test name
Test status
Simulation time 1337767111 ps
CPU time 21 seconds
Started Jun 29 04:42:20 PM PDT 24
Finished Jun 29 04:42:42 PM PDT 24
Peak memory 209604 kb
Host smart-0e81594e-e7d2-41ec-9982-dec9c567c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171800684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2171800684
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.217193439
Short name T451
Test name
Test status
Simulation time 278807219 ps
CPU time 3.1 seconds
Started Jun 29 04:42:20 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 206860 kb
Host smart-45080e43-4d0f-44fa-b81c-cdd2b7cba199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217193439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.217193439
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.573940990
Short name T490
Test name
Test status
Simulation time 964833904 ps
CPU time 5.68 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 218128 kb
Host smart-5d31d845-d0a6-4316-a83e-c95d50eccca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573940990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.573940990
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1358202611
Short name T909
Test name
Test status
Simulation time 302687957 ps
CPU time 16.96 seconds
Started Jun 29 04:42:14 PM PDT 24
Finished Jun 29 04:42:32 PM PDT 24
Peak memory 222764 kb
Host smart-4465ffe4-e39e-472a-a89f-a21f23ac8e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358202611 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1358202611
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3146569955
Short name T111
Test name
Test status
Simulation time 81480414 ps
CPU time 4.79 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 214216 kb
Host smart-90414b87-fa1d-46ce-a6f4-49a3956a7b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146569955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3146569955
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1994007446
Short name T108
Test name
Test status
Simulation time 2106477209 ps
CPU time 5.71 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:25 PM PDT 24
Peak memory 210348 kb
Host smart-062c7bb3-00db-4d05-bf0a-6ae506c4702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994007446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1994007446
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4079746469
Short name T497
Test name
Test status
Simulation time 52248208 ps
CPU time 0.88 seconds
Started Jun 29 04:42:27 PM PDT 24
Finished Jun 29 04:42:28 PM PDT 24
Peak memory 206052 kb
Host smart-5a638b7f-8b1c-4e3a-a127-c036745e12e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079746469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4079746469
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1151240217
Short name T361
Test name
Test status
Simulation time 64859793 ps
CPU time 2.67 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 214192 kb
Host smart-2f83c279-13d2-4f13-9881-4ae4e7da724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151240217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1151240217
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4155804415
Short name T242
Test name
Test status
Simulation time 381498661 ps
CPU time 6.38 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:26 PM PDT 24
Peak memory 213888 kb
Host smart-5f1163fe-6e46-4087-985e-f500c83226eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155804415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4155804415
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.679610744
Short name T96
Test name
Test status
Simulation time 273539807 ps
CPU time 6.88 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 220912 kb
Host smart-6e166e25-7829-4d8b-be01-dd3ed0d12ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679610744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.679610744
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1595703872
Short name T888
Test name
Test status
Simulation time 185426459 ps
CPU time 3.79 seconds
Started Jun 29 04:42:24 PM PDT 24
Finished Jun 29 04:42:28 PM PDT 24
Peak memory 214140 kb
Host smart-9e6c8fb5-8fa0-4946-a38a-394dac6047c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595703872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1595703872
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2666354993
Short name T777
Test name
Test status
Simulation time 128721642 ps
CPU time 2.21 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:21 PM PDT 24
Peak memory 216736 kb
Host smart-f2ebc0dd-48d8-4429-bcd4-cfc2eb24dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666354993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2666354993
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3010779450
Short name T285
Test name
Test status
Simulation time 102207746 ps
CPU time 3.84 seconds
Started Jun 29 04:42:17 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 206780 kb
Host smart-9f2ee732-0a90-4558-9c78-58d1515f0f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010779450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3010779450
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1344410856
Short name T489
Test name
Test status
Simulation time 152679384 ps
CPU time 2.55 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:22 PM PDT 24
Peak memory 206964 kb
Host smart-e0d30c38-fae5-4307-9b0d-3a2561b547b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344410856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1344410856
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.369227766
Short name T887
Test name
Test status
Simulation time 38457300 ps
CPU time 2.73 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:23 PM PDT 24
Peak memory 208640 kb
Host smart-c299fb51-e885-40dc-a8b9-1f74c8fc1671
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369227766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.369227766
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.856128359
Short name T258
Test name
Test status
Simulation time 78901692 ps
CPU time 2.27 seconds
Started Jun 29 04:42:16 PM PDT 24
Finished Jun 29 04:42:19 PM PDT 24
Peak memory 206988 kb
Host smart-f1d02d1c-41ee-4273-a896-df17b3850d6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856128359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.856128359
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3347092398
Short name T81
Test name
Test status
Simulation time 194844195 ps
CPU time 5.13 seconds
Started Jun 29 04:42:23 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 214336 kb
Host smart-ea251a38-4445-43bf-a289-70bb928b0da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347092398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3347092398
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2863512968
Short name T637
Test name
Test status
Simulation time 28747767 ps
CPU time 1.96 seconds
Started Jun 29 04:42:18 PM PDT 24
Finished Jun 29 04:42:21 PM PDT 24
Peak memory 208156 kb
Host smart-07b3b8d9-da96-4aa1-ad5c-4213d07ee75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863512968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2863512968
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2310555849
Short name T386
Test name
Test status
Simulation time 10756968896 ps
CPU time 46.53 seconds
Started Jun 29 04:42:23 PM PDT 24
Finished Jun 29 04:43:10 PM PDT 24
Peak memory 222344 kb
Host smart-453ebb9c-ee41-4542-917a-d9c545288439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310555849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2310555849
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1787994951
Short name T717
Test name
Test status
Simulation time 50098312 ps
CPU time 2.05 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 209720 kb
Host smart-141ab4fc-1e25-4747-91c8-b2f9987760a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787994951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1787994951
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2834856602
Short name T103
Test name
Test status
Simulation time 109189217 ps
CPU time 0.71 seconds
Started Jun 29 04:42:23 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 206052 kb
Host smart-09acd62f-64cf-4705-87ec-81a2f146dded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834856602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2834856602
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2863524009
Short name T19
Test name
Test status
Simulation time 74640130 ps
CPU time 3.38 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:30 PM PDT 24
Peak memory 221460 kb
Host smart-4b6676c5-fb24-46d6-a148-3794bd8c1643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863524009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2863524009
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2986068779
Short name T344
Test name
Test status
Simulation time 160728757 ps
CPU time 3.62 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:30 PM PDT 24
Peak memory 209052 kb
Host smart-b4564a76-5a18-4bd8-807f-118e357fb0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986068779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2986068779
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4103138620
Short name T293
Test name
Test status
Simulation time 22316341 ps
CPU time 1.59 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:28 PM PDT 24
Peak memory 214204 kb
Host smart-a74e60e5-411b-4116-887d-f90303e81636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103138620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4103138620
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3372462686
Short name T275
Test name
Test status
Simulation time 256913440 ps
CPU time 5.35 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:32 PM PDT 24
Peak memory 215060 kb
Host smart-572f8b30-5cea-4b6a-8b0c-b74a40491e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372462686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3372462686
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.295971765
Short name T313
Test name
Test status
Simulation time 127273272 ps
CPU time 3.62 seconds
Started Jun 29 04:42:27 PM PDT 24
Finished Jun 29 04:42:31 PM PDT 24
Peak memory 220724 kb
Host smart-9d61a445-3901-41e2-867f-573ba89462bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295971765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.295971765
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4022041668
Short name T821
Test name
Test status
Simulation time 145768224 ps
CPU time 3.5 seconds
Started Jun 29 04:42:25 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 209876 kb
Host smart-d574fd29-e0c5-425f-b2d4-c72655400b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022041668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4022041668
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1378490023
Short name T324
Test name
Test status
Simulation time 687093840 ps
CPU time 3.75 seconds
Started Jun 29 04:42:25 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 207188 kb
Host smart-5a76fc57-a268-40c1-bf94-4cf561569fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378490023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1378490023
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2965700688
Short name T530
Test name
Test status
Simulation time 114355787 ps
CPU time 3.65 seconds
Started Jun 29 04:42:23 PM PDT 24
Finished Jun 29 04:42:27 PM PDT 24
Peak memory 206840 kb
Host smart-379d3f5e-9f50-4a28-980b-f7e87d466d56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965700688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2965700688
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1225182562
Short name T559
Test name
Test status
Simulation time 342565178 ps
CPU time 6.93 seconds
Started Jun 29 04:42:25 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 207892 kb
Host smart-59045160-7eff-457b-bd1d-29d9f0aafb2d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225182562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1225182562
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2494738746
Short name T667
Test name
Test status
Simulation time 2836928873 ps
CPU time 13.73 seconds
Started Jun 29 04:42:27 PM PDT 24
Finished Jun 29 04:42:41 PM PDT 24
Peak memory 208784 kb
Host smart-c744a9d4-6923-43a1-afe8-081ed9d50dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494738746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2494738746
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2147322538
Short name T466
Test name
Test status
Simulation time 6111795940 ps
CPU time 14 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:41 PM PDT 24
Peak memory 208372 kb
Host smart-70cc2a72-1abb-47c1-a03e-0f57931cc0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147322538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2147322538
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4251062556
Short name T281
Test name
Test status
Simulation time 1091033865 ps
CPU time 14.17 seconds
Started Jun 29 04:42:28 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 215756 kb
Host smart-59f4a7ea-8be2-47bc-82d9-0bda54e98779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251062556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4251062556
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4037253805
Short name T899
Test name
Test status
Simulation time 107365210 ps
CPU time 7.98 seconds
Started Jun 29 04:42:24 PM PDT 24
Finished Jun 29 04:42:32 PM PDT 24
Peak memory 222540 kb
Host smart-64a0e789-e2c0-4b88-bca2-0df62570feae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037253805 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4037253805
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2062315143
Short name T716
Test name
Test status
Simulation time 73765182 ps
CPU time 3.69 seconds
Started Jun 29 04:42:24 PM PDT 24
Finished Jun 29 04:42:28 PM PDT 24
Peak memory 209348 kb
Host smart-95cd204a-a0e8-4232-ac0a-1932b2e9493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062315143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2062315143
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4056759537
Short name T834
Test name
Test status
Simulation time 722278668 ps
CPU time 4.07 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:31 PM PDT 24
Peak memory 210444 kb
Host smart-7e5bbe02-5274-46f7-96fd-2421eabbc9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056759537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4056759537
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3907993196
Short name T650
Test name
Test status
Simulation time 25977998 ps
CPU time 0.79 seconds
Started Jun 29 04:42:33 PM PDT 24
Finished Jun 29 04:42:34 PM PDT 24
Peak memory 206052 kb
Host smart-ba6fec37-25e0-41b2-88b6-de1b2bfb558f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907993196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3907993196
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2037371706
Short name T877
Test name
Test status
Simulation time 55887758 ps
CPU time 2.01 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:37 PM PDT 24
Peak memory 218252 kb
Host smart-f906db25-5a18-4413-a94d-fe3639a79ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037371706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2037371706
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3409672858
Short name T95
Test name
Test status
Simulation time 141685017 ps
CPU time 2.86 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:39 PM PDT 24
Peak memory 209032 kb
Host smart-cce8fd45-3bcc-48a1-9427-05fa01471e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409672858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3409672858
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3767733781
Short name T869
Test name
Test status
Simulation time 151116759 ps
CPU time 2.92 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:39 PM PDT 24
Peak memory 222236 kb
Host smart-3733cb8d-dd82-47e3-b353-3d004bda56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767733781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3767733781
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3150398016
Short name T876
Test name
Test status
Simulation time 138639286 ps
CPU time 5.03 seconds
Started Jun 29 04:42:33 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 220412 kb
Host smart-5eb7b1cf-70d5-49e2-8842-2621c242124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150398016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3150398016
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2517359375
Short name T612
Test name
Test status
Simulation time 1270828939 ps
CPU time 8.88 seconds
Started Jun 29 04:42:27 PM PDT 24
Finished Jun 29 04:42:37 PM PDT 24
Peak memory 208016 kb
Host smart-4045b4ed-3376-4a49-8a83-71ca182e5468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517359375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2517359375
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.305723667
Short name T689
Test name
Test status
Simulation time 93057393 ps
CPU time 2.79 seconds
Started Jun 29 04:42:26 PM PDT 24
Finished Jun 29 04:42:30 PM PDT 24
Peak memory 208476 kb
Host smart-56167366-5439-4fc2-a23e-47881dfd573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305723667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.305723667
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4105622273
Short name T870
Test name
Test status
Simulation time 29826080 ps
CPU time 2.24 seconds
Started Jun 29 04:42:24 PM PDT 24
Finished Jun 29 04:42:27 PM PDT 24
Peak memory 206952 kb
Host smart-824fafaa-87b2-42e6-8aa7-067c88b830eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105622273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4105622273
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4026038227
Short name T856
Test name
Test status
Simulation time 101392071 ps
CPU time 2.27 seconds
Started Jun 29 04:42:25 PM PDT 24
Finished Jun 29 04:42:28 PM PDT 24
Peak memory 206836 kb
Host smart-e591a2de-76e8-4d4f-ab46-f0c220070263
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026038227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4026038227
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1459851116
Short name T256
Test name
Test status
Simulation time 390811577 ps
CPU time 7.88 seconds
Started Jun 29 04:42:27 PM PDT 24
Finished Jun 29 04:42:36 PM PDT 24
Peak memory 208632 kb
Host smart-b6156653-61a3-455f-a507-8bc029800f01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459851116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1459851116
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2054157607
Short name T439
Test name
Test status
Simulation time 192594436 ps
CPU time 2.34 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:35 PM PDT 24
Peak memory 216140 kb
Host smart-e7389dee-5597-4dc5-8a5a-dbe5ab062320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054157607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2054157607
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2202816888
Short name T473
Test name
Test status
Simulation time 226351399 ps
CPU time 2.66 seconds
Started Jun 29 04:42:28 PM PDT 24
Finished Jun 29 04:42:31 PM PDT 24
Peak memory 207868 kb
Host smart-ffa1a64c-95d6-4f20-a803-74590b70eecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202816888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2202816888
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2391179589
Short name T300
Test name
Test status
Simulation time 546059374 ps
CPU time 4.83 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:37 PM PDT 24
Peak memory 214220 kb
Host smart-c222b18d-0335-4bb3-a74d-1cb587962d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391179589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2391179589
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2157920318
Short name T635
Test name
Test status
Simulation time 105841475 ps
CPU time 2.2 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 209848 kb
Host smart-0347c6da-7896-42dd-94e8-7e311c5a8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157920318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2157920318
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3044535882
Short name T804
Test name
Test status
Simulation time 24599488 ps
CPU time 0.75 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 206052 kb
Host smart-a6f0b159-032b-4eac-a5dc-08355454a922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044535882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3044535882
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.336569870
Short name T429
Test name
Test status
Simulation time 124521300 ps
CPU time 6.73 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:39 PM PDT 24
Peak memory 215708 kb
Host smart-13378797-9142-4bcb-88e2-09dcb5883be3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=336569870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.336569870
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3762737730
Short name T310
Test name
Test status
Simulation time 478016408 ps
CPU time 2.42 seconds
Started Jun 29 04:42:37 PM PDT 24
Finished Jun 29 04:42:40 PM PDT 24
Peak memory 207464 kb
Host smart-cda62f57-3d84-4310-b354-ad260fbc5e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762737730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3762737730
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3099034372
Short name T677
Test name
Test status
Simulation time 49515645 ps
CPU time 3.25 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:36 PM PDT 24
Peak memory 222452 kb
Host smart-e079f34e-fd78-4eff-80db-fc89e303f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099034372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3099034372
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1184608126
Short name T587
Test name
Test status
Simulation time 2272739012 ps
CPU time 13.3 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:48 PM PDT 24
Peak memory 207980 kb
Host smart-8835a293-e8ea-4bf6-892f-99de10587b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184608126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1184608126
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2614276997
Short name T763
Test name
Test status
Simulation time 76177120 ps
CPU time 3.48 seconds
Started Jun 29 04:42:37 PM PDT 24
Finished Jun 29 04:42:41 PM PDT 24
Peak memory 208772 kb
Host smart-f05ea58f-3b9d-4cc9-b936-dc893409573f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614276997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2614276997
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1778419719
Short name T721
Test name
Test status
Simulation time 139550642 ps
CPU time 2.68 seconds
Started Jun 29 04:42:33 PM PDT 24
Finished Jun 29 04:42:36 PM PDT 24
Peak memory 206996 kb
Host smart-e163b563-177b-4a3c-b963-0341375c49ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778419719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1778419719
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4093197571
Short name T347
Test name
Test status
Simulation time 54428189 ps
CPU time 2.96 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:35 PM PDT 24
Peak memory 206992 kb
Host smart-3dbeaad9-9efb-48b5-9d7e-4384f4dd33d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093197571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4093197571
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2566950503
Short name T463
Test name
Test status
Simulation time 117625837 ps
CPU time 2.27 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:35 PM PDT 24
Peak memory 208384 kb
Host smart-78f9b33a-7307-40af-b51d-7e7aced5c14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566950503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2566950503
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3583482465
Short name T658
Test name
Test status
Simulation time 32663149 ps
CPU time 2.07 seconds
Started Jun 29 04:42:33 PM PDT 24
Finished Jun 29 04:42:35 PM PDT 24
Peak memory 206756 kb
Host smart-3498165d-aa1e-4c21-ad3b-766aa0a65209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583482465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3583482465
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.649309452
Short name T323
Test name
Test status
Simulation time 261944695 ps
CPU time 4.84 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:40 PM PDT 24
Peak memory 207596 kb
Host smart-f587ac0f-3069-4359-918d-5e01fa6c7bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649309452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.649309452
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3711694435
Short name T467
Test name
Test status
Simulation time 13085304 ps
CPU time 0.93 seconds
Started Jun 29 04:42:41 PM PDT 24
Finished Jun 29 04:42:42 PM PDT 24
Peak memory 205988 kb
Host smart-e0e05200-d42f-4d2f-b23a-a569f8853691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711694435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3711694435
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2412066338
Short name T705
Test name
Test status
Simulation time 309128385 ps
CPU time 4.52 seconds
Started Jun 29 04:42:38 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 209484 kb
Host smart-c697b5ca-ddf5-4dbb-a5f4-322e6c7a123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412066338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2412066338
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2048253964
Short name T31
Test name
Test status
Simulation time 93692697 ps
CPU time 2.06 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 209288 kb
Host smart-2d4910c9-7e47-4110-a1dd-733a71b29ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048253964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2048253964
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2276038633
Short name T913
Test name
Test status
Simulation time 51339080 ps
CPU time 3.14 seconds
Started Jun 29 04:42:43 PM PDT 24
Finished Jun 29 04:42:46 PM PDT 24
Peak memory 214360 kb
Host smart-9569f424-f408-447f-96d7-f5a6e692bd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276038633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2276038633
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2790023447
Short name T41
Test name
Test status
Simulation time 104637574 ps
CPU time 2.87 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 215600 kb
Host smart-c73c2563-c700-4f54-bfe2-5e5d03fe4402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790023447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2790023447
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1086505803
Short name T383
Test name
Test status
Simulation time 2497998356 ps
CPU time 26.07 seconds
Started Jun 29 04:42:41 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 214388 kb
Host smart-3817209f-3b9c-4d94-b394-2c123c7ff641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086505803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1086505803
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2201237851
Short name T718
Test name
Test status
Simulation time 133258454 ps
CPU time 4.71 seconds
Started Jun 29 04:42:33 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 207868 kb
Host smart-9e659be0-48dc-491f-903b-98826e2e22de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201237851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2201237851
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1474429933
Short name T295
Test name
Test status
Simulation time 307133140 ps
CPU time 3.59 seconds
Started Jun 29 04:42:34 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 208812 kb
Host smart-e6fd4f45-4ed3-4af4-adcf-96386efbc5be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474429933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1474429933
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2253474443
Short name T605
Test name
Test status
Simulation time 34687368 ps
CPU time 2.37 seconds
Started Jun 29 04:42:32 PM PDT 24
Finished Jun 29 04:42:35 PM PDT 24
Peak memory 208672 kb
Host smart-b92a9109-3e6a-4e27-9a0b-bf39dc6591e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253474443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2253474443
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1439890348
Short name T555
Test name
Test status
Simulation time 119313471 ps
CPU time 2.3 seconds
Started Jun 29 04:42:47 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 216052 kb
Host smart-e855f38a-8f63-4b30-b592-6976af3ef3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439890348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1439890348
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3045782211
Short name T450
Test name
Test status
Simulation time 230278615 ps
CPU time 2.63 seconds
Started Jun 29 04:42:35 PM PDT 24
Finished Jun 29 04:42:38 PM PDT 24
Peak memory 208232 kb
Host smart-5f4fcee6-cbb4-4252-9266-e6cff56fb5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045782211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3045782211
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3344993062
Short name T238
Test name
Test status
Simulation time 285004043 ps
CPU time 2.82 seconds
Started Jun 29 04:42:39 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 207572 kb
Host smart-e1d18454-b4dd-49b2-b742-683bb11c8ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344993062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3344993062
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3028812197
Short name T421
Test name
Test status
Simulation time 142138780 ps
CPU time 3.17 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 210408 kb
Host smart-5a5af4a9-dc51-4e0e-ab4a-d51701853c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028812197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3028812197
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.726837145
Short name T918
Test name
Test status
Simulation time 10287089 ps
CPU time 0.86 seconds
Started Jun 29 04:42:46 PM PDT 24
Finished Jun 29 04:42:47 PM PDT 24
Peak memory 206056 kb
Host smart-ce20ea35-2f8f-4a1d-81ea-647377afbb1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726837145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.726837145
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4288322882
Short name T36
Test name
Test status
Simulation time 896131440 ps
CPU time 5.62 seconds
Started Jun 29 04:42:42 PM PDT 24
Finished Jun 29 04:42:48 PM PDT 24
Peak memory 209372 kb
Host smart-75178a9c-202c-43c0-aaaf-6ddd4928f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288322882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4288322882
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2486747410
Short name T672
Test name
Test status
Simulation time 672976416 ps
CPU time 3.28 seconds
Started Jun 29 04:42:42 PM PDT 24
Finished Jun 29 04:42:46 PM PDT 24
Peak memory 207592 kb
Host smart-61a5f051-66f9-4162-9b32-c2fa11f56739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486747410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2486747410
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2292652223
Short name T252
Test name
Test status
Simulation time 40658985 ps
CPU time 3.02 seconds
Started Jun 29 04:42:39 PM PDT 24
Finished Jun 29 04:42:43 PM PDT 24
Peak memory 222012 kb
Host smart-3f8dae84-7d5e-43bf-8aea-0d333c5a2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292652223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2292652223
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1737133873
Short name T510
Test name
Test status
Simulation time 21553161 ps
CPU time 1.41 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:42 PM PDT 24
Peak memory 207008 kb
Host smart-5c27f6de-6a19-47bc-99ba-749e5916fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737133873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1737133873
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1025163125
Short name T580
Test name
Test status
Simulation time 2723452376 ps
CPU time 11.18 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 214332 kb
Host smart-2ff85130-90a0-41d8-a3e2-35b2bfb44f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025163125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1025163125
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2342855397
Short name T373
Test name
Test status
Simulation time 38826790 ps
CPU time 1.69 seconds
Started Jun 29 04:42:46 PM PDT 24
Finished Jun 29 04:42:48 PM PDT 24
Peak memory 206920 kb
Host smart-4c4df340-ad3b-4384-b9e3-0db4db8e24fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342855397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2342855397
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1149552245
Short name T589
Test name
Test status
Simulation time 70678260 ps
CPU time 3.24 seconds
Started Jun 29 04:42:41 PM PDT 24
Finished Jun 29 04:42:45 PM PDT 24
Peak memory 208572 kb
Host smart-8f2f8288-e25b-45c2-be9b-2f45464c5b16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149552245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1149552245
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3116479392
Short name T639
Test name
Test status
Simulation time 191274939 ps
CPU time 2.7 seconds
Started Jun 29 04:42:41 PM PDT 24
Finished Jun 29 04:42:44 PM PDT 24
Peak memory 208724 kb
Host smart-c36b3ba4-d2b9-401f-868e-a1596d6886a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116479392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3116479392
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2456489036
Short name T627
Test name
Test status
Simulation time 734776998 ps
CPU time 5.22 seconds
Started Jun 29 04:42:39 PM PDT 24
Finished Jun 29 04:42:45 PM PDT 24
Peak memory 208144 kb
Host smart-fe3e5c85-b518-4ffd-b7af-cf9e5ec68d3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456489036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2456489036
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1419183668
Short name T319
Test name
Test status
Simulation time 57033896 ps
CPU time 2.27 seconds
Started Jun 29 04:42:38 PM PDT 24
Finished Jun 29 04:42:41 PM PDT 24
Peak memory 208208 kb
Host smart-487ffdb1-3820-4c40-9bf7-bf700bb22ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419183668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1419183668
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1525631198
Short name T664
Test name
Test status
Simulation time 184477123 ps
CPU time 5.91 seconds
Started Jun 29 04:42:38 PM PDT 24
Finished Jun 29 04:42:44 PM PDT 24
Peak memory 208172 kb
Host smart-e292af99-271d-48cd-907e-58f3a3fc18b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525631198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1525631198
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4117920909
Short name T77
Test name
Test status
Simulation time 4884344927 ps
CPU time 137.35 seconds
Started Jun 29 04:42:46 PM PDT 24
Finished Jun 29 04:45:03 PM PDT 24
Peak memory 217404 kb
Host smart-59b2272d-c634-45dc-97ed-abe26694b317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117920909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4117920909
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.18255327
Short name T774
Test name
Test status
Simulation time 1380473851 ps
CPU time 8.92 seconds
Started Jun 29 04:42:40 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 218992 kb
Host smart-148cf9b7-c95e-4c0f-9b63-9b996885dd02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255327 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.18255327
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2806600313
Short name T838
Test name
Test status
Simulation time 250430468 ps
CPU time 8.66 seconds
Started Jun 29 04:42:39 PM PDT 24
Finished Jun 29 04:42:48 PM PDT 24
Peak memory 207240 kb
Host smart-38092236-2d28-42dc-8333-d794a3571429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806600313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2806600313
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.820668877
Short name T723
Test name
Test status
Simulation time 124746462 ps
CPU time 1.85 seconds
Started Jun 29 04:42:47 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 210144 kb
Host smart-8a7ae673-fecc-44a5-a1ad-766724e9aa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820668877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.820668877
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1628140589
Short name T499
Test name
Test status
Simulation time 9499311 ps
CPU time 0.76 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 206052 kb
Host smart-9d78006d-8ceb-491e-939d-7a927e4624fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628140589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1628140589
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2195434771
Short name T443
Test name
Test status
Simulation time 149564466 ps
CPU time 2.86 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 214820 kb
Host smart-aab5685d-080f-48c3-8d3f-f036c15789ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195434771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2195434771
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2608110582
Short name T222
Test name
Test status
Simulation time 44222556 ps
CPU time 2.66 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 209288 kb
Host smart-0e0e050c-8231-489a-8997-cc03f74fca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608110582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2608110582
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3556371359
Short name T847
Test name
Test status
Simulation time 277598211 ps
CPU time 2.93 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 209848 kb
Host smart-4d222df9-cfbd-41ae-8ec8-8e307127291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556371359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3556371359
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3969349494
Short name T713
Test name
Test status
Simulation time 192833938 ps
CPU time 5.33 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 222300 kb
Host smart-ed647935-6c77-459b-9965-9fc0f6bc9fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969349494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3969349494
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1220358744
Short name T267
Test name
Test status
Simulation time 101741007 ps
CPU time 4.92 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:55 PM PDT 24
Peak memory 207064 kb
Host smart-c546276d-9563-410d-b24d-056e10f721cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220358744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1220358744
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3884434644
Short name T889
Test name
Test status
Simulation time 77771716 ps
CPU time 2.29 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:50 PM PDT 24
Peak memory 206888 kb
Host smart-1de20cc9-701b-4383-bdc3-6391a5f3e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884434644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3884434644
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.863046604
Short name T828
Test name
Test status
Simulation time 384644941 ps
CPU time 3.31 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 206988 kb
Host smart-39d1c843-6c5e-4abc-9ae6-2649e94d7755
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863046604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.863046604
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3500130850
Short name T613
Test name
Test status
Simulation time 503870533 ps
CPU time 6.8 seconds
Started Jun 29 04:42:46 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 208628 kb
Host smart-5c4e149b-3f07-4c85-9043-7a3792921273
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500130850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3500130850
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3422796598
Short name T209
Test name
Test status
Simulation time 113029128 ps
CPU time 3.17 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:42:55 PM PDT 24
Peak memory 208752 kb
Host smart-8641e7a3-8749-40a2-8380-c1704758c406
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422796598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3422796598
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.76873436
Short name T493
Test name
Test status
Simulation time 193532444 ps
CPU time 1.84 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 215528 kb
Host smart-5a1f7e64-24b0-4881-ae17-0e713b9cab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76873436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.76873436
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2190326362
Short name T456
Test name
Test status
Simulation time 514527433 ps
CPU time 2.8 seconds
Started Jun 29 04:42:41 PM PDT 24
Finished Jun 29 04:42:44 PM PDT 24
Peak memory 208420 kb
Host smart-059e16d6-ca5b-4058-9825-e4dfd3711d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190326362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2190326362
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.613799793
Short name T76
Test name
Test status
Simulation time 472573406 ps
CPU time 18.58 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 216736 kb
Host smart-3aeb58ca-2de1-4ed1-a585-bea89aac96a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613799793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.613799793
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3342272392
Short name T779
Test name
Test status
Simulation time 132500172 ps
CPU time 3.72 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:42:55 PM PDT 24
Peak memory 209300 kb
Host smart-84d2a2db-04c4-4f98-82eb-cc1dc4dec2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342272392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3342272392
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3085041540
Short name T409
Test name
Test status
Simulation time 993288689 ps
CPU time 22.73 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:43:15 PM PDT 24
Peak memory 210364 kb
Host smart-a45d8cfd-6e4b-404e-8a7e-3de3c9c6655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085041540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3085041540
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2396198993
Short name T638
Test name
Test status
Simulation time 11722986 ps
CPU time 0.93 seconds
Started Jun 29 04:41:37 PM PDT 24
Finished Jun 29 04:41:38 PM PDT 24
Peak memory 206200 kb
Host smart-da20fc59-ad11-4554-b902-9141bfaa44ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396198993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2396198993
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3661132355
Short name T830
Test name
Test status
Simulation time 284408317 ps
CPU time 2.6 seconds
Started Jun 29 04:41:35 PM PDT 24
Finished Jun 29 04:41:37 PM PDT 24
Peak memory 219096 kb
Host smart-6ae602cc-176a-463b-bcc3-ef7a0f15ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661132355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3661132355
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.797912638
Short name T62
Test name
Test status
Simulation time 70821019 ps
CPU time 3.31 seconds
Started Jun 29 04:41:26 PM PDT 24
Finished Jun 29 04:41:30 PM PDT 24
Peak memory 208392 kb
Host smart-a07944aa-204b-455f-84ab-68bebffd9d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797912638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.797912638
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.818911584
Short name T403
Test name
Test status
Simulation time 93862576 ps
CPU time 3.76 seconds
Started Jun 29 04:41:35 PM PDT 24
Finished Jun 29 04:41:40 PM PDT 24
Peak memory 220444 kb
Host smart-27790b56-95fc-4a09-809f-3cd4de8238a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818911584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.818911584
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2668375951
Short name T628
Test name
Test status
Simulation time 125010289 ps
CPU time 2.52 seconds
Started Jun 29 04:41:35 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 208348 kb
Host smart-824ea764-cbf1-4967-8989-2285a87f70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668375951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2668375951
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.928951703
Short name T354
Test name
Test status
Simulation time 65811313 ps
CPU time 3.58 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:29 PM PDT 24
Peak memory 218528 kb
Host smart-23030647-4005-4924-aed3-73400e1e4ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928951703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.928951703
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.185705718
Short name T599
Test name
Test status
Simulation time 48459549 ps
CPU time 2.55 seconds
Started Jun 29 04:41:32 PM PDT 24
Finished Jun 29 04:41:35 PM PDT 24
Peak memory 206804 kb
Host smart-21481ff8-bbeb-4756-ac4e-8822f67f2ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185705718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.185705718
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1866523772
Short name T333
Test name
Test status
Simulation time 233772158 ps
CPU time 3.03 seconds
Started Jun 29 04:41:32 PM PDT 24
Finished Jun 29 04:41:35 PM PDT 24
Peak memory 206704 kb
Host smart-f3797fd4-1c9b-423f-9613-57298c826830
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866523772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1866523772
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.486959553
Short name T853
Test name
Test status
Simulation time 2487497491 ps
CPU time 48.38 seconds
Started Jun 29 04:41:28 PM PDT 24
Finished Jun 29 04:42:17 PM PDT 24
Peak memory 208100 kb
Host smart-6488b829-ab87-49df-81a8-4698343d8792
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486959553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.486959553
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.340332688
Short name T688
Test name
Test status
Simulation time 223853494 ps
CPU time 2.96 seconds
Started Jun 29 04:41:29 PM PDT 24
Finished Jun 29 04:41:32 PM PDT 24
Peak memory 206876 kb
Host smart-2202d23f-c079-4caf-aa96-9a1b13bebd8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340332688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.340332688
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.444882303
Short name T764
Test name
Test status
Simulation time 165937546 ps
CPU time 2.7 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 207804 kb
Host smart-9fa80644-cc2b-4fc0-95a0-056ff22743da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444882303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.444882303
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.939069573
Short name T648
Test name
Test status
Simulation time 183891653 ps
CPU time 2.29 seconds
Started Jun 29 04:41:25 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 207020 kb
Host smart-271d8520-0151-4248-b7c9-d9ed79664a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939069573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.939069573
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1175610053
Short name T554
Test name
Test status
Simulation time 280505793 ps
CPU time 6.68 seconds
Started Jun 29 04:41:37 PM PDT 24
Finished Jun 29 04:41:44 PM PDT 24
Peak memory 208588 kb
Host smart-71748c83-0ee9-4ff9-9a61-b197e196e691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175610053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1175610053
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3730835742
Short name T131
Test name
Test status
Simulation time 152694015 ps
CPU time 9.33 seconds
Started Jun 29 04:41:35 PM PDT 24
Finished Jun 29 04:41:45 PM PDT 24
Peak memory 220216 kb
Host smart-b43c50b2-dec2-497c-bee3-6b740b2088a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730835742 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3730835742
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.387520443
Short name T372
Test name
Test status
Simulation time 1236455693 ps
CPU time 7.15 seconds
Started Jun 29 04:41:37 PM PDT 24
Finished Jun 29 04:41:44 PM PDT 24
Peak memory 207500 kb
Host smart-1e18b40d-391c-493c-a2d1-cc42e48eeff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387520443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.387520443
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4242783584
Short name T825
Test name
Test status
Simulation time 67522481 ps
CPU time 0.8 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:50 PM PDT 24
Peak memory 205976 kb
Host smart-6e244e88-f471-4993-b74a-59facc05a30a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242783584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4242783584
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.7695876
Short name T695
Test name
Test status
Simulation time 77823745 ps
CPU time 3.08 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 210248 kb
Host smart-bf13ae89-5160-4309-9ed0-cb34a1edbd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7695876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.7695876
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2992769482
Short name T820
Test name
Test status
Simulation time 6861588840 ps
CPU time 66.84 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 214384 kb
Host smart-04ef9177-0a09-4a94-9ef8-d7c59e43cccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992769482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2992769482
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2473844292
Short name T534
Test name
Test status
Simulation time 1435455277 ps
CPU time 6.31 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:42:57 PM PDT 24
Peak memory 219672 kb
Host smart-8eb08e86-5e6c-4258-a358-9b9c6cefb1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473844292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2473844292
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1681144379
Short name T265
Test name
Test status
Simulation time 64456237 ps
CPU time 3.57 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 208612 kb
Host smart-17981a31-7fab-4fca-a000-d547ed62ec5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681144379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1681144379
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4289125603
Short name T875
Test name
Test status
Simulation time 952997341 ps
CPU time 2.82 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:42:54 PM PDT 24
Peak memory 208312 kb
Host smart-52863265-a159-4f9b-90a4-b4735f68f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289125603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4289125603
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2577263426
Short name T533
Test name
Test status
Simulation time 221961035 ps
CPU time 3.29 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 208616 kb
Host smart-922c9af3-9d6b-45ee-a832-2d0ade966b3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577263426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2577263426
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2416306628
Short name T263
Test name
Test status
Simulation time 192918799 ps
CPU time 2.78 seconds
Started Jun 29 04:42:47 PM PDT 24
Finished Jun 29 04:42:50 PM PDT 24
Peak memory 208508 kb
Host smart-571ad76a-6f98-4e14-ac09-a985a3a106ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416306628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2416306628
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2445106811
Short name T902
Test name
Test status
Simulation time 631089689 ps
CPU time 7.82 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 208884 kb
Host smart-5e47fe03-ecb1-455a-b742-d2ba05a0b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445106811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2445106811
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3798500671
Short name T465
Test name
Test status
Simulation time 265699431 ps
CPU time 3.35 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:52 PM PDT 24
Peak memory 208152 kb
Host smart-f1ab4bc4-9421-4e8d-89d4-9a62fd2b1b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798500671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3798500671
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2112341485
Short name T48
Test name
Test status
Simulation time 1731767978 ps
CPU time 64.04 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:43:54 PM PDT 24
Peak memory 221220 kb
Host smart-d4a484b1-2962-4909-a69c-92ccfff1f6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112341485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2112341485
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3494847739
Short name T462
Test name
Test status
Simulation time 8409059691 ps
CPU time 33.76 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 218360 kb
Host smart-61881237-7318-4e19-bed3-e7046c2e2e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494847739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3494847739
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2723856367
Short name T101
Test name
Test status
Simulation time 86853437 ps
CPU time 2.69 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 210128 kb
Host smart-66e33ba5-7405-4c0c-8489-c9d7c972c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723856367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2723856367
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3465815303
Short name T503
Test name
Test status
Simulation time 22016876 ps
CPU time 0.75 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:42:59 PM PDT 24
Peak memory 205988 kb
Host smart-babedd0e-60d0-43e5-8442-20c6ffa55b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465815303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3465815303
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1595927303
Short name T440
Test name
Test status
Simulation time 211013082 ps
CPU time 4.19 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 214332 kb
Host smart-3ffeb3bb-f0ee-470b-8990-4ac790b0374e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595927303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1595927303
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3088035035
Short name T363
Test name
Test status
Simulation time 77044255 ps
CPU time 2.94 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 210476 kb
Host smart-6c0829b6-fb2e-4911-b09d-54a5e6d22ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088035035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3088035035
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4175465417
Short name T891
Test name
Test status
Simulation time 221507303 ps
CPU time 7.97 seconds
Started Jun 29 04:42:59 PM PDT 24
Finished Jun 29 04:43:07 PM PDT 24
Peak memory 219868 kb
Host smart-0ae471b1-9bb9-4f28-9520-393ecf5c3c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175465417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4175465417
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.78918865
Short name T414
Test name
Test status
Simulation time 212884233 ps
CPU time 2.76 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:05 PM PDT 24
Peak memory 214164 kb
Host smart-1001a392-a237-4d32-8344-4d42ee09eb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78918865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.78918865
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.823887534
Short name T49
Test name
Test status
Simulation time 213034157 ps
CPU time 2.32 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 219916 kb
Host smart-fb3e8890-d458-4f09-8d7c-1e73240d3872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823887534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.823887534
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3649438608
Short name T346
Test name
Test status
Simulation time 176526526 ps
CPU time 6.69 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 207980 kb
Host smart-800a4588-f0dc-4976-a79b-e413eacaf11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649438608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3649438608
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3557534626
Short name T357
Test name
Test status
Simulation time 335600338 ps
CPU time 4.21 seconds
Started Jun 29 04:42:51 PM PDT 24
Finished Jun 29 04:42:56 PM PDT 24
Peak memory 206904 kb
Host smart-f172fe12-9dc7-411e-a511-555122fd8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557534626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3557534626
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1775030883
Short name T495
Test name
Test status
Simulation time 2247702857 ps
CPU time 24.62 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:43:15 PM PDT 24
Peak memory 208596 kb
Host smart-f4b1e33b-bdc3-4419-b830-d9850e41cc5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775030883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1775030883
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1613728047
Short name T112
Test name
Test status
Simulation time 29024263 ps
CPU time 2.19 seconds
Started Jun 29 04:42:49 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 206684 kb
Host smart-a734feaf-002c-466a-b16a-80a4e1b45b75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613728047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1613728047
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2581698553
Short name T306
Test name
Test status
Simulation time 461292204 ps
CPU time 7.05 seconds
Started Jun 29 04:42:48 PM PDT 24
Finished Jun 29 04:42:56 PM PDT 24
Peak memory 208604 kb
Host smart-6ba74236-87d9-463c-8c57-5a1a79cc2adc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581698553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2581698553
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2931816116
Short name T702
Test name
Test status
Simulation time 63816823 ps
CPU time 3.01 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 208676 kb
Host smart-ac6735bc-86cc-499a-a012-8617fdbb671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931816116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2931816116
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1182773752
Short name T454
Test name
Test status
Simulation time 31762965 ps
CPU time 2.2 seconds
Started Jun 29 04:42:50 PM PDT 24
Finished Jun 29 04:42:53 PM PDT 24
Peak memory 207176 kb
Host smart-8b341a34-b8d9-41c0-9d6c-4f0eb5831ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182773752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1182773752
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3990784068
Short name T251
Test name
Test status
Simulation time 1227688935 ps
CPU time 31.19 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:33 PM PDT 24
Peak memory 215216 kb
Host smart-dc5dcf5f-507e-449c-ab00-515da393c341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990784068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3990784068
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.947391450
Short name T584
Test name
Test status
Simulation time 78440436 ps
CPU time 3.93 seconds
Started Jun 29 04:42:56 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 208428 kb
Host smart-002c4167-d058-4538-9cf5-4062b15d2583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947391450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.947391450
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.129314381
Short name T772
Test name
Test status
Simulation time 398095129 ps
CPU time 2.81 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:05 PM PDT 24
Peak memory 210296 kb
Host smart-74bf8a5c-9b3c-4656-a8a0-3dcaa9f8f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129314381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.129314381
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4129841694
Short name T649
Test name
Test status
Simulation time 77388168 ps
CPU time 0.99 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:42:59 PM PDT 24
Peak memory 206180 kb
Host smart-99886dad-0499-4339-a1f9-698de0422c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129841694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4129841694
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3293966475
Short name T516
Test name
Test status
Simulation time 206617486 ps
CPU time 3.11 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:05 PM PDT 24
Peak memory 214412 kb
Host smart-71c377f8-92b5-4b19-99c3-e71bb8344c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293966475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3293966475
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.4003957976
Short name T338
Test name
Test status
Simulation time 160347940 ps
CPU time 2.89 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 214364 kb
Host smart-f1a49045-ff37-471d-a13a-1ac112e681e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003957976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.4003957976
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1883982898
Short name T40
Test name
Test status
Simulation time 52411041 ps
CPU time 2.8 seconds
Started Jun 29 04:42:59 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 215704 kb
Host smart-6e72fdec-5672-46e6-b105-3f1f4eaf12b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883982898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1883982898
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.411272529
Short name T378
Test name
Test status
Simulation time 1094557678 ps
CPU time 8.16 seconds
Started Jun 29 04:42:55 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 207932 kb
Host smart-bc39885f-bfab-4ab3-84d2-ca89a0bf8294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411272529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.411272529
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3616996037
Short name T655
Test name
Test status
Simulation time 254366330 ps
CPU time 3.5 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 206120 kb
Host smart-1a8b166e-1ea6-460a-904b-839f151e0634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616996037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3616996037
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3079035005
Short name T474
Test name
Test status
Simulation time 291689700 ps
CPU time 5.94 seconds
Started Jun 29 04:42:54 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 208548 kb
Host smart-e6a4cd4a-c1fb-448f-89d9-5b8a5c6508e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079035005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3079035005
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2608776316
Short name T528
Test name
Test status
Simulation time 788419578 ps
CPU time 5.55 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:03 PM PDT 24
Peak memory 209052 kb
Host smart-1ca08483-9f3a-48e6-bfe8-8866a64c38d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608776316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2608776316
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.635009694
Short name T538
Test name
Test status
Simulation time 435091556 ps
CPU time 3.51 seconds
Started Jun 29 04:42:59 PM PDT 24
Finished Jun 29 04:43:03 PM PDT 24
Peak memory 208180 kb
Host smart-cd24e9a9-fddb-408c-8806-c06443b0d4c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635009694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.635009694
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4048024270
Short name T437
Test name
Test status
Simulation time 1782139881 ps
CPU time 10.44 seconds
Started Jun 29 04:42:55 PM PDT 24
Finished Jun 29 04:43:06 PM PDT 24
Peak memory 218452 kb
Host smart-6b12d366-ce07-4cbc-93ac-0db924f7a02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048024270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4048024270
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.105283057
Short name T505
Test name
Test status
Simulation time 318653133 ps
CPU time 4.75 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 208248 kb
Host smart-6c8543af-8db2-49bb-aa2c-62b22aaeec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105283057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.105283057
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2939315050
Short name T73
Test name
Test status
Simulation time 168742934 ps
CPU time 9.76 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 222504 kb
Host smart-6270abc6-9ad4-4003-bc07-770cdc70ee43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939315050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2939315050
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1116320513
Short name T123
Test name
Test status
Simulation time 1778476244 ps
CPU time 13.08 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 222512 kb
Host smart-613bbdd7-52f3-4ec7-9e36-e6e674e07adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116320513 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1116320513
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2261485457
Short name T82
Test name
Test status
Simulation time 401082428 ps
CPU time 5.35 seconds
Started Jun 29 04:43:03 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 210252 kb
Host smart-b89e5a1a-8830-4edd-9fae-8fc877930fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261485457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2261485457
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3190877191
Short name T754
Test name
Test status
Simulation time 72098470 ps
CPU time 1.75 seconds
Started Jun 29 04:42:56 PM PDT 24
Finished Jun 29 04:42:58 PM PDT 24
Peak memory 209556 kb
Host smart-38b772d5-f5cf-40f1-ac04-bf755cec2334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190877191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3190877191
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.52486253
Short name T642
Test name
Test status
Simulation time 10829048 ps
CPU time 0.93 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:05 PM PDT 24
Peak memory 206048 kb
Host smart-b9dbc415-bc47-4ec1-8863-e414db28fab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52486253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.52486253
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2557541348
Short name T376
Test name
Test status
Simulation time 45621183 ps
CPU time 3.25 seconds
Started Jun 29 04:42:56 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 215796 kb
Host smart-a951b308-1cfa-49de-958c-6277a82ad857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557541348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2557541348
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2411048567
Short name T148
Test name
Test status
Simulation time 134607822 ps
CPU time 5.52 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:07 PM PDT 24
Peak memory 217636 kb
Host smart-78a8d435-00ef-47f7-81ac-ce37605a6551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411048567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2411048567
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3372924502
Short name T778
Test name
Test status
Simulation time 382832921 ps
CPU time 3.87 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:43:03 PM PDT 24
Peak memory 209920 kb
Host smart-79eeab56-035f-41d9-abd7-f60dd069a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372924502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3372924502
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2852362547
Short name T398
Test name
Test status
Simulation time 295728368 ps
CPU time 6.28 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 209104 kb
Host smart-11e725c2-2bc4-4749-8b05-a1607a37cb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852362547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2852362547
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.307495718
Short name T665
Test name
Test status
Simulation time 79427677 ps
CPU time 3.67 seconds
Started Jun 29 04:42:59 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 214252 kb
Host smart-34ea90dd-8510-4754-9745-53f7db6a1e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307495718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.307495718
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.2367069708
Short name T514
Test name
Test status
Simulation time 253323111 ps
CPU time 5.83 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 208092 kb
Host smart-a5d768f6-a032-4ee6-b6c7-dfab395afbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367069708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2367069708
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.672152805
Short name T379
Test name
Test status
Simulation time 619260659 ps
CPU time 4.02 seconds
Started Jun 29 04:42:55 PM PDT 24
Finished Jun 29 04:42:59 PM PDT 24
Peak memory 207932 kb
Host smart-d7467fb5-10ff-46de-af42-1dbc39be8289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672152805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.672152805
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3978370072
Short name T782
Test name
Test status
Simulation time 3370703790 ps
CPU time 21.59 seconds
Started Jun 29 04:43:00 PM PDT 24
Finished Jun 29 04:43:23 PM PDT 24
Peak memory 208496 kb
Host smart-4e9c146a-8f04-497d-bceb-d353f555bac3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978370072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3978370072
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3064260275
Short name T622
Test name
Test status
Simulation time 34031774 ps
CPU time 2.38 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 206980 kb
Host smart-a26ded2d-5cf2-470e-9f59-5dfcc9a9e921
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064260275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3064260275
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3823604078
Short name T391
Test name
Test status
Simulation time 255315486 ps
CPU time 3.31 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 207204 kb
Host smart-21b15e88-6fa5-4784-a3b8-40119c13a461
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823604078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3823604078
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1324768932
Short name T626
Test name
Test status
Simulation time 287885546 ps
CPU time 2.51 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:05 PM PDT 24
Peak memory 208900 kb
Host smart-3bcf3864-e40d-4f60-b4e4-3d519ac86ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324768932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1324768932
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1227038545
Short name T606
Test name
Test status
Simulation time 38247308 ps
CPU time 2.26 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 207212 kb
Host smart-e008aab0-b994-4378-bab7-0a8e70c3b101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227038545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1227038545
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1056852123
Short name T71
Test name
Test status
Simulation time 2062892533 ps
CPU time 44.7 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 222428 kb
Host smart-6cff0e90-a9aa-4574-b7d7-9fafcd7921db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056852123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1056852123
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2403440325
Short name T662
Test name
Test status
Simulation time 39952971 ps
CPU time 2.76 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:00 PM PDT 24
Peak memory 214284 kb
Host smart-c0fdd744-cb07-43c6-b520-e22ab59a05e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403440325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2403440325
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4092211944
Short name T410
Test name
Test status
Simulation time 60825904 ps
CPU time 2.33 seconds
Started Jun 29 04:43:00 PM PDT 24
Finished Jun 29 04:43:03 PM PDT 24
Peak memory 210168 kb
Host smart-68f9e93f-0ba6-43ef-9dc0-024103f29485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092211944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4092211944
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4053198588
Short name T447
Test name
Test status
Simulation time 132801238 ps
CPU time 0.86 seconds
Started Jun 29 04:43:05 PM PDT 24
Finished Jun 29 04:43:07 PM PDT 24
Peak memory 205940 kb
Host smart-6748028e-44db-4deb-9255-82f0bbb191db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053198588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4053198588
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4122346011
Short name T915
Test name
Test status
Simulation time 118797276 ps
CPU time 3.04 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 214304 kb
Host smart-d628b45c-03a8-4a7c-a035-634c9e6046c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122346011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4122346011
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.23981144
Short name T434
Test name
Test status
Simulation time 42294743 ps
CPU time 2.07 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:07 PM PDT 24
Peak memory 218280 kb
Host smart-733cba25-bf20-4d6c-b9b5-154b69e0aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23981144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.23981144
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1819560864
Short name T396
Test name
Test status
Simulation time 1552851233 ps
CPU time 47.43 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:56 PM PDT 24
Peak memory 214164 kb
Host smart-54ed8f3f-1c45-483e-8fa8-0240593156fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819560864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1819560864
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4242877809
Short name T813
Test name
Test status
Simulation time 168575230 ps
CPU time 6.15 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 214284 kb
Host smart-fbcad6f5-e4e7-4d8e-bcb4-55afcb5d3d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242877809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4242877809
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2933303396
Short name T42
Test name
Test status
Simulation time 78980308 ps
CPU time 2.55 seconds
Started Jun 29 04:43:05 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 214324 kb
Host smart-3128021d-a9b1-433e-aa58-3813c8fadd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933303396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2933303396
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3504746889
Short name T660
Test name
Test status
Simulation time 104407581 ps
CPU time 2.26 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 208772 kb
Host smart-34c474ff-a8c4-476d-b5c2-db109b91c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504746889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3504746889
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3884310833
Short name T840
Test name
Test status
Simulation time 119385613 ps
CPU time 3.09 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 206932 kb
Host smart-536a43ea-a6f8-4e2e-9f97-1c4a3cc196f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884310833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3884310833
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2457361982
Short name T866
Test name
Test status
Simulation time 250225530 ps
CPU time 3.29 seconds
Started Jun 29 04:42:57 PM PDT 24
Finished Jun 29 04:43:01 PM PDT 24
Peak memory 208660 kb
Host smart-aabf7237-33dd-4b19-a05b-6c932b648f21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457361982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2457361982
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3336870507
Short name T547
Test name
Test status
Simulation time 43409599 ps
CPU time 2.24 seconds
Started Jun 29 04:43:01 PM PDT 24
Finished Jun 29 04:43:04 PM PDT 24
Peak memory 208668 kb
Host smart-ee23e2e0-6155-4503-a397-7cf5650995b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336870507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3336870507
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3253681951
Short name T663
Test name
Test status
Simulation time 77243670 ps
CPU time 2.39 seconds
Started Jun 29 04:43:10 PM PDT 24
Finished Jun 29 04:43:13 PM PDT 24
Peak memory 208256 kb
Host smart-d344e60f-1dac-463b-b82c-415cea460ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253681951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3253681951
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1984331058
Short name T546
Test name
Test status
Simulation time 556665211 ps
CPU time 9.46 seconds
Started Jun 29 04:42:58 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 206820 kb
Host smart-9f31f3a2-d28a-444f-a8b8-92de92b5e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984331058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1984331058
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3277416498
Short name T671
Test name
Test status
Simulation time 92544998 ps
CPU time 3.09 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 207408 kb
Host smart-b2cbed01-c9d4-409b-8da8-876d6a55c02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277416498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3277416498
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3475926214
Short name T570
Test name
Test status
Simulation time 176372531 ps
CPU time 3.29 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:12 PM PDT 24
Peak memory 209924 kb
Host smart-d1029c04-f891-4d0f-a417-ede2f851e1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475926214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3475926214
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3558349781
Short name T596
Test name
Test status
Simulation time 41124437 ps
CPU time 0.75 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 206060 kb
Host smart-693f9e89-7714-4447-a630-dce723ec6597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558349781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3558349781
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4238171909
Short name T647
Test name
Test status
Simulation time 70661822 ps
CPU time 3.66 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:10 PM PDT 24
Peak memory 207676 kb
Host smart-5e7a73a6-4c23-4283-b1c1-ea880813c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238171909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4238171909
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2315788715
Short name T51
Test name
Test status
Simulation time 1781600156 ps
CPU time 3.28 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 209648 kb
Host smart-07e79291-7347-4aca-8134-a07efd29bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315788715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2315788715
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3697810284
Short name T3
Test name
Test status
Simulation time 1039806615 ps
CPU time 4.47 seconds
Started Jun 29 04:43:09 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 207312 kb
Host smart-928d2256-0821-4ba7-91e0-e1936ca20ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697810284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3697810284
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.535565567
Short name T860
Test name
Test status
Simulation time 7252470501 ps
CPU time 42.25 seconds
Started Jun 29 04:43:08 PM PDT 24
Finished Jun 29 04:43:51 PM PDT 24
Peak memory 208420 kb
Host smart-a91faba3-642f-4231-b26e-7b5375ace397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535565567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.535565567
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.136781322
Short name T332
Test name
Test status
Simulation time 29457598 ps
CPU time 1.94 seconds
Started Jun 29 04:43:08 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 207212 kb
Host smart-30a6f461-9d05-448d-a17e-2971d8380317
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136781322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.136781322
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3703938556
Short name T375
Test name
Test status
Simulation time 62822380 ps
CPU time 2.37 seconds
Started Jun 29 04:43:10 PM PDT 24
Finished Jun 29 04:43:13 PM PDT 24
Peak memory 206808 kb
Host smart-398bb5cb-666a-4bf4-b514-8ce9323c52cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703938556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3703938556
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.928304631
Short name T316
Test name
Test status
Simulation time 60823494 ps
CPU time 3.12 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 208692 kb
Host smart-0f0ea4a7-e6bf-446c-b2c4-8d0fff684bba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928304631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.928304631
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1973358575
Short name T196
Test name
Test status
Simulation time 303269786 ps
CPU time 4.91 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:13 PM PDT 24
Peak memory 216220 kb
Host smart-8252a01a-6eff-48d6-9d46-4e0d8abf6d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973358575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1973358575
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2396978927
Short name T195
Test name
Test status
Simulation time 198157337 ps
CPU time 3.46 seconds
Started Jun 29 04:43:08 PM PDT 24
Finished Jun 29 04:43:12 PM PDT 24
Peak memory 208684 kb
Host smart-15d48c1d-07bb-40c3-8d86-538e638facfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396978927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2396978927
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1777698000
Short name T765
Test name
Test status
Simulation time 1231353702 ps
CPU time 6.48 seconds
Started Jun 29 04:43:08 PM PDT 24
Finished Jun 29 04:43:16 PM PDT 24
Peak memory 207884 kb
Host smart-e54f8fc6-ca31-42a9-8f00-cae096000f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777698000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1777698000
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1255920659
Short name T171
Test name
Test status
Simulation time 28877690 ps
CPU time 1.45 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 209756 kb
Host smart-034c90cb-0802-4b02-a970-9edf65153979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255920659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1255920659
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.328902794
Short name T759
Test name
Test status
Simulation time 25432876 ps
CPU time 0.84 seconds
Started Jun 29 04:43:17 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 206048 kb
Host smart-6d9b0691-cc3d-4370-be0e-e2cfa1784018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328902794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.328902794
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2151915697
Short name T910
Test name
Test status
Simulation time 53384546 ps
CPU time 3.86 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 214352 kb
Host smart-524693fa-8c7a-4798-a598-726351643760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151915697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2151915697
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.584221129
Short name T835
Test name
Test status
Simulation time 343536959 ps
CPU time 10.26 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 218404 kb
Host smart-82d5dcac-10cf-4e88-abf4-13d42b54cdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584221129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.584221129
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1921885384
Short name T858
Test name
Test status
Simulation time 106443295 ps
CPU time 2 seconds
Started Jun 29 04:43:11 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 214768 kb
Host smart-ce88d2c1-568d-4cac-a996-f774234c60be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921885384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1921885384
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2848719662
Short name T592
Test name
Test status
Simulation time 136002403 ps
CPU time 2.5 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:08 PM PDT 24
Peak memory 209716 kb
Host smart-e4a734e4-f639-4386-b4fc-1b71ce602789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848719662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2848719662
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.627951400
Short name T632
Test name
Test status
Simulation time 92694873 ps
CPU time 2.96 seconds
Started Jun 29 04:43:11 PM PDT 24
Finished Jun 29 04:43:15 PM PDT 24
Peak memory 214388 kb
Host smart-f7059310-e7d8-4d5b-bf89-1ccf8c27f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627951400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.627951400
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.185821260
Short name T633
Test name
Test status
Simulation time 27583233 ps
CPU time 2.18 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 206932 kb
Host smart-08ad269d-697a-4828-ba2a-a9742062d803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185821260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.185821260
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.913587873
Short name T455
Test name
Test status
Simulation time 629148197 ps
CPU time 4.34 seconds
Started Jun 29 04:43:04 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 208876 kb
Host smart-67120b23-9d84-4a0e-9a60-3664cdbc0bd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913587873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.913587873
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.816338462
Short name T321
Test name
Test status
Simulation time 213899731 ps
CPU time 6.92 seconds
Started Jun 29 04:43:07 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 208004 kb
Host smart-e099405f-85d2-4dc8-81ba-25613a8f7cd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816338462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.816338462
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3215386040
Short name T629
Test name
Test status
Simulation time 92671303 ps
CPU time 3.6 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:10 PM PDT 24
Peak memory 208704 kb
Host smart-c455f2bb-06e1-4cfe-abe8-5c51d95d4ced
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215386040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3215386040
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3985186350
Short name T603
Test name
Test status
Simulation time 180677829 ps
CPU time 2.96 seconds
Started Jun 29 04:43:09 PM PDT 24
Finished Jun 29 04:43:12 PM PDT 24
Peak memory 214208 kb
Host smart-8ae462f3-aa35-470a-b1c0-d4887460f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985186350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3985186350
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.175892380
Short name T198
Test name
Test status
Simulation time 58279671 ps
CPU time 2.09 seconds
Started Jun 29 04:43:08 PM PDT 24
Finished Jun 29 04:43:11 PM PDT 24
Peak memory 206844 kb
Host smart-ea20cdf7-2a00-4c98-9715-1411f6715f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175892380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.175892380
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1762498353
Short name T694
Test name
Test status
Simulation time 837741631 ps
CPU time 9.15 seconds
Started Jun 29 04:43:17 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 222616 kb
Host smart-5b5f05be-9625-43d2-b54d-c6a6633d3e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762498353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1762498353
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2029106761
Short name T808
Test name
Test status
Simulation time 57680744 ps
CPU time 3.68 seconds
Started Jun 29 04:43:05 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 208236 kb
Host smart-53340f6b-dee9-41a2-9852-f4e538c8a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029106761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2029106761
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.486683228
Short name T769
Test name
Test status
Simulation time 100185390 ps
CPU time 2.53 seconds
Started Jun 29 04:43:06 PM PDT 24
Finished Jun 29 04:43:09 PM PDT 24
Peak memory 210336 kb
Host smart-2cba3d0d-003b-4d7b-b555-95d2bcd4e539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486683228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.486683228
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.615164423
Short name T552
Test name
Test status
Simulation time 13083763 ps
CPU time 0.89 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 206064 kb
Host smart-af885d2f-6de6-495b-8c0a-ee69102326be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615164423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.615164423
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1101974823
Short name T431
Test name
Test status
Simulation time 187054046 ps
CPU time 9.74 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 214332 kb
Host smart-7a703ae6-a5e3-4f0e-9b0a-7d85e77f72ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101974823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1101974823
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2713354761
Short name T154
Test name
Test status
Simulation time 91924593 ps
CPU time 3.93 seconds
Started Jun 29 04:43:20 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 222684 kb
Host smart-d6b1a684-90af-44d6-a1dc-360bd4706e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713354761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2713354761
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1583135373
Short name T893
Test name
Test status
Simulation time 131766529 ps
CPU time 2.54 seconds
Started Jun 29 04:43:19 PM PDT 24
Finished Jun 29 04:43:22 PM PDT 24
Peak memory 207432 kb
Host smart-757902c2-b772-4a15-97f3-62ddf7a942ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583135373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1583135373
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4144109990
Short name T401
Test name
Test status
Simulation time 266352620 ps
CPU time 3.01 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 214312 kb
Host smart-b652d769-9ee7-4bdb-8c08-ccb2ddf39761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144109990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4144109990
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2684848492
Short name T67
Test name
Test status
Simulation time 171300402 ps
CPU time 3.13 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:20 PM PDT 24
Peak memory 208408 kb
Host smart-bfdba686-356f-45fe-86a0-bedd7e15f7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684848492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2684848492
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3811357482
Short name T351
Test name
Test status
Simulation time 8818803021 ps
CPU time 60.01 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 218716 kb
Host smart-ad611612-8111-4b8d-b1b0-d5372b79158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811357482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3811357482
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.916462152
Short name T207
Test name
Test status
Simulation time 67453214 ps
CPU time 2.76 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:20 PM PDT 24
Peak memory 206960 kb
Host smart-bb26f46d-ca5d-4bba-8fda-36759f931f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916462152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.916462152
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3751798063
Short name T845
Test name
Test status
Simulation time 3690728477 ps
CPU time 38.68 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:54 PM PDT 24
Peak memory 208608 kb
Host smart-9ffd4d83-e496-4572-97a7-1215f6a9fdf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751798063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3751798063
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1185182221
Short name T709
Test name
Test status
Simulation time 249133602 ps
CPU time 3.12 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 208648 kb
Host smart-5f91777a-a6b2-466d-8221-66bd2d8f1c4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185182221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1185182221
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3274653337
Short name T388
Test name
Test status
Simulation time 4822105411 ps
CPU time 33.88 seconds
Started Jun 29 04:43:12 PM PDT 24
Finished Jun 29 04:43:46 PM PDT 24
Peak memory 208588 kb
Host smart-7ce3d6f8-5d8c-4e32-a26d-99f3c23b53d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274653337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3274653337
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1979699778
Short name T133
Test name
Test status
Simulation time 215237507 ps
CPU time 1.8 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 216020 kb
Host smart-19c91fa3-accb-417f-8dc6-37b0df3457c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979699778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1979699778
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3560474901
Short name T526
Test name
Test status
Simulation time 98794066 ps
CPU time 2.98 seconds
Started Jun 29 04:43:15 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 207844 kb
Host smart-3bad4a3f-db9c-453c-b79a-6f56d84f8262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560474901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3560474901
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2525296702
Short name T678
Test name
Test status
Simulation time 579294766 ps
CPU time 22.35 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:39 PM PDT 24
Peak memory 217136 kb
Host smart-3dc84cde-2e49-49ff-bd68-fc72981c4b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525296702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2525296702
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3559318325
Short name T124
Test name
Test status
Simulation time 96523154 ps
CPU time 5.81 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:20 PM PDT 24
Peak memory 222504 kb
Host smart-d4e0b11e-6ec4-4bcf-80d2-69cec247225d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559318325 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3559318325
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2955325490
Short name T539
Test name
Test status
Simulation time 7924486032 ps
CPU time 36.07 seconds
Started Jun 29 04:43:15 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 209528 kb
Host smart-178e3858-293b-45ee-84e6-d5ff1d111b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955325490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2955325490
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1051729712
Short name T37
Test name
Test status
Simulation time 1349584865 ps
CPU time 31.68 seconds
Started Jun 29 04:43:12 PM PDT 24
Finished Jun 29 04:43:44 PM PDT 24
Peak memory 211048 kb
Host smart-724b1543-9572-46ec-9717-1b065597c451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051729712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1051729712
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1722436325
Short name T545
Test name
Test status
Simulation time 67606626 ps
CPU time 0.97 seconds
Started Jun 29 04:43:18 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 206176 kb
Host smart-2eaa7e70-75f6-489e-801c-fbf9eef69dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722436325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1722436325
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2821815207
Short name T416
Test name
Test status
Simulation time 998835175 ps
CPU time 28.26 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:45 PM PDT 24
Peak memory 214592 kb
Host smart-3a6b2a64-445f-4406-af61-0f4ec5edde14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821815207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2821815207
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2401305482
Short name T803
Test name
Test status
Simulation time 996051343 ps
CPU time 19.31 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 214320 kb
Host smart-0905ca26-de95-4547-9f11-c119124afcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401305482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2401305482
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2570318215
Short name T742
Test name
Test status
Simulation time 73658352 ps
CPU time 2.33 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:16 PM PDT 24
Peak memory 208716 kb
Host smart-3f5e127d-2464-474b-8d91-c08df4890f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570318215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2570318215
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1193889092
Short name T90
Test name
Test status
Simulation time 89438264 ps
CPU time 2.13 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 214320 kb
Host smart-5595d77e-7f78-4609-9cf1-90579f84f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193889092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1193889092
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2559401617
Short name T270
Test name
Test status
Simulation time 70733881 ps
CPU time 2.35 seconds
Started Jun 29 04:43:15 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 214196 kb
Host smart-f80c96b9-c724-4dcb-964a-3f3cf95b23b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559401617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2559401617
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.485972569
Short name T220
Test name
Test status
Simulation time 509232470 ps
CPU time 4.39 seconds
Started Jun 29 04:43:18 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 208364 kb
Host smart-228c5f61-fb2e-4fdc-85d0-5735a34d1a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485972569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.485972569
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1887342968
Short name T342
Test name
Test status
Simulation time 67256670 ps
CPU time 4.01 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 214236 kb
Host smart-d53b88e5-46c9-4fa2-ad03-bcfb68b4a992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887342968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1887342968
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.150997439
Short name T720
Test name
Test status
Simulation time 155818086 ps
CPU time 6.21 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:20 PM PDT 24
Peak memory 208364 kb
Host smart-fe56d82a-55b6-4225-8b6d-3e16e36f94db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150997439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.150997439
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2465427259
Short name T527
Test name
Test status
Simulation time 36868039 ps
CPU time 2.53 seconds
Started Jun 29 04:43:18 PM PDT 24
Finished Jun 29 04:43:21 PM PDT 24
Peak memory 206892 kb
Host smart-dbe6e23d-bb23-4604-8f43-d87a91bd0a45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465427259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2465427259
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1739990978
Short name T848
Test name
Test status
Simulation time 201363575 ps
CPU time 2.5 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 206932 kb
Host smart-71221dfe-bd72-429a-9a37-74ca0f418ac0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739990978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1739990978
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3535417335
Short name T327
Test name
Test status
Simulation time 1019335806 ps
CPU time 8.98 seconds
Started Jun 29 04:43:15 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 207960 kb
Host smart-080ade5d-ce56-437a-9fa3-361133a57e89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535417335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3535417335
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.63066632
Short name T197
Test name
Test status
Simulation time 227534069 ps
CPU time 3.02 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:17 PM PDT 24
Peak memory 209756 kb
Host smart-cebd4a79-4aa8-4b34-9df2-8858d1331690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63066632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.63066632
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1038636335
Short name T449
Test name
Test status
Simulation time 99452006 ps
CPU time 2.47 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:15 PM PDT 24
Peak memory 206864 kb
Host smart-e4e6d11a-48f7-40fe-9242-b1908e12a1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038636335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1038636335
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3184973412
Short name T339
Test name
Test status
Simulation time 6145692960 ps
CPU time 64.48 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:44:19 PM PDT 24
Peak memory 222432 kb
Host smart-97a28e32-d4cb-49a1-9cd4-727499c9ba38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184973412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3184973412
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3779170799
Short name T900
Test name
Test status
Simulation time 1515966638 ps
CPU time 19.12 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 223796 kb
Host smart-a79b4425-6ebc-4c29-abdd-cf5de2a5a6f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779170799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3779170799
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.23378214
Short name T833
Test name
Test status
Simulation time 192860991 ps
CPU time 3.57 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 214192 kb
Host smart-d8e437f5-7144-414e-998e-c58b468a6cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23378214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.23378214
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2791687885
Short name T412
Test name
Test status
Simulation time 214114260 ps
CPU time 2.5 seconds
Started Jun 29 04:43:17 PM PDT 24
Finished Jun 29 04:43:20 PM PDT 24
Peak memory 209772 kb
Host smart-ece8032f-74c1-47e1-9bfc-6c554da79455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791687885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2791687885
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.462723369
Short name T457
Test name
Test status
Simulation time 16073593 ps
CPU time 0.92 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:23 PM PDT 24
Peak memory 206176 kb
Host smart-26d11704-59cf-4304-9549-f29b20eb4aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462723369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.462723369
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2634800428
Short name T420
Test name
Test status
Simulation time 147752066 ps
CPU time 3.09 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:18 PM PDT 24
Peak memory 214332 kb
Host smart-010d6755-ce2a-4c91-9f86-50d7618d38c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634800428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2634800428
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1275389697
Short name T68
Test name
Test status
Simulation time 207151552 ps
CPU time 3.3 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 222800 kb
Host smart-834d337c-4bdf-433b-9786-ce8430784783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275389697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1275389697
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1158542886
Short name T699
Test name
Test status
Simulation time 459300819 ps
CPU time 5.47 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:22 PM PDT 24
Peak memory 209716 kb
Host smart-673b6f50-1bc7-467f-9e6f-e212a6c5c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158542886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1158542886
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3250680181
Short name T335
Test name
Test status
Simulation time 43681321 ps
CPU time 2.38 seconds
Started Jun 29 04:43:18 PM PDT 24
Finished Jun 29 04:43:22 PM PDT 24
Peak memory 214264 kb
Host smart-32360f6d-4d6c-43d1-b403-5fb53d098fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250680181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3250680181
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2225074051
Short name T225
Test name
Test status
Simulation time 296996023 ps
CPU time 3.71 seconds
Started Jun 29 04:43:18 PM PDT 24
Finished Jun 29 04:43:22 PM PDT 24
Peak memory 214332 kb
Host smart-8ec676e0-e5bd-457f-97fe-3f2e5d212e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225074051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2225074051
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4234015298
Short name T722
Test name
Test status
Simulation time 203037284 ps
CPU time 4.82 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:21 PM PDT 24
Peak memory 209448 kb
Host smart-9b6999e4-c439-4a0b-8010-b5f768d4ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234015298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4234015298
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.709035992
Short name T424
Test name
Test status
Simulation time 262966981 ps
CPU time 5.22 seconds
Started Jun 29 04:43:13 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 206640 kb
Host smart-1d1df5bb-eabe-4d20-9c19-ecc5fce2f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709035992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.709035992
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2406034341
Short name T659
Test name
Test status
Simulation time 31884068 ps
CPU time 2.34 seconds
Started Jun 29 04:43:16 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 207340 kb
Host smart-0d51e987-a37b-4208-b7d1-9fd79562b85a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406034341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2406034341
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.459320148
Short name T863
Test name
Test status
Simulation time 488298147 ps
CPU time 3.62 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 208656 kb
Host smart-f261edf5-c1ef-4a60-820f-1e5d940bd3f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459320148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.459320148
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.827384918
Short name T710
Test name
Test status
Simulation time 134504488 ps
CPU time 2.34 seconds
Started Jun 29 04:43:18 PM PDT 24
Finished Jun 29 04:43:21 PM PDT 24
Peak memory 206820 kb
Host smart-0987cdfb-9cab-4968-b66e-372c48efaf3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827384918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.827384918
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.328351493
Short name T855
Test name
Test status
Simulation time 902029801 ps
CPU time 7.27 seconds
Started Jun 29 04:43:17 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 218448 kb
Host smart-8e5728cd-c947-4d21-87e5-d8d2af9efe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328351493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.328351493
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.336018932
Short name T805
Test name
Test status
Simulation time 79901352 ps
CPU time 3.64 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 208376 kb
Host smart-e1fe929f-6361-43b7-907a-0b2c6ee354aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336018932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.336018932
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4209000787
Short name T191
Test name
Test status
Simulation time 1059525461 ps
CPU time 24.91 seconds
Started Jun 29 04:43:14 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 220108 kb
Host smart-843755b2-2312-445b-ba2f-d7c11c88e0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209000787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4209000787
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3747446501
Short name T600
Test name
Test status
Simulation time 487338489 ps
CPU time 3.96 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 209564 kb
Host smart-6d6849c8-5110-4097-abf4-a67797d27d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747446501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3747446501
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.259314748
Short name T413
Test name
Test status
Simulation time 82369856 ps
CPU time 1.82 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:23 PM PDT 24
Peak memory 209948 kb
Host smart-7a7b7ea5-662b-430f-bbb0-d60565443fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259314748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.259314748
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1005603568
Short name T762
Test name
Test status
Simulation time 36418473 ps
CPU time 0.79 seconds
Started Jun 29 04:41:45 PM PDT 24
Finished Jun 29 04:41:47 PM PDT 24
Peak memory 205980 kb
Host smart-fe1e41ae-1938-4101-b403-caea2b6408a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005603568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1005603568
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3014891939
Short name T444
Test name
Test status
Simulation time 1007327187 ps
CPU time 53.08 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 214320 kb
Host smart-d46471bc-5e83-4bd9-b4d5-c49c54a7ec0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014891939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3014891939
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1018005867
Short name T326
Test name
Test status
Simulation time 3707891908 ps
CPU time 22.06 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:41:59 PM PDT 24
Peak memory 216600 kb
Host smart-054b4178-2c30-4f78-b59d-07d8116e87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018005867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1018005867
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.109373486
Short name T93
Test name
Test status
Simulation time 205658593 ps
CPU time 5.31 seconds
Started Jun 29 04:41:48 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 209028 kb
Host smart-1a82957e-6d3f-4837-ac0b-66e2669ccb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109373486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.109373486
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3285975793
Short name T294
Test name
Test status
Simulation time 83746748 ps
CPU time 2.06 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 214252 kb
Host smart-b0c82bb4-15e0-4cdb-8abe-5ffdd44a4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285975793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3285975793
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1270883242
Short name T884
Test name
Test status
Simulation time 508203136 ps
CPU time 2.56 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 214316 kb
Host smart-e8d737b1-6a16-48a9-ac69-e3b44b4dd3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270883242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1270883242
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2031402206
Short name T843
Test name
Test status
Simulation time 872416560 ps
CPU time 7.24 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:41:44 PM PDT 24
Peak memory 218300 kb
Host smart-9466e3b6-8610-49af-bbc1-136f01077f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031402206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2031402206
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3595861289
Short name T13
Test name
Test status
Simulation time 1960292127 ps
CPU time 15.67 seconds
Started Jun 29 04:41:46 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 236184 kb
Host smart-f87fe3f8-936a-4b8e-86a0-07a2542cf3c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595861289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3595861289
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3185469669
Short name T916
Test name
Test status
Simulation time 117712342 ps
CPU time 2.85 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 206908 kb
Host smart-6021e767-f1e1-4db9-85d8-48cb0c7783f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185469669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3185469669
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3180022825
Short name T617
Test name
Test status
Simulation time 501957354 ps
CPU time 4.58 seconds
Started Jun 29 04:41:37 PM PDT 24
Finished Jun 29 04:41:42 PM PDT 24
Peak memory 208448 kb
Host smart-3c652d40-839d-4723-ab37-5ef2430a0902
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180022825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3180022825
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.516206222
Short name T565
Test name
Test status
Simulation time 923162912 ps
CPU time 6.33 seconds
Started Jun 29 04:41:35 PM PDT 24
Finished Jun 29 04:41:42 PM PDT 24
Peak memory 208344 kb
Host smart-49cf82c9-5b5c-47c4-b677-b0c066bfe720
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516206222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.516206222
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.919765837
Short name T901
Test name
Test status
Simulation time 1773554236 ps
CPU time 42.63 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:42:19 PM PDT 24
Peak memory 207944 kb
Host smart-247e35f9-ec55-406a-b85b-fe88550cc710
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919765837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.919765837
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3712882619
Short name T531
Test name
Test status
Simulation time 714610427 ps
CPU time 3.78 seconds
Started Jun 29 04:41:45 PM PDT 24
Finished Jun 29 04:41:49 PM PDT 24
Peak memory 214192 kb
Host smart-5ebdc641-b08c-4146-a827-51695e16aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712882619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3712882619
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2183634913
Short name T867
Test name
Test status
Simulation time 315070395 ps
CPU time 1.99 seconds
Started Jun 29 04:41:36 PM PDT 24
Finished Jun 29 04:41:39 PM PDT 24
Peak memory 208508 kb
Host smart-96c1612f-f332-4e6e-a57d-60bac8f9231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183634913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2183634913
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2747746621
Short name T194
Test name
Test status
Simulation time 980819100 ps
CPU time 36.58 seconds
Started Jun 29 04:41:46 PM PDT 24
Finished Jun 29 04:42:23 PM PDT 24
Peak memory 221176 kb
Host smart-fc1be150-eb65-47c0-ad0c-594e74601bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747746621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2747746621
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2592677000
Short name T815
Test name
Test status
Simulation time 647411582 ps
CPU time 10.69 seconds
Started Jun 29 04:41:48 PM PDT 24
Finished Jun 29 04:41:59 PM PDT 24
Peak memory 222492 kb
Host smart-71e68455-c3fd-439e-897b-ab816d0c4e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592677000 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2592677000
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1950864468
Short name T492
Test name
Test status
Simulation time 80275292 ps
CPU time 3.28 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:55 PM PDT 24
Peak memory 207212 kb
Host smart-7569811d-8e84-4f9b-afea-e1f149db0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950864468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1950864468
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2341583373
Short name T823
Test name
Test status
Simulation time 288756828 ps
CPU time 3.06 seconds
Started Jun 29 04:41:46 PM PDT 24
Finished Jun 29 04:41:50 PM PDT 24
Peak memory 210448 kb
Host smart-da121f54-79bf-488c-8f1d-1e85284ca149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341583373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2341583373
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2809632388
Short name T864
Test name
Test status
Simulation time 11044034 ps
CPU time 0.89 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 205948 kb
Host smart-1a3d566f-4439-4bd7-a868-af647b5c495c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809632388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2809632388
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2534609190
Short name T38
Test name
Test status
Simulation time 37060674 ps
CPU time 2.71 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 214304 kb
Host smart-41e488db-1f40-4235-b819-ab08a28bf394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534609190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2534609190
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3034683030
Short name T218
Test name
Test status
Simulation time 498068142 ps
CPU time 6.91 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:28 PM PDT 24
Peak memory 214220 kb
Host smart-7c3f4e77-b6aa-44d3-8d38-f628dc20249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034683030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3034683030
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2925796937
Short name T885
Test name
Test status
Simulation time 265070723 ps
CPU time 2.49 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 209244 kb
Host smart-0335e023-994d-43ab-945d-e78d1031245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925796937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2925796937
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.495095816
Short name T278
Test name
Test status
Simulation time 723441918 ps
CPU time 9.22 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:31 PM PDT 24
Peak memory 214220 kb
Host smart-cf9f9e1e-dc24-4445-a8e4-dd58eb96fb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495095816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.495095816
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1988527252
Short name T472
Test name
Test status
Simulation time 77535468 ps
CPU time 2.36 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 214768 kb
Host smart-c2b942f1-e60d-4a22-9d1c-d6c32ccf10cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988527252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1988527252
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.137074952
Short name T315
Test name
Test status
Simulation time 788881127 ps
CPU time 5.02 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 214304 kb
Host smart-58119c4a-1c06-4674-9d06-741f9d97f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137074952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.137074952
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.72288963
Short name T461
Test name
Test status
Simulation time 168042417 ps
CPU time 3.39 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 208332 kb
Host smart-ac48fef2-510a-410f-b948-c209a7ea9a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72288963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.72288963
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1718308838
Short name T248
Test name
Test status
Simulation time 714787141 ps
CPU time 17.95 seconds
Started Jun 29 04:43:26 PM PDT 24
Finished Jun 29 04:43:44 PM PDT 24
Peak memory 208440 kb
Host smart-d7e629f6-ba2f-4bce-b501-f3a6c4ef00e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718308838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1718308838
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3874566355
Short name T775
Test name
Test status
Simulation time 349279924 ps
CPU time 4.25 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 208948 kb
Host smart-814c3686-62e9-4c16-a8b4-a357cd963718
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874566355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3874566355
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.519177834
Short name T350
Test name
Test status
Simulation time 66640385 ps
CPU time 3.21 seconds
Started Jun 29 04:43:24 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 208468 kb
Host smart-0887670f-0a7f-434b-b407-ab005fb51c9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519177834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.519177834
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.755193642
Short name T496
Test name
Test status
Simulation time 52152949 ps
CPU time 2.05 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 215724 kb
Host smart-c0d32b5c-aa8c-41e3-a24a-46e66102f0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755193642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.755193642
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4139735790
Short name T201
Test name
Test status
Simulation time 73458638 ps
CPU time 1.62 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:29 PM PDT 24
Peak memory 206600 kb
Host smart-109c3b0d-8ad9-4580-a426-0dfbeb3b7637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139735790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4139735790
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2193379108
Short name T286
Test name
Test status
Simulation time 17395689543 ps
CPU time 215.89 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:47:00 PM PDT 24
Peak memory 222096 kb
Host smart-d615908f-da1f-4f31-9af7-8f0832e456d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193379108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2193379108
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1078158354
Short name T183
Test name
Test status
Simulation time 982523549 ps
CPU time 9.09 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:32 PM PDT 24
Peak memory 222540 kb
Host smart-1888b92c-e234-4cb9-9398-d27d501ea72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078158354 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1078158354
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4073211357
Short name T809
Test name
Test status
Simulation time 305020648 ps
CPU time 4.91 seconds
Started Jun 29 04:43:26 PM PDT 24
Finished Jun 29 04:43:31 PM PDT 24
Peak memory 209304 kb
Host smart-c7ac863d-9e05-4e92-a975-4ef499c31ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073211357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4073211357
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1329773125
Short name T411
Test name
Test status
Simulation time 129672259 ps
CPU time 2.91 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 210356 kb
Host smart-7aba62d3-a4e2-49f1-8b9b-17a20348f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329773125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1329773125
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2757891975
Short name T675
Test name
Test status
Simulation time 223966988 ps
CPU time 0.8 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:28 PM PDT 24
Peak memory 206036 kb
Host smart-4fa069af-be2d-42e6-a56a-3525cc56faff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757891975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2757891975
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3047542177
Short name T436
Test name
Test status
Simulation time 52738577 ps
CPU time 3.33 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 222380 kb
Host smart-45019bb8-a61b-4397-82c6-71f32323c501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047542177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3047542177
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.340673130
Short name T683
Test name
Test status
Simulation time 461043156 ps
CPU time 4.65 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 222744 kb
Host smart-ddcb3407-b917-479a-ae1a-ce36c3b85e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340673130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.340673130
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2155461263
Short name T298
Test name
Test status
Simulation time 88320034 ps
CPU time 2.03 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 208160 kb
Host smart-59bc4570-c7b5-46ab-8942-f56ba74a0a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155461263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2155461263
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2616047680
Short name T405
Test name
Test status
Simulation time 84882361 ps
CPU time 3.12 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 219148 kb
Host smart-49a8e09a-d2d7-4604-a499-afe10b6b2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616047680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2616047680
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2715902986
Short name T621
Test name
Test status
Simulation time 90092747 ps
CPU time 3.32 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 207368 kb
Host smart-82ac1d3e-dfab-4662-b324-63963f863a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715902986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2715902986
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.436896181
Short name T690
Test name
Test status
Simulation time 283011006 ps
CPU time 3.96 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:31 PM PDT 24
Peak memory 207580 kb
Host smart-a8f24d2a-9514-4ef9-9532-e42db2542e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436896181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.436896181
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2696726886
Short name T568
Test name
Test status
Simulation time 49597349 ps
CPU time 2.74 seconds
Started Jun 29 04:43:20 PM PDT 24
Finished Jun 29 04:43:24 PM PDT 24
Peak memory 207000 kb
Host smart-ec749de3-1b13-4da5-ac16-352afb9d1ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696726886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2696726886
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2460260224
Short name T895
Test name
Test status
Simulation time 90121733 ps
CPU time 3.51 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 208504 kb
Host smart-96b9b09e-4495-462d-b56e-93e6bdc692a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460260224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2460260224
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.246404560
Short name T706
Test name
Test status
Simulation time 550139876 ps
CPU time 3 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 206772 kb
Host smart-add32362-752a-440e-8ed2-243c8d10d00a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246404560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.246404560
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.554717030
Short name T128
Test name
Test status
Simulation time 206700978 ps
CPU time 5.76 seconds
Started Jun 29 04:43:24 PM PDT 24
Finished Jun 29 04:43:30 PM PDT 24
Peak memory 207892 kb
Host smart-06f8c3e8-8b35-4e58-99e9-1362dab2433d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554717030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.554717030
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3146746367
Short name T556
Test name
Test status
Simulation time 1063644815 ps
CPU time 3.77 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:27 PM PDT 24
Peak memory 208032 kb
Host smart-41752a4f-dbc5-471c-8f0e-17c388e0bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146746367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3146746367
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3301122810
Short name T591
Test name
Test status
Simulation time 103970464 ps
CPU time 3.04 seconds
Started Jun 29 04:43:25 PM PDT 24
Finished Jun 29 04:43:28 PM PDT 24
Peak memory 206628 kb
Host smart-9b055d8f-98d7-4a0d-b736-c7b11a07315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301122810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3301122810
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1581415665
Short name T771
Test name
Test status
Simulation time 1060335290 ps
CPU time 24.52 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 215944 kb
Host smart-5aeccd3b-e9a0-4916-ab15-640280a45e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581415665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1581415665
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.4278399218
Short name T673
Test name
Test status
Simulation time 182391902 ps
CPU time 11.57 seconds
Started Jun 29 04:43:25 PM PDT 24
Finished Jun 29 04:43:37 PM PDT 24
Peak memory 222508 kb
Host smart-cb305712-6b6a-4400-aff0-7c1170707208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278399218 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.4278399218
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2908273842
Short name T5
Test name
Test status
Simulation time 158331935 ps
CPU time 3.08 seconds
Started Jun 29 04:43:21 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 208824 kb
Host smart-6f8bb167-ad7e-46e2-8f52-c0cd5f303f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908273842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2908273842
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2798735725
Short name T177
Test name
Test status
Simulation time 3176705606 ps
CPU time 9.96 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:37 PM PDT 24
Peak memory 211148 kb
Host smart-022eac1f-8ba0-45d8-968c-83bbf6865d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798735725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2798735725
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4268956
Short name T651
Test name
Test status
Simulation time 43362451 ps
CPU time 0.86 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 206048 kb
Host smart-1a0d9b0a-7bb3-451c-9301-24ff700b0796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4268956
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.838201853
Short name T919
Test name
Test status
Simulation time 199576597 ps
CPU time 10.25 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:41 PM PDT 24
Peak memory 222168 kb
Host smart-03598eec-ef0d-4eca-ae78-05fcb1efa2a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838201853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.838201853
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3397541514
Short name T35
Test name
Test status
Simulation time 1026524672 ps
CPU time 2.76 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 218252 kb
Host smart-157b2fa6-3681-4b73-ba47-4a8b313d9452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397541514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3397541514
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3230578486
Short name T358
Test name
Test status
Simulation time 100824499 ps
CPU time 2.11 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:33 PM PDT 24
Peak memory 214276 kb
Host smart-611c2407-2162-4bb3-b7e3-0b9dd426e8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230578486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3230578486
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.307410001
Short name T786
Test name
Test status
Simulation time 132146254 ps
CPU time 3.56 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:31 PM PDT 24
Peak memory 209316 kb
Host smart-d50d2247-42c7-4797-9251-6562ecdf621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307410001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.307410001
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1056902916
Short name T381
Test name
Test status
Simulation time 263533300 ps
CPU time 7.63 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 222444 kb
Host smart-f7e35ae5-6bc0-41cc-8340-2c4ced8e2f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056902916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1056902916
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1832030547
Short name T512
Test name
Test status
Simulation time 530832316 ps
CPU time 6.16 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:37 PM PDT 24
Peak memory 210204 kb
Host smart-0f33f7f7-b368-4ef2-a138-fb352fec4388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832030547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1832030547
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.112186782
Short name T597
Test name
Test status
Simulation time 137582074 ps
CPU time 5.86 seconds
Started Jun 29 04:43:27 PM PDT 24
Finished Jun 29 04:43:33 PM PDT 24
Peak memory 214208 kb
Host smart-18f24136-b234-4143-aeb3-1ca21af54dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112186782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.112186782
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3045299904
Short name T550
Test name
Test status
Simulation time 51995522 ps
CPU time 2.79 seconds
Started Jun 29 04:43:25 PM PDT 24
Finished Jun 29 04:43:28 PM PDT 24
Peak memory 206880 kb
Host smart-6c1a5ac4-5ada-449c-88de-4fee3355c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045299904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3045299904
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2539167693
Short name T588
Test name
Test status
Simulation time 3476035220 ps
CPU time 53.64 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 208416 kb
Host smart-73db660e-f0c8-4e63-adb2-f10501a1c5aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539167693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2539167693
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2340120698
Short name T453
Test name
Test status
Simulation time 58703953 ps
CPU time 2.84 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:25 PM PDT 24
Peak memory 206920 kb
Host smart-0fe1c2ff-4df7-43a3-a7f8-cd400ef80dac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340120698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2340120698
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2503428883
Short name T733
Test name
Test status
Simulation time 279418539 ps
CPU time 3.3 seconds
Started Jun 29 04:43:22 PM PDT 24
Finished Jun 29 04:43:26 PM PDT 24
Peak memory 208496 kb
Host smart-6b3a8263-e2ca-4f21-afc4-0b6c6012b301
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503428883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2503428883
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2765281788
Short name T751
Test name
Test status
Simulation time 41086283 ps
CPU time 1.92 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:32 PM PDT 24
Peak memory 207684 kb
Host smart-62d73ca1-5b77-4601-91dd-1c13f8c0347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765281788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2765281788
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3951685461
Short name T674
Test name
Test status
Simulation time 86438757 ps
CPU time 1.83 seconds
Started Jun 29 04:43:26 PM PDT 24
Finished Jun 29 04:43:29 PM PDT 24
Peak memory 207124 kb
Host smart-3b3bdd7d-cdda-4c52-8c9f-d1f935d21bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951685461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3951685461
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1735938130
Short name T228
Test name
Test status
Simulation time 3429439570 ps
CPU time 31.03 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:44:02 PM PDT 24
Peak memory 215780 kb
Host smart-a33f3605-7aac-4bf5-8d92-f44ab3fe719f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735938130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1735938130
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.876123590
Short name T602
Test name
Test status
Simulation time 444258472 ps
CPU time 4.78 seconds
Started Jun 29 04:43:23 PM PDT 24
Finished Jun 29 04:43:28 PM PDT 24
Peak memory 207416 kb
Host smart-a1699021-1d37-4673-8518-bb2440fcdc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876123590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.876123590
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2990176105
Short name T737
Test name
Test status
Simulation time 56984416 ps
CPU time 2.64 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 209896 kb
Host smart-d2144a2d-e0ee-4297-b1f0-7ccd529fcade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990176105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2990176105
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2796221911
Short name T573
Test name
Test status
Simulation time 18425109 ps
CPU time 0.7 seconds
Started Jun 29 04:43:29 PM PDT 24
Finished Jun 29 04:43:30 PM PDT 24
Peak memory 206052 kb
Host smart-b0cbb2e4-bd0c-4207-a58c-3c96039600e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796221911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2796221911
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1317589764
Short name T880
Test name
Test status
Simulation time 77495766 ps
CPU time 2.53 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 208940 kb
Host smart-292162da-8999-4936-b408-c1c00b9da751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317589764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1317589764
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2455505352
Short name T640
Test name
Test status
Simulation time 159703615 ps
CPU time 3.07 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 208224 kb
Host smart-8a7b8aa6-7f81-4f66-a61d-65746a09ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455505352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2455505352
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4014054
Short name T832
Test name
Test status
Simulation time 76102862 ps
CPU time 3.77 seconds
Started Jun 29 04:43:33 PM PDT 24
Finished Jun 29 04:43:37 PM PDT 24
Peak memory 209056 kb
Host smart-c03f5467-b84c-4874-97a6-d275d9b0760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4014054
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1120574026
Short name T1
Test name
Test status
Simulation time 141196762 ps
CPU time 2.34 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 222104 kb
Host smart-559ee759-e50a-4006-865d-f77a5d3ec5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120574026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1120574026
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3120494912
Short name T57
Test name
Test status
Simulation time 93614023 ps
CPU time 3.65 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 208432 kb
Host smart-fe4e8ed2-e1e9-4e58-8512-5c1bd2077cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120494912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3120494912
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3877273778
Short name T776
Test name
Test status
Simulation time 210294655 ps
CPU time 6.29 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:39 PM PDT 24
Peak memory 214200 kb
Host smart-0cf6f280-993e-412f-83ea-48dd73c068bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877273778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3877273778
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4031933193
Short name T200
Test name
Test status
Simulation time 6471549451 ps
CPU time 47.64 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:44:20 PM PDT 24
Peak memory 208584 kb
Host smart-d73806ae-9d7f-470b-b39d-69e1826ac113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031933193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4031933193
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1253042517
Short name T107
Test name
Test status
Simulation time 248412481 ps
CPU time 3.19 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 206940 kb
Host smart-698d9d18-1a82-436f-b219-78dad22afb86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253042517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1253042517
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4163188767
Short name T464
Test name
Test status
Simulation time 125998456 ps
CPU time 4.35 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:37 PM PDT 24
Peak memory 208820 kb
Host smart-95376f70-688d-4379-81b9-413713f8f316
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163188767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4163188767
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.843393943
Short name T625
Test name
Test status
Simulation time 808950982 ps
CPU time 8.51 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:41 PM PDT 24
Peak memory 209020 kb
Host smart-d1f3efd2-fe61-4fa2-8068-751a7bf718ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843393943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.843393943
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2377716206
Short name T301
Test name
Test status
Simulation time 175760171 ps
CPU time 2.93 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 210500 kb
Host smart-954005c1-74c7-43d9-a451-9e7aae46f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377716206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2377716206
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1138006144
Short name T755
Test name
Test status
Simulation time 171472354 ps
CPU time 5.97 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:38 PM PDT 24
Peak memory 208528 kb
Host smart-97f9ba0a-5a88-4cc6-9dc6-1dacb97b8057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138006144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1138006144
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1749425765
Short name T307
Test name
Test status
Simulation time 4461490828 ps
CPU time 104.16 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:45:15 PM PDT 24
Peak memory 221764 kb
Host smart-e187d1f9-b81b-48bd-b6df-47ff75a1b7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749425765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1749425765
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2211728943
Short name T390
Test name
Test status
Simulation time 262937174 ps
CPU time 4.22 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 207592 kb
Host smart-7f9e4513-f9e9-49d2-83d1-222538ae02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211728943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2211728943
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.6670748
Short name T58
Test name
Test status
Simulation time 98001230 ps
CPU time 2.61 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 210904 kb
Host smart-a24dcfd2-a908-4ae3-9719-59f450333fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6670748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.6670748
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1217518875
Short name T712
Test name
Test status
Simulation time 47520949 ps
CPU time 0.81 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:39 PM PDT 24
Peak memory 205948 kb
Host smart-972bfb1a-ec78-44c5-82d5-cf651edaa908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217518875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1217518875
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3494602574
Short name T78
Test name
Test status
Simulation time 799650046 ps
CPU time 5.14 seconds
Started Jun 29 04:43:29 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 207144 kb
Host smart-f0fd54ed-ffac-404a-8a6a-e7569fa5a611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494602574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3494602574
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.232807
Short name T784
Test name
Test status
Simulation time 779867193 ps
CPU time 5.64 seconds
Started Jun 29 04:43:29 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 214216 kb
Host smart-ff5f5278-a2b7-4f08-b205-df0e46d1cc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.232807
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1576648739
Short name T696
Test name
Test status
Simulation time 65132474 ps
CPU time 2.52 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 214176 kb
Host smart-cc1b7081-1f2a-4492-b36d-d88b6cc77eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576648739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1576648739
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4047074573
Short name T445
Test name
Test status
Simulation time 102249123 ps
CPU time 2.46 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 215188 kb
Host smart-3c01545f-201b-43c1-be9a-cad1ddb4c4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047074573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4047074573
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1629387580
Short name T609
Test name
Test status
Simulation time 991520871 ps
CPU time 9.59 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:42 PM PDT 24
Peak memory 207528 kb
Host smart-9f7d7fa4-37dd-4393-b6ff-4420b1a512f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629387580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1629387580
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.717071784
Short name T700
Test name
Test status
Simulation time 343297650 ps
CPU time 4.09 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 206752 kb
Host smart-a235fadb-436c-4bb2-a036-441f664af40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717071784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.717071784
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.26102212
Short name T734
Test name
Test status
Simulation time 128027907 ps
CPU time 5.27 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 207140 kb
Host smart-5699ae17-34f3-4eb6-8816-afacd4a53b14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.26102212
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4069621735
Short name T872
Test name
Test status
Simulation time 94819011 ps
CPU time 2.78 seconds
Started Jun 29 04:43:35 PM PDT 24
Finished Jun 29 04:43:38 PM PDT 24
Peak memory 206856 kb
Host smart-079260f3-b8bd-43ce-8313-338137ba62c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069621735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4069621735
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1956113575
Short name T521
Test name
Test status
Simulation time 79248826 ps
CPU time 2.82 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:36 PM PDT 24
Peak memory 208128 kb
Host smart-ba4280c9-e31d-4a53-9d0a-43241fd5642c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956113575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1956113575
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1049654584
Short name T576
Test name
Test status
Simulation time 79603794 ps
CPU time 1.89 seconds
Started Jun 29 04:43:31 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 214324 kb
Host smart-724a4916-5c47-4ec6-afac-8ad9975c7cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049654584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1049654584
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1459335848
Short name T914
Test name
Test status
Simulation time 56306921 ps
CPU time 2.63 seconds
Started Jun 29 04:43:32 PM PDT 24
Finished Jun 29 04:43:35 PM PDT 24
Peak memory 206668 kb
Host smart-2813ffa5-56e1-435d-9bde-801cc534c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459335848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1459335848
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4231136059
Short name T631
Test name
Test status
Simulation time 3378763643 ps
CPU time 25.02 seconds
Started Jun 29 04:43:33 PM PDT 24
Finished Jun 29 04:43:58 PM PDT 24
Peak memory 208376 kb
Host smart-44e1663a-656b-49e5-90f0-05712c709358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231136059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4231136059
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.317545526
Short name T426
Test name
Test status
Simulation time 158487619 ps
CPU time 3.07 seconds
Started Jun 29 04:43:30 PM PDT 24
Finished Jun 29 04:43:33 PM PDT 24
Peak memory 210000 kb
Host smart-b20df0a3-3aed-422c-8f02-95ba0b401d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317545526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.317545526
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4175537869
Short name T645
Test name
Test status
Simulation time 20367349 ps
CPU time 0.8 seconds
Started Jun 29 04:43:39 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 206016 kb
Host smart-87d0eee0-61a7-4ae1-ae8d-30b4dac510a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175537869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4175537869
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.35470815
Short name T369
Test name
Test status
Simulation time 221155342 ps
CPU time 4.44 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:42 PM PDT 24
Peak memory 214332 kb
Host smart-8f7f68d8-7207-458f-84f3-17492c1f097c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35470815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.35470815
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2473385998
Short name T153
Test name
Test status
Simulation time 54378058 ps
CPU time 2.67 seconds
Started Jun 29 04:43:39 PM PDT 24
Finished Jun 29 04:43:43 PM PDT 24
Peak memory 216116 kb
Host smart-20b8eb46-2362-409b-b75e-cffd3f413e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473385998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2473385998
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2888267413
Short name T309
Test name
Test status
Simulation time 186088420 ps
CPU time 5.19 seconds
Started Jun 29 04:43:36 PM PDT 24
Finished Jun 29 04:43:42 PM PDT 24
Peak memory 218444 kb
Host smart-a0b93783-c9e6-4c8b-9b1f-71019f3c1a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888267413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2888267413
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2140266528
Short name T292
Test name
Test status
Simulation time 217813429 ps
CPU time 3.06 seconds
Started Jun 29 04:43:36 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 214276 kb
Host smart-206194dc-ae20-4949-8750-d6968dbe9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140266528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2140266528
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.919527212
Short name T548
Test name
Test status
Simulation time 29832524 ps
CPU time 1.84 seconds
Started Jun 29 04:43:43 PM PDT 24
Finished Jun 29 04:43:46 PM PDT 24
Peak memory 207212 kb
Host smart-3654ad3e-bcfb-4297-bdd9-46798788d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919527212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.919527212
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1320724307
Short name T509
Test name
Test status
Simulation time 98182973 ps
CPU time 4.79 seconds
Started Jun 29 04:43:39 PM PDT 24
Finished Jun 29 04:43:45 PM PDT 24
Peak memory 207196 kb
Host smart-9d0896a5-459c-4634-a930-bb302c2e019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320724307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1320724307
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1795048345
Short name T395
Test name
Test status
Simulation time 2273051177 ps
CPU time 15.03 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 208384 kb
Host smart-6eeb7caf-e989-4ce3-b51e-dfbb1e560b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795048345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1795048345
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3440208290
Short name T261
Test name
Test status
Simulation time 203771259 ps
CPU time 3.27 seconds
Started Jun 29 04:43:39 PM PDT 24
Finished Jun 29 04:43:43 PM PDT 24
Peak memory 206848 kb
Host smart-764666ee-5006-4cd1-bbac-ab54ca707ff0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440208290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3440208290
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.735197894
Short name T519
Test name
Test status
Simulation time 126900805 ps
CPU time 4.84 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:43 PM PDT 24
Peak memory 208004 kb
Host smart-d3b49ef0-81e2-408c-a24e-bd65fe83b130
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735197894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.735197894
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.338283557
Short name T729
Test name
Test status
Simulation time 721175052 ps
CPU time 5.24 seconds
Started Jun 29 04:43:43 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 208280 kb
Host smart-2d978cad-86fd-4e59-a0ec-ab5bb8b5a58a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338283557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.338283557
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2115671398
Short name T277
Test name
Test status
Simulation time 82830248 ps
CPU time 1.93 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:41 PM PDT 24
Peak memory 208688 kb
Host smart-e94652db-6e24-47dc-9664-5c3bc63d2ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115671398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2115671398
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2568342150
Short name T623
Test name
Test status
Simulation time 72481963 ps
CPU time 2.34 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 208384 kb
Host smart-cca24c63-3c07-4397-9f28-6de8ca222909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568342150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2568342150
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3660463497
Short name T127
Test name
Test status
Simulation time 2294877753 ps
CPU time 22.16 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:44:01 PM PDT 24
Peak memory 222624 kb
Host smart-c18f20ad-b631-4325-b8ee-016f3d2ae569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660463497 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3660463497
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3611418851
Short name T806
Test name
Test status
Simulation time 81648872 ps
CPU time 2.82 seconds
Started Jun 29 04:43:36 PM PDT 24
Finished Jun 29 04:43:39 PM PDT 24
Peak memory 210188 kb
Host smart-9e6e08ac-24bb-4c3a-ab67-9ccf54c48965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611418851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3611418851
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2860680517
Short name T727
Test name
Test status
Simulation time 194139407 ps
CPU time 2.82 seconds
Started Jun 29 04:43:36 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 210268 kb
Host smart-ec619813-cef0-4426-bef6-5e3362af0529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860680517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2860680517
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1122071314
Short name T634
Test name
Test status
Simulation time 10815600 ps
CPU time 0.86 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 206052 kb
Host smart-92899db2-5a07-47ce-bd2d-babb6b2860e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122071314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1122071314
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.235729373
Short name T417
Test name
Test status
Simulation time 560117170 ps
CPU time 8.23 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:47 PM PDT 24
Peak memory 215196 kb
Host smart-13305f18-ce29-4e40-839f-04ee986a2630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235729373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.235729373
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.4169956931
Short name T61
Test name
Test status
Simulation time 84557778 ps
CPU time 3.76 seconds
Started Jun 29 04:43:36 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 209240 kb
Host smart-a99bd919-d6b4-43e8-a9db-37126cad54a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169956931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.4169956931
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4259148131
Short name T394
Test name
Test status
Simulation time 4483171723 ps
CPU time 47 seconds
Started Jun 29 04:43:39 PM PDT 24
Finished Jun 29 04:44:27 PM PDT 24
Peak memory 222560 kb
Host smart-13edd78b-9153-4474-aa3c-3611b738b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259148131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4259148131
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3046429754
Short name T276
Test name
Test status
Simulation time 145090325 ps
CPU time 2.63 seconds
Started Jun 29 04:43:40 PM PDT 24
Finished Jun 29 04:43:43 PM PDT 24
Peak memory 214444 kb
Host smart-6ecc3c0a-dae6-49e1-9a18-b764cff914de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046429754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3046429754
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3876570014
Short name T668
Test name
Test status
Simulation time 114006894 ps
CPU time 2.6 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:42 PM PDT 24
Peak memory 214692 kb
Host smart-1cdcac82-47d7-4b3a-81f7-3eae95b05acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876570014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3876570014
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2573144931
Short name T340
Test name
Test status
Simulation time 62132892 ps
CPU time 3.8 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:41 PM PDT 24
Peak memory 214408 kb
Host smart-eaeea467-4a8e-4e36-a723-e967c4bf5cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573144931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2573144931
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2573141683
Short name T827
Test name
Test status
Simulation time 383025323 ps
CPU time 5.39 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 208856 kb
Host smart-1c5e3244-8482-4bde-9e1d-cb5b00d43d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573141683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2573141683
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1991670902
Short name T679
Test name
Test status
Simulation time 166037105 ps
CPU time 3.76 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:42 PM PDT 24
Peak memory 208700 kb
Host smart-e0468823-aa5d-47f5-a111-7fabd9ded353
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991670902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1991670902
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3208482915
Short name T491
Test name
Test status
Simulation time 189664197 ps
CPU time 3.68 seconds
Started Jun 29 04:43:40 PM PDT 24
Finished Jun 29 04:43:44 PM PDT 24
Peak memory 208564 kb
Host smart-7d768b01-2b0b-4e38-9685-c8528b03aecb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208482915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3208482915
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1470398726
Short name T481
Test name
Test status
Simulation time 33718644 ps
CPU time 2.45 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:41 PM PDT 24
Peak memory 208576 kb
Host smart-b5c30e0c-ad04-4ddb-93a7-bff17555f3db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470398726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1470398726
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3953009394
Short name T894
Test name
Test status
Simulation time 68401717 ps
CPU time 2.27 seconds
Started Jun 29 04:43:37 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 208156 kb
Host smart-de8a6bc8-c592-4a92-997b-638c6ed10611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953009394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3953009394
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3592588526
Short name T574
Test name
Test status
Simulation time 22647435 ps
CPU time 1.76 seconds
Started Jun 29 04:43:39 PM PDT 24
Finished Jun 29 04:43:41 PM PDT 24
Peak memory 206824 kb
Host smart-85c98006-4d3c-48c2-9694-c80f8c734895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592588526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3592588526
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.348863868
Short name T744
Test name
Test status
Simulation time 6210268535 ps
CPU time 37.74 seconds
Started Jun 29 04:43:41 PM PDT 24
Finished Jun 29 04:44:19 PM PDT 24
Peak memory 208688 kb
Host smart-cad50052-b869-4953-8174-dce7871ad409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348863868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.348863868
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4253239865
Short name T780
Test name
Test status
Simulation time 38474342 ps
CPU time 2.07 seconds
Started Jun 29 04:43:38 PM PDT 24
Finished Jun 29 04:43:40 PM PDT 24
Peak memory 209864 kb
Host smart-49edd4b5-7e07-493c-ad5c-b2f16bfa5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253239865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4253239865
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4151309961
Short name T682
Test name
Test status
Simulation time 28695445 ps
CPU time 0.71 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:48 PM PDT 24
Peak memory 206028 kb
Host smart-fc003751-53a2-463c-a1b4-a8ef197ccfbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151309961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4151309961
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3430648296
Short name T325
Test name
Test status
Simulation time 210589485 ps
CPU time 3.45 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 218288 kb
Host smart-561d367f-0334-4451-b710-dae786bbfa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430648296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3430648296
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3609458025
Short name T50
Test name
Test status
Simulation time 1150273192 ps
CPU time 3.22 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:48 PM PDT 24
Peak memory 214324 kb
Host smart-09912060-7c1c-4ac8-bb87-4f012c967e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609458025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3609458025
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3537241908
Short name T92
Test name
Test status
Simulation time 1574599691 ps
CPU time 4.48 seconds
Started Jun 29 04:43:43 PM PDT 24
Finished Jun 29 04:43:47 PM PDT 24
Peak memory 220824 kb
Host smart-9fcdd977-d157-437a-93d2-1e156e6b1719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537241908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3537241908
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.474794379
Short name T246
Test name
Test status
Simulation time 30346476 ps
CPU time 1.86 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:47 PM PDT 24
Peak memory 214260 kb
Host smart-453e3d3b-89dd-42c2-99b0-0f25d3920d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474794379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.474794379
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4283782491
Short name T575
Test name
Test status
Simulation time 528282674 ps
CPU time 4.38 seconds
Started Jun 29 04:43:52 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 214324 kb
Host smart-e1252595-9be6-46c7-a602-d00f13d032e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283782491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4283782491
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3984741759
Short name T287
Test name
Test status
Simulation time 246707634 ps
CPU time 5 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 208080 kb
Host smart-1edb3f29-85b1-4629-a853-5c08a6e157d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984741759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3984741759
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1930835933
Short name T681
Test name
Test status
Simulation time 197164071 ps
CPU time 7.06 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 207876 kb
Host smart-7ed1725d-1977-4bee-b244-19ae7d517dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930835933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1930835933
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3821420723
Short name T18
Test name
Test status
Simulation time 36271897 ps
CPU time 2.59 seconds
Started Jun 29 04:43:50 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 208556 kb
Host smart-a63bece0-45fe-4282-8cf0-6f949ad9e50c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821420723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3821420723
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1345538277
Short name T697
Test name
Test status
Simulation time 443099485 ps
CPU time 3.45 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 207148 kb
Host smart-6db7fde8-e39c-4b56-9ae2-cc61c7ca1b1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345538277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1345538277
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3606901732
Short name T701
Test name
Test status
Simulation time 727293233 ps
CPU time 7.58 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 208816 kb
Host smart-b83de834-7afd-4d86-a77e-ed0322409328
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606901732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3606901732
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3561014411
Short name T341
Test name
Test status
Simulation time 291306809 ps
CPU time 2.13 seconds
Started Jun 29 04:43:42 PM PDT 24
Finished Jun 29 04:43:45 PM PDT 24
Peak memory 214424 kb
Host smart-6c74696a-16ec-4c31-9138-821427b946ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561014411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3561014411
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1691707182
Short name T836
Test name
Test status
Simulation time 136105524 ps
CPU time 4.6 seconds
Started Jun 29 04:43:40 PM PDT 24
Finished Jun 29 04:43:45 PM PDT 24
Peak memory 208232 kb
Host smart-d697e590-cc07-498c-80b8-01e0a081898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691707182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1691707182
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3909468914
Short name T182
Test name
Test status
Simulation time 1337762448 ps
CPU time 20.45 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 220424 kb
Host smart-e8d47296-66e1-48b4-9f99-2e8a727317cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909468914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3909468914
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1473628676
Short name T80
Test name
Test status
Simulation time 284441096 ps
CPU time 7.8 seconds
Started Jun 29 04:43:47 PM PDT 24
Finished Jun 29 04:43:55 PM PDT 24
Peak memory 222472 kb
Host smart-2c190dcc-f562-437f-80c4-e77f8e9f89b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473628676 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1473628676
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3171515888
Short name T656
Test name
Test status
Simulation time 1157243971 ps
CPU time 24.33 seconds
Started Jun 29 04:43:52 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 208152 kb
Host smart-9a449afe-71b4-453d-8f6a-53b0482bc6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171515888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3171515888
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2975933148
Short name T581
Test name
Test status
Simulation time 349165479 ps
CPU time 7.41 seconds
Started Jun 29 04:43:43 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 211124 kb
Host smart-98496972-aec8-4371-929e-88a132b7adc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975933148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2975933148
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3341754737
Short name T459
Test name
Test status
Simulation time 14521065 ps
CPU time 0.79 seconds
Started Jun 29 04:43:47 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 205940 kb
Host smart-43017c15-d01b-4158-b834-afa35149624b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341754737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3341754737
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2552938776
Short name T297
Test name
Test status
Simulation time 213476509 ps
CPU time 4.23 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:51 PM PDT 24
Peak memory 215648 kb
Host smart-fec817b9-3139-4986-9211-5a15eb769cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552938776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2552938776
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3309547641
Short name T535
Test name
Test status
Simulation time 733672451 ps
CPU time 9.32 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:55 PM PDT 24
Peak memory 209712 kb
Host smart-136962a7-e59a-4903-9980-49fd9618cd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309547641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3309547641
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4070317922
Short name T44
Test name
Test status
Simulation time 38293450 ps
CPU time 1.92 seconds
Started Jun 29 04:43:49 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 214320 kb
Host smart-1b26db75-0e54-49fb-b2fe-98693cdc0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070317922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4070317922
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.571752719
Short name T879
Test name
Test status
Simulation time 118747690 ps
CPU time 3.67 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 214164 kb
Host smart-0bd50712-5c1f-44f5-adb1-6ff1e1c39e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571752719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.571752719
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2981838361
Short name T644
Test name
Test status
Simulation time 155457230 ps
CPU time 4.89 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 209584 kb
Host smart-3a1d66a0-2489-4a36-aaff-28ef37a2cd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981838361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2981838361
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1951304429
Short name T692
Test name
Test status
Simulation time 241026464 ps
CPU time 3.49 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 208060 kb
Host smart-7dca6ac1-c875-4df2-a326-5de671e3e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951304429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1951304429
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2134053104
Short name T479
Test name
Test status
Simulation time 12578148833 ps
CPU time 30.21 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 208664 kb
Host smart-547d33c2-744c-4f37-99ec-62452dad4d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134053104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2134053104
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1673162769
Short name T328
Test name
Test status
Simulation time 910322632 ps
CPU time 22.84 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:44:07 PM PDT 24
Peak memory 208840 kb
Host smart-3267c298-6586-41a1-9996-9d01b324d823
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673162769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1673162769
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2925699593
Short name T563
Test name
Test status
Simulation time 63473435 ps
CPU time 2.41 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:48 PM PDT 24
Peak memory 206280 kb
Host smart-4555a86c-626c-46b3-9979-2b7436f8d11c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925699593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2925699593
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.411662682
Short name T317
Test name
Test status
Simulation time 23845136 ps
CPU time 2.06 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 208976 kb
Host smart-a966af3b-5eb2-42dc-b90f-4337ca68820f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411662682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.411662682
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.435231123
Short name T259
Test name
Test status
Simulation time 205026691 ps
CPU time 2.7 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 209808 kb
Host smart-2970e5ae-5c62-4dcc-8e8c-5dc4448af929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435231123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.435231123
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3235970575
Short name T693
Test name
Test status
Simulation time 340689733 ps
CPU time 4.41 seconds
Started Jun 29 04:43:44 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 208296 kb
Host smart-552d19a0-2ae0-4a71-b51f-25ba8d8d4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235970575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3235970575
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1463113794
Short name T162
Test name
Test status
Simulation time 1208780331 ps
CPU time 21.5 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:44:07 PM PDT 24
Peak memory 223300 kb
Host smart-d9e31584-8477-4805-850d-ff6b28648f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463113794 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1463113794
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1240363335
Short name T308
Test name
Test status
Simulation time 58861592 ps
CPU time 2.24 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 208140 kb
Host smart-cda9a2e6-6097-49fd-b784-d2b9aab5f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240363335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1240363335
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4222534349
Short name T59
Test name
Test status
Simulation time 83027770 ps
CPU time 2.32 seconds
Started Jun 29 04:43:49 PM PDT 24
Finished Jun 29 04:43:52 PM PDT 24
Peak memory 210188 kb
Host smart-b1722743-bc5d-401d-bfd5-79b7181dbb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222534349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4222534349
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2057232656
Short name T595
Test name
Test status
Simulation time 54765513 ps
CPU time 0.82 seconds
Started Jun 29 04:43:47 PM PDT 24
Finished Jun 29 04:43:48 PM PDT 24
Peak memory 206056 kb
Host smart-da80e5a0-41d4-4c12-b361-fa6f87b606d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057232656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2057232656
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1774371230
Short name T392
Test name
Test status
Simulation time 196134474 ps
CPU time 2.68 seconds
Started Jun 29 04:43:50 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 215528 kb
Host smart-ccb5cf99-0aa9-477e-8b77-b79edee017b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774371230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1774371230
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.353794813
Short name T359
Test name
Test status
Simulation time 77591335 ps
CPU time 3.71 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:59 PM PDT 24
Peak memory 218260 kb
Host smart-54cbc7a5-67e2-48ce-8fac-a6f402159f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353794813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.353794813
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3221568820
Short name T99
Test name
Test status
Simulation time 84390412 ps
CPU time 4.49 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:51 PM PDT 24
Peak memory 208984 kb
Host smart-814597a7-af35-47e9-b861-e6428da6f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221568820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3221568820
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2276334394
Short name T816
Test name
Test status
Simulation time 51017547 ps
CPU time 1.57 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:56 PM PDT 24
Peak memory 214636 kb
Host smart-4c0d06d6-f5f2-42b9-a954-49bb64d880f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276334394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2276334394
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1366044613
Short name T264
Test name
Test status
Simulation time 3592886914 ps
CPU time 10.49 seconds
Started Jun 29 04:43:47 PM PDT 24
Finished Jun 29 04:43:58 PM PDT 24
Peak memory 218368 kb
Host smart-6b36de7a-132d-40ae-ad4c-2b75107a1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366044613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1366044613
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1556589937
Short name T572
Test name
Test status
Simulation time 25436361 ps
CPU time 2.14 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 208576 kb
Host smart-ab89a121-fa65-45bf-9cc5-bbc21ca794b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556589937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1556589937
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.265429435
Short name T614
Test name
Test status
Simulation time 351697715 ps
CPU time 7.5 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:54 PM PDT 24
Peak memory 207556 kb
Host smart-e85b41df-eda9-4f26-953b-617dfddba449
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265429435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.265429435
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3751876563
Short name T708
Test name
Test status
Simulation time 26815439 ps
CPU time 2.23 seconds
Started Jun 29 04:43:45 PM PDT 24
Finished Jun 29 04:43:48 PM PDT 24
Peak memory 208940 kb
Host smart-41b011b9-7453-479d-8a7e-e67803dd2254
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751876563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3751876563
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3046155904
Short name T460
Test name
Test status
Simulation time 229070694 ps
CPU time 2.36 seconds
Started Jun 29 04:43:48 PM PDT 24
Finished Jun 29 04:43:50 PM PDT 24
Peak memory 206800 kb
Host smart-b3af8c1e-64df-46fb-830d-624ff7e0ae09
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046155904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3046155904
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1091326041
Short name T541
Test name
Test status
Simulation time 66018121 ps
CPU time 1.69 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:49 PM PDT 24
Peak memory 215500 kb
Host smart-507ae5f6-1d43-49ef-a5ef-f74adf7b6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091326041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1091326041
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1127510936
Short name T513
Test name
Test status
Simulation time 87856889 ps
CPU time 2.21 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 206696 kb
Host smart-f34a1094-044b-48fd-ab53-795939e7c5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127510936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1127510936
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1517149270
Short name T859
Test name
Test status
Simulation time 197942653 ps
CPU time 8.36 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:55 PM PDT 24
Peak memory 216252 kb
Host smart-ab02165d-be03-4cfb-a901-b92de53ad020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517149270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1517149270
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1782578794
Short name T868
Test name
Test status
Simulation time 1523024805 ps
CPU time 8.45 seconds
Started Jun 29 04:43:46 PM PDT 24
Finished Jun 29 04:43:55 PM PDT 24
Peak memory 222548 kb
Host smart-00c64b0c-34d7-4105-a923-9b263dfcbb6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782578794 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1782578794
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3339918240
Short name T329
Test name
Test status
Simulation time 13069459973 ps
CPU time 29.03 seconds
Started Jun 29 04:43:43 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 214380 kb
Host smart-d2c880ec-4444-4a40-9b6a-586cee7cdda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339918240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3339918240
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3108160657
Short name T508
Test name
Test status
Simulation time 1314156664 ps
CPU time 6.54 seconds
Started Jun 29 04:43:50 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 210524 kb
Host smart-c8fbf533-71d7-40c8-8e49-ea17d497f9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108160657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3108160657
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1874010287
Short name T817
Test name
Test status
Simulation time 39533364 ps
CPU time 0.86 seconds
Started Jun 29 04:41:54 PM PDT 24
Finished Jun 29 04:41:55 PM PDT 24
Peak memory 205876 kb
Host smart-3055103b-1464-4d51-8898-34aed519eeb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874010287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1874010287
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1271933103
Short name T896
Test name
Test status
Simulation time 215810548 ps
CPU time 2.28 seconds
Started Jun 29 04:41:53 PM PDT 24
Finished Jun 29 04:41:55 PM PDT 24
Peak memory 208152 kb
Host smart-06531e00-765e-4ca2-b5b4-d466d496d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271933103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1271933103
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1248860663
Short name T620
Test name
Test status
Simulation time 476062742 ps
CPU time 3.97 seconds
Started Jun 29 04:41:45 PM PDT 24
Finished Jun 29 04:41:49 PM PDT 24
Peak memory 214304 kb
Host smart-d1b55e6c-b0d9-4e7d-9d0b-3fd53956c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248860663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1248860663
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3674036721
Short name T110
Test name
Test status
Simulation time 238870789 ps
CPU time 6.36 seconds
Started Jun 29 04:41:42 PM PDT 24
Finished Jun 29 04:41:49 PM PDT 24
Peak memory 209048 kb
Host smart-6838b213-16d0-41ab-9700-bee9d34b5850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674036721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3674036721
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3017947354
Short name T904
Test name
Test status
Simulation time 59449992 ps
CPU time 2.88 seconds
Started Jun 29 04:41:45 PM PDT 24
Finished Jun 29 04:41:48 PM PDT 24
Peak memory 207228 kb
Host smart-f99edb25-3dac-4e86-8e3b-abbfb6ff0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017947354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3017947354
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1489855146
Short name T106
Test name
Test status
Simulation time 162053709 ps
CPU time 4.79 seconds
Started Jun 29 04:41:46 PM PDT 24
Finished Jun 29 04:41:52 PM PDT 24
Peak memory 208120 kb
Host smart-46057c8f-4da4-4247-acc7-dc1f39d4b8d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489855146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1489855146
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2598689637
Short name T16
Test name
Test status
Simulation time 3472577411 ps
CPU time 21.85 seconds
Started Jun 29 04:41:44 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 208276 kb
Host smart-e554be6f-3587-4af0-9111-f07c387c7782
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598689637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2598689637
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3980433911
Short name T757
Test name
Test status
Simulation time 100875288 ps
CPU time 2.64 seconds
Started Jun 29 04:41:45 PM PDT 24
Finished Jun 29 04:41:49 PM PDT 24
Peak memory 206884 kb
Host smart-283bda25-9a91-4e33-aa60-6bd769184131
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980433911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3980433911
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3647300942
Short name T249
Test name
Test status
Simulation time 63009279 ps
CPU time 2.96 seconds
Started Jun 29 04:41:48 PM PDT 24
Finished Jun 29 04:41:51 PM PDT 24
Peak memory 209592 kb
Host smart-146d82b8-86ae-4e53-87fc-61007d2e9533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647300942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3647300942
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4186326843
Short name T427
Test name
Test status
Simulation time 495370529 ps
CPU time 10.27 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:42:01 PM PDT 24
Peak memory 208540 kb
Host smart-5d60b78c-e5eb-41dd-b373-f4467c9b7d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186326843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4186326843
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2697992254
Short name T846
Test name
Test status
Simulation time 740885710 ps
CPU time 24.09 seconds
Started Jun 29 04:41:44 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 214320 kb
Host smart-7de8d471-dd5c-4232-828f-ece18da6c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697992254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2697992254
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1629091888
Short name T126
Test name
Test status
Simulation time 327088079 ps
CPU time 6.54 seconds
Started Jun 29 04:41:52 PM PDT 24
Finished Jun 29 04:41:59 PM PDT 24
Peak memory 210636 kb
Host smart-058539fa-34ce-4c87-a1d3-173a83e7e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629091888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1629091888
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1308170258
Short name T878
Test name
Test status
Simulation time 15853073 ps
CPU time 0.75 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:43:59 PM PDT 24
Peak memory 206048 kb
Host smart-564ebd4f-9a4a-481d-b9c9-387538816eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308170258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1308170258
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1913414748
Short name T418
Test name
Test status
Simulation time 73456688 ps
CPU time 4.52 seconds
Started Jun 29 04:43:52 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 214340 kb
Host smart-65736ec4-1d25-4520-83d4-03666519156f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913414748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1913414748
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.149617161
Short name T26
Test name
Test status
Simulation time 808895543 ps
CPU time 2.47 seconds
Started Jun 29 04:43:56 PM PDT 24
Finished Jun 29 04:43:59 PM PDT 24
Peak memory 209144 kb
Host smart-340f3e90-a548-480f-89c7-fd5af0cf4c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149617161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.149617161
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.349729306
Short name T670
Test name
Test status
Simulation time 72726256 ps
CPU time 3.62 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:02 PM PDT 24
Peak memory 213792 kb
Host smart-05cd78fa-f3d2-4471-afc6-6456b31bd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349729306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.349729306
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.697858788
Short name T399
Test name
Test status
Simulation time 34572703 ps
CPU time 2.62 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 214260 kb
Host smart-e7320932-9aea-4364-92fb-5964f38e157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697858788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.697858788
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3365892215
Short name T494
Test name
Test status
Simulation time 391842194 ps
CPU time 4.94 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 218520 kb
Host smart-ab206b7e-2720-495a-809a-9e389f220273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365892215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3365892215
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2770400559
Short name T749
Test name
Test status
Simulation time 110971100 ps
CPU time 3.97 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:02 PM PDT 24
Peak memory 214296 kb
Host smart-445ece71-ae25-4d07-b9d9-530211ca2ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770400559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2770400559
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2403663689
Short name T320
Test name
Test status
Simulation time 2330951607 ps
CPU time 5.86 seconds
Started Jun 29 04:43:47 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 208616 kb
Host smart-9fdee8f7-3b10-4c5d-bc2c-115bff7811cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403663689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2403663689
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4163268966
Short name T543
Test name
Test status
Simulation time 862818641 ps
CPU time 3.2 seconds
Started Jun 29 04:43:50 PM PDT 24
Finished Jun 29 04:43:54 PM PDT 24
Peak memory 208276 kb
Host smart-4689fc72-450b-462c-bcfa-e22bc84475c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163268966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4163268966
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.505390622
Short name T761
Test name
Test status
Simulation time 1833562517 ps
CPU time 5.32 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 208616 kb
Host smart-db7eae1e-ca54-459e-b916-241dad0db1c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505390622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.505390622
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1029885573
Short name T305
Test name
Test status
Simulation time 1748305902 ps
CPU time 5.51 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:03 PM PDT 24
Peak memory 207848 kb
Host smart-a82463dc-e9e5-4aec-a640-f498f92c5a91
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029885573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1029885573
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1937920485
Short name T345
Test name
Test status
Simulation time 105898947 ps
CPU time 2.87 seconds
Started Jun 29 04:43:55 PM PDT 24
Finished Jun 29 04:43:58 PM PDT 24
Peak memory 209124 kb
Host smart-81586495-3aa1-4938-abd6-8114849d8e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937920485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1937920485
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3907643848
Short name T598
Test name
Test status
Simulation time 104285501 ps
CPU time 2.5 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 208508 kb
Host smart-8bd051b8-6d90-479f-b0f8-4817863b3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907643848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3907643848
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2640425477
Short name T282
Test name
Test status
Simulation time 15137896301 ps
CPU time 56.05 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:55 PM PDT 24
Peak memory 221764 kb
Host smart-e6bea95e-b8dd-4276-8830-9a52206bbb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640425477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2640425477
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3850098043
Short name T129
Test name
Test status
Simulation time 183602174 ps
CPU time 6.59 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:44:01 PM PDT 24
Peak memory 207640 kb
Host smart-779c0dc6-4586-4bc2-9313-19fdf8df0ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850098043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3850098043
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3078879219
Short name T691
Test name
Test status
Simulation time 508298167 ps
CPU time 3.35 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:43:58 PM PDT 24
Peak memory 210740 kb
Host smart-f7a21f1e-694c-4f05-9ab1-b38ee7b0bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078879219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3078879219
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2004757520
Short name T781
Test name
Test status
Simulation time 13726226 ps
CPU time 0.8 seconds
Started Jun 29 04:43:55 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 205944 kb
Host smart-7c04c4d5-4f2f-496f-9b8c-a0f333ab6da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004757520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2004757520
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3434217169
Short name T571
Test name
Test status
Simulation time 86351343 ps
CPU time 2.56 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:01 PM PDT 24
Peak memory 208176 kb
Host smart-6e717f59-2275-4dc7-9a0a-cf59f15327d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434217169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3434217169
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1921735011
Short name T865
Test name
Test status
Simulation time 92353384 ps
CPU time 1.69 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:43:56 PM PDT 24
Peak memory 214320 kb
Host smart-deb810c7-a1b1-41d4-b46e-522c09e3c741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921735011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1921735011
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3879685360
Short name T487
Test name
Test status
Simulation time 409572790 ps
CPU time 3.7 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:43:58 PM PDT 24
Peak memory 214220 kb
Host smart-6b682f8b-0871-4a25-b519-95648cc6c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879685360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3879685360
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3904175797
Short name T14
Test name
Test status
Simulation time 51592308 ps
CPU time 3.4 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 222332 kb
Host smart-45f24233-d62f-4d3f-b7cb-3335d7fb5ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904175797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3904175797
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1563653305
Short name T912
Test name
Test status
Simulation time 43573551 ps
CPU time 2 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 214332 kb
Host smart-1002f230-2500-40cf-9faf-d52587cbd879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563653305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1563653305
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.306682661
Short name T641
Test name
Test status
Simulation time 299801044 ps
CPU time 3.98 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:59 PM PDT 24
Peak memory 214316 kb
Host smart-a798dd32-d282-46d3-8e24-54fd9ab44ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306682661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.306682661
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.886096188
Short name T284
Test name
Test status
Simulation time 1064385472 ps
CPU time 15.83 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:44:10 PM PDT 24
Peak memory 208312 kb
Host smart-c151beb5-3dd6-418e-bd88-951d90265b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886096188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.886096188
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4134376039
Short name T654
Test name
Test status
Simulation time 35951622 ps
CPU time 2.49 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 208724 kb
Host smart-444dcce5-2a68-4a30-828b-49e541c9b053
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134376039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4134376039
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3121577110
Short name T367
Test name
Test status
Simulation time 76918454 ps
CPU time 2.45 seconds
Started Jun 29 04:43:58 PM PDT 24
Finished Jun 29 04:44:01 PM PDT 24
Peak memory 206948 kb
Host smart-fbd637a9-86ae-4fb6-9627-6cdd69f538db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121577110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3121577110
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2943894605
Short name T819
Test name
Test status
Simulation time 150020492 ps
CPU time 2.77 seconds
Started Jun 29 04:43:56 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 208788 kb
Host smart-7cd8c884-0350-42c2-9e0a-1f5414e870f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943894605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2943894605
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3310982910
Short name T630
Test name
Test status
Simulation time 31400038 ps
CPU time 2.2 seconds
Started Jun 29 04:43:55 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 214308 kb
Host smart-046562e4-4edd-4107-b889-788dfc6b6ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310982910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3310982910
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3935330164
Short name T485
Test name
Test status
Simulation time 77924573 ps
CPU time 3.32 seconds
Started Jun 29 04:43:55 PM PDT 24
Finished Jun 29 04:43:59 PM PDT 24
Peak memory 208832 kb
Host smart-f4bd9759-d058-4ab7-bfc3-c40f3a8da121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935330164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3935330164
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3400253748
Short name T758
Test name
Test status
Simulation time 342227872 ps
CPU time 11.7 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 214236 kb
Host smart-d156006a-8719-4374-be12-6dc6f972781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400253748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3400253748
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1428221293
Short name T704
Test name
Test status
Simulation time 43633587 ps
CPU time 2.15 seconds
Started Jun 29 04:43:56 PM PDT 24
Finished Jun 29 04:43:58 PM PDT 24
Peak memory 209820 kb
Host smart-b920b21e-86eb-4861-bd20-3a9bff56637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428221293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1428221293
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2749258962
Short name T476
Test name
Test status
Simulation time 27151162 ps
CPU time 0.74 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:04 PM PDT 24
Peak memory 206044 kb
Host smart-2b309707-97d3-4280-afb1-8078c24d75c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749258962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2749258962
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3610251667
Short name T746
Test name
Test status
Simulation time 445422206 ps
CPU time 4.35 seconds
Started Jun 29 04:44:07 PM PDT 24
Finished Jun 29 04:44:13 PM PDT 24
Peak memory 218416 kb
Host smart-2a940a31-8df6-4f55-a988-2805e2102b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610251667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3610251667
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.184469057
Short name T288
Test name
Test status
Simulation time 354884523 ps
CPU time 2.75 seconds
Started Jun 29 04:43:54 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 218196 kb
Host smart-916565b1-3d97-4614-8734-343e1931e3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184469057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.184469057
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1630277307
Short name T271
Test name
Test status
Simulation time 161209899 ps
CPU time 2.56 seconds
Started Jun 29 04:43:59 PM PDT 24
Finished Jun 29 04:44:02 PM PDT 24
Peak memory 219224 kb
Host smart-67d3e725-d66c-4ea6-a9af-2d72ed029709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630277307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1630277307
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2137713376
Short name T433
Test name
Test status
Simulation time 177477616 ps
CPU time 2.71 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:01 PM PDT 24
Peak memory 208284 kb
Host smart-80721958-bdea-4523-9286-df9a8a70469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137713376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2137713376
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1626551269
Short name T740
Test name
Test status
Simulation time 1247920949 ps
CPU time 4.69 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:03 PM PDT 24
Peak memory 207212 kb
Host smart-ec6bf449-ac17-4db7-9b7b-02aa1aac8a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626551269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1626551269
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2791083120
Short name T619
Test name
Test status
Simulation time 119261024 ps
CPU time 2.58 seconds
Started Jun 29 04:43:57 PM PDT 24
Finished Jun 29 04:44:01 PM PDT 24
Peak memory 206864 kb
Host smart-eb028412-089e-4557-9219-f5ee2bf4c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791083120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2791083120
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4074625412
Short name T908
Test name
Test status
Simulation time 206763066 ps
CPU time 2.82 seconds
Started Jun 29 04:43:56 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 208964 kb
Host smart-c2e240aa-a940-4d5f-ac19-2289c4d6a9a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074625412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4074625412
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2851123126
Short name T279
Test name
Test status
Simulation time 87664323 ps
CPU time 4 seconds
Started Jun 29 04:43:56 PM PDT 24
Finished Jun 29 04:44:02 PM PDT 24
Peak memory 208744 kb
Host smart-0ef9ec7f-f993-458f-b81a-acfefca67580
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851123126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2851123126
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2500571426
Short name T657
Test name
Test status
Simulation time 245408368 ps
CPU time 3.25 seconds
Started Jun 29 04:43:53 PM PDT 24
Finished Jun 29 04:43:57 PM PDT 24
Peak memory 208600 kb
Host smart-bade1366-f795-452d-8e10-b32238cc6146
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500571426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2500571426
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4068706086
Short name T770
Test name
Test status
Simulation time 329104854 ps
CPU time 4.72 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:13 PM PDT 24
Peak memory 210212 kb
Host smart-fb4beb85-8003-4c4a-a4be-df0d3ea02095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068706086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4068706086
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1504374686
Short name T422
Test name
Test status
Simulation time 276201989 ps
CPU time 2.49 seconds
Started Jun 29 04:43:56 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 208456 kb
Host smart-e48cf1cd-021c-47b1-96b7-b690e4eb19fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504374686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1504374686
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3888314692
Short name T181
Test name
Test status
Simulation time 465247517 ps
CPU time 11.26 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:19 PM PDT 24
Peak memory 220188 kb
Host smart-c529a8cd-6626-4500-ac6c-f30f68b88335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888314692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3888314692
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3396313622
Short name T125
Test name
Test status
Simulation time 174584232 ps
CPU time 7.56 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 222540 kb
Host smart-0d7067f4-f0d5-46fb-92ef-988cad463e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396313622 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3396313622
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3918104677
Short name T488
Test name
Test status
Simulation time 92576075 ps
CPU time 2.04 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:05 PM PDT 24
Peak memory 208192 kb
Host smart-5473f575-b592-4670-9ce7-7e4fc647f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918104677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3918104677
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1996446033
Short name T837
Test name
Test status
Simulation time 139805233 ps
CPU time 2 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 210352 kb
Host smart-4bda1e13-e4bb-4830-a23e-d672417a0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996446033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1996446033
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2058252455
Short name T102
Test name
Test status
Simulation time 22041719 ps
CPU time 0.88 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:08 PM PDT 24
Peak memory 205944 kb
Host smart-93ed45e1-2c40-473b-9359-712a25ebd640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058252455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2058252455
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2391397913
Short name T798
Test name
Test status
Simulation time 138240427 ps
CPU time 2.91 seconds
Started Jun 29 04:44:04 PM PDT 24
Finished Jun 29 04:44:09 PM PDT 24
Peak memory 214336 kb
Host smart-e4af9a17-c9d0-4d98-b9ae-8bfa739aa7f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391397913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2391397913
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3030705654
Short name T799
Test name
Test status
Simulation time 170703474 ps
CPU time 3.69 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 214724 kb
Host smart-9b171d8e-d392-4d59-ba4d-7c6590f8c7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030705654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3030705654
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2618223004
Short name T561
Test name
Test status
Simulation time 147083168 ps
CPU time 2.58 seconds
Started Jun 29 04:44:07 PM PDT 24
Finished Jun 29 04:44:11 PM PDT 24
Peak memory 218228 kb
Host smart-54f2148f-8e9c-4672-a5f0-6121e229c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618223004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2618223004
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1336706066
Short name T362
Test name
Test status
Simulation time 813644824 ps
CPU time 18.38 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:22 PM PDT 24
Peak memory 209204 kb
Host smart-5a4ffb77-d9e9-49a2-b9e7-b0b58c7355e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336706066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1336706066
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2783155997
Short name T748
Test name
Test status
Simulation time 403302492 ps
CPU time 3.23 seconds
Started Jun 29 04:44:07 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 214380 kb
Host smart-39ac4937-ddc6-4641-9b4c-3bc4b6f6e6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783155997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2783155997
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.773885337
Short name T542
Test name
Test status
Simulation time 169290863 ps
CPU time 1.37 seconds
Started Jun 29 04:44:01 PM PDT 24
Finished Jun 29 04:44:04 PM PDT 24
Peak memory 206120 kb
Host smart-12cab646-67fa-439d-bcf6-4fbcdf3d47c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773885337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.773885337
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2445999688
Short name T707
Test name
Test status
Simulation time 543051564 ps
CPU time 4.45 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:09 PM PDT 24
Peak memory 207580 kb
Host smart-e5c32fd8-aeff-418a-8687-c000af41b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445999688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2445999688
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.793706222
Short name T747
Test name
Test status
Simulation time 313424442 ps
CPU time 4.62 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:08 PM PDT 24
Peak memory 208432 kb
Host smart-2cde5dd5-3a29-4fc7-b93e-7d876c788c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793706222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.793706222
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1708849128
Short name T374
Test name
Test status
Simulation time 259478600 ps
CPU time 3.58 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 208828 kb
Host smart-8086f2e7-a03f-460a-abad-e405efe957c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708849128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1708849128
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4222039279
Short name T583
Test name
Test status
Simulation time 1295077248 ps
CPU time 37.87 seconds
Started Jun 29 04:44:04 PM PDT 24
Finished Jun 29 04:44:44 PM PDT 24
Peak memory 209204 kb
Host smart-dac607b1-1651-4deb-be22-d24b84297723
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222039279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4222039279
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2359084633
Short name T560
Test name
Test status
Simulation time 59062397 ps
CPU time 3.07 seconds
Started Jun 29 04:44:01 PM PDT 24
Finished Jun 29 04:44:05 PM PDT 24
Peak memory 208308 kb
Host smart-98c62810-9986-45a8-b4ef-087d7b694f75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359084633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2359084633
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1575651214
Short name T254
Test name
Test status
Simulation time 230075416 ps
CPU time 2.94 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 214308 kb
Host smart-93a1f23c-f9cb-46d3-833a-6a1c1660c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575651214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1575651214
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3850052565
Short name T446
Test name
Test status
Simulation time 155050930 ps
CPU time 2.51 seconds
Started Jun 29 04:44:01 PM PDT 24
Finished Jun 29 04:44:05 PM PDT 24
Peak memory 208588 kb
Host smart-dd774860-d528-4ea3-9164-49955e4f7f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850052565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3850052565
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.337285639
Short name T240
Test name
Test status
Simulation time 1512511295 ps
CPU time 17.62 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:28 PM PDT 24
Peak memory 216500 kb
Host smart-2b411d83-8874-475a-9e48-f47a2d7b78bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337285639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.337285639
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3991265038
Short name T841
Test name
Test status
Simulation time 280289734 ps
CPU time 9.19 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:17 PM PDT 24
Peak memory 208180 kb
Host smart-6225ea2e-027b-45ab-8775-2ff786116913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991265038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3991265038
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3037079327
Short name T407
Test name
Test status
Simulation time 203670295 ps
CPU time 2.25 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 210492 kb
Host smart-a1d4e760-ba60-4d25-a114-7cc80c7c3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037079327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3037079327
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1651162058
Short name T469
Test name
Test status
Simulation time 42964607 ps
CPU time 0.82 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:09 PM PDT 24
Peak memory 206060 kb
Host smart-36d0543f-3176-49d8-9d5e-a50a6cb6d24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651162058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1651162058
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4231685896
Short name T430
Test name
Test status
Simulation time 130507878 ps
CPU time 2.45 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:05 PM PDT 24
Peak memory 214340 kb
Host smart-15168224-3094-4b2e-b5ab-78ab28d639bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231685896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4231685896
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.960047036
Short name T253
Test name
Test status
Simulation time 2101575052 ps
CPU time 7.69 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:11 PM PDT 24
Peak memory 218300 kb
Host smart-cedd898a-a027-4aaa-a60f-d0d545d6ec5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960047036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.960047036
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3549693934
Short name T586
Test name
Test status
Simulation time 175036987 ps
CPU time 3.78 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:09 PM PDT 24
Peak memory 214324 kb
Host smart-22511e17-e0db-4191-abe5-d20edc115e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549693934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3549693934
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2903797166
Short name T84
Test name
Test status
Simulation time 115948409 ps
CPU time 4.5 seconds
Started Jun 29 04:44:01 PM PDT 24
Finished Jun 29 04:44:07 PM PDT 24
Peak memory 214196 kb
Host smart-8dc16378-3f9d-4991-993b-342f6ad7ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903797166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2903797166
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1479727262
Short name T794
Test name
Test status
Simulation time 1666997903 ps
CPU time 4.53 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 209280 kb
Host smart-ff9c2ef6-a111-48be-965d-6b0c33c65684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479727262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1479727262
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1457317131
Short name T616
Test name
Test status
Simulation time 241007030 ps
CPU time 6.7 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 208772 kb
Host smart-6f74a648-26e6-4d7c-9664-1f18b27b305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457317131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1457317131
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3597005456
Short name T562
Test name
Test status
Simulation time 1000388770 ps
CPU time 33.6 seconds
Started Jun 29 04:44:04 PM PDT 24
Finished Jun 29 04:44:39 PM PDT 24
Peak memory 208980 kb
Host smart-5e8a9e1c-6530-4a89-a6b7-3de29515508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597005456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3597005456
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3104141209
Short name T525
Test name
Test status
Simulation time 1086953154 ps
CPU time 5.55 seconds
Started Jun 29 04:44:04 PM PDT 24
Finished Jun 29 04:44:13 PM PDT 24
Peak memory 206944 kb
Host smart-869b2832-0e2b-4057-9c47-4365137aee86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104141209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3104141209
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.167367595
Short name T636
Test name
Test status
Simulation time 82016028 ps
CPU time 2.91 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:11 PM PDT 24
Peak memory 206912 kb
Host smart-f719962a-95e7-4119-9997-2e5b9620d7b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167367595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.167367595
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.616326151
Short name T458
Test name
Test status
Simulation time 115510686 ps
CPU time 3.88 seconds
Started Jun 29 04:44:07 PM PDT 24
Finished Jun 29 04:44:13 PM PDT 24
Peak memory 208528 kb
Host smart-eaf7c057-54e8-4f74-89c5-d2351c1311d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616326151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.616326151
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2597676222
Short name T646
Test name
Test status
Simulation time 239433696 ps
CPU time 6.19 seconds
Started Jun 29 04:44:07 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 208252 kb
Host smart-e9f568b4-1f4f-4f96-92da-a26af7a9f442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597676222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2597676222
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3567824349
Short name T724
Test name
Test status
Simulation time 53819148 ps
CPU time 2.47 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:10 PM PDT 24
Peak memory 206912 kb
Host smart-a8d61cc5-68fa-4dc8-abab-c3b6bfb5730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567824349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3567824349
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.562858135
Short name T822
Test name
Test status
Simulation time 447943483 ps
CPU time 23.03 seconds
Started Jun 29 04:44:04 PM PDT 24
Finished Jun 29 04:44:28 PM PDT 24
Peak memory 222688 kb
Host smart-23a632e0-e243-43cb-8110-704d56faa357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562858135 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.562858135
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.689392789
Short name T883
Test name
Test status
Simulation time 442022806 ps
CPU time 4.06 seconds
Started Jun 29 04:44:01 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 207276 kb
Host smart-29f5a218-fc97-4da5-9f80-d4ae579b2660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689392789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.689392789
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4170205356
Short name T652
Test name
Test status
Simulation time 107997684 ps
CPU time 3.99 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 210480 kb
Host smart-6f1b715b-b511-483c-ba89-baa817ceeb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170205356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4170205356
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2397346738
Short name T732
Test name
Test status
Simulation time 10971521 ps
CPU time 0.86 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 206048 kb
Host smart-f890472b-c21f-4da2-a96a-7393aa520a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397346738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2397346738
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4260390437
Short name T432
Test name
Test status
Simulation time 215850166 ps
CPU time 4.08 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:09 PM PDT 24
Peak memory 214332 kb
Host smart-9896b8ef-f91b-4e2f-8761-c06a6f307e4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260390437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4260390437
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4237197021
Short name T28
Test name
Test status
Simulation time 128372482 ps
CPU time 4.95 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:17 PM PDT 24
Peak memory 218340 kb
Host smart-c2de2e11-318c-4e0a-a675-0a166f7e0693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237197021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4237197021
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1954673185
Short name T69
Test name
Test status
Simulation time 474401983 ps
CPU time 9.3 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 209608 kb
Host smart-65a08022-faac-420d-9c1b-4caf00b9079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954673185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1954673185
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3056869303
Short name T897
Test name
Test status
Simulation time 99237736 ps
CPU time 2.02 seconds
Started Jun 29 04:44:01 PM PDT 24
Finished Jun 29 04:44:04 PM PDT 24
Peak memory 214324 kb
Host smart-bf9a7748-473e-4292-9c55-5f41c6d07c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056869303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3056869303
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2107010561
Short name T826
Test name
Test status
Simulation time 61944473 ps
CPU time 2.82 seconds
Started Jun 29 04:44:03 PM PDT 24
Finished Jun 29 04:44:07 PM PDT 24
Peak memory 210076 kb
Host smart-fb23b9a1-4053-4cd6-aa4f-44d202a0cbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107010561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2107010561
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1593167381
Short name T892
Test name
Test status
Simulation time 236265272 ps
CPU time 6.98 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 208196 kb
Host smart-3e2803e0-ca0a-4df1-b4ba-af7005d042be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593167381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1593167381
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3941723478
Short name T365
Test name
Test status
Simulation time 692536289 ps
CPU time 11.55 seconds
Started Jun 29 04:44:04 PM PDT 24
Finished Jun 29 04:44:17 PM PDT 24
Peak memory 208740 kb
Host smart-aeb6dda5-26b2-46d6-add6-2cde6cb22396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941723478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3941723478
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.193407407
Short name T262
Test name
Test status
Simulation time 36120763 ps
CPU time 2.33 seconds
Started Jun 29 04:44:05 PM PDT 24
Finished Jun 29 04:44:10 PM PDT 24
Peak memory 206904 kb
Host smart-bd240786-e085-4e31-8ec0-b7b0e3989100
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193407407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.193407407
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2549379361
Short name T611
Test name
Test status
Simulation time 3186727437 ps
CPU time 16.08 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 208376 kb
Host smart-6151a288-67b5-4062-9a08-7e271c647330
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549379361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2549379361
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.609399669
Short name T500
Test name
Test status
Simulation time 374935017 ps
CPU time 7.24 seconds
Started Jun 29 04:44:06 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 207992 kb
Host smart-6d27ecdc-f08c-49d2-93e5-9a905ece1172
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609399669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.609399669
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1623858069
Short name T536
Test name
Test status
Simulation time 184279162 ps
CPU time 2.74 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 209912 kb
Host smart-ba97d0c7-8e2b-411d-8386-99fd4a6b2755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623858069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1623858069
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1722805910
Short name T886
Test name
Test status
Simulation time 147641391 ps
CPU time 2.22 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:05 PM PDT 24
Peak memory 206840 kb
Host smart-958d510f-19e4-4780-bd1e-05557bd4237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722805910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1722805910
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.690163627
Short name T75
Test name
Test status
Simulation time 2410136203 ps
CPU time 24.73 seconds
Started Jun 29 04:44:12 PM PDT 24
Finished Jun 29 04:44:38 PM PDT 24
Peak memory 215860 kb
Host smart-29e5bbe9-32d3-4729-854f-1d326183d56e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690163627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.690163627
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3504280492
Short name T511
Test name
Test status
Simulation time 263760487 ps
CPU time 2.99 seconds
Started Jun 29 04:44:02 PM PDT 24
Finished Jun 29 04:44:06 PM PDT 24
Peak memory 208352 kb
Host smart-23f44b64-db91-4e33-b5ea-e29779e0c7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504280492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3504280492
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.622909681
Short name T55
Test name
Test status
Simulation time 38163707 ps
CPU time 1.58 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 209784 kb
Host smart-96ecd8ca-000d-4774-9550-4e4cf70ea107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622909681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.622909681
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1754174535
Short name T452
Test name
Test status
Simulation time 13865795 ps
CPU time 0.89 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 206052 kb
Host smart-0be4235a-67dd-4f92-ac20-6ca37368668c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754174535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1754174535
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.856885023
Short name T582
Test name
Test status
Simulation time 628513788 ps
CPU time 4.75 seconds
Started Jun 29 04:44:11 PM PDT 24
Finished Jun 29 04:44:17 PM PDT 24
Peak memory 214696 kb
Host smart-5a0aea69-cb9d-42b7-a27d-d72cc1ed963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856885023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.856885023
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.713208613
Short name T255
Test name
Test status
Simulation time 139983213 ps
CPU time 3.35 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 214316 kb
Host smart-6472ede6-1a89-414e-94d9-9d5e94c4fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713208613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.713208613
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1315919799
Short name T578
Test name
Test status
Simulation time 43585638 ps
CPU time 3.02 seconds
Started Jun 29 04:44:08 PM PDT 24
Finished Jun 29 04:44:13 PM PDT 24
Peak memory 214348 kb
Host smart-de687645-10b2-41bf-8803-5d0560610924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315919799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1315919799
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1281422179
Short name T244
Test name
Test status
Simulation time 351881198 ps
CPU time 3.53 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 214264 kb
Host smart-691c84e5-b7ef-4d5b-95d7-32325a80bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281422179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1281422179
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2351909292
Short name T844
Test name
Test status
Simulation time 221024979 ps
CPU time 3.25 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 209984 kb
Host smart-2207d95f-120b-48da-afd8-6908fb2aa47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351909292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2351909292
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1892905120
Short name T653
Test name
Test status
Simulation time 310273759 ps
CPU time 7.73 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:31 PM PDT 24
Peak memory 208168 kb
Host smart-30f9ac4e-6ffc-47d5-993e-cf590590f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892905120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1892905120
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3519117192
Short name T318
Test name
Test status
Simulation time 97004061 ps
CPU time 3.79 seconds
Started Jun 29 04:44:11 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 208696 kb
Host smart-e13dc8fb-ba23-4c2d-8130-1373c3736efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519117192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3519117192
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3538572685
Short name T741
Test name
Test status
Simulation time 120266817 ps
CPU time 4.11 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 208528 kb
Host smart-523ef157-cd55-4584-a076-b2118abf0589
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538572685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3538572685
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1923967063
Short name T643
Test name
Test status
Simulation time 158528811 ps
CPU time 3.84 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 208916 kb
Host smart-942fb498-4cf8-4c58-a234-75e35a039358
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923967063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1923967063
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.736623741
Short name T502
Test name
Test status
Simulation time 459778485 ps
CPU time 3.1 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 207024 kb
Host smart-18697242-5f54-44b4-a898-a45648b84a18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736623741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.736623741
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3297449472
Short name T839
Test name
Test status
Simulation time 756711314 ps
CPU time 9.48 seconds
Started Jun 29 04:44:11 PM PDT 24
Finished Jun 29 04:44:22 PM PDT 24
Peak memory 208520 kb
Host smart-2eca8416-0585-481a-a021-984abb4f6a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297449472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3297449472
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3165023863
Short name T739
Test name
Test status
Simulation time 1085346067 ps
CPU time 3.39 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 206920 kb
Host smart-78914e1e-f48d-40ee-9cc1-19090e96677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165023863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3165023863
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1650896908
Short name T296
Test name
Test status
Simulation time 242388994 ps
CPU time 6.59 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:18 PM PDT 24
Peak memory 210176 kb
Host smart-de4e77c3-9981-4985-a105-a4ae19e8e672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650896908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1650896908
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3759881937
Short name T83
Test name
Test status
Simulation time 97545398 ps
CPU time 1.45 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:13 PM PDT 24
Peak memory 209748 kb
Host smart-f4aa510a-c1cb-481f-9ecd-6819f8810407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759881937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3759881937
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.816134832
Short name T468
Test name
Test status
Simulation time 12823709 ps
CPU time 0.86 seconds
Started Jun 29 04:44:12 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 205956 kb
Host smart-4d1ed5ff-ab8d-4362-80b2-57f5ee8729ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816134832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.816134832
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.233546336
Short name T29
Test name
Test status
Simulation time 119738425 ps
CPU time 4.85 seconds
Started Jun 29 04:44:12 PM PDT 24
Finished Jun 29 04:44:18 PM PDT 24
Peak memory 214216 kb
Host smart-3946f71f-ba9e-4505-87e2-01afef535572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233546336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.233546336
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3846360596
Short name T903
Test name
Test status
Simulation time 95841066 ps
CPU time 4.15 seconds
Started Jun 29 04:44:13 PM PDT 24
Finished Jun 29 04:44:18 PM PDT 24
Peak memory 210336 kb
Host smart-c3912bd3-11d2-4591-a0dc-5d4eea00f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846360596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3846360596
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2810955973
Short name T94
Test name
Test status
Simulation time 1509368307 ps
CPU time 19.94 seconds
Started Jun 29 04:44:08 PM PDT 24
Finished Jun 29 04:44:30 PM PDT 24
Peak memory 214316 kb
Host smart-354319ca-5128-4d88-8c57-adb732cf13cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810955973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2810955973
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.543724784
Short name T97
Test name
Test status
Simulation time 139458213 ps
CPU time 2.77 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 211536 kb
Host smart-e75d7556-434e-4ff5-a377-f622a986cf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543724784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.543724784
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4186341500
Short name T224
Test name
Test status
Simulation time 464051958 ps
CPU time 3.6 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 215832 kb
Host smart-1ee34512-6e5e-4770-9ad8-0b3c3ec869dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186341500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4186341500
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.524725125
Short name T790
Test name
Test status
Simulation time 307510065 ps
CPU time 3.77 seconds
Started Jun 29 04:44:09 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 208660 kb
Host smart-0ec12d0c-849b-43cb-83eb-c9ea6b4d631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524725125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.524725125
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1848956623
Short name T728
Test name
Test status
Simulation time 26793721 ps
CPU time 2.12 seconds
Started Jun 29 04:44:13 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 208380 kb
Host smart-6e96c79a-b0c1-4382-ac5b-dda384b21609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848956623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1848956623
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1584795575
Short name T801
Test name
Test status
Simulation time 50867236 ps
CPU time 2.6 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 208212 kb
Host smart-34b04603-123c-4846-8054-3af6d98cc39b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584795575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1584795575
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3711962527
Short name T824
Test name
Test status
Simulation time 206610207 ps
CPU time 2.69 seconds
Started Jun 29 04:44:07 PM PDT 24
Finished Jun 29 04:44:11 PM PDT 24
Peak memory 208164 kb
Host smart-e6cdd3cc-8b89-4a97-a622-785c43fe0318
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711962527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3711962527
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.928703559
Short name T343
Test name
Test status
Simulation time 226150090 ps
CPU time 3.3 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 208736 kb
Host smart-35f0f27c-3570-4905-8d55-62114ba5a1b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928703559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.928703559
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2171843685
Short name T203
Test name
Test status
Simulation time 69026231 ps
CPU time 2.67 seconds
Started Jun 29 04:44:08 PM PDT 24
Finished Jun 29 04:44:12 PM PDT 24
Peak memory 214356 kb
Host smart-55503ba8-5976-47a9-a03f-54e968d6be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171843685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2171843685
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3330884904
Short name T15
Test name
Test status
Simulation time 151689250 ps
CPU time 4.13 seconds
Started Jun 29 04:44:10 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 208504 kb
Host smart-cd65fea4-9593-4222-998c-27758ec19811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330884904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3330884904
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.262646252
Short name T356
Test name
Test status
Simulation time 1269262713 ps
CPU time 9.78 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:33 PM PDT 24
Peak memory 218284 kb
Host smart-e0c279b2-2b78-4428-87f5-bf51097b6963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262646252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.262646252
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1589180716
Short name T905
Test name
Test status
Simulation time 92915488 ps
CPU time 2.05 seconds
Started Jun 29 04:44:14 PM PDT 24
Finished Jun 29 04:44:16 PM PDT 24
Peak memory 209916 kb
Host smart-b67140a9-7ba8-4ec4-8100-7e7af0b2a386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589180716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1589180716
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2982842842
Short name T787
Test name
Test status
Simulation time 11550443 ps
CPU time 0.9 seconds
Started Jun 29 04:44:19 PM PDT 24
Finished Jun 29 04:44:21 PM PDT 24
Peak memory 206064 kb
Host smart-1c0d3379-e519-4f3b-bee5-07977b6b8837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982842842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2982842842
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1731667669
Short name T10
Test name
Test status
Simulation time 70382202 ps
CPU time 2.6 seconds
Started Jun 29 04:44:17 PM PDT 24
Finished Jun 29 04:44:21 PM PDT 24
Peak memory 214696 kb
Host smart-77998131-be8a-4c85-8056-cd282f775a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731667669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1731667669
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3042356216
Short name T593
Test name
Test status
Simulation time 22476656 ps
CPU time 1.43 seconds
Started Jun 29 04:44:20 PM PDT 24
Finished Jun 29 04:44:22 PM PDT 24
Peak memory 207052 kb
Host smart-6cea64d0-32d6-4f02-92e1-caffb894ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042356216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3042356216
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2622781343
Short name T45
Test name
Test status
Simulation time 480484433 ps
CPU time 5.7 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:29 PM PDT 24
Peak memory 214680 kb
Host smart-4a6ceae9-3647-4b81-85bf-063f5b6abb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622781343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2622781343
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4262402258
Short name T272
Test name
Test status
Simulation time 979441407 ps
CPU time 5.54 seconds
Started Jun 29 04:44:25 PM PDT 24
Finished Jun 29 04:44:31 PM PDT 24
Peak memory 222196 kb
Host smart-997fedc9-e958-4c98-8331-3fa016426492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262402258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4262402258
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2810673030
Short name T56
Test name
Test status
Simulation time 1223156978 ps
CPU time 4.89 seconds
Started Jun 29 04:44:17 PM PDT 24
Finished Jun 29 04:44:23 PM PDT 24
Peak memory 218768 kb
Host smart-4ab497a8-889c-4bda-a2e0-36ccf8469cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810673030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2810673030
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2075972994
Short name T818
Test name
Test status
Simulation time 80646268 ps
CPU time 2.02 seconds
Started Jun 29 04:44:11 PM PDT 24
Finished Jun 29 04:44:14 PM PDT 24
Peak memory 207964 kb
Host smart-faf7402d-09dd-481a-b6a2-afa16eb424aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075972994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2075972994
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2850553332
Short name T604
Test name
Test status
Simulation time 471189414 ps
CPU time 3.94 seconds
Started Jun 29 04:44:13 PM PDT 24
Finished Jun 29 04:44:17 PM PDT 24
Peak memory 208356 kb
Host smart-28147e15-5b5b-4427-ba32-02e74fadab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850553332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2850553332
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2162052154
Short name T204
Test name
Test status
Simulation time 97894570 ps
CPU time 3.22 seconds
Started Jun 29 04:44:14 PM PDT 24
Finished Jun 29 04:44:18 PM PDT 24
Peak memory 206944 kb
Host smart-73925322-8f4a-4cc2-a0c7-a6e1f454bac8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162052154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2162052154
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1714631590
Short name T532
Test name
Test status
Simulation time 25888136 ps
CPU time 1.83 seconds
Started Jun 29 04:44:12 PM PDT 24
Finished Jun 29 04:44:15 PM PDT 24
Peak memory 207668 kb
Host smart-0dd60e5c-5d5a-48f6-94b5-047d307ee88f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714631590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1714631590
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2103376011
Short name T566
Test name
Test status
Simulation time 244877492 ps
CPU time 3.29 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 206924 kb
Host smart-90dcfec6-7fe1-4823-a530-a1f072062233
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103376011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2103376011
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.730577597
Short name T756
Test name
Test status
Simulation time 407026705 ps
CPU time 3.08 seconds
Started Jun 29 04:44:20 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 214324 kb
Host smart-fc05643c-575e-4201-a34f-53b40dcfdae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730577597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.730577597
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.153157669
Short name T569
Test name
Test status
Simulation time 6828947819 ps
CPU time 29.5 seconds
Started Jun 29 04:44:11 PM PDT 24
Finished Jun 29 04:44:41 PM PDT 24
Peak memory 208384 kb
Host smart-1993bc73-2120-417f-8104-ead538eb135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153157669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.153157669
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.7002458
Short name T753
Test name
Test status
Simulation time 166507573 ps
CPU time 7.04 seconds
Started Jun 29 04:44:25 PM PDT 24
Finished Jun 29 04:44:33 PM PDT 24
Peak memory 209140 kb
Host smart-3584f38d-3bbc-4faa-8eff-0d6ed49f468b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7002458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.7002458
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.489870068
Short name T334
Test name
Test status
Simulation time 1466819163 ps
CPU time 11.68 seconds
Started Jun 29 04:44:19 PM PDT 24
Finished Jun 29 04:44:31 PM PDT 24
Peak memory 208184 kb
Host smart-4ca63a23-08be-46c6-8583-6746b15286ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489870068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.489870068
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2023434481
Short name T523
Test name
Test status
Simulation time 232676500 ps
CPU time 1.95 seconds
Started Jun 29 04:44:24 PM PDT 24
Finished Jun 29 04:44:27 PM PDT 24
Peak memory 210328 kb
Host smart-fdec02ec-61de-4451-a752-65f0df8decf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023434481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2023434481
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2889747920
Short name T726
Test name
Test status
Simulation time 10939591 ps
CPU time 0.78 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 206064 kb
Host smart-dc6f87bc-37b9-41bf-b28d-43aebd7d8008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889747920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2889747920
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2064575441
Short name T714
Test name
Test status
Simulation time 347689831 ps
CPU time 2.73 seconds
Started Jun 29 04:44:25 PM PDT 24
Finished Jun 29 04:44:29 PM PDT 24
Peak memory 220476 kb
Host smart-56342c9d-4b4f-496e-ae46-d84f7578382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064575441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2064575441
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1432786707
Short name T615
Test name
Test status
Simulation time 102839007 ps
CPU time 3.48 seconds
Started Jun 29 04:44:18 PM PDT 24
Finished Jun 29 04:44:23 PM PDT 24
Peak memory 214236 kb
Host smart-47ea6a09-2731-4bc3-ab35-e54507e7f6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432786707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1432786707
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2898828770
Short name T257
Test name
Test status
Simulation time 296211110 ps
CPU time 6.18 seconds
Started Jun 29 04:44:19 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 214240 kb
Host smart-f3b67196-e4a6-4ac8-8c40-305d3cd58c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898828770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2898828770
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.252203424
Short name T290
Test name
Test status
Simulation time 67870187 ps
CPU time 3.96 seconds
Started Jun 29 04:44:18 PM PDT 24
Finished Jun 29 04:44:23 PM PDT 24
Peak memory 220644 kb
Host smart-876ee20d-4087-4134-9de2-2280c2d8e541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252203424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.252203424
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2122857365
Short name T179
Test name
Test status
Simulation time 64479804 ps
CPU time 3.03 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 214368 kb
Host smart-2e4243bf-12f1-4232-8923-f40b8e7ae99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122857365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2122857365
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1556268936
Short name T715
Test name
Test status
Simulation time 7034622750 ps
CPU time 48.69 seconds
Started Jun 29 04:44:18 PM PDT 24
Finished Jun 29 04:45:08 PM PDT 24
Peak memory 209380 kb
Host smart-4fc3d7ed-3cf3-44f3-a063-8d0eac4fe468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556268936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1556268936
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2990975281
Short name T793
Test name
Test status
Simulation time 184770882 ps
CPU time 6.37 seconds
Started Jun 29 04:44:17 PM PDT 24
Finished Jun 29 04:44:25 PM PDT 24
Peak memory 208360 kb
Host smart-e6869c5c-acc6-45aa-baf8-ac1dd44971ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990975281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2990975281
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2810487570
Short name T590
Test name
Test status
Simulation time 228994774 ps
CPU time 7.11 seconds
Started Jun 29 04:44:19 PM PDT 24
Finished Jun 29 04:44:27 PM PDT 24
Peak memory 208048 kb
Host smart-61f34194-bb55-4568-858e-9e6ced6a3efa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810487570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2810487570
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.385541174
Short name T425
Test name
Test status
Simulation time 50013720 ps
CPU time 2.91 seconds
Started Jun 29 04:44:20 PM PDT 24
Finished Jun 29 04:44:24 PM PDT 24
Peak memory 206848 kb
Host smart-7fc1e831-baf3-41c0-9abc-f52ad26ef303
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385541174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.385541174
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3615228722
Short name T109
Test name
Test status
Simulation time 290368048 ps
CPU time 5.13 seconds
Started Jun 29 04:44:19 PM PDT 24
Finished Jun 29 04:44:25 PM PDT 24
Peak memory 208564 kb
Host smart-313129aa-f731-47af-9133-f4ec04ba67ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615228722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3615228722
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.481310673
Short name T791
Test name
Test status
Simulation time 160765820 ps
CPU time 2.19 seconds
Started Jun 29 04:44:22 PM PDT 24
Finished Jun 29 04:44:25 PM PDT 24
Peak memory 209108 kb
Host smart-985c3f02-f53f-4de6-a583-c069f1f1b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481310673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.481310673
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2649347160
Short name T478
Test name
Test status
Simulation time 839436629 ps
CPU time 5.02 seconds
Started Jun 29 04:44:17 PM PDT 24
Finished Jun 29 04:44:23 PM PDT 24
Peak memory 206928 kb
Host smart-a5126de7-6c89-4b92-9853-189fa61b6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649347160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2649347160
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.857853422
Short name T881
Test name
Test status
Simulation time 66888304 ps
CPU time 0.72 seconds
Started Jun 29 04:44:18 PM PDT 24
Finished Jun 29 04:44:19 PM PDT 24
Peak memory 205904 kb
Host smart-cbe2efcb-13db-4c03-83cf-2c6a32a02b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857853422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.857853422
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2823419808
Short name T687
Test name
Test status
Simulation time 153278117 ps
CPU time 4.69 seconds
Started Jun 29 04:44:21 PM PDT 24
Finished Jun 29 04:44:26 PM PDT 24
Peak memory 208004 kb
Host smart-c2763921-887f-452c-ae99-1e53b9568552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823419808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2823419808
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1785857668
Short name T130
Test name
Test status
Simulation time 215756228 ps
CPU time 2.74 seconds
Started Jun 29 04:44:25 PM PDT 24
Finished Jun 29 04:44:28 PM PDT 24
Peak memory 209972 kb
Host smart-4ea69ad8-1fe0-4cb6-afa1-21b74352f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785857668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1785857668
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1092963872
Short name T854
Test name
Test status
Simulation time 70287003 ps
CPU time 0.79 seconds
Started Jun 29 04:41:50 PM PDT 24
Finished Jun 29 04:41:52 PM PDT 24
Peak memory 205980 kb
Host smart-af307fc3-3dcc-414e-80aa-402ab66d7b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092963872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1092963872
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1804143420
Short name T435
Test name
Test status
Simulation time 122711132 ps
CPU time 4.56 seconds
Started Jun 29 04:41:53 PM PDT 24
Finished Jun 29 04:41:58 PM PDT 24
Peak memory 215684 kb
Host smart-94a68fd7-ae40-4f4e-a0a4-b5fede9fe093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804143420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1804143420
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2427431329
Short name T745
Test name
Test status
Simulation time 52677126 ps
CPU time 3.31 seconds
Started Jun 29 04:41:50 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 222860 kb
Host smart-bf8cbe86-9a97-434e-9ed4-27a06ad2fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427431329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2427431329
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2092073116
Short name T504
Test name
Test status
Simulation time 143328720 ps
CPU time 2.72 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 208984 kb
Host smart-74a2f121-6559-4686-a566-7ce9a9db33db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092073116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2092073116
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2801196234
Short name T610
Test name
Test status
Simulation time 91026894 ps
CPU time 2.1 seconds
Started Jun 29 04:41:55 PM PDT 24
Finished Jun 29 04:41:57 PM PDT 24
Peak memory 214340 kb
Host smart-017219ac-b41a-4b03-b43c-75204fa82f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801196234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2801196234
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1321791708
Short name T438
Test name
Test status
Simulation time 160363519 ps
CPU time 2.89 seconds
Started Jun 29 04:41:54 PM PDT 24
Finished Jun 29 04:41:57 PM PDT 24
Peak memory 214148 kb
Host smart-3bff6740-085a-41a2-bedc-db886bcab4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321791708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1321791708
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.707190541
Short name T483
Test name
Test status
Simulation time 72508394 ps
CPU time 3.17 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:55 PM PDT 24
Peak memory 206116 kb
Host smart-0b0b1205-3599-46e9-b5f7-7fa33500071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707190541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.707190541
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3253572554
Short name T807
Test name
Test status
Simulation time 176934332 ps
CPU time 4.65 seconds
Started Jun 29 04:41:53 PM PDT 24
Finished Jun 29 04:41:58 PM PDT 24
Peak memory 207576 kb
Host smart-a7689b0d-1f25-40aa-a0d8-39d845d08827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253572554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3253572554
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3891855523
Short name T564
Test name
Test status
Simulation time 40944474 ps
CPU time 2.67 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 208444 kb
Host smart-c16a306f-d59e-4ee5-9ed1-e889cdc84d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891855523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3891855523
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2189595748
Short name T299
Test name
Test status
Simulation time 83694690 ps
CPU time 3.12 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:55 PM PDT 24
Peak memory 206980 kb
Host smart-7d93cd60-7dfb-4dbb-b6af-a96ee468f045
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189595748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2189595748
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.155369632
Short name T384
Test name
Test status
Simulation time 595390622 ps
CPU time 2.76 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 208504 kb
Host smart-106feb6c-3648-4e5c-897a-bafae4a2f993
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155369632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.155369632
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2261527559
Short name T760
Test name
Test status
Simulation time 1431375007 ps
CPU time 34.33 seconds
Started Jun 29 04:41:58 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 207984 kb
Host smart-b6a9c32a-bab0-4af5-9f62-7d02cf3e5cf5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261527559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2261527559
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.219695769
Short name T577
Test name
Test status
Simulation time 895879657 ps
CPU time 16.25 seconds
Started Jun 29 04:41:51 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 214412 kb
Host smart-836b488b-9cc7-4cde-b5be-79afa637a09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219695769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.219695769
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3219540294
Short name T669
Test name
Test status
Simulation time 116103919 ps
CPU time 3.06 seconds
Started Jun 29 04:41:54 PM PDT 24
Finished Jun 29 04:41:58 PM PDT 24
Peak memory 207912 kb
Host smart-c9781af4-0b73-4f2e-a1cc-37023b2b96b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219540294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3219540294
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.575188512
Short name T47
Test name
Test status
Simulation time 1389119464 ps
CPU time 30.4 seconds
Started Jun 29 04:41:54 PM PDT 24
Finished Jun 29 04:42:25 PM PDT 24
Peak memory 222488 kb
Host smart-509f59af-1126-4b40-a7a1-c6712484767b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575188512 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.575188512
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.689683404
Short name T199
Test name
Test status
Simulation time 304170759 ps
CPU time 5.37 seconds
Started Jun 29 04:41:58 PM PDT 24
Finished Jun 29 04:42:04 PM PDT 24
Peak memory 210164 kb
Host smart-7cf642b0-9b7c-4f6a-9eb1-a04106950da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689683404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.689683404
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1477927693
Short name T553
Test name
Test status
Simulation time 734094631 ps
CPU time 3.07 seconds
Started Jun 29 04:41:54 PM PDT 24
Finished Jun 29 04:41:57 PM PDT 24
Peak memory 210268 kb
Host smart-fd6f9a61-4338-43ca-a054-2ecbfa354fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477927693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1477927693
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.949123476
Short name T731
Test name
Test status
Simulation time 17291906 ps
CPU time 0.91 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:02 PM PDT 24
Peak memory 206160 kb
Host smart-74fe6258-9743-4961-904e-924c1ad0e597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949123476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.949123476
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2079412922
Short name T235
Test name
Test status
Simulation time 438854106 ps
CPU time 5.93 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:07 PM PDT 24
Peak memory 214752 kb
Host smart-55c106a5-6c14-43b3-a508-3c22cc445a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079412922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2079412922
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.307499643
Short name T65
Test name
Test status
Simulation time 143846808 ps
CPU time 4.29 seconds
Started Jun 29 04:42:03 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 221776 kb
Host smart-69b59a2e-e10b-44d6-a326-27ed5136e949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307499643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.307499643
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2519723772
Short name T680
Test name
Test status
Simulation time 207942068 ps
CPU time 3.95 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 214316 kb
Host smart-ee084663-520e-425b-a2c6-ff650fe9c065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519723772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2519723772
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1445443062
Short name T852
Test name
Test status
Simulation time 91208011 ps
CPU time 4.36 seconds
Started Jun 29 04:42:05 PM PDT 24
Finished Jun 29 04:42:10 PM PDT 24
Peak memory 217436 kb
Host smart-a340dd2e-c2d4-457c-809c-08b11d605674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445443062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1445443062
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1110348850
Short name T873
Test name
Test status
Simulation time 417180038 ps
CPU time 4.39 seconds
Started Jun 29 04:42:05 PM PDT 24
Finished Jun 29 04:42:10 PM PDT 24
Peak memory 222384 kb
Host smart-7f8a0d64-86d0-4d83-a98d-192a34f7db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110348850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1110348850
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3500109704
Short name T180
Test name
Test status
Simulation time 84933828 ps
CPU time 3.45 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:04 PM PDT 24
Peak memory 220572 kb
Host smart-0cd336b7-073d-4201-9fb1-87ad25a99e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500109704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3500109704
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2399856975
Short name T666
Test name
Test status
Simulation time 223508057 ps
CPU time 3.48 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 207752 kb
Host smart-1708c455-fb6e-4f8c-9526-d16549507d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399856975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2399856975
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1389080628
Short name T303
Test name
Test status
Simulation time 75474319 ps
CPU time 3.55 seconds
Started Jun 29 04:41:55 PM PDT 24
Finished Jun 29 04:41:59 PM PDT 24
Peak memory 208796 kb
Host smart-313c7f4f-eac9-441a-b42b-0b53bb5b89a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389080628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1389080628
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4071700169
Short name T507
Test name
Test status
Simulation time 855075618 ps
CPU time 21.3 seconds
Started Jun 29 04:41:58 PM PDT 24
Finished Jun 29 04:42:20 PM PDT 24
Peak memory 208848 kb
Host smart-e7f71bef-735e-4388-ac71-50d44fa084b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071700169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4071700169
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2688173558
Short name T842
Test name
Test status
Simulation time 20502928410 ps
CPU time 32.45 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:33 PM PDT 24
Peak memory 208204 kb
Host smart-8fd387cc-6895-4d47-86c8-6b56d0b3a6be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688173558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2688173558
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.550846215
Short name T783
Test name
Test status
Simulation time 262905595 ps
CPU time 4.13 seconds
Started Jun 29 04:41:59 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 208748 kb
Host smart-d8ebf2c4-faa6-44a0-8600-047a36b32ee4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550846215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.550846215
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2374819307
Short name T608
Test name
Test status
Simulation time 548704530 ps
CPU time 11.52 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:13 PM PDT 24
Peak memory 208888 kb
Host smart-73a0131b-9b03-4a86-8dae-6599da05a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374819307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2374819307
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3919693504
Short name T579
Test name
Test status
Simulation time 46281153 ps
CPU time 2.39 seconds
Started Jun 29 04:41:50 PM PDT 24
Finished Jun 29 04:41:53 PM PDT 24
Peak memory 208628 kb
Host smart-0791c2dc-4642-4f9a-9150-9dc1d6db784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919693504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3919693504
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3385557570
Short name T906
Test name
Test status
Simulation time 378771575 ps
CPU time 19.51 seconds
Started Jun 29 04:42:03 PM PDT 24
Finished Jun 29 04:42:23 PM PDT 24
Peak memory 214344 kb
Host smart-6154aade-e403-4f46-a99b-2ff83d3d42af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385557570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3385557570
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2347936726
Short name T515
Test name
Test status
Simulation time 168017095 ps
CPU time 4.14 seconds
Started Jun 29 04:41:59 PM PDT 24
Finished Jun 29 04:42:04 PM PDT 24
Peak memory 209244 kb
Host smart-788e836c-915a-4b5c-ba51-291aed9a6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347936726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2347936726
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3509849667
Short name T766
Test name
Test status
Simulation time 111245153 ps
CPU time 2.67 seconds
Started Jun 29 04:41:59 PM PDT 24
Finished Jun 29 04:42:02 PM PDT 24
Peak memory 209800 kb
Host smart-82c14cb3-ab4b-4a34-a2ad-00aed4c25b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509849667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3509849667
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4183842835
Short name T738
Test name
Test status
Simulation time 17791554 ps
CPU time 1 seconds
Started Jun 29 04:42:03 PM PDT 24
Finished Jun 29 04:42:04 PM PDT 24
Peak memory 206080 kb
Host smart-e91feae4-21a6-468e-9bd3-a66057cdf7b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183842835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4183842835
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1602253398
Short name T441
Test name
Test status
Simulation time 115605230 ps
CPU time 3.58 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 214744 kb
Host smart-4be828b5-f104-4f9d-9196-73b6f14ea0d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602253398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1602253398
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3799632129
Short name T25
Test name
Test status
Simulation time 96875809 ps
CPU time 4.63 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 217516 kb
Host smart-806b6795-6b84-48c8-8ce2-d64d49ff0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799632129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3799632129
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3125595997
Short name T624
Test name
Test status
Simulation time 3130983125 ps
CPU time 17.51 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:20 PM PDT 24
Peak memory 208692 kb
Host smart-2bbadf31-8fcd-400c-a0db-6c7057e763a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125595997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3125595997
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2633206752
Short name T743
Test name
Test status
Simulation time 74560244 ps
CPU time 3.88 seconds
Started Jun 29 04:41:59 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 214308 kb
Host smart-9c817360-5563-4cf6-a84d-3871ec20c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633206752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2633206752
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.4154961307
Short name T360
Test name
Test status
Simulation time 312608202 ps
CPU time 5.1 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 222488 kb
Host smart-92fb1aab-713b-4e42-9ea5-0ca2ef79239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154961307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.4154961307
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1826824179
Short name T227
Test name
Test status
Simulation time 180319565 ps
CPU time 2.79 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 208224 kb
Host smart-723f738d-2596-4599-9c99-3c59b981cf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826824179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1826824179
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2153423295
Short name T355
Test name
Test status
Simulation time 287226199 ps
CPU time 3.9 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 215184 kb
Host smart-0d6648e8-32a9-440e-a657-b65ca7753618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153423295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2153423295
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2470131811
Short name T348
Test name
Test status
Simulation time 631163303 ps
CPU time 4.4 seconds
Started Jun 29 04:42:03 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 208316 kb
Host smart-2bdb13d2-83f0-4cb0-b5dd-762d54c060fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470131811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2470131811
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2918455230
Short name T480
Test name
Test status
Simulation time 79945002 ps
CPU time 2.18 seconds
Started Jun 29 04:41:59 PM PDT 24
Finished Jun 29 04:42:02 PM PDT 24
Peak memory 206932 kb
Host smart-bcda26e2-9ff5-49a0-98cd-ca39029b332a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918455230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2918455230
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.735394492
Short name T917
Test name
Test status
Simulation time 198951151 ps
CPU time 4.57 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 208700 kb
Host smart-c36709d4-d836-4477-9332-1f874bfb72fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735394492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.735394492
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3010597898
Short name T85
Test name
Test status
Simulation time 1695670138 ps
CPU time 21.72 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:24 PM PDT 24
Peak memory 208784 kb
Host smart-ed3431c2-f871-44db-979c-2b6edd19aac1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010597898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3010597898
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3927379847
Short name T302
Test name
Test status
Simulation time 82968509 ps
CPU time 2.54 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 209608 kb
Host smart-9445c1a5-77ae-47ec-a2f4-e2ec8c1a29c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927379847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3927379847
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1298019986
Short name T557
Test name
Test status
Simulation time 138438949 ps
CPU time 3.26 seconds
Started Jun 29 04:42:02 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 208800 kb
Host smart-5308b704-9952-4631-b544-f0caee02175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298019986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1298019986
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3185611373
Short name T74
Test name
Test status
Simulation time 2606246808 ps
CPU time 28.06 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:28 PM PDT 24
Peak memory 222564 kb
Host smart-7b525c53-be70-4d08-bc8d-f9c0ebe15075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185611373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3185611373
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.971110490
Short name T789
Test name
Test status
Simulation time 468615826 ps
CPU time 4.41 seconds
Started Jun 29 04:42:04 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 214336 kb
Host smart-368ce345-0934-4c4c-b879-cb89fbbd66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971110490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.971110490
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2065195921
Short name T773
Test name
Test status
Simulation time 73395497 ps
CPU time 2.05 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 210260 kb
Host smart-50f4f4f8-7451-41fe-8844-e6ea488f9748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065195921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2065195921
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3080461167
Short name T477
Test name
Test status
Simulation time 10492730 ps
CPU time 0.85 seconds
Started Jun 29 04:42:15 PM PDT 24
Finished Jun 29 04:42:17 PM PDT 24
Peak memory 205936 kb
Host smart-1c14141d-0a1d-43d0-a6e6-ef5ea7e61827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080461167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3080461167
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2431888984
Short name T234
Test name
Test status
Simulation time 766329025 ps
CPU time 42.81 seconds
Started Jun 29 04:42:03 PM PDT 24
Finished Jun 29 04:42:46 PM PDT 24
Peak memory 214968 kb
Host smart-5eb4d072-bb28-4527-95b3-18a763b43edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431888984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2431888984
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2962580536
Short name T212
Test name
Test status
Simulation time 281421518 ps
CPU time 3.68 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 209264 kb
Host smart-a7adf142-3064-4f62-b947-7b560e3eec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962580536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2962580536
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3188437097
Short name T517
Test name
Test status
Simulation time 68211825 ps
CPU time 3.19 seconds
Started Jun 29 04:42:04 PM PDT 24
Finished Jun 29 04:42:07 PM PDT 24
Peak memory 214316 kb
Host smart-dc79c082-ece9-4e3d-91d7-e16da506d3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188437097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3188437097
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3334384404
Short name T685
Test name
Test status
Simulation time 1310893275 ps
CPU time 3.57 seconds
Started Jun 29 04:41:58 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 214328 kb
Host smart-f8638d94-2397-4777-b678-16b56889dc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334384404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3334384404
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4151861782
Short name T382
Test name
Test status
Simulation time 267595194 ps
CPU time 2.91 seconds
Started Jun 29 04:42:03 PM PDT 24
Finished Jun 29 04:42:06 PM PDT 24
Peak memory 214264 kb
Host smart-91b18904-55ca-4615-8a0d-92f2c05240dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151861782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4151861782
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1906800066
Short name T529
Test name
Test status
Simulation time 36205707 ps
CPU time 2.51 seconds
Started Jun 29 04:42:04 PM PDT 24
Finished Jun 29 04:42:07 PM PDT 24
Peak memory 209408 kb
Host smart-cccdf609-8ac6-4b83-97fe-5cb58e4e4aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906800066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1906800066
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2369082116
Short name T851
Test name
Test status
Simulation time 224960314 ps
CPU time 6.64 seconds
Started Jun 29 04:42:05 PM PDT 24
Finished Jun 29 04:42:12 PM PDT 24
Peak memory 209912 kb
Host smart-3c3aa663-7cb6-4c51-b9b4-79b96be28a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369082116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2369082116
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1605551511
Short name T792
Test name
Test status
Simulation time 222728698 ps
CPU time 6.13 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 208448 kb
Host smart-09ea5701-3b75-4cad-8398-114dd114c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605551511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1605551511
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4118631074
Short name T676
Test name
Test status
Simulation time 139842452 ps
CPU time 6 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:08 PM PDT 24
Peak memory 206752 kb
Host smart-11589567-2daf-45be-80e7-844f4c1948ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118631074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4118631074
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3299654857
Short name T540
Test name
Test status
Simulation time 66629137 ps
CPU time 3.3 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 208132 kb
Host smart-cec5e42c-33c6-4fe1-801e-30693e15e0e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299654857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3299654857
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.294855633
Short name T549
Test name
Test status
Simulation time 248938565 ps
CPU time 6.93 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:09 PM PDT 24
Peak memory 208884 kb
Host smart-18505dfc-0424-4237-8bac-3ebd415a201a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294855633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.294855633
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2804282533
Short name T861
Test name
Test status
Simulation time 56652038 ps
CPU time 2.15 seconds
Started Jun 29 04:42:01 PM PDT 24
Finished Jun 29 04:42:04 PM PDT 24
Peak memory 214352 kb
Host smart-c794bcaa-7d92-431b-8ef0-d5aa9d17c822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804282533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2804282533
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.503980764
Short name T686
Test name
Test status
Simulation time 178407626 ps
CPU time 4.05 seconds
Started Jun 29 04:42:00 PM PDT 24
Finished Jun 29 04:42:05 PM PDT 24
Peak memory 208072 kb
Host smart-c4bf6ff8-2460-4a28-a2ed-2e45f5af959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503980764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.503980764
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2406951646
Short name T231
Test name
Test status
Simulation time 5281197794 ps
CPU time 40.04 seconds
Started Jun 29 04:42:09 PM PDT 24
Finished Jun 29 04:42:50 PM PDT 24
Peak memory 222244 kb
Host smart-d223cb4b-4e03-4f0f-8a98-3cda2eacb93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406951646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2406951646
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1225052200
Short name T684
Test name
Test status
Simulation time 2400052987 ps
CPU time 11.37 seconds
Started Jun 29 04:42:02 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 214452 kb
Host smart-8565a642-94f2-4b99-847d-73e5fbfe3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225052200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1225052200
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2581277643
Short name T767
Test name
Test status
Simulation time 37739468 ps
CPU time 2.09 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:11 PM PDT 24
Peak memory 210136 kb
Host smart-d0c8a040-a0aa-4468-90a0-b1f9f938986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581277643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2581277643
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3122773063
Short name T2
Test name
Test status
Simulation time 16481281 ps
CPU time 0.77 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:11 PM PDT 24
Peak memory 205936 kb
Host smart-4c1272f7-0aa4-4ee9-ad68-5f0235638f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122773063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3122773063
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2093370841
Short name T442
Test name
Test status
Simulation time 1386023759 ps
CPU time 18.61 seconds
Started Jun 29 04:42:11 PM PDT 24
Finished Jun 29 04:42:30 PM PDT 24
Peak memory 214388 kb
Host smart-6bcfe8e1-b1a9-40b1-8107-0588e8f11331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093370841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2093370841
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1347529654
Short name T371
Test name
Test status
Simulation time 173026341 ps
CPU time 2.91 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:13 PM PDT 24
Peak memory 218092 kb
Host smart-c8c42bbb-ac5f-4b0f-b77f-1bb4555e36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347529654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1347529654
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2647956611
Short name T874
Test name
Test status
Simulation time 171400103 ps
CPU time 2.14 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:11 PM PDT 24
Peak memory 210080 kb
Host smart-44bbaf8c-f6c1-4872-8a35-a398095a1e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647956611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2647956611
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1056994157
Short name T898
Test name
Test status
Simulation time 292444490 ps
CPU time 3.62 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:12 PM PDT 24
Peak memory 214340 kb
Host smart-7f7127b0-caec-4d7c-80cf-4512ab66adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056994157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1056994157
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.527201155
Short name T736
Test name
Test status
Simulation time 83007657 ps
CPU time 3.7 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:15 PM PDT 24
Peak memory 214176 kb
Host smart-940411c9-755e-4c02-85e6-6f531909a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527201155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.527201155
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3145608160
Short name T849
Test name
Test status
Simulation time 57068179 ps
CPU time 2.1 seconds
Started Jun 29 04:42:07 PM PDT 24
Finished Jun 29 04:42:10 PM PDT 24
Peak memory 214264 kb
Host smart-5dfeb3f3-6b78-4fef-a055-187f50d26c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145608160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3145608160
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1058186832
Short name T423
Test name
Test status
Simulation time 186281158 ps
CPU time 5.75 seconds
Started Jun 29 04:42:09 PM PDT 24
Finished Jun 29 04:42:16 PM PDT 24
Peak memory 207540 kb
Host smart-72ce8c50-0588-45c6-a6c5-475ed1b91e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058186832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1058186832
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3960796112
Short name T752
Test name
Test status
Simulation time 34536535 ps
CPU time 2.02 seconds
Started Jun 29 04:42:11 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 206720 kb
Host smart-f781864f-38b6-43e5-b8db-719d4b75c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960796112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3960796112
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.392703268
Short name T537
Test name
Test status
Simulation time 1012775628 ps
CPU time 7.2 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:18 PM PDT 24
Peak memory 208136 kb
Host smart-cea55202-68ce-4d25-9d4b-e39d35ee7066
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392703268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.392703268
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2779427490
Short name T501
Test name
Test status
Simulation time 432894314 ps
CPU time 3.77 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:15 PM PDT 24
Peak memory 206972 kb
Host smart-bc0115a2-044e-4c71-a897-5d9cc1771b4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779427490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2779427490
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3634487288
Short name T567
Test name
Test status
Simulation time 207500839 ps
CPU time 6.29 seconds
Started Jun 29 04:42:11 PM PDT 24
Finished Jun 29 04:42:18 PM PDT 24
Peak memory 207940 kb
Host smart-3221cc58-b642-418b-bf2a-86741ee079b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634487288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3634487288
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3518488147
Short name T353
Test name
Test status
Simulation time 816324185 ps
CPU time 5.22 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 214172 kb
Host smart-1e13dfd9-3491-483a-8810-00bd02a3d047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518488147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3518488147
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3619432880
Short name T890
Test name
Test status
Simulation time 118881024 ps
CPU time 3.93 seconds
Started Jun 29 04:42:09 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 208024 kb
Host smart-db19bc51-f100-4581-9841-86c1c55c60be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619432880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3619432880
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3057605486
Short name T190
Test name
Test status
Simulation time 5207127174 ps
CPU time 39.33 seconds
Started Jun 29 04:42:10 PM PDT 24
Finished Jun 29 04:42:50 PM PDT 24
Peak memory 209156 kb
Host smart-5967ed61-0715-4c01-baec-e144233df8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057605486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3057605486
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2145574166
Short name T800
Test name
Test status
Simulation time 3046443523 ps
CPU time 7.3 seconds
Started Jun 29 04:42:09 PM PDT 24
Finished Jun 29 04:42:17 PM PDT 24
Peak memory 218264 kb
Host smart-065cab06-f382-49e3-b851-3ef8b7ab6a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145574166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2145574166
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3375853421
Short name T797
Test name
Test status
Simulation time 102139990 ps
CPU time 3.15 seconds
Started Jun 29 04:42:08 PM PDT 24
Finished Jun 29 04:42:12 PM PDT 24
Peak memory 210072 kb
Host smart-2389fbad-cab8-472e-8709-cc29a2a5f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375853421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3375853421
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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