Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	13	36	73.47

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	12	23	65.71	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	54	1			T52	1		T53	1		T32	1
auto[OpGenId]	12	1			T5	1		T58	1		T61	1
auto[OpGenSwOut]	23	1			T70	1		T63	1		T67	1
auto[OpGenHwOut]	15	1			T34	1		T7	1		T19	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1598	1			T85	5		T29	3		T58	1
auto[StInit]	92	1			T5	1		T30	1		T108	2
auto[StCreatorRootKey]	54	1			T85	1		T30	1		T63	1
auto[StOwnerIntKey]	45	1			T30	1		T69	1		T70	1
auto[StOwnerKey]	35	1			T85	1		T58	2		T71	1
auto[StDisabled]	373	1			T85	3		T29	8		T30	2
auto[StInvalid]	50	1			T3	1		T39	1		T59	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3222

1

T1

1

T2

1

T3

2

auto[1]

104

1

T5

1

T58

1

T70

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1594	1			T85	5		T29	3		T58	1
auto[StReset]	auto[1]	4	1			T60	1		T119	1		T180	1
auto[StInit]	auto[0]	46	1			T30	1		T108	2		T199	1
auto[StInit]	auto[1]	46	1			T5	1		T52	1		T32	1
auto[StCreatorRootKey]	auto[0]	32	1			T85	1		T30	1		T31	1
auto[StCreatorRootKey]	auto[1]	22	1			T63	1		T66	1		T8	1
auto[StOwnerIntKey]	auto[0]	35	1			T30	1		T69	1		T108	2
auto[StOwnerIntKey]	auto[1]	10	1			T70	1		T34	1		T53	1
auto[StOwnerKey]	auto[0]	25	1			T85	1		T58	1		T71	1
auto[StOwnerKey]	auto[1]	10	1			T58	1		T9	1		T200	1
auto[StDisabled]	auto[0]	361	1			T85	3		T29	8		T30	2
auto[StDisabled]	auto[1]	12	1			T7	1		T54	1		T201	1
auto[StInvalid]	auto[0]	50	1			T3	1		T39	1		T59	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	12	23	65.71	12

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	2	1			T119	1		T202	1		-	-
auto[StReset]	auto[OpGenSwOut]	1	1			T180	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T60	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	24	1			T52	1		T32	1		T196	1
auto[StInit]	auto[OpGenId]	7	1			T5	1		T61	1		T203	2
auto[StInit]	auto[OpGenSwOut]	10	1			T106	1		T204	1		T205	1
auto[StInit]	auto[OpGenHwOut]	5	1			T55	1		T206	1		T207	1
auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T66	1		T8	1		T208	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T209	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T63	1		T67	1		T210	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T211	1		T84	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T53	1		T212	1		T166	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T213	1		T192	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T70	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T34	1		T19	1		T214	1
auto[StOwnerKey]	auto[OpAdvance]	5	1			T200	1		T215	1		T216	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T58	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T217	1		T218	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T9	1		T219	1		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T54	1		T201	1		T79	2
auto[StDisabled]	auto[OpGenId]	1	1			T220	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T77	1		T83	1		T217	1
auto[StDisabled]	auto[OpGenHwOut]	2	1			T7	1		T221	1		-	-