Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4529

1

T1

15

T2

10

T3

4

auto[1]

509

1

T1

3

T2

2

T4

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4529

1

T1

15

T2

10

T3

4

auto[1]

509

1

T1

3

T2

2

T4

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4501

1

T1

15

T2

12

T3

4

auto[1]

537

1

T1

3

T14

1

T85

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4501

1

T1

15

T2

12

T3

4

auto[1]

537

1

T1

3

T14

1

T85

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	452	1			T1	4		T3	1		T28	1
auto[OpGenId]	1009	1			T1	5		T3	2		T14	1
auto[OpGenSwOut]	1011	1			T1	2		T3	1		T14	1
auto[OpGenHwOut]	2512	1			T1	7		T2	12		T4	11
auto[OpDisable]	54	1			T26	1		T68	1		T58	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	452	1			T1	4		T3	1		T28	1
auto[OpGenId]	1009	1			T1	5		T3	2		T14	1
auto[OpGenSwOut]	1011	1			T1	2		T3	1		T14	1
auto[OpGenHwOut]	2512	1			T1	7		T2	12		T4	11
auto[OpDisable]	54	1			T26	1		T68	1		T58	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4511

1

T1

13

T2

12

T3

4

auto[1]

527

1

T1

5

T17

1

T51

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4511

1

T1

13

T2

12

T3

4

auto[1]

527

1

T1

5

T17

1

T51

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4706

1

T1

8

T2

12

T3

4

auto[1]

332

1

T1

10

T156

7

T142

5

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1722	1			T1	6		T2	2		T3	1
auto[1]	691	1			T1	3		T2	3		T3	1
auto[2]	628	1			T1	7		T2	4		T3	1
auto[3]	654	1			T1	1		T4	1		T51	1
auto[4]	317	1			T2	2		T4	2		T17	1
auto[5]	356	1			T2	1		T17	1		T51	2
auto[6]	310	1			T4	1		T14	1		T51	1
auto[7]	360	1			T1	1		T3	1		T4	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1343	1			T1	1		T2	3		T3	1
clear_one[1]	691	1			T1	3		T2	3		T3	1
clear_one[2]	628	1			T1	7		T2	4		T3	1
clear_one[3]	654	1			T1	1		T4	1		T51	1
clear_none	1722	1			T1	6		T2	2		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	947	1			T1	3		T2	4		T4	3
auto[StInit]	612	1			T1	5		T2	1		T4	1
auto[StCreatorRootKey]	541	1			T1	4		T2	1		T4	1
auto[StOwnerIntKey]	463	1			T2	1		T4	1		T51	1
auto[StOwnerKey]	467	1			T1	1		T2	1		T4	1
auto[StDisabled]	1700	1			T1	5		T2	4		T4	4
auto[StInvalid]	308	1			T3	4		T41	4		T39	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	947	1			T1	3		T2	4		T4	3
auto[StInit]	612	1			T1	5		T2	1		T4	1
auto[StCreatorRootKey]	541	1			T1	4		T2	1		T4	1
auto[StOwnerIntKey]	463	1			T2	1		T4	1		T51	1
auto[StOwnerKey]	467	1			T1	1		T2	1		T4	1
auto[StDisabled]	1700	1			T1	5		T2	4		T4	4
auto[StInvalid]	308	1			T3	4		T41	4		T39	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	6	1			T146	1		T222	2		T223	1
auto[0]	auto[StReset]	auto[OpGenId]	140	1			T1	1		T17	2		T41	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	143	1			T41	1		T56	1		T85	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	244	1			T2	1		T4	1		T51	2
auto[0]	auto[StInit]	auto[OpAdvance]	49	1			T1	1		T52	1		T107	1
auto[0]	auto[StInit]	auto[OpGenId]	80	1			T29	1		T58	2		T139	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	81	1			T39	1		T86	1		T69	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	161	1			T2	1		T15	1		T29	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T58	1		T52	1		T224	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	49	1			T85	1		T29	1		T68	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	49	1			T29	1		T30	1		T58	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	85	1			T1	4		T29	1		T131	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T70	1		T53	1		T144	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T29	1		T68	1		T135	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T108	1		T225	1		T61	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T136	1		T226	1		T52	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T227	1		T228	1		T77	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T58	1		T115	1		T229	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T52	1		T72	1		T54	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T17	1		T140	1		T188	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	25	1			T52	1		T188	1		T142	2
auto[0]	auto[StDisabled]	auto[OpGenId]	46	1			T14	1		T29	2		T137	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T14	1		T85	1		T29	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T4	1		T87	1		T131	1
auto[0]	auto[StDisabled]	auto[OpDisable]	10	1			T26	1		T230	1		T231	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	18	1			T3	1		T59	1		T232	1
auto[0]	auto[StInvalid]	auto[OpGenId]	28	1			T41	1		T57	1		T233	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T95	1		T234	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	32	1			T57	1		T59	1		T95	1
auto[1]	auto[StReset]	auto[OpGenId]	13	1			T109	1		T236	1		T130	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	14	1			T41	1		T58	1		T237	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	51	1			T1	1		T4	1		T51	1
auto[1]	auto[StInit]	auto[OpAdvance]	2	1			T200	1		T25	1		-	-
auto[1]	auto[StInit]	auto[OpGenId]	7	1			T142	1		T238	1		T25	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T108	1		T239	1		T166	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T240	1		T241	1		T203	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T242	1		T243	1		T244	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T29	1		T245	1		T200	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T128	1		T67	1		T212	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T2	1		T141	1		T53	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T54	1		T246	1		T247	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T58	1		T248	1		T93	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T249	1		T203	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T2	1		T29	1		T251	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T252	1		T253	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	19	1			T29	1		T58	1		T137	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T108	1		T52	1		T246	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T87	1		T18	1		T52	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	38	1			T188	1		T143	2		T61	1
auto[1]	auto[StDisabled]	auto[OpGenId]	61	1			T17	1		T58	1		T108	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T1	1		T29	1		T58	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T1	1		T2	1		T51	1
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T58	1		T52	2		T196	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T109	1		T255	1		T256	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T3	1		T59	1		T255	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T257	1		T256	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T259	1		T235	1		T260	1
auto[2]	auto[StReset]	auto[OpGenId]	16	1			T63	1		T261	1		T129	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	14	1			T52	1		T32	1		T54	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T2	2		T51	1		T85	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T262	1		T24	2		T25	2
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T1	3		T58	1		T23	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T28	1		T237	1		T24	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	25	1			T1	1		T4	1		T17	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T142	1		T263	1		T61	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T61	1		T264	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T85	1		T9	1		T266	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T140	1		T248	1		T267	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T268	1		T54	1		T269	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T142	2		T270	1		T116	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T197	1		T54	1		T264	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T18	1		T140	1		T190	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T252	1		T271	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T85	1		T58	1		T142	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T85	1		T135	1		T198	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T141	1		T142	1		T273	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	27	1			T1	2		T28	1		T188	1
auto[2]	auto[StDisabled]	auto[OpGenId]	47	1			T29	1		T135	2		T52	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T1	1		T29	1		T58	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	138	1			T2	2		T4	2		T51	1
auto[2]	auto[StDisabled]	auto[OpDisable]	5	1			T78	1		T274	1		T275	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T109	1		T234	1		T276	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T277	1		T278	2		T279	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T3	1		T41	1		T109	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T64	1		T280	1		T281	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T1	1		T29	1		T142	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T34	1		T61	1		T230	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	58	1			T138	1		T198	2		T95	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T29	1		T282	1		T269	2
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T188	1		T198	1		T74	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T23	1		T74	1		T283	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	17	1			T226	1		T267	1		T284	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T58	1		T285	1		T254	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T58	1		T69	1		T96	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T236	1		T203	1		T286	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T4	1		T87	1		T190	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T156	1		T94	1		T236	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T58	1		T70	1		T238	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T198	1		T287	1		T79	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T85	1		T141	1		T108	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T236	1		T116	1		T288	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T108	1		T76	1		T261	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T58	1		T70	1		T197	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T7	1		T289	1		T96	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T52	1		T198	2		T156	1
auto[3]	auto[StDisabled]	auto[OpGenId]	44	1			T58	1		T139	1		T52	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	39	1			T137	1		T52	1		T290	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T51	1		T85	1		T28	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T68	1		T266	1		T291	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	10	1			T64	1		T292	1		T293	1
auto[3]	auto[StInvalid]	auto[OpGenId]	6	1			T234	1		T259	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T39	1		T255	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T39	1		T255	2		T295	1
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T91	1		T296	1		T297	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T85	1		T74	1		T298	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T4	1		T140	1		T248	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T265	1		T299	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T52	1		T24	1		T166	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	1	1			T300	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T301	1		T254	1		T302	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	2	1			T54	1		T209	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T303	1		T64	1		T83	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T137	1		T72	1		T110	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T29	1		T304	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T29	1		T52	1		T130	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T72	1		T305	1		T78	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T4	1		T51	1		T87	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T156	1		T306	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T307	1		T308	1		T309	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T58	1		T52	1		T290	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T2	1		T131	1		T156	2
auto[4]	auto[StDisabled]	auto[OpAdvance]	15	1			T225	1		T310	1		T311	1
auto[4]	auto[StDisabled]	auto[OpGenId]	28	1			T58	1		T312	1		T61	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T17	1		T58	1		T156	2
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T2	1		T26	1		T226	2
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T313	1		T314	1		T167	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T109	1		T278	1		T276	1
auto[4]	auto[StInvalid]	auto[OpGenId]	8	1			T95	1		T315	1		T279	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T41	1		T233	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T235	1		T317	1		T279	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T137	1		T108	1		T72	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	5	1			T34	1		T203	1		T318	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	31	1			T2	1		T41	1		T319	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T261	1		T320	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T90	1		T321	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T29	1		T319	1		T322	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	16	1			T230	1		T112	1		T323	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T253	1		T324	1		T325	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T254	1		T217	1		T326	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T29	1		T230	1		T203	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T51	1		T327	1		T328	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T108	1		T329	1		T330	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T331	1		T332	1		T333	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T314	1		T334	1		T324	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T29	1		T289	1		T335	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T133	1		T52	1		T336	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	12	1			T54	1		T337	1		T78	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T338	1		T245	1		T79	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T51	1		T226	1		T339	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	21	1			T52	1		T236	1		T54	1
auto[5]	auto[StDisabled]	auto[OpGenId]	17	1			T249	1		T196	1		T200	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T58	1		T139	1		T61	2
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T17	1		T87	1		T138	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T78	2		T340	1		T217	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	3	1			T59	1		T232	1		T88	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T39	1		T232	1		T341	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T342	1		T343	1		T344	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T59	1		T293	1		T345	1
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T346	1		T200	1		T347	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	6	1			T248	1		T113	1		T342	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	21	1			T108	1		T110	1		T348	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T61	1		T286	1		T300	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T137	1		T349	1		T254	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T130	1		T245	1		T25	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	19	1			T30	1		T62	1		T350	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T351	1		T352	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T162	1		T353	1		T166	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T18	1		T67	1		T354	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T70	1		T273	1		T250	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T355	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T356	1		T357	2		T358	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T58	2		T359	1		T298	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T29	1		T237	1		T240	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T360	1		T334	1		T361	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T130	1		T362	1		T363	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T128	1		T205	1		T254	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T190	1		T54	1		T364	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	6	1			T365	1		T366	1		T330	1
auto[6]	auto[StDisabled]	auto[OpGenId]	20	1			T29	1		T331	1		T312	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T29	1		T93	1		T74	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T4	1		T14	1		T51	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T84	1		T367	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	10	1			T234	1		T257	1		T256	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T41	1		T39	1		T259	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T57	1		T294	1		T344	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T29	1		T236	1		T368	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T128	1		T342	1		T74	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T369	1		T370	1		T129	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T34	1		T310	1		T324	1
auto[7]	auto[StInit]	auto[OpGenId]	8	1			T27	1		T371	2		T372	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	11	1			T263	1		T19	1		T54	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T140	1		T328	1		T196	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T66	1		T356	1		T373	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T198	1		T332	1		T374	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T85	1		T200	1		T375	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T226	1		T376	1		T323	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T212	1		T166	1		T215	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T138	1		T55	1		T167	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T97	1		T89	1		T377	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T74	1		T200	1		T360	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T1	1		T29	1		T320	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	12	1			T359	1		T61	1		T310	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T79	1		T378	1		T351	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T4	1		T86	1		T369	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	13	1			T61	1		T92	1		T252	1
auto[7]	auto[StDisabled]	auto[OpGenId]	27	1			T227	1		T61	1		T224	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T197	1		T115	1		T249	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T87	1		T131	1		T108	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T62	1		T130	1		T239	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T279	1		T281	1		T379	1
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T3	1		T341	1		T380	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T109	1		T341	1		T342	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T95	1		T233	1		T235	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1343

1

T1

1

T2

3

T3

1

clear_one[1]

auto[0]

auto[0]

auto[0]

380

1

T1

2

T2

3

T3

1

clear_one[1]

auto[0]

auto[0]

auto[1]

127

1

T1

1

T51

1

T29

1

clear_one[1]

auto[0]

auto[1]

auto[0]

142

1

T29

1

T141

2

T70

1

clear_one[1]

auto[0]

auto[1]

auto[1]

42

1

T29

1

T18

1

T52

2

clear_one[2]

auto[0]

auto[0]

auto[0]

349

1

T1

4

T2

2

T3

1

clear_one[2]

auto[0]

auto[0]

auto[1]

135

1

T1

3

T51

1

T29

1

clear_one[2]

auto[1]

auto[0]

auto[0]

118

1

T2

2

T4

2

T28

1

clear_one[2]

auto[1]

auto[0]

auto[1]

26

1

T52

1

T381

1

T382

1

clear_one[3]

auto[0]

auto[0]

auto[0]

396

1

T1

1

T51

1

T39

2

clear_one[3]

auto[0]

auto[1]

auto[0]

97

1

T131

2

T141

3

T198

2

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T4

1

T28

1

T87

2

clear_one[3]

auto[1]

auto[1]

auto[0]

34

1

T29

1

T383

1

T54

2

clear_none

auto[0]

auto[0]

auto[0]

1234

1

T1

3

T2

2

T3

1

clear_none

auto[0]

auto[0]

auto[1]

114

1

T17

1

T26

1

T68

1

clear_none

auto[0]

auto[1]

auto[0]

135

1

T14

1

T131

2

T58

1

clear_none

auto[0]

auto[1]

auto[1]

35

1

T136

1

T52

2

T188

1

clear_none

auto[1]

auto[0]

auto[0]

124

1

T4

1

T87

1

T58

1

clear_none

auto[1]

auto[0]

auto[1]

28

1

T61

1

T115

2

T384

1

clear_none

auto[1]

auto[1]

auto[0]

32

1

T1

2

T85

1

T385

1

clear_none

auto[1]

auto[1]

auto[1]

20

1

T1

1

T386

1

T54

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1248	1			T1	1		T2	3		T3	1
clear_all	auto[1]	95	1			T156	4		T303	3		T252	1
clear_one[1]	auto[0]	615	1			T1	2		T2	3		T3	1
clear_one[1]	auto[1]	76	1			T1	1		T143	7		T144	2
clear_one[2]	auto[0]	568	1			T1	2		T2	4		T3	1
clear_one[2]	auto[1]	60	1			T1	5		T156	1		T142	3
clear_one[3]	auto[0]	629	1			T1	1		T4	1		T51	1
clear_one[3]	auto[1]	25	1			T156	1		T116	1		T244	1
clear_none	auto[0]	1646	1			T1	2		T2	2		T3	1
clear_none	auto[1]	76	1			T1	4		T156	1		T142	2