Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10383

1

T1

26

T2

12

T4

14

auto[Attestation]

7029

1

T1

10

T2

2

T4

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2443	1			T1	5		T5	1		T6	2
auto[Aes]	3247	1			T1	6		T2	14		T4	18
auto[Kmac]	3182	1			T1	6		T14	1		T16	6
auto[Otbn]	3116	1			T1	7		T6	1		T14	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7066	1			T1	8		T2	8		T3	1
auto[OpGenId]	5424	1			T1	12		T6	3		T14	3
auto[OpGenSwOut]	5385	1			T1	14		T6	5		T14	3
auto[OpGenHwOut]	6603	1			T1	10		T2	14		T4	18
auto[OpDisable]	117	1			T26	1		T56	1		T29	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9803

1

T1

12

T2

8

T3

1

auto[OpDoneFail]

14792

1

T1

32

T2

14

T4

18

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6079	1			T1	16		T2	7		T3	1
auto[StInit]	3474	1			T1	6		T2	2		T4	2
auto[StCreatorRootKey]	2929	1			T1	6		T2	2		T4	2
auto[StOwnerIntKey]	2539	1			T1	3		T2	2		T4	2
auto[StOwnerKey]	2289	1			T1	1		T2	2		T4	2
auto[StDisabled]	7285	1			T1	12		T2	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	274	1			T1	1		T16	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	96	1			T1	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T1	1		T26	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T6	1		T27	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T58	1		T135	1		T52	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	208	1			T1	1		T29	5		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T1	2		T16	2		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	101	1			T56	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	72	1			T29	2		T132	1		T58	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	61	1			T85	1		T58	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	61	1			T14	1		T58	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	191	1			T6	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	329	1			T1	3		T16	3		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T29	1		T30	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T28	1		T29	2		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	56	1			T28	1		T30	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T16	1		T29	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	204	1			T16	2		T17	1		T85	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	283	1			T16	1		T38	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	96	1			T85	2		T29	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	65	1			T27	2		T29	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	63	1			T28	1		T58	2		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T85	1		T29	2		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	186	1			T1	1		T29	1		T58	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	52	1			T61	2		T74	1		T196	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	89	1			T86	1		T58	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T30	1		T132	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T1	1		T27	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T86	1		T7	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	191	1			T6	1		T38	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	77	1			T85	2		T29	2		T58	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T26	1		T85	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	78	1			T6	1		T38	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	51	1			T29	1		T133	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	60	1			T85	1		T58	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	208	1			T1	1		T17	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T85	1		T29	1		T108	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	88	1			T26	1		T28	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T69	1		T188	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T58	3		T69	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	45	1			T29	1		T58	1		T135	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	180	1			T29	2		T58	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T85	3		T29	1		T58	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T85	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T15	1		T85	2		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T1	1		T38	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T6	1		T29	2		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	220	1			T1	1		T14	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	275	1			T41	1		T27	1		T85	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	84	1			T29	1		T58	4		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T85	1		T28	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	48	1			T58	2		T52	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T15	1		T86	1		T58	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	138	1			T26	1		T28	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	473	1			T2	6		T4	10		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	90	1			T1	1		T4	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	89	1			T2	1		T27	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T2	1		T4	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	262	1			T1	1		T2	3		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	497	1			T1	1		T41	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T29	1		T86	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T131	1		T30	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	107	1			T14	1		T29	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T29	1		T18	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	245	1			T26	1		T29	3		T131	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	455	1			T1	2		T17	1		T51	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	110	1			T86	1		T132	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T1	1		T17	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T26	1		T29	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	71	1			T51	1		T86	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	244	1			T1	1		T51	1		T29	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T108	2		T52	1		T61	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T5	1		T29	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	57	1			T29	1		T71	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	60	1			T17	1		T85	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T85	1		T29	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	158	1			T15	1		T85	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	52	1			T58	1		T108	2		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	118	1			T29	2		T87	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T2	1		T28	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	91	1			T4	1		T28	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T29	1		T133	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	284	1			T2	1		T4	3		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	56	1			T85	1		T29	1		T58	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	99	1			T17	1		T86	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T1	2		T136	2		T71	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	78	1			T27	1		T85	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	90	1			T131	1		T30	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	258	1			T17	1		T29	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T85	1		T29	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T15	1		T51	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T51	1		T86	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T51	1		T136	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	92	1			T17	1		T30	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	267	1			T14	1		T51	3		T85	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T1	1		T6	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	590	1			T1	3		T16	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	172	1			T14	1		T85	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	629	1			T1	2		T6	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	176	1			T16	1		T28	1		T29	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	662	1			T1	3		T16	5		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	175	1			T27	2		T85	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	576	1			T1	1		T16	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	163	1			T1	1		T27	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	350	1			T6	1		T38	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	179	1			T6	1		T38	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	402	1			T1	1		T17	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T29	1		T58	4		T69	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	342	1			T26	1		T85	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	186	1			T1	1		T6	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	410	1			T1	1		T14	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T15	1		T85	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	512	1			T41	1		T26	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	259	1			T1	1		T2	2		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	868	1			T1	2		T2	10		T4	12
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T14	1		T29	2		T131	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	864	1			T1	1		T41	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	247	1			T1	1		T17	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	818	1			T1	3		T17	1		T51	6
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	151	1			T17	1		T85	2		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	326	1			T5	1		T15	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	262	1			T2	1		T4	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T2	1		T4	3		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	246	1			T1	2		T27	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	426	1			T17	2		T85	1		T29	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T17	1		T51	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	444	1			T14	1		T15	1		T51	4