Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30663

1

T1

48

T2

27

T3

31

auto[1]

287

1

T1

8

T156

4

T142

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30672	1			T1	48		T2	27		T3	31
auto[134217728:268435455]	4	1			T116	1		T269	1		T413	1
auto[268435456:402653183]	9	1			T143	1		T414	1		T415	1
auto[402653184:536870911]	9	1			T371	1		T401	1		T365	1
auto[536870912:671088639]	6	1			T311	1		T413	4		T416	1
auto[671088640:805306367]	9	1			T1	1		T156	1		T413	1
auto[805306368:939524095]	8	1			T303	1		T145	2		T146	1
auto[939524096:1073741823]	16	1			T144	1		T145	1		T146	1
auto[1073741824:1207959551]	7	1			T116	1		T252	1		T311	1
auto[1207959552:1342177279]	14	1			T156	1		T303	1		T146	1
auto[1342177280:1476395007]	6	1			T1	1		T146	1		T417	1
auto[1476395008:1610612735]	7	1			T142	1		T228	1		T244	1
auto[1610612736:1744830463]	16	1			T1	3		T144	1		T116	1
auto[1744830464:1879048191]	9	1			T145	1		T146	1		T371	1
auto[1879048192:2013265919]	9	1			T303	1		T144	1		T244	1
auto[2013265920:2147483647]	14	1			T303	1		T144	2		T116	1
auto[2147483648:2281701375]	13	1			T1	1		T244	2		T269	1
auto[2281701376:2415919103]	9	1			T146	1		T244	1		T296	1
auto[2415919104:2550136831]	7	1			T269	1		T296	1		T223	1
auto[2550136832:2684354559]	5	1			T116	1		T324	1		T365	1
auto[2684354560:2818572287]	8	1			T303	1		T252	1		T146	1
auto[2818572288:2952790015]	7	1			T146	1		T354	1		T418	1
auto[2952790016:3087007743]	9	1			T311	1		T365	1		T223	2
auto[3087007744:3221225471]	8	1			T143	1		T303	1		T144	1
auto[3221225472:3355443199]	4	1			T146	1		T413	1		T415	1
auto[3355443200:3489660927]	8	1			T244	1		T311	3		T324	1
auto[3489660928:3623878655]	12	1			T156	1		T144	1		T146	1
auto[3623878656:3758096383]	5	1			T419	1		T311	1		T420	1
auto[3758096384:3892314111]	11	1			T156	1		T142	1		T146	2
auto[3892314112:4026531839]	14	1			T1	1		T244	1		T269	1
auto[4026531840:4160749567]	7	1			T1	1		T244	1		T371	1
auto[4160749568:4294967295]	8	1			T142	1		T146	1		T222	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30663	1			T1	48		T2	27		T3	31
auto[0:134217727]	auto[1]	9	1			T146	1		T311	1		T371	1
auto[134217728:268435455]	auto[1]	4	1			T116	1		T269	1		T413	1
auto[268435456:402653183]	auto[1]	9	1			T143	1		T414	1		T415	1
auto[402653184:536870911]	auto[1]	9	1			T371	1		T401	1		T365	1
auto[536870912:671088639]	auto[1]	6	1			T311	1		T413	4		T416	1
auto[671088640:805306367]	auto[1]	9	1			T1	1		T156	1		T413	1
auto[805306368:939524095]	auto[1]	8	1			T303	1		T145	2		T146	1
auto[939524096:1073741823]	auto[1]	16	1			T144	1		T145	1		T146	1
auto[1073741824:1207959551]	auto[1]	7	1			T116	1		T252	1		T311	1
auto[1207959552:1342177279]	auto[1]	14	1			T156	1		T303	1		T146	1
auto[1342177280:1476395007]	auto[1]	6	1			T1	1		T146	1		T417	1
auto[1476395008:1610612735]	auto[1]	7	1			T142	1		T228	1		T244	1
auto[1610612736:1744830463]	auto[1]	16	1			T1	3		T144	1		T116	1
auto[1744830464:1879048191]	auto[1]	9	1			T145	1		T146	1		T371	1
auto[1879048192:2013265919]	auto[1]	9	1			T303	1		T144	1		T244	1
auto[2013265920:2147483647]	auto[1]	14	1			T303	1		T144	2		T116	1
auto[2147483648:2281701375]	auto[1]	13	1			T1	1		T244	2		T269	1
auto[2281701376:2415919103]	auto[1]	9	1			T146	1		T244	1		T296	1
auto[2415919104:2550136831]	auto[1]	7	1			T269	1		T296	1		T223	1
auto[2550136832:2684354559]	auto[1]	5	1			T116	1		T324	1		T365	1
auto[2684354560:2818572287]	auto[1]	8	1			T303	1		T252	1		T146	1
auto[2818572288:2952790015]	auto[1]	7	1			T146	1		T354	1		T418	1
auto[2952790016:3087007743]	auto[1]	9	1			T311	1		T365	1		T223	2
auto[3087007744:3221225471]	auto[1]	8	1			T143	1		T303	1		T144	1
auto[3221225472:3355443199]	auto[1]	4	1			T146	1		T413	1		T415	1
auto[3355443200:3489660927]	auto[1]	8	1			T244	1		T311	3		T324	1
auto[3489660928:3623878655]	auto[1]	12	1			T156	1		T144	1		T146	1
auto[3623878656:3758096383]	auto[1]	5	1			T419	1		T311	1		T420	1
auto[3758096384:3892314111]	auto[1]	11	1			T156	1		T142	1		T146	2
auto[3892314112:4026531839]	auto[1]	14	1			T1	1		T244	1		T269	1
auto[4026531840:4160749567]	auto[1]	7	1			T1	1		T244	1		T371	1
auto[4160749568:4294967295]	auto[1]	8	1			T142	1		T146	1		T222	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1454

1

T1

3

T3

3

T5

3

auto[1]

1676

1

T1

5

T3

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T3	1		T85	1		T132	1
auto[134217728:268435455]	92	1			T41	1		T26	1		T29	1
auto[268435456:402653183]	105	1			T86	1		T108	1		T7	2
auto[402653184:536870911]	90	1			T57	1		T28	2		T29	3
auto[536870912:671088639]	85	1			T5	1		T29	1		T108	1
auto[671088640:805306367]	88	1			T26	1		T85	1		T29	1
auto[805306368:939524095]	106	1			T1	1		T5	1		T27	1
auto[939524096:1073741823]	93	1			T27	1		T56	1		T85	1
auto[1073741824:1207959551]	85	1			T57	1		T29	1		T30	2
auto[1207959552:1342177279]	114	1			T41	2		T29	1		T30	2
auto[1342177280:1476395007]	94	1			T5	1		T29	1		T133	1
auto[1476395008:1610612735]	93	1			T3	1		T5	1		T41	1
auto[1610612736:1744830463]	107	1			T3	1		T39	1		T28	1
auto[1744830464:1879048191]	98	1			T39	1		T29	2		T86	1
auto[1879048192:2013265919]	102	1			T29	1		T58	1		T142	1
auto[2013265920:2147483647]	110	1			T27	1		T30	1		T58	2
auto[2147483648:2281701375]	105	1			T29	2		T86	2		T71	1
auto[2281701376:2415919103]	106	1			T57	1		T58	1		T69	1
auto[2415919104:2550136831]	100	1			T29	1		T58	2		T135	1
auto[2550136832:2684354559]	95	1			T1	1		T29	1		T86	1
auto[2684354560:2818572287]	91	1			T57	1		T29	2		T30	1
auto[2818572288:2952790015]	103	1			T39	1		T58	2		T69	1
auto[2952790016:3087007743]	91	1			T3	1		T39	1		T29	3
auto[3087007744:3221225471]	73	1			T1	1		T3	1		T52	1
auto[3221225472:3355443199]	110	1			T1	1		T85	1		T52	1
auto[3355443200:3489660927]	123	1			T29	3		T68	1		T52	6
auto[3489660928:3623878655]	101	1			T85	1		T29	3		T58	1
auto[3623878656:3758096383]	85	1			T1	2		T85	1		T28	1
auto[3758096384:3892314111]	112	1			T1	1		T85	1		T29	1
auto[3892314112:4026531839]	93	1			T1	1		T5	1		T85	2
auto[4026531840:4160749567]	104	1			T29	1		T58	1		T136	1
auto[4160749568:4294967295]	88	1			T5	1		T29	2		T69	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30	1			T319	1		T61	1		T303	1
auto[0:134217727]	auto[1]	58	1			T3	1		T85	1		T132	1
auto[134217728:268435455]	auto[0]	37	1			T41	1		T29	1		T108	1
auto[134217728:268435455]	auto[1]	55	1			T26	1		T30	1		T58	1
auto[268435456:402653183]	auto[0]	54	1			T54	1		T421	1		T74	1
auto[268435456:402653183]	auto[1]	51	1			T86	1		T108	1		T7	2
auto[402653184:536870911]	auto[0]	41	1			T57	1		T28	1		T29	2
auto[402653184:536870911]	auto[1]	49	1			T28	1		T29	1		T52	1
auto[536870912:671088639]	auto[0]	33	1			T5	1		T188	1		T198	1
auto[536870912:671088639]	auto[1]	52	1			T29	1		T108	1		T189	1
auto[671088640:805306367]	auto[0]	39	1			T227	1		T61	1		T54	1
auto[671088640:805306367]	auto[1]	49	1			T26	1		T85	1		T29	1
auto[805306368:939524095]	auto[0]	48	1			T5	1		T39	2		T85	1
auto[805306368:939524095]	auto[1]	58	1			T1	1		T27	1		T29	1
auto[939524096:1073741823]	auto[0]	46	1			T29	1		T30	2		T197	1
auto[939524096:1073741823]	auto[1]	47	1			T27	1		T56	1		T85	1
auto[1073741824:1207959551]	auto[0]	39	1			T57	1		T29	1		T30	1
auto[1073741824:1207959551]	auto[1]	46	1			T30	1		T108	1		T63	1
auto[1207959552:1342177279]	auto[0]	59	1			T41	1		T30	1		T58	1
auto[1207959552:1342177279]	auto[1]	55	1			T41	1		T29	1		T30	1
auto[1342177280:1476395007]	auto[0]	42	1			T29	1		T58	1		T52	1
auto[1342177280:1476395007]	auto[1]	52	1			T5	1		T133	1		T58	2
auto[1476395008:1610612735]	auto[0]	42	1			T3	1		T41	1		T58	1
auto[1476395008:1610612735]	auto[1]	51	1			T5	1		T26	1		T57	1
auto[1610612736:1744830463]	auto[0]	52	1			T3	1		T39	1		T62	1
auto[1610612736:1744830463]	auto[1]	55	1			T28	1		T29	1		T58	2
auto[1744830464:1879048191]	auto[0]	47	1			T39	1		T29	1		T86	1
auto[1744830464:1879048191]	auto[1]	51	1			T29	1		T58	1		T135	1
auto[1879048192:2013265919]	auto[0]	45	1			T107	1		T232	1		T243	1
auto[1879048192:2013265919]	auto[1]	57	1			T29	1		T58	1		T142	1
auto[2013265920:2147483647]	auto[0]	52	1			T30	1		T69	1		T63	1
auto[2013265920:2147483647]	auto[1]	58	1			T27	1		T58	2		T188	1
auto[2147483648:2281701375]	auto[0]	62	1			T29	2		T86	1		T52	2
auto[2147483648:2281701375]	auto[1]	43	1			T86	1		T71	1		T52	1
auto[2281701376:2415919103]	auto[0]	51	1			T57	1		T58	1		T69	1
auto[2281701376:2415919103]	auto[1]	55	1			T31	2		T53	1		T107	1
auto[2415919104:2550136831]	auto[0]	41	1			T58	1		T31	1		T91	1
auto[2415919104:2550136831]	auto[1]	59	1			T29	1		T58	1		T135	1
auto[2550136832:2684354559]	auto[0]	45	1			T1	1		T86	1		T58	1
auto[2550136832:2684354559]	auto[1]	50	1			T29	1		T132	1		T58	2
auto[2684354560:2818572287]	auto[0]	47	1			T57	1		T29	1		T30	1
auto[2684354560:2818572287]	auto[1]	44	1			T29	1		T58	1		T70	1
auto[2818572288:2952790015]	auto[0]	38	1			T39	1		T69	1		T188	1
auto[2818572288:2952790015]	auto[1]	65	1			T58	2		T135	1		T52	2
auto[2952790016:3087007743]	auto[0]	43	1			T39	1		T29	3		T63	1
auto[2952790016:3087007743]	auto[1]	48	1			T3	1		T133	1		T188	1
auto[3087007744:3221225471]	auto[0]	36	1			T1	1		T3	1		T52	1
auto[3087007744:3221225471]	auto[1]	37	1			T109	1		T197	1		T232	1
auto[3221225472:3355443199]	auto[0]	50	1			T52	1		T107	1		T238	1
auto[3221225472:3355443199]	auto[1]	60	1			T1	1		T85	1		T242	1
auto[3355443200:3489660927]	auto[0]	60	1			T29	3		T68	1		T52	2
auto[3355443200:3489660927]	auto[1]	63	1			T52	4		T53	2		T143	1
auto[3489660928:3623878655]	auto[0]	48	1			T29	2		T52	1		T238	1
auto[3489660928:3623878655]	auto[1]	53	1			T85	1		T29	1		T58	1
auto[3623878656:3758096383]	auto[0]	43	1			T85	1		T29	1		T58	1
auto[3623878656:3758096383]	auto[1]	42	1			T1	2		T28	1		T108	1
auto[3758096384:3892314111]	auto[0]	64	1			T58	1		T71	1		T52	2
auto[3758096384:3892314111]	auto[1]	48	1			T1	1		T85	1		T29	1
auto[3892314112:4026531839]	auto[0]	36	1			T1	1		T142	1		T143	1
auto[3892314112:4026531839]	auto[1]	57	1			T5	1		T85	2		T28	1
auto[4026531840:4160749567]	auto[0]	50	1			T29	1		T63	1		T52	1
auto[4026531840:4160749567]	auto[1]	54	1			T58	1		T136	1		T422	1
auto[4160749568:4294967295]	auto[0]	34	1			T5	1		T63	1		T109	1
auto[4160749568:4294967295]	auto[1]	54	1			T29	2		T69	1		T108	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1454

1

T1

4

T3

3

T5

4

auto[1]

1675

1

T1

4

T3

2

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T41	1		T85	1		T58	1
auto[134217728:268435455]	100	1			T3	1		T29	1		T86	1
auto[268435456:402653183]	92	1			T26	1		T57	1		T85	1
auto[402653184:536870911]	103	1			T5	1		T28	1		T29	1
auto[536870912:671088639]	103	1			T5	1		T57	1		T29	1
auto[671088640:805306367]	102	1			T27	1		T29	4		T133	1
auto[805306368:939524095]	103	1			T28	1		T29	1		T30	1
auto[939524096:1073741823]	97	1			T26	1		T39	2		T85	1
auto[1073741824:1207959551]	107	1			T57	1		T29	1		T63	2
auto[1207959552:1342177279]	81	1			T3	1		T85	1		T29	1
auto[1342177280:1476395007]	85	1			T5	1		T41	1		T26	1
auto[1476395008:1610612735]	105	1			T1	1		T85	1		T29	1
auto[1610612736:1744830463]	97	1			T1	1		T57	1		T29	1
auto[1744830464:1879048191]	96	1			T29	1		T86	1		T58	1
auto[1879048192:2013265919]	105	1			T3	1		T29	1		T132	1
auto[2013265920:2147483647]	107	1			T1	1		T29	2		T58	4
auto[2147483648:2281701375]	97	1			T29	1		T30	1		T70	1
auto[2281701376:2415919103]	98	1			T28	1		T132	1		T68	1
auto[2415919104:2550136831]	87	1			T27	1		T29	3		T109	1
auto[2550136832:2684354559]	112	1			T39	1		T29	1		T58	1
auto[2684354560:2818572287]	103	1			T29	3		T30	1		T58	2
auto[2818572288:2952790015]	87	1			T1	2		T56	1		T85	1
auto[2952790016:3087007743]	97	1			T1	1		T39	1		T85	1
auto[3087007744:3221225471]	109	1			T28	1		T69	1		T70	1
auto[3221225472:3355443199]	108	1			T3	1		T5	1		T41	1
auto[3355443200:3489660927]	91	1			T29	2		T58	1		T143	1
auto[3489660928:3623878655]	89	1			T86	1		T30	1		T242	1
auto[3623878656:3758096383]	78	1			T5	1		T85	1		T29	1
auto[3758096384:3892314111]	105	1			T3	1		T5	1		T41	1
auto[3892314112:4026531839]	77	1			T1	2		T39	1		T29	1
auto[4026531840:4160749567]	108	1			T39	1		T28	1		T29	1
auto[4160749568:4294967295]	94	1			T69	1		T108	1		T52	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T41	1		T63	1		T96	1
auto[0:134217727]	auto[1]	63	1			T85	1		T58	1		T108	1
auto[134217728:268435455]	auto[0]	46	1			T3	1		T30	1		T52	1
auto[134217728:268435455]	auto[1]	54	1			T29	1		T86	1		T53	1
auto[268435456:402653183]	auto[0]	32	1			T57	1		T85	1		T109	1
auto[268435456:402653183]	auto[1]	60	1			T26	1		T29	1		T86	1
auto[402653184:536870911]	auto[0]	46	1			T5	1		T28	1		T29	1
auto[402653184:536870911]	auto[1]	57	1			T70	1		T71	1		T108	1
auto[536870912:671088639]	auto[0]	51	1			T29	1		T18	1		T59	1
auto[536870912:671088639]	auto[1]	52	1			T5	1		T57	1		T30	1
auto[671088640:805306367]	auto[0]	42	1			T29	3		T136	1		T52	2
auto[671088640:805306367]	auto[1]	60	1			T27	1		T29	1		T133	1
auto[805306368:939524095]	auto[0]	51	1			T28	1		T227	1		T236	1
auto[805306368:939524095]	auto[1]	52	1			T29	1		T30	1		T58	1
auto[939524096:1073741823]	auto[0]	34	1			T39	2		T30	1		T109	1
auto[939524096:1073741823]	auto[1]	63	1			T26	1		T85	1		T29	1
auto[1073741824:1207959551]	auto[0]	57	1			T57	1		T29	1		T63	1
auto[1073741824:1207959551]	auto[1]	50	1			T63	1		T52	1		T242	1
auto[1207959552:1342177279]	auto[0]	40	1			T3	1		T29	1		T86	1
auto[1207959552:1342177279]	auto[1]	41	1			T85	1		T71	1		T96	1
auto[1342177280:1476395007]	auto[0]	43	1			T5	1		T41	1		T26	1
auto[1342177280:1476395007]	auto[1]	42	1			T29	1		T52	2		T31	1
auto[1476395008:1610612735]	auto[0]	50	1			T29	1		T68	1		T52	1
auto[1476395008:1610612735]	auto[1]	55	1			T1	1		T85	1		T132	1
auto[1610612736:1744830463]	auto[0]	42	1			T1	1		T57	1		T198	1
auto[1610612736:1744830463]	auto[1]	55	1			T29	1		T135	2		T188	1
auto[1744830464:1879048191]	auto[0]	42	1			T29	1		T58	1		T107	1
auto[1744830464:1879048191]	auto[1]	54	1			T86	1		T108	1		T52	1
auto[1879048192:2013265919]	auto[0]	55	1			T69	2		T62	1		T52	1
auto[1879048192:2013265919]	auto[1]	50	1			T3	1		T29	1		T132	1
auto[2013265920:2147483647]	auto[0]	53	1			T1	1		T29	1		T58	1
auto[2013265920:2147483647]	auto[1]	54	1			T29	1		T58	3		T135	1
auto[2147483648:2281701375]	auto[0]	41	1			T30	1		T108	1		T143	1
auto[2147483648:2281701375]	auto[1]	56	1			T29	1		T70	1		T52	1
auto[2281701376:2415919103]	auto[0]	45	1			T52	1		T34	1		T341	1
auto[2281701376:2415919103]	auto[1]	53	1			T28	1		T132	1		T68	1
auto[2415919104:2550136831]	auto[0]	38	1			T29	1		T109	1		T255	1
auto[2415919104:2550136831]	auto[1]	49	1			T27	1		T29	2		T225	1
auto[2550136832:2684354559]	auto[0]	47	1			T39	1		T63	1		T96	1
auto[2550136832:2684354559]	auto[1]	65	1			T29	1		T58	1		T319	1
auto[2684354560:2818572287]	auto[0]	49	1			T29	1		T58	2		T70	1
auto[2684354560:2818572287]	auto[1]	54	1			T29	2		T30	1		T63	1
auto[2818572288:2952790015]	auto[0]	39	1			T1	1		T29	1		T69	1
auto[2818572288:2952790015]	auto[1]	48	1			T1	1		T56	1		T85	1
auto[2952790016:3087007743]	auto[0]	56	1			T39	1		T29	2		T58	1
auto[2952790016:3087007743]	auto[1]	41	1			T1	1		T85	1		T30	1
auto[3087007744:3221225471]	auto[0]	56	1			T28	1		T69	1		T52	1
auto[3087007744:3221225471]	auto[1]	53	1			T70	1		T53	1		T107	1
auto[3221225472:3355443199]	auto[0]	55	1			T3	1		T5	1		T41	1
auto[3221225472:3355443199]	auto[1]	53	1			T85	1		T29	1		T132	1
auto[3355443200:3489660927]	auto[0]	43	1			T29	2		T143	1		T331	1
auto[3355443200:3489660927]	auto[1]	48	1			T58	1		T225	1		T32	1
auto[3489660928:3623878655]	auto[0]	42	1			T268	1		T109	1		T91	1
auto[3489660928:3623878655]	auto[1]	47	1			T86	1		T30	1		T242	1
auto[3623878656:3758096383]	auto[0]	42	1			T5	1		T29	1		T69	1
auto[3623878656:3758096383]	auto[1]	36	1			T85	1		T58	1		T108	1
auto[3758096384:3892314111]	auto[0]	37	1			T41	1		T29	1		T30	1
auto[3758096384:3892314111]	auto[1]	68	1			T3	1		T5	1		T27	1
auto[3892314112:4026531839]	auto[0]	34	1			T1	1		T39	1		T29	1
auto[3892314112:4026531839]	auto[1]	43	1			T1	1		T58	1		T198	1
auto[4026531840:4160749567]	auto[0]	62	1			T39	1		T29	1		T30	1
auto[4026531840:4160749567]	auto[1]	46	1			T28	1		T108	1		T43	1
auto[4160749568:4294967295]	auto[0]	41	1			T69	1		T52	1		T341	1
auto[4160749568:4294967295]	auto[1]	53	1			T108	1		T188	1		T243	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1446

1

T1

2

T3

3

T5

3

auto[1]

1683

1

T1

6

T3

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T26	1		T29	2		T58	2
auto[134217728:268435455]	76	1			T1	1		T3	1		T41	1
auto[268435456:402653183]	100	1			T57	1		T30	1		T58	5
auto[402653184:536870911]	96	1			T3	1		T39	1		T29	1
auto[536870912:671088639]	89	1			T1	1		T5	1		T85	1
auto[671088640:805306367]	100	1			T1	1		T56	1		T28	1
auto[805306368:939524095]	121	1			T39	1		T29	2		T86	1
auto[939524096:1073741823]	104	1			T1	1		T85	1		T29	3
auto[1073741824:1207959551]	94	1			T41	1		T29	3		T86	1
auto[1207959552:1342177279]	105	1			T3	1		T85	1		T29	1
auto[1342177280:1476395007]	87	1			T29	1		T30	1		T132	1
auto[1476395008:1610612735]	92	1			T5	1		T27	1		T57	1
auto[1610612736:1744830463]	93	1			T5	1		T29	1		T69	1
auto[1744830464:1879048191]	102	1			T3	1		T27	1		T29	1
auto[1879048192:2013265919]	95	1			T29	1		T133	1		T58	1
auto[2013265920:2147483647]	84	1			T85	1		T29	1		T30	1
auto[2147483648:2281701375]	86	1			T1	1		T58	1		T52	2
auto[2281701376:2415919103]	98	1			T1	1		T85	1		T62	1
auto[2415919104:2550136831]	85	1			T85	1		T29	2		T30	1
auto[2550136832:2684354559]	104	1			T27	1		T39	1		T28	1
auto[2684354560:2818572287]	92	1			T5	1		T57	1		T85	1
auto[2818572288:2952790015]	90	1			T29	3		T30	1		T58	4
auto[2952790016:3087007743]	115	1			T1	1		T5	1		T29	4
auto[3087007744:3221225471]	80	1			T57	1		T28	1		T29	1
auto[3221225472:3355443199]	106	1			T29	2		T68	1		T69	1
auto[3355443200:3489660927]	95	1			T30	1		T70	1		T108	1
auto[3489660928:3623878655]	110	1			T41	1		T26	1		T39	1
auto[3623878656:3758096383]	101	1			T1	1		T39	1		T85	1
auto[3758096384:3892314111]	98	1			T26	1		T57	1		T85	1
auto[3892314112:4026531839]	114	1			T41	1		T28	1		T58	2
auto[4026531840:4160749567]	103	1			T29	1		T68	1		T58	2
auto[4160749568:4294967295]	103	1			T3	1		T5	1		T85	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T58	1		T62	1		T52	2
auto[0:134217727]	auto[1]	53	1			T26	1		T29	2		T58	1
auto[134217728:268435455]	auto[0]	35	1			T1	1		T41	1		T39	1
auto[134217728:268435455]	auto[1]	41	1			T3	1		T86	2		T70	1
auto[268435456:402653183]	auto[0]	47	1			T57	1		T58	2		T96	1
auto[268435456:402653183]	auto[1]	53	1			T30	1		T58	3		T52	2
auto[402653184:536870911]	auto[0]	47	1			T3	1		T39	1		T52	1
auto[402653184:536870911]	auto[1]	49	1			T29	1		T58	1		T136	1
auto[536870912:671088639]	auto[0]	39	1			T29	1		T86	1		T58	1
auto[536870912:671088639]	auto[1]	50	1			T1	1		T5	1		T85	1
auto[671088640:805306367]	auto[0]	46	1			T1	1		T28	1		T108	1
auto[671088640:805306367]	auto[1]	54	1			T56	1		T30	1		T132	1
auto[805306368:939524095]	auto[0]	60	1			T39	1		T86	1		T58	1
auto[805306368:939524095]	auto[1]	61	1			T29	2		T30	1		T58	1
auto[939524096:1073741823]	auto[0]	46	1			T29	2		T30	1		T7	1
auto[939524096:1073741823]	auto[1]	58	1			T1	1		T85	1		T29	1
auto[1073741824:1207959551]	auto[0]	47	1			T41	1		T29	2		T30	1
auto[1073741824:1207959551]	auto[1]	47	1			T29	1		T86	1		T132	1
auto[1207959552:1342177279]	auto[0]	41	1			T3	1		T61	2		T54	1
auto[1207959552:1342177279]	auto[1]	64	1			T85	1		T29	1		T70	1
auto[1342177280:1476395007]	auto[0]	35	1			T29	1		T30	1		T132	1
auto[1342177280:1476395007]	auto[1]	52	1			T58	2		T135	1		T7	1
auto[1476395008:1610612735]	auto[0]	36	1			T5	1		T57	1		T29	1
auto[1476395008:1610612735]	auto[1]	56	1			T27	1		T29	1		T108	1
auto[1610612736:1744830463]	auto[0]	37	1			T69	1		T108	1		T52	1
auto[1610612736:1744830463]	auto[1]	56	1			T5	1		T29	1		T108	1
auto[1744830464:1879048191]	auto[0]	54	1			T29	1		T69	1		T188	1
auto[1744830464:1879048191]	auto[1]	48	1			T3	1		T27	1		T135	1
auto[1879048192:2013265919]	auto[0]	47	1			T29	1		T18	1		T52	1
auto[1879048192:2013265919]	auto[1]	48	1			T133	1		T58	1		T108	1
auto[2013265920:2147483647]	auto[0]	50	1			T85	1		T29	1		T30	1
auto[2013265920:2147483647]	auto[1]	34	1			T58	2		T156	1		T107	1
auto[2147483648:2281701375]	auto[0]	38	1			T58	1		T143	1		T255	1
auto[2147483648:2281701375]	auto[1]	48	1			T1	1		T52	2		T242	1
auto[2281701376:2415919103]	auto[0]	42	1			T62	1		T52	2		T107	1
auto[2281701376:2415919103]	auto[1]	56	1			T1	1		T85	1		T52	1
auto[2415919104:2550136831]	auto[0]	43	1			T30	1		T58	1		T63	2
auto[2415919104:2550136831]	auto[1]	42	1			T85	1		T29	2		T331	1
auto[2550136832:2684354559]	auto[0]	50	1			T39	1		T29	1		T52	1
auto[2550136832:2684354559]	auto[1]	54	1			T27	1		T28	1		T133	1
auto[2684354560:2818572287]	auto[0]	38	1			T5	1		T142	1		T54	1
auto[2684354560:2818572287]	auto[1]	54	1			T57	1		T85	1		T71	1
auto[2818572288:2952790015]	auto[0]	35	1			T29	1		T30	1		T58	2
auto[2818572288:2952790015]	auto[1]	55	1			T29	2		T58	2		T70	1
auto[2952790016:3087007743]	auto[0]	59	1			T5	1		T29	3		T69	1
auto[2952790016:3087007743]	auto[1]	56	1			T1	1		T29	1		T133	1
auto[3087007744:3221225471]	auto[0]	39	1			T57	1		T29	1		T18	1
auto[3087007744:3221225471]	auto[1]	41	1			T28	1		T132	1		T54	1
auto[3221225472:3355443199]	auto[0]	49	1			T29	1		T68	1		T69	1
auto[3221225472:3355443199]	auto[1]	57	1			T29	1		T135	1		T23	1
auto[3355443200:3489660927]	auto[0]	43	1			T30	1		T34	1		T95	1
auto[3355443200:3489660927]	auto[1]	52	1			T70	1		T108	1		T95	1
auto[3489660928:3623878655]	auto[0]	62	1			T39	1		T29	1		T58	1
auto[3489660928:3623878655]	auto[1]	48	1			T41	1		T26	1		T132	1
auto[3623878656:3758096383]	auto[0]	37	1			T39	1		T85	1		T52	1
auto[3623878656:3758096383]	auto[1]	64	1			T1	1		T52	1		T319	1
auto[3758096384:3892314111]	auto[0]	50	1			T57	1		T29	2		T58	1
auto[3758096384:3892314111]	auto[1]	48	1			T26	1		T85	1		T136	1
auto[3892314112:4026531839]	auto[0]	50	1			T41	1		T28	1		T58	2
auto[3892314112:4026531839]	auto[1]	64	1			T52	1		T31	2		T7	1
auto[4026531840:4160749567]	auto[0]	40	1			T52	1		T238	1		T295	1
auto[4026531840:4160749567]	auto[1]	63	1			T29	1		T68	1		T58	2
auto[4160749568:4294967295]	auto[0]	46	1			T3	1		T30	1		T52	1
auto[4160749568:4294967295]	auto[1]	57	1			T5	1		T85	1		T28	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1446

1

T1

3

T3

3

T5

4

auto[1]

1683

1

T1

5

T3

2

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T85	1		T28	1		T29	1
auto[134217728:268435455]	109	1			T57	1		T29	1		T86	1
auto[268435456:402653183]	92	1			T1	1		T30	1		T108	1
auto[402653184:536870911]	110	1			T3	1		T26	1		T27	1
auto[536870912:671088639]	94	1			T27	1		T85	1		T29	2
auto[671088640:805306367]	104	1			T5	1		T28	1		T29	1
auto[805306368:939524095]	104	1			T39	2		T30	1		T58	1
auto[939524096:1073741823]	102	1			T41	1		T29	1		T58	2
auto[1073741824:1207959551]	91	1			T1	2		T29	1		T86	1
auto[1207959552:1342177279]	94	1			T41	1		T29	3		T86	1
auto[1342177280:1476395007]	103	1			T85	1		T28	1		T29	2
auto[1476395008:1610612735]	88	1			T26	1		T29	1		T135	1
auto[1610612736:1744830463]	84	1			T3	1		T41	1		T29	3
auto[1744830464:1879048191]	97	1			T29	1		T58	1		T18	1
auto[1879048192:2013265919]	99	1			T1	1		T5	2		T85	1
auto[2013265920:2147483647]	93	1			T1	2		T28	1		T29	2
auto[2147483648:2281701375]	105	1			T3	1		T41	1		T26	1
auto[2281701376:2415919103]	110	1			T85	1		T28	1		T86	1
auto[2415919104:2550136831]	102	1			T1	1		T39	1		T29	2
auto[2550136832:2684354559]	84	1			T3	1		T5	1		T132	1
auto[2684354560:2818572287]	96	1			T39	1		T85	1		T29	3
auto[2818572288:2952790015]	95	1			T29	2		T30	1		T132	1
auto[2952790016:3087007743]	106	1			T56	1		T58	2		T7	1
auto[3087007744:3221225471]	87	1			T39	1		T57	2		T85	2
auto[3221225472:3355443199]	97	1			T39	1		T69	1		T70	1
auto[3355443200:3489660927]	99	1			T1	1		T29	1		T70	1
auto[3489660928:3623878655]	85	1			T29	1		T58	1		T108	1
auto[3623878656:3758096383]	96	1			T5	1		T57	1		T85	1
auto[3758096384:3892314111]	100	1			T29	2		T30	1		T58	1
auto[3892314112:4026531839]	96	1			T29	1		T58	1		T108	1
auto[4026531840:4160749567]	96	1			T3	1		T29	1		T30	1
auto[4160749568:4294967295]	121	1			T5	1		T27	1		T29	1