Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4114

1

T1

14

T3

6

T5

12

auto[1]

2144

1

T1

2

T3

4

T41

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	198	1			T27	2		T57	2		T28	2
auto[134217728:268435455]	192	1			T27	2		T29	6		T86	2
auto[268435456:402653183]	164	1			T39	2		T85	2		T29	4
auto[402653184:536870911]	166	1			T39	2		T29	2		T136	2
auto[536870912:671088639]	180	1			T3	2		T5	4		T28	2
auto[671088640:805306367]	202	1			T1	4		T29	4		T133	2
auto[805306368:939524095]	212	1			T26	2		T86	2		T68	2
auto[939524096:1073741823]	214	1			T29	4		T58	4		T135	2
auto[1073741824:1207959551]	188	1			T41	2		T26	2		T28	2
auto[1207959552:1342177279]	220	1			T1	2		T29	6		T58	2
auto[1342177280:1476395007]	198	1			T27	2		T85	4		T29	2
auto[1476395008:1610612735]	190	1			T39	2		T52	2		T34	2
auto[1610612736:1744830463]	200	1			T29	2		T58	2		T135	2
auto[1744830464:1879048191]	180	1			T3	2		T41	2		T85	6
auto[1879048192:2013265919]	188	1			T5	2		T29	2		T30	4
auto[2013265920:2147483647]	230	1			T1	2		T5	2		T57	2
auto[2147483648:2281701375]	188	1			T1	2		T85	4		T58	2
auto[2281701376:2415919103]	190	1			T41	2		T52	2		T198	2
auto[2415919104:2550136831]	164	1			T26	2		T39	2		T29	4
auto[2550136832:2684354559]	244	1			T1	2		T57	2		T29	2
auto[2684354560:2818572287]	206	1			T3	4		T28	2		T29	4
auto[2818572288:2952790015]	196	1			T1	2		T30	2		T133	2
auto[2952790016:3087007743]	186	1			T29	4		T86	2		T58	2
auto[3087007744:3221225471]	196	1			T5	2		T29	2		T132	2
auto[3221225472:3355443199]	204	1			T41	2		T39	2		T29	2
auto[3355443200:3489660927]	164	1			T69	2		T108	4		T52	2
auto[3489660928:3623878655]	208	1			T1	2		T39	2		T56	2
auto[3623878656:3758096383]	166	1			T132	2		T58	2		T62	2
auto[3758096384:3892314111]	212	1			T5	2		T85	2		T29	4
auto[3892314112:4026531839]	182	1			T3	2		T57	2		T85	2
auto[4026531840:4160749567]	216	1			T29	2		T70	2		T63	4
auto[4160749568:4294967295]	214	1			T57	2		T58	2		T108	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	114	1			T27	2		T57	2		T29	2
auto[0:134217727]	auto[1]	84	1			T28	2		T69	2		T71	2
auto[134217728:268435455]	auto[0]	120	1			T29	4		T58	6		T52	4
auto[134217728:268435455]	auto[1]	72	1			T27	2		T29	2		T86	2
auto[268435456:402653183]	auto[0]	108	1			T39	2		T85	2		T70	2
auto[268435456:402653183]	auto[1]	56	1			T29	4		T30	2		T54	2
auto[402653184:536870911]	auto[0]	108	1			T39	2		T136	2		T96	2
auto[402653184:536870911]	auto[1]	58	1			T29	2		T189	2		T53	2
auto[536870912:671088639]	auto[0]	118	1			T3	2		T5	4		T136	2
auto[536870912:671088639]	auto[1]	62	1			T28	2		T29	2		T58	2
auto[671088640:805306367]	auto[0]	126	1			T1	2		T29	2		T133	2
auto[671088640:805306367]	auto[1]	76	1			T1	2		T29	2		T58	4
auto[805306368:939524095]	auto[0]	136	1			T86	2		T68	2		T58	2
auto[805306368:939524095]	auto[1]	76	1			T26	2		T75	2		T142	2
auto[939524096:1073741823]	auto[0]	144	1			T29	4		T58	4		T135	2
auto[939524096:1073741823]	auto[1]	70	1			T143	2		T426	2		T54	2
auto[1073741824:1207959551]	auto[0]	124	1			T41	2		T30	2		T18	2
auto[1073741824:1207959551]	auto[1]	64	1			T26	2		T28	2		T242	2
auto[1207959552:1342177279]	auto[0]	138	1			T1	2		T29	4		T58	2
auto[1207959552:1342177279]	auto[1]	82	1			T29	2		T135	2		T236	2
auto[1342177280:1476395007]	auto[0]	144	1			T27	2		T85	4		T29	2
auto[1342177280:1476395007]	auto[1]	54	1			T68	2		T268	2		T53	2
auto[1476395008:1610612735]	auto[0]	124	1			T39	2		T34	2		T197	2
auto[1476395008:1610612735]	auto[1]	66	1			T52	2		T109	2		T227	2
auto[1610612736:1744830463]	auto[0]	136	1			T29	2		T188	2		T156	2
auto[1610612736:1744830463]	auto[1]	64	1			T58	2		T135	2		T108	2
auto[1744830464:1879048191]	auto[0]	116	1			T3	2		T30	2		T58	2
auto[1744830464:1879048191]	auto[1]	64	1			T41	2		T85	6		T28	2
auto[1879048192:2013265919]	auto[0]	142	1			T5	2		T29	2		T30	2
auto[1879048192:2013265919]	auto[1]	46	1			T30	2		T132	2		T70	2
auto[2013265920:2147483647]	auto[0]	160	1			T1	2		T5	2		T57	2
auto[2013265920:2147483647]	auto[1]	70	1			T29	4		T86	2		T58	2
auto[2147483648:2281701375]	auto[0]	116	1			T1	2		T71	2		T63	2
auto[2147483648:2281701375]	auto[1]	72	1			T85	4		T58	2		T52	2
auto[2281701376:2415919103]	auto[0]	136	1			T41	2		T52	2		T198	2
auto[2281701376:2415919103]	auto[1]	54	1			T232	2		T144	2		T336	2
auto[2415919104:2550136831]	auto[0]	126	1			T26	2		T29	2		T30	2
auto[2415919104:2550136831]	auto[1]	38	1			T39	2		T29	2		T58	2
auto[2550136832:2684354559]	auto[0]	154	1			T1	2		T57	2		T29	2
auto[2550136832:2684354559]	auto[1]	90	1			T312	2		T243	2		T144	2
auto[2684354560:2818572287]	auto[0]	140	1			T3	2		T29	2		T133	2
auto[2684354560:2818572287]	auto[1]	66	1			T3	2		T28	2		T29	2
auto[2818572288:2952790015]	auto[0]	118	1			T1	2		T133	2		T58	2
auto[2818572288:2952790015]	auto[1]	78	1			T30	2		T277	2		T261	2
auto[2952790016:3087007743]	auto[0]	132	1			T29	2		T86	2		T58	2
auto[2952790016:3087007743]	auto[1]	54	1			T29	2		T53	2		T92	2
auto[3087007744:3221225471]	auto[0]	126	1			T5	2		T132	2		T109	2
auto[3087007744:3221225471]	auto[1]	70	1			T29	2		T243	2		T247	2
auto[3221225472:3355443199]	auto[0]	150	1			T41	2		T39	2		T29	2
auto[3221225472:3355443199]	auto[1]	54	1			T71	2		T108	2		T53	2
auto[3355443200:3489660927]	auto[0]	108	1			T69	2		T108	2		T52	2
auto[3355443200:3489660927]	auto[1]	56	1			T108	2		T242	2		T53	2
auto[3489660928:3623878655]	auto[0]	130	1			T1	2		T29	2		T58	2
auto[3489660928:3623878655]	auto[1]	78	1			T39	2		T56	2		T29	2
auto[3623878656:3758096383]	auto[0]	84	1			T132	2		T62	2		T52	4
auto[3623878656:3758096383]	auto[1]	82	1			T58	2		T96	2		T237	2
auto[3758096384:3892314111]	auto[0]	126	1			T5	2		T58	2		T52	4
auto[3758096384:3892314111]	auto[1]	86	1			T85	2		T29	4		T30	2
auto[3892314112:4026531839]	auto[0]	112	1			T85	2		T68	2		T69	2
auto[3892314112:4026531839]	auto[1]	70	1			T3	2		T57	2		T29	2
auto[4026531840:4160749567]	auto[0]	150	1			T29	2		T70	2		T63	4
auto[4026531840:4160749567]	auto[1]	66	1			T7	2		T96	2		T227	2
auto[4160749568:4294967295]	auto[0]	148	1			T57	2		T58	2		T63	2
auto[4160749568:4294967295]	auto[1]	66	1			T108	2		T107	2		T213	2