Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2754

1

T1

8

T3

5

T5

1

auto[1]

331

1

T1

13

T156

6

T142

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T52	2		T242	1		T319	1
auto[134217728:268435455]	98	1			T1	1		T85	1		T29	1
auto[268435456:402653183]	100	1			T1	1		T41	1		T29	1
auto[402653184:536870911]	99	1			T39	1		T58	2		T135	1
auto[536870912:671088639]	94	1			T1	1		T29	2		T63	1
auto[671088640:805306367]	95	1			T1	1		T85	2		T29	2
auto[805306368:939524095]	79	1			T1	1		T3	1		T26	1
auto[939524096:1073741823]	100	1			T29	2		T58	1		T63	1
auto[1073741824:1207959551]	106	1			T1	1		T85	1		T29	2
auto[1207959552:1342177279]	101	1			T1	2		T85	1		T29	2
auto[1342177280:1476395007]	84	1			T1	1		T133	1		T58	1
auto[1476395008:1610612735]	109	1			T85	1		T29	2		T30	1
auto[1610612736:1744830463]	105	1			T26	1		T85	1		T30	1
auto[1744830464:1879048191]	102	1			T3	1		T30	1		T58	1
auto[1879048192:2013265919]	101	1			T29	1		T30	1		T58	2
auto[2013265920:2147483647]	71	1			T1	1		T26	1		T85	1
auto[2147483648:2281701375]	107	1			T1	1		T28	1		T29	3
auto[2281701376:2415919103]	72	1			T29	1		T58	1		T52	2
auto[2415919104:2550136831]	99	1			T1	1		T39	1		T57	1
auto[2550136832:2684354559]	98	1			T1	1		T41	1		T57	1
auto[2684354560:2818572287]	85	1			T1	1		T57	1		T28	1
auto[2818572288:2952790015]	115	1			T1	1		T3	1		T41	1
auto[2952790016:3087007743]	103	1			T3	1		T27	1		T39	1
auto[3087007744:3221225471]	105	1			T3	1		T29	1		T52	1
auto[3221225472:3355443199]	106	1			T39	1		T57	1		T30	1
auto[3355443200:3489660927]	117	1			T1	3		T41	1		T39	1
auto[3489660928:3623878655]	84	1			T27	1		T58	2		T69	1
auto[3623878656:3758096383]	101	1			T1	1		T27	1		T39	1
auto[3758096384:3892314111]	90	1			T1	2		T29	2		T86	1
auto[3892314112:4026531839]	82	1			T5	1		T29	1		T86	1
auto[4026531840:4160749567]	91	1			T56	1		T29	1		T69	1
auto[4160749568:4294967295]	88	1			T85	1		T29	1		T30	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	84	1			T52	2		T242	1		T319	1
auto[0:134217727]	auto[1]	14	1			T144	1		T146	2		T269	1
auto[134217728:268435455]	auto[0]	85	1			T85	1		T29	1		T30	1
auto[134217728:268435455]	auto[1]	13	1			T1	1		T144	1		T146	1
auto[268435456:402653183]	auto[0]	97	1			T1	1		T41	1		T29	1
auto[268435456:402653183]	auto[1]	3	1			T244	1		T417	1		T424	1
auto[402653184:536870911]	auto[0]	89	1			T39	1		T58	2		T135	1
auto[402653184:536870911]	auto[1]	10	1			T156	1		T228	1		T296	1
auto[536870912:671088639]	auto[0]	80	1			T29	2		T63	1		T52	1
auto[536870912:671088639]	auto[1]	14	1			T1	1		T144	2		T252	1
auto[671088640:805306367]	auto[0]	91	1			T85	2		T29	2		T70	1
auto[671088640:805306367]	auto[1]	4	1			T1	1		T365	1		T362	1
auto[805306368:939524095]	auto[0]	67	1			T3	1		T26	1		T29	2
auto[805306368:939524095]	auto[1]	12	1			T1	1		T156	1		T311	1
auto[939524096:1073741823]	auto[0]	89	1			T29	2		T58	1		T63	1
auto[939524096:1073741823]	auto[1]	11	1			T156	2		T142	1		T145	1
auto[1073741824:1207959551]	auto[0]	92	1			T85	1		T29	2		T86	1
auto[1073741824:1207959551]	auto[1]	14	1			T1	1		T156	1		T144	1
auto[1207959552:1342177279]	auto[0]	88	1			T1	2		T85	1		T29	2
auto[1207959552:1342177279]	auto[1]	13	1			T228	2		T244	1		T311	1
auto[1342177280:1476395007]	auto[0]	72	1			T133	1		T58	1		T69	1
auto[1342177280:1476395007]	auto[1]	12	1			T1	1		T144	1		T222	1
auto[1476395008:1610612735]	auto[0]	99	1			T85	1		T29	2		T30	1
auto[1476395008:1610612735]	auto[1]	10	1			T303	1		T269	1		T415	1
auto[1610612736:1744830463]	auto[0]	91	1			T26	1		T85	1		T30	1
auto[1610612736:1744830463]	auto[1]	14	1			T303	1		T228	1		T311	1
auto[1744830464:1879048191]	auto[0]	92	1			T3	1		T30	1		T58	1
auto[1744830464:1879048191]	auto[1]	10	1			T143	1		T330	1		T223	1
auto[1879048192:2013265919]	auto[0]	87	1			T29	1		T30	1		T58	2
auto[1879048192:2013265919]	auto[1]	14	1			T142	1		T143	1		T222	1
auto[2013265920:2147483647]	auto[0]	62	1			T1	1		T26	1		T85	1
auto[2013265920:2147483647]	auto[1]	9	1			T244	1		T269	2		T362	1
auto[2147483648:2281701375]	auto[0]	97	1			T28	1		T29	3		T133	1
auto[2147483648:2281701375]	auto[1]	10	1			T1	1		T296	1		T222	1
auto[2281701376:2415919103]	auto[0]	68	1			T29	1		T58	1		T52	2
auto[2281701376:2415919103]	auto[1]	4	1			T144	1		T244	1		T427	1
auto[2415919104:2550136831]	auto[0]	89	1			T39	1		T57	1		T29	1
auto[2415919104:2550136831]	auto[1]	10	1			T1	1		T252	1		T228	1
auto[2550136832:2684354559]	auto[0]	85	1			T41	1		T57	1		T28	1
auto[2550136832:2684354559]	auto[1]	13	1			T1	1		T252	1		T146	1
auto[2684354560:2818572287]	auto[0]	77	1			T1	1		T57	1		T28	1
auto[2684354560:2818572287]	auto[1]	8	1			T222	1		T354	1		T330	1
auto[2818572288:2952790015]	auto[0]	102	1			T3	1		T41	1		T85	1
auto[2818572288:2952790015]	auto[1]	13	1			T1	1		T116	1		T252	1
auto[2952790016:3087007743]	auto[0]	90	1			T3	1		T27	1		T39	1
auto[2952790016:3087007743]	auto[1]	13	1			T142	1		T143	1		T146	2
auto[3087007744:3221225471]	auto[0]	99	1			T3	1		T29	1		T52	1
auto[3087007744:3221225471]	auto[1]	6	1			T269	2		T330	1		T425	1
auto[3221225472:3355443199]	auto[0]	93	1			T39	1		T57	1		T30	1
auto[3221225472:3355443199]	auto[1]	13	1			T156	1		T146	1		T269	2
auto[3355443200:3489660927]	auto[0]	104	1			T1	3		T41	1		T39	1
auto[3355443200:3489660927]	auto[1]	13	1			T144	2		T252	2		T146	1
auto[3489660928:3623878655]	auto[0]	79	1			T27	1		T58	2		T69	1
auto[3489660928:3623878655]	auto[1]	5	1			T401	1		T362	2		T413	1
auto[3623878656:3758096383]	auto[0]	87	1			T27	1		T39	1		T29	2
auto[3623878656:3758096383]	auto[1]	14	1			T1	1		T144	1		T145	1
auto[3758096384:3892314111]	auto[0]	79	1			T29	2		T86	1		T68	2
auto[3758096384:3892314111]	auto[1]	11	1			T1	2		T144	1		T324	1
auto[3892314112:4026531839]	auto[0]	77	1			T5	1		T29	1		T86	1
auto[3892314112:4026531839]	auto[1]	5	1			T311	1		T413	1		T355	1
auto[4026531840:4160749567]	auto[0]	86	1			T56	1		T29	1		T69	1
auto[4026531840:4160749567]	auto[1]	5	1			T146	1		T222	1		T413	1
auto[4160749568:4294967295]	auto[0]	77	1			T85	1		T29	1		T30	1
auto[4160749568:4294967295]	auto[1]	11	1			T143	1		T144	1		T116	1