Unified Coverage Report :: Group Instance : sealing_sw_binding_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1452

1

T1

4

T3

3

T5

3

auto[1]

1677

1

T1

4

T3

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T5	1		T41	2		T28	1
auto[134217728:268435455]	89	1			T5	2		T39	1		T29	1
auto[268435456:402653183]	108	1			T3	1		T85	1		T28	1
auto[402653184:536870911]	117	1			T5	1		T26	1		T85	1
auto[536870912:671088639]	98	1			T1	1		T57	1		T29	2
auto[671088640:805306367]	95	1			T1	1		T86	2		T58	2
auto[805306368:939524095]	96	1			T3	1		T41	1		T27	1
auto[939524096:1073741823]	91	1			T1	1		T29	1		T86	1
auto[1073741824:1207959551]	96	1			T26	1		T85	1		T30	1
auto[1207959552:1342177279]	99	1			T85	1		T29	2		T52	2
auto[1342177280:1476395007]	85	1			T57	1		T28	1		T29	1
auto[1476395008:1610612735]	105	1			T29	2		T58	2		T63	2
auto[1610612736:1744830463]	90	1			T28	1		T135	1		T136	1
auto[1744830464:1879048191]	108	1			T1	1		T3	1		T57	1
auto[1879048192:2013265919]	96	1			T39	1		T57	1		T85	1
auto[2013265920:2147483647]	99	1			T29	2		T30	2		T69	1
auto[2147483648:2281701375]	104	1			T27	1		T30	1		T69	1
auto[2281701376:2415919103]	86	1			T39	1		T133	1		T135	1
auto[2415919104:2550136831]	104	1			T3	2		T39	1		T58	3
auto[2550136832:2684354559]	86	1			T1	1		T27	1		T29	1
auto[2684354560:2818572287]	101	1			T5	1		T29	3		T86	1
auto[2818572288:2952790015]	100	1			T1	1		T85	1		T29	1
auto[2952790016:3087007743]	84	1			T29	1		T30	1		T58	1
auto[3087007744:3221225471]	98	1			T57	1		T29	4		T58	1
auto[3221225472:3355443199]	88	1			T85	1		T29	2		T133	1
auto[3355443200:3489660927]	88	1			T29	2		T86	1		T133	1
auto[3489660928:3623878655]	97	1			T39	2		T29	2		T68	1
auto[3623878656:3758096383]	89	1			T1	1		T41	1		T29	1
auto[3758096384:3892314111]	108	1			T1	1		T5	1		T29	3
auto[3892314112:4026531839]	111	1			T58	2		T52	3		T242	2
auto[4026531840:4160749567]	104	1			T29	1		T30	1		T108	1
auto[4160749568:4294967295]	95	1			T26	1		T56	1		T58	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T5	1		T41	1		T29	2
auto[0:134217727]	auto[1]	69	1			T41	1		T28	1		T70	2
auto[134217728:268435455]	auto[0]	46	1			T5	1		T39	1		T29	1
auto[134217728:268435455]	auto[1]	43	1			T5	1		T58	1		T96	1
auto[268435456:402653183]	auto[0]	44	1			T3	1		T28	1		T29	1
auto[268435456:402653183]	auto[1]	64	1			T85	1		T29	1		T132	1
auto[402653184:536870911]	auto[0]	54	1			T29	1		T69	1		T52	2
auto[402653184:536870911]	auto[1]	63	1			T5	1		T26	1		T85	1
auto[536870912:671088639]	auto[0]	55	1			T57	1		T29	2		T30	1
auto[536870912:671088639]	auto[1]	43	1			T1	1		T58	1		T71	1
auto[671088640:805306367]	auto[0]	48	1			T86	2		T58	1		T59	1
auto[671088640:805306367]	auto[1]	47	1			T1	1		T58	1		T135	1
auto[805306368:939524095]	auto[0]	38	1			T3	1		T41	1		T69	1
auto[805306368:939524095]	auto[1]	58	1			T27	1		T85	2		T28	1
auto[939524096:1073741823]	auto[0]	55	1			T1	1		T58	1		T63	1
auto[939524096:1073741823]	auto[1]	36	1			T29	1		T86	1		T43	1
auto[1073741824:1207959551]	auto[0]	44	1			T26	1		T18	1		T23	1
auto[1073741824:1207959551]	auto[1]	52	1			T85	1		T30	1		T132	2
auto[1207959552:1342177279]	auto[0]	52	1			T85	1		T29	2		T52	1
auto[1207959552:1342177279]	auto[1]	47	1			T52	1		T156	1		T7	1
auto[1342177280:1476395007]	auto[0]	42	1			T28	1		T29	1		T30	1
auto[1342177280:1476395007]	auto[1]	43	1			T57	1		T135	1		T108	1
auto[1476395008:1610612735]	auto[0]	47	1			T29	1		T58	1		T63	2
auto[1476395008:1610612735]	auto[1]	58	1			T29	1		T58	1		T319	1
auto[1610612736:1744830463]	auto[0]	39	1			T135	1		T34	2		T198	1
auto[1610612736:1744830463]	auto[1]	51	1			T28	1		T136	1		T188	1
auto[1744830464:1879048191]	auto[0]	47	1			T1	1		T57	1		T30	1
auto[1744830464:1879048191]	auto[1]	61	1			T3	1		T85	1		T70	1
auto[1879048192:2013265919]	auto[0]	49	1			T39	1		T57	1		T108	1
auto[1879048192:2013265919]	auto[1]	47	1			T85	1		T58	1		T69	1
auto[2013265920:2147483647]	auto[0]	45	1			T29	2		T30	1		T69	1
auto[2013265920:2147483647]	auto[1]	54	1			T30	1		T70	1		T331	1
auto[2147483648:2281701375]	auto[0]	43	1			T69	1		T242	1		T143	1
auto[2147483648:2281701375]	auto[1]	61	1			T27	1		T30	1		T52	1
auto[2281701376:2415919103]	auto[0]	45	1			T39	1		T108	1		T23	1
auto[2281701376:2415919103]	auto[1]	41	1			T133	1		T135	1		T52	1
auto[2415919104:2550136831]	auto[0]	45	1			T3	1		T39	1		T58	1
auto[2415919104:2550136831]	auto[1]	59	1			T3	1		T58	2		T18	1
auto[2550136832:2684354559]	auto[0]	42	1			T1	1		T29	1		T69	2
auto[2550136832:2684354559]	auto[1]	44	1			T27	1		T30	2		T58	1
auto[2684354560:2818572287]	auto[0]	46	1			T29	1		T70	1		T238	1
auto[2684354560:2818572287]	auto[1]	55	1			T5	1		T29	2		T86	1
auto[2818572288:2952790015]	auto[0]	42	1			T85	1		T29	1		T52	1
auto[2818572288:2952790015]	auto[1]	58	1			T1	1		T30	1		T58	1
auto[2952790016:3087007743]	auto[0]	39	1			T30	1		T58	1		T18	1
auto[2952790016:3087007743]	auto[1]	45	1			T29	1		T52	1		T188	1
auto[3087007744:3221225471]	auto[0]	47	1			T57	1		T29	2		T58	1
auto[3087007744:3221225471]	auto[1]	51	1			T29	2		T62	1		T108	1
auto[3221225472:3355443199]	auto[0]	32	1			T52	1		T7	1		T74	1
auto[3221225472:3355443199]	auto[1]	56	1			T85	1		T29	2		T133	1
auto[3355443200:3489660927]	auto[0]	36	1			T58	1		T52	1		T109	1
auto[3355443200:3489660927]	auto[1]	52	1			T29	2		T86	1		T133	1
auto[3489660928:3623878655]	auto[0]	48	1			T39	2		T29	1		T68	1
auto[3489660928:3623878655]	auto[1]	49	1			T29	1		T71	1		T52	2
auto[3623878656:3758096383]	auto[0]	48	1			T41	1		T29	1		T68	1
auto[3623878656:3758096383]	auto[1]	41	1			T1	1		T52	1		T225	1
auto[3758096384:3892314111]	auto[0]	47	1			T1	1		T5	1		T29	1
auto[3758096384:3892314111]	auto[1]	61	1			T29	2		T71	1		T108	1
auto[3892314112:4026531839]	auto[0]	51	1			T58	1		T52	2		T109	1
auto[3892314112:4026531839]	auto[1]	60	1			T58	1		T52	1		T242	2
auto[4026531840:4160749567]	auto[0]	43	1			T30	1		T108	1		T383	1
auto[4026531840:4160749567]	auto[1]	61	1			T29	1		T95	1		T142	1
auto[4160749568:4294967295]	auto[0]	48	1			T58	1		T69	1		T63	1
auto[4160749568:4294967295]	auto[1]	47	1			T26	1		T56	1		T58	2