Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.04 97.91 98.11 100.00 99.02 98.41 91.22


Total test records in report: 1079
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T1003 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.39120739 Jun 30 04:49:11 PM PDT 24 Jun 30 04:49:23 PM PDT 24 1338949941 ps
T1004 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3905233699 Jun 30 04:48:42 PM PDT 24 Jun 30 04:48:45 PM PDT 24 111176655 ps
T1005 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1275731984 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:14 PM PDT 24 97669139 ps
T1006 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.487039323 Jun 30 04:49:25 PM PDT 24 Jun 30 04:49:27 PM PDT 24 12554608 ps
T1007 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3172279579 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:13 PM PDT 24 182398631 ps
T1008 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2638589043 Jun 30 04:48:43 PM PDT 24 Jun 30 04:48:54 PM PDT 24 169058658 ps
T1009 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3064625465 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:21 PM PDT 24 27066043 ps
T1010 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3793977622 Jun 30 04:49:25 PM PDT 24 Jun 30 04:49:36 PM PDT 24 951362461 ps
T170 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1427557535 Jun 30 04:48:35 PM PDT 24 Jun 30 04:48:43 PM PDT 24 2056361071 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2354728145 Jun 30 04:48:48 PM PDT 24 Jun 30 04:48:49 PM PDT 24 14264500 ps
T1012 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.544229752 Jun 30 04:48:56 PM PDT 24 Jun 30 04:49:07 PM PDT 24 449286766 ps
T1013 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1692662416 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:33 PM PDT 24 26692701 ps
T1014 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2381260108 Jun 30 04:48:41 PM PDT 24 Jun 30 04:48:48 PM PDT 24 150132076 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.273448097 Jun 30 04:48:42 PM PDT 24 Jun 30 04:48:56 PM PDT 24 456958736 ps
T1016 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2765254346 Jun 30 04:49:26 PM PDT 24 Jun 30 04:49:28 PM PDT 24 16637937 ps
T1017 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3811947028 Jun 30 04:49:25 PM PDT 24 Jun 30 04:49:27 PM PDT 24 39944313 ps
T1018 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1211519702 Jun 30 04:49:24 PM PDT 24 Jun 30 04:49:25 PM PDT 24 24172128 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1766900401 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:15 PM PDT 24 255710067 ps
T1020 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1313040733 Jun 30 04:49:03 PM PDT 24 Jun 30 04:49:04 PM PDT 24 46055556 ps
T1021 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1203943568 Jun 30 04:48:48 PM PDT 24 Jun 30 04:48:51 PM PDT 24 60988053 ps
T1022 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3450112965 Jun 30 04:49:18 PM PDT 24 Jun 30 04:49:20 PM PDT 24 114414943 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4138317732 Jun 30 04:49:24 PM PDT 24 Jun 30 04:49:26 PM PDT 24 57029128 ps
T1024 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2070503892 Jun 30 04:49:27 PM PDT 24 Jun 30 04:49:30 PM PDT 24 11721826 ps
T1025 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.165461685 Jun 30 04:49:21 PM PDT 24 Jun 30 04:49:24 PM PDT 24 156354915 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.834241404 Jun 30 04:48:41 PM PDT 24 Jun 30 04:48:45 PM PDT 24 22966552 ps
T1027 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1086770459 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:21 PM PDT 24 607285202 ps
T1028 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3534868757 Jun 30 04:49:08 PM PDT 24 Jun 30 04:49:11 PM PDT 24 32374440 ps
T1029 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3684734421 Jun 30 04:48:56 PM PDT 24 Jun 30 04:49:00 PM PDT 24 665216126 ps
T1030 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2205489088 Jun 30 04:49:11 PM PDT 24 Jun 30 04:49:16 PM PDT 24 156316452 ps
T1031 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3914051129 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:14 PM PDT 24 113587704 ps
T1032 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1789091851 Jun 30 04:48:53 PM PDT 24 Jun 30 04:49:01 PM PDT 24 264414241 ps
T1033 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1195702772 Jun 30 04:49:26 PM PDT 24 Jun 30 04:49:27 PM PDT 24 8690478 ps
T1034 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4097834328 Jun 30 04:48:54 PM PDT 24 Jun 30 04:48:55 PM PDT 24 42154424 ps
T1035 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2306566821 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:20 PM PDT 24 38364403 ps
T1036 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2649345349 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:22 PM PDT 24 81462748 ps
T1037 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1266221492 Jun 30 04:48:55 PM PDT 24 Jun 30 04:48:58 PM PDT 24 33978161 ps
T160 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2068222129 Jun 30 04:49:03 PM PDT 24 Jun 30 04:49:12 PM PDT 24 770891720 ps
T1038 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1429657359 Jun 30 04:48:40 PM PDT 24 Jun 30 04:48:44 PM PDT 24 12522475 ps
T1039 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3114184013 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:13 PM PDT 24 15485745 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2238257412 Jun 30 04:48:41 PM PDT 24 Jun 30 04:48:47 PM PDT 24 66378648 ps
T1041 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3322015064 Jun 30 04:49:25 PM PDT 24 Jun 30 04:49:26 PM PDT 24 29892430 ps
T1042 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1986418290 Jun 30 04:48:57 PM PDT 24 Jun 30 04:49:00 PM PDT 24 110189904 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2418776168 Jun 30 04:48:49 PM PDT 24 Jun 30 04:48:51 PM PDT 24 61656342 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3302700143 Jun 30 04:48:49 PM PDT 24 Jun 30 04:48:51 PM PDT 24 79376919 ps
T1045 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1462616715 Jun 30 04:49:18 PM PDT 24 Jun 30 04:49:23 PM PDT 24 2041361740 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3625818042 Jun 30 04:48:41 PM PDT 24 Jun 30 04:48:44 PM PDT 24 62085891 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.950035786 Jun 30 04:49:24 PM PDT 24 Jun 30 04:49:32 PM PDT 24 249883037 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4153786880 Jun 30 04:48:52 PM PDT 24 Jun 30 04:49:02 PM PDT 24 408022057 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2191657345 Jun 30 04:48:42 PM PDT 24 Jun 30 04:48:45 PM PDT 24 175697737 ps
T1050 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1848558919 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:12 PM PDT 24 9459270 ps
T1051 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2250706899 Jun 30 04:48:59 PM PDT 24 Jun 30 04:49:02 PM PDT 24 103447926 ps
T1052 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3092342535 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:21 PM PDT 24 112217173 ps
T1053 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4124801877 Jun 30 04:49:02 PM PDT 24 Jun 30 04:49:04 PM PDT 24 246809514 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.396213167 Jun 30 04:49:02 PM PDT 24 Jun 30 04:49:08 PM PDT 24 212378912 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1772867185 Jun 30 04:49:04 PM PDT 24 Jun 30 04:49:07 PM PDT 24 206974145 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4235002921 Jun 30 04:48:53 PM PDT 24 Jun 30 04:48:55 PM PDT 24 196373958 ps
T1057 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1797990096 Jun 30 04:48:48 PM PDT 24 Jun 30 04:48:50 PM PDT 24 24331057 ps
T1058 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3254094995 Jun 30 04:49:05 PM PDT 24 Jun 30 04:49:07 PM PDT 24 175620526 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3221815976 Jun 30 04:49:20 PM PDT 24 Jun 30 04:49:24 PM PDT 24 288219477 ps
T1060 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1328498470 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:22 PM PDT 24 48452027 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.507539562 Jun 30 04:49:11 PM PDT 24 Jun 30 04:49:15 PM PDT 24 56366686 ps
T1062 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4281499664 Jun 30 04:48:48 PM PDT 24 Jun 30 04:48:53 PM PDT 24 432733842 ps
T1063 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4102481605 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:25 PM PDT 24 1268435363 ps
T1064 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1368090252 Jun 30 04:48:42 PM PDT 24 Jun 30 04:48:46 PM PDT 24 64260464 ps
T1065 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2968777779 Jun 30 04:49:19 PM PDT 24 Jun 30 04:49:21 PM PDT 24 73522201 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3158572637 Jun 30 04:48:56 PM PDT 24 Jun 30 04:48:58 PM PDT 24 261743683 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3293636107 Jun 30 04:48:48 PM PDT 24 Jun 30 04:48:56 PM PDT 24 191989810 ps
T1068 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1606685223 Jun 30 04:48:41 PM PDT 24 Jun 30 04:48:58 PM PDT 24 2236099005 ps
T1069 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1894776463 Jun 30 04:49:20 PM PDT 24 Jun 30 04:49:22 PM PDT 24 37570195 ps
T1070 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1544048024 Jun 30 04:49:04 PM PDT 24 Jun 30 04:49:13 PM PDT 24 405314692 ps
T1071 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3683061066 Jun 30 04:49:26 PM PDT 24 Jun 30 04:49:28 PM PDT 24 71065835 ps
T1072 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2217657088 Jun 30 04:49:18 PM PDT 24 Jun 30 04:49:33 PM PDT 24 1456546923 ps
T1073 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1467741005 Jun 30 04:49:24 PM PDT 24 Jun 30 04:49:26 PM PDT 24 11870475 ps
T1074 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2395659901 Jun 30 04:49:04 PM PDT 24 Jun 30 04:49:07 PM PDT 24 45651340 ps
T1075 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3779917416 Jun 30 04:49:26 PM PDT 24 Jun 30 04:49:28 PM PDT 24 22889477 ps
T1076 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3310901965 Jun 30 04:49:10 PM PDT 24 Jun 30 04:49:12 PM PDT 24 32830743 ps
T1077 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3509282063 Jun 30 04:49:02 PM PDT 24 Jun 30 04:49:03 PM PDT 24 14404765 ps
T1078 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2466714044 Jun 30 04:48:57 PM PDT 24 Jun 30 04:49:01 PM PDT 24 121327402 ps
T1079 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.660733168 Jun 30 04:49:27 PM PDT 24 Jun 30 04:49:29 PM PDT 24 10055509 ps

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.662660077
Short name T1
Test name
Test status
Simulation time 436358672 ps
CPU time 12.41 seconds
Started Jun 30 05:45:55 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 215956 kb
Host smart-5004fe22-d0ab-43aa-8057-c8254d2f8d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662660077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.662660077
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2668430068
Short name T58
Test name
Test status
Simulation time 34319654518 ps
CPU time 388.53 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:50:40 PM PDT 24
Peak memory 220476 kb
Host smart-0d5f6393-4783-4547-a710-608bde5a07e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668430068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2668430068
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3186973141
Short name T52
Test name
Test status
Simulation time 6297464580 ps
CPU time 187.52 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:47:19 PM PDT 24
Peak memory 222568 kb
Host smart-ff30dd2d-4253-4002-82d5-8251c903718d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186973141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3186973141
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1528595049
Short name T128
Test name
Test status
Simulation time 1071509878 ps
CPU time 19.76 seconds
Started Jun 30 05:46:14 PM PDT 24
Finished Jun 30 05:46:34 PM PDT 24
Peak memory 222572 kb
Host smart-2b71bf1d-9c53-4971-b3a5-d0c6105cec07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528595049 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1528595049
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2410195202
Short name T11
Test name
Test status
Simulation time 361805204 ps
CPU time 9.12 seconds
Started Jun 30 05:43:59 PM PDT 24
Finished Jun 30 05:44:08 PM PDT 24
Peak memory 237260 kb
Host smart-f77cc834-e281-46a0-863b-f812a9757dda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410195202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2410195202
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2157074370
Short name T29
Test name
Test status
Simulation time 1679310361 ps
CPU time 24.77 seconds
Started Jun 30 05:43:44 PM PDT 24
Finished Jun 30 05:44:10 PM PDT 24
Peak memory 222504 kb
Host smart-4cbdb5ec-8f32-4f05-beee-d3de3c87c747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157074370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2157074370
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3667425524
Short name T67
Test name
Test status
Simulation time 742207655 ps
CPU time 11.53 seconds
Started Jun 30 05:45:14 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 222912 kb
Host smart-337aaff0-ea67-42c0-993a-a186662a7f26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667425524 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3667425524
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.845930720
Short name T109
Test name
Test status
Simulation time 46089038 ps
CPU time 2.4 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 214348 kb
Host smart-75ab7f4c-9592-4936-a63b-ed975d9a0c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845930720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.845930720
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3082497438
Short name T8
Test name
Test status
Simulation time 71327032 ps
CPU time 2.16 seconds
Started Jun 30 05:44:20 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 217456 kb
Host smart-4a42acbf-7324-480f-85a5-5031f3283981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082497438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3082497438
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1478868021
Short name T413
Test name
Test status
Simulation time 3555250720 ps
CPU time 45.33 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:45 PM PDT 24
Peak memory 214384 kb
Host smart-f3f89275-c1ff-4224-a48b-f7f03e968610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478868021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1478868021
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.760460679
Short name T120
Test name
Test status
Simulation time 1024718550 ps
CPU time 13.73 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:33 PM PDT 24
Peak memory 214080 kb
Host smart-29639fba-4b95-4755-9c98-26bcd80285a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760460679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.760460679
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2736290129
Short name T10
Test name
Test status
Simulation time 282043806 ps
CPU time 5.55 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 219552 kb
Host smart-10690150-bda8-4274-b296-66b2d28e99bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736290129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2736290129
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2598681178
Short name T54
Test name
Test status
Simulation time 1078451790 ps
CPU time 38.59 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 222008 kb
Host smart-3bdc47eb-7a9a-4563-a29d-552aef68f724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598681178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2598681178
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2029008612
Short name T39
Test name
Test status
Simulation time 156394069 ps
CPU time 4.88 seconds
Started Jun 30 05:46:02 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 214264 kb
Host smart-c2c88a7a-b076-463d-ba4b-04377cb9a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029008612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2029008612
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2727319663
Short name T89
Test name
Test status
Simulation time 171960667 ps
CPU time 5.5 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 209164 kb
Host smart-499fb6aa-486e-4b50-a0e0-ca7633d15cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727319663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2727319663
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1182856555
Short name T85
Test name
Test status
Simulation time 1017882821 ps
CPU time 14.12 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:46:00 PM PDT 24
Peak memory 222604 kb
Host smart-26c0943a-78f4-48c5-bfbf-08b62a713d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182856555 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1182856555
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1873918266
Short name T157
Test name
Test status
Simulation time 195576252 ps
CPU time 2.23 seconds
Started Jun 30 04:48:57 PM PDT 24
Finished Jun 30 04:49:01 PM PDT 24
Peak memory 216988 kb
Host smart-12216dae-dcca-45d9-80f0-74d7193d4774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873918266 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1873918266
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1391152833
Short name T223
Test name
Test status
Simulation time 1022285689 ps
CPU time 7.77 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 214308 kb
Host smart-25ac5535-1f46-4dcc-8c65-d2e5dd62169c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391152833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1391152833
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2664956243
Short name T61
Test name
Test status
Simulation time 7617474624 ps
CPU time 44.3 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:46:54 PM PDT 24
Peak memory 216356 kb
Host smart-155601b1-18cc-4d89-890b-a2a37ccf7a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664956243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2664956243
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2670262506
Short name T352
Test name
Test status
Simulation time 488188515 ps
CPU time 24.35 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:29 PM PDT 24
Peak memory 214316 kb
Host smart-05ae55e2-7c15-4a0e-b451-f91c7e148acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670262506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2670262506
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2804362088
Short name T34
Test name
Test status
Simulation time 167130454 ps
CPU time 4.03 seconds
Started Jun 30 05:45:52 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 214360 kb
Host smart-bc14c6f3-416b-4bea-a863-cafe503305ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804362088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2804362088
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.579746286
Short name T244
Test name
Test status
Simulation time 2461637685 ps
CPU time 32.27 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 215972 kb
Host smart-ec3b43d3-c570-44b0-b68d-8dd3033cae9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579746286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.579746286
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4040448123
Short name T180
Test name
Test status
Simulation time 69662684 ps
CPU time 2.2 seconds
Started Jun 30 05:43:52 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 215644 kb
Host smart-73e94065-457f-4adb-a645-637e4bdc2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040448123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4040448123
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.350354916
Short name T78
Test name
Test status
Simulation time 20457584284 ps
CPU time 192.62 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:48:47 PM PDT 24
Peak memory 222588 kb
Host smart-a410e01f-4f82-4176-bf51-587a3b2389d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350354916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.350354916
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.547563300
Short name T116
Test name
Test status
Simulation time 230329302 ps
CPU time 6.67 seconds
Started Jun 30 05:43:49 PM PDT 24
Finished Jun 30 05:43:56 PM PDT 24
Peak memory 214344 kb
Host smart-9912c50a-5cdb-4a69-993a-96832eceb75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547563300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.547563300
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.211902940
Short name T123
Test name
Test status
Simulation time 285513512 ps
CPU time 3.07 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:16 PM PDT 24
Peak memory 213904 kb
Host smart-ad0fa89c-8248-4c2f-a759-0e80d9dd19cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211902940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.211902940
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2653736744
Short name T754
Test name
Test status
Simulation time 281391487 ps
CPU time 7.46 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:49 PM PDT 24
Peak memory 209840 kb
Host smart-5a0c355b-1abf-4746-9b69-ba872828344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653736744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2653736744
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2245140651
Short name T108
Test name
Test status
Simulation time 947439236 ps
CPU time 17.09 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:15 PM PDT 24
Peak memory 220488 kb
Host smart-7359bc41-05ee-453e-b706-d65c68aa7cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245140651 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2245140651
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.622255751
Short name T5
Test name
Test status
Simulation time 164026900 ps
CPU time 2.16 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 219988 kb
Host smart-56b8c22e-bcb7-4c3a-9fd7-ec0c0113ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622255751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.622255751
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1237445724
Short name T119
Test name
Test status
Simulation time 183597653 ps
CPU time 2.35 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:46 PM PDT 24
Peak memory 215436 kb
Host smart-192ef6db-b7be-4abf-8bcd-13adb0ad3a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237445724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1237445724
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3887546819
Short name T432
Test name
Test status
Simulation time 541449592 ps
CPU time 6.27 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 214336 kb
Host smart-a6ddc144-2a99-40c0-8076-45b658341787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887546819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3887546819
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.150783219
Short name T98
Test name
Test status
Simulation time 881207707 ps
CPU time 5.19 seconds
Started Jun 30 05:45:44 PM PDT 24
Finished Jun 30 05:45:49 PM PDT 24
Peak memory 209244 kb
Host smart-a970000e-4341-4488-9e00-4cdb7d0a868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150783219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.150783219
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.241448976
Short name T217
Test name
Test status
Simulation time 6310643623 ps
CPU time 49.64 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 215456 kb
Host smart-9ab12411-3470-4c84-9134-5de2de039ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241448976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.241448976
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4161058389
Short name T48
Test name
Test status
Simulation time 766183117 ps
CPU time 8.27 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:44:00 PM PDT 24
Peak memory 210836 kb
Host smart-51b3ff9f-e69f-443a-85a0-08b510788808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161058389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4161058389
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3114340763
Short name T30
Test name
Test status
Simulation time 124233011 ps
CPU time 8.6 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:25 PM PDT 24
Peak memory 222504 kb
Host smart-a43faab6-91c0-4f89-91c3-0fc1fe040a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114340763 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3114340763
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3552920973
Short name T357
Test name
Test status
Simulation time 1458146924 ps
CPU time 79.67 seconds
Started Jun 30 05:44:39 PM PDT 24
Finished Jun 30 05:46:00 PM PDT 24
Peak memory 214424 kb
Host smart-642b3ca0-2d78-4a4e-8307-4d7a8b5d456f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552920973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3552920973
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1827296095
Short name T142
Test name
Test status
Simulation time 51670706 ps
CPU time 3.78 seconds
Started Jun 30 05:46:22 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 222532 kb
Host smart-d10b286c-9813-4ee1-be2b-496d63d6d417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827296095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1827296095
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.369292082
Short name T439
Test name
Test status
Simulation time 245233863 ps
CPU time 0.95 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 206012 kb
Host smart-a406d37f-fb9b-400c-8391-4e07985c92f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369292082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.369292082
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2528117311
Short name T279
Test name
Test status
Simulation time 260624044 ps
CPU time 2.25 seconds
Started Jun 30 05:45:26 PM PDT 24
Finished Jun 30 05:45:29 PM PDT 24
Peak memory 214408 kb
Host smart-95cc31bf-50f2-4654-b259-cf7656f43483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528117311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2528117311
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3802123426
Short name T165
Test name
Test status
Simulation time 340751796 ps
CPU time 5.49 seconds
Started Jun 30 04:48:55 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 215508 kb
Host smart-5532e1bf-a37f-400f-85f7-e424cf321ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802123426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3802123426
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1380930540
Short name T130
Test name
Test status
Simulation time 544826575 ps
CPU time 11.19 seconds
Started Jun 30 05:44:39 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 222632 kb
Host smart-4a8153a7-8f0e-4322-b91d-fe75ae7c4902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380930540 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1380930540
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1112205670
Short name T420
Test name
Test status
Simulation time 3590552094 ps
CPU time 42.19 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 214400 kb
Host smart-8807a95b-08b6-4cb8-8b67-d29e4106b175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112205670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1112205670
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.642983068
Short name T166
Test name
Test status
Simulation time 593090040 ps
CPU time 20.49 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:45:11 PM PDT 24
Peak memory 221040 kb
Host smart-19637dbf-4b6a-48ca-84bc-98dd53e74795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642983068 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.642983068
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2277296106
Short name T79
Test name
Test status
Simulation time 1174595443 ps
CPU time 37.97 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 222580 kb
Host smart-ea20503d-22c5-4e56-9f21-71a28f3917bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277296106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2277296106
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3478642233
Short name T746
Test name
Test status
Simulation time 108711932579 ps
CPU time 380.02 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:52:30 PM PDT 24
Peak memory 222548 kb
Host smart-139d9103-9b70-4976-a228-a59069551417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478642233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3478642233
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3006612813
Short name T143
Test name
Test status
Simulation time 99643732 ps
CPU time 3.96 seconds
Started Jun 30 05:43:58 PM PDT 24
Finished Jun 30 05:44:03 PM PDT 24
Peak memory 214564 kb
Host smart-14c670b1-416d-4db7-90fb-0f9491d8413d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006612813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3006612813
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1775235109
Short name T25
Test name
Test status
Simulation time 55155954 ps
CPU time 2.2 seconds
Started Jun 30 05:44:27 PM PDT 24
Finished Jun 30 05:44:30 PM PDT 24
Peak memory 209544 kb
Host smart-ca312afb-0456-4576-92b3-ca58b1915015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775235109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1775235109
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1605455704
Short name T7
Test name
Test status
Simulation time 65287729 ps
CPU time 4.91 seconds
Started Jun 30 05:46:02 PM PDT 24
Finished Jun 30 05:46:07 PM PDT 24
Peak memory 214352 kb
Host smart-01bad7af-ffca-4d12-a88d-e60f688be56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605455704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1605455704
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3364425452
Short name T168
Test name
Test status
Simulation time 1298394613 ps
CPU time 12.3 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 213940 kb
Host smart-1257830c-30b7-4333-97b5-add9d0164965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364425452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3364425452
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1602216799
Short name T216
Test name
Test status
Simulation time 75930602 ps
CPU time 2.61 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 221828 kb
Host smart-da3b2d20-e158-4847-9500-020d2a77acbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602216799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1602216799
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3992844800
Short name T95
Test name
Test status
Simulation time 30399230 ps
CPU time 1.97 seconds
Started Jun 30 05:45:04 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 214472 kb
Host smart-67c4e80d-9ff1-4e92-93a5-3ee1bbb9c00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992844800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3992844800
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1874968786
Short name T588
Test name
Test status
Simulation time 1070406278 ps
CPU time 3.72 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:39 PM PDT 24
Peak memory 214276 kb
Host smart-453f342a-83ce-4439-946e-ff24fb79ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874968786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1874968786
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3450781473
Short name T323
Test name
Test status
Simulation time 184674422 ps
CPU time 2.5 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 208960 kb
Host smart-1c77fccd-3dde-4c38-aef8-e3a55a389241
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450781473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3450781473
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3042993893
Short name T254
Test name
Test status
Simulation time 782031457 ps
CPU time 11.01 seconds
Started Jun 30 05:44:00 PM PDT 24
Finished Jun 30 05:44:12 PM PDT 24
Peak memory 222504 kb
Host smart-e4034e07-939d-42a5-8b73-7c0a702d8a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042993893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3042993893
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3828085999
Short name T64
Test name
Test status
Simulation time 38474404 ps
CPU time 2.85 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:46:12 PM PDT 24
Peak memory 220744 kb
Host smart-af3423ac-5c6e-4e92-b19b-478635e9b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828085999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3828085999
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.821282691
Short name T172
Test name
Test status
Simulation time 73852972 ps
CPU time 2.24 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 209884 kb
Host smart-9c963b85-0985-4880-8c8f-59332f6d8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821282691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.821282691
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3797775413
Short name T159
Test name
Test status
Simulation time 663140352 ps
CPU time 5.14 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:34 PM PDT 24
Peak memory 213592 kb
Host smart-a4c4ac78-bf67-4b63-bdf1-5243a6a79815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797775413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3797775413
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.697841651
Short name T177
Test name
Test status
Simulation time 95791148 ps
CPU time 4.72 seconds
Started Jun 30 04:49:09 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 213524 kb
Host smart-2d823d57-75f3-4fc0-9c1b-0e6a28df6841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697841651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
697841651
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3865049679
Short name T50
Test name
Test status
Simulation time 2164426489 ps
CPU time 12.16 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:44:05 PM PDT 24
Peak memory 233016 kb
Host smart-6bda77f9-38df-4e1f-b1c6-afa537360fc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865049679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3865049679
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3481983977
Short name T60
Test name
Test status
Simulation time 21851349 ps
CPU time 2.05 seconds
Started Jun 30 05:46:06 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 217276 kb
Host smart-94c41344-e24b-4598-8270-c6260ba28f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481983977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3481983977
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2322553168
Short name T156
Test name
Test status
Simulation time 232244694 ps
CPU time 13.12 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:56 PM PDT 24
Peak memory 214336 kb
Host smart-e9f730cc-fe93-4540-a214-e626bf1e7f30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322553168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2322553168
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.352579244
Short name T57
Test name
Test status
Simulation time 144113047 ps
CPU time 2.74 seconds
Started Jun 30 05:43:45 PM PDT 24
Finished Jun 30 05:43:48 PM PDT 24
Peak memory 214340 kb
Host smart-629b013e-1469-4dc5-8ecf-ede287a30888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352579244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.352579244
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.915479794
Short name T84
Test name
Test status
Simulation time 2180083845 ps
CPU time 40.67 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 215236 kb
Host smart-4131bf08-b458-47e5-ada5-f2618e1fbbc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915479794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.915479794
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3678242777
Short name T345
Test name
Test status
Simulation time 113886427 ps
CPU time 4.81 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 214312 kb
Host smart-27df28bb-ae7d-4617-a52c-2ed650eb8df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678242777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3678242777
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2044288288
Short name T365
Test name
Test status
Simulation time 116194366 ps
CPU time 4.01 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 214336 kb
Host smart-6bf368f1-e6bf-4c1c-95a4-9175f46a7eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044288288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2044288288
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2054720423
Short name T232
Test name
Test status
Simulation time 35541985 ps
CPU time 2.45 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:54 PM PDT 24
Peak memory 214316 kb
Host smart-3b47196f-e9c6-4f40-88b0-8a9bada78296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054720423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2054720423
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2090383044
Short name T70
Test name
Test status
Simulation time 511641708 ps
CPU time 10.37 seconds
Started Jun 30 05:46:15 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 219736 kb
Host smart-fc32c95d-0b55-4986-a8e6-4b2ce2f7f02b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090383044 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2090383044
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.70083050
Short name T196
Test name
Test status
Simulation time 2189328751 ps
CPU time 50.94 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:47:00 PM PDT 24
Peak memory 216756 kb
Host smart-3e5f7ef3-fa99-45c0-9e55-34f1fc5fabd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70083050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.70083050
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1928255033
Short name T118
Test name
Test status
Simulation time 86988788 ps
CPU time 2.83 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:15 PM PDT 24
Peak memory 217604 kb
Host smart-51ed38c9-95bc-423d-a5ab-57394e815535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928255033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1928255033
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.787963661
Short name T209
Test name
Test status
Simulation time 16082822825 ps
CPU time 35.32 seconds
Started Jun 30 05:43:36 PM PDT 24
Finished Jun 30 05:44:12 PM PDT 24
Peak memory 222428 kb
Host smart-d0db66c7-6bc9-4e44-a740-84bef1abc6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787963661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.787963661
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3622123316
Short name T671
Test name
Test status
Simulation time 112994886 ps
CPU time 3.23 seconds
Started Jun 30 05:44:21 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 210468 kb
Host smart-5babfbc0-2f75-49e5-9e09-86fbb6bd89a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622123316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3622123316
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1291748935
Short name T320
Test name
Test status
Simulation time 2140460302 ps
CPU time 31.88 seconds
Started Jun 30 05:44:17 PM PDT 24
Finished Jun 30 05:44:50 PM PDT 24
Peak memory 215096 kb
Host smart-978f7228-2fff-4cef-a7e1-f542c449c959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291748935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1291748935
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1285235475
Short name T90
Test name
Test status
Simulation time 354394382 ps
CPU time 11.86 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 220968 kb
Host smart-1f6a971a-1219-494e-8b0c-48a77c0c977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285235475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1285235475
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3784816698
Short name T706
Test name
Test status
Simulation time 482416642 ps
CPU time 2.69 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:44 PM PDT 24
Peak memory 214224 kb
Host smart-5ef1c029-bf6a-4eb1-8c84-2250fe22c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784816698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3784816698
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3987420046
Short name T361
Test name
Test status
Simulation time 30171790 ps
CPU time 2.32 seconds
Started Jun 30 05:45:14 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 207732 kb
Host smart-4849c49b-f210-4ca9-9fcb-31f4aa9a2083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987420046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3987420046
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.888864857
Short name T512
Test name
Test status
Simulation time 150356898 ps
CPU time 3.88 seconds
Started Jun 30 05:45:18 PM PDT 24
Finished Jun 30 05:45:22 PM PDT 24
Peak memory 208740 kb
Host smart-ad4cfe7d-d3ef-4336-93eb-fe085381f738
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888864857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.888864857
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.558759580
Short name T83
Test name
Test status
Simulation time 968687841 ps
CPU time 36.98 seconds
Started Jun 30 05:43:56 PM PDT 24
Finished Jun 30 05:44:34 PM PDT 24
Peak memory 222316 kb
Host smart-78401a1b-8324-4b8c-a313-d68117128aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558759580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.558759580
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3337484149
Short name T23
Test name
Test status
Simulation time 35828806 ps
CPU time 2.66 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:07 PM PDT 24
Peak memory 208460 kb
Host smart-0801a962-7986-4637-bb6d-1ccba353ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337484149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3337484149
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1427557535
Short name T170
Test name
Test status
Simulation time 2056361071 ps
CPU time 7.24 seconds
Started Jun 30 04:48:35 PM PDT 24
Finished Jun 30 04:48:43 PM PDT 24
Peak memory 213668 kb
Host smart-139c14ce-f243-4563-936f-d7795fdc0707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427557535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1427557535
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4175159914
Short name T171
Test name
Test status
Simulation time 817560638 ps
CPU time 8.37 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 213660 kb
Host smart-b9034f94-4209-41db-b415-0c7ca6601728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175159914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4175159914
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.228738162
Short name T173
Test name
Test status
Simulation time 258724733 ps
CPU time 9.14 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:29 PM PDT 24
Peak memory 213632 kb
Host smart-56886b94-a448-4010-81b2-ec490df84129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228738162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.228738162
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2236281849
Short name T179
Test name
Test status
Simulation time 339434688 ps
CPU time 3.94 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 213596 kb
Host smart-35d8944c-63af-49c6-9a60-1c9e06dea535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236281849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2236281849
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1658139392
Short name T161
Test name
Test status
Simulation time 110322358 ps
CPU time 2.73 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 209772 kb
Host smart-02c88957-3ffa-404b-a82f-2494e3489a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658139392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1658139392
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1420005628
Short name T178
Test name
Test status
Simulation time 522725959 ps
CPU time 7.9 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:50 PM PDT 24
Peak memory 210732 kb
Host smart-1058ae6b-c458-497f-97e3-bba59b38e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420005628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1420005628
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2209304654
Short name T117
Test name
Test status
Simulation time 99500338 ps
CPU time 3.68 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 218620 kb
Host smart-67232bb6-5459-4582-8590-a1a74efe9252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209304654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2209304654
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3731694732
Short name T390
Test name
Test status
Simulation time 111857031 ps
CPU time 3.67 seconds
Started Jun 30 04:48:57 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 205480 kb
Host smart-96a6e7b9-b957-41af-90f2-d938fb819cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731694732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3731694732
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3325929990
Short name T434
Test name
Test status
Simulation time 809859294 ps
CPU time 11.56 seconds
Started Jun 30 05:44:17 PM PDT 24
Finished Jun 30 05:44:29 PM PDT 24
Peak memory 222388 kb
Host smart-cd4dc30a-9d8a-44ff-a644-5d4be6279ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325929990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3325929990
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_random.487391019
Short name T356
Test name
Test status
Simulation time 585049203 ps
CPU time 4.75 seconds
Started Jun 30 05:44:20 PM PDT 24
Finished Jun 30 05:44:25 PM PDT 24
Peak memory 209496 kb
Host smart-ea013d06-4de4-4f28-9df0-92df26a96882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487391019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.487391019
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1190965460
Short name T53
Test name
Test status
Simulation time 357907793 ps
CPU time 13.45 seconds
Started Jun 30 05:44:22 PM PDT 24
Finished Jun 30 05:44:35 PM PDT 24
Peak memory 222636 kb
Host smart-4e07a96d-ed5c-4e9d-be4d-12d947e29c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190965460 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1190965460
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3021443820
Short name T192
Test name
Test status
Simulation time 2742071279 ps
CPU time 19.15 seconds
Started Jun 30 05:44:35 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 222624 kb
Host smart-cf907d11-e4ad-4943-96fc-4ac5d9258910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021443820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3021443820
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3750979304
Short name T464
Test name
Test status
Simulation time 75114552 ps
CPU time 2.87 seconds
Started Jun 30 05:44:24 PM PDT 24
Finished Jun 30 05:44:28 PM PDT 24
Peak memory 209876 kb
Host smart-bfa688da-a36a-4303-b28a-388209fc0a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750979304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3750979304
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3714122705
Short name T443
Test name
Test status
Simulation time 480816570 ps
CPU time 10.57 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 208236 kb
Host smart-6f567d45-0a43-438b-ab2f-93f1fbdc49c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714122705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3714122705
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.473420805
Short name T498
Test name
Test status
Simulation time 199140997 ps
CPU time 7.82 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 208068 kb
Host smart-f7e4a4f6-4acb-450e-903b-e1b973477b8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473420805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.473420805
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3221903446
Short name T219
Test name
Test status
Simulation time 316757737 ps
CPU time 3.55 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 210316 kb
Host smart-9a0422a7-aab0-4f4e-9a46-84fe3c5703a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221903446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3221903446
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1291950745
Short name T355
Test name
Test status
Simulation time 55596199 ps
CPU time 4.03 seconds
Started Jun 30 05:44:50 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 214352 kb
Host smart-ad509073-1e3f-41e7-9812-1d0e6e8d82f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291950745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1291950745
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3884235629
Short name T300
Test name
Test status
Simulation time 3680582515 ps
CPU time 95.64 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:45:28 PM PDT 24
Peak memory 221360 kb
Host smart-bf7bc8ef-80e2-4b7b-b1d4-e11284542e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884235629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3884235629
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1633254238
Short name T55
Test name
Test status
Simulation time 1370111047 ps
CPU time 15.79 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:45 PM PDT 24
Peak memory 215984 kb
Host smart-1616745a-2f8f-4785-bbee-50682188715e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633254238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1633254238
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1093776675
Short name T425
Test name
Test status
Simulation time 1199646677 ps
CPU time 16.91 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 214796 kb
Host smart-74b2cb63-a343-4e05-a4d6-b50feb17c12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093776675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1093776675
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.602543295
Short name T220
Test name
Test status
Simulation time 72779369 ps
CPU time 2.8 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 208888 kb
Host smart-edc1ea20-a844-4c80-9922-4a5a680c093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602543295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.602543295
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1044899023
Short name T265
Test name
Test status
Simulation time 334683809 ps
CPU time 2.46 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 218484 kb
Host smart-6c3c0c9f-cc2e-4ae9-86e8-84c16e9fc736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044899023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1044899023
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1776764921
Short name T154
Test name
Test status
Simulation time 489793843 ps
CPU time 8.88 seconds
Started Jun 30 04:48:40 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 205568 kb
Host smart-f9e66093-2cb6-462d-a03a-5eb693f04a3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776764921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
776764921
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.273448097
Short name T1015
Test name
Test status
Simulation time 456958736 ps
CPU time 12.27 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:56 PM PDT 24
Peak memory 205304 kb
Host smart-6052df62-3326-46b6-ac26-3eb2201513ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273448097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.273448097
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2841806939
Short name T955
Test name
Test status
Simulation time 44911694 ps
CPU time 1.12 seconds
Started Jun 30 04:48:35 PM PDT 24
Finished Jun 30 04:48:37 PM PDT 24
Peak memory 205472 kb
Host smart-a4e8da9c-b708-4c80-85b0-29c2d362634d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841806939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
841806939
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.760940782
Short name T990
Test name
Test status
Simulation time 68377827 ps
CPU time 1.47 seconds
Started Jun 30 04:48:44 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 213964 kb
Host smart-fec4b4ce-e1c0-4d6c-9bbc-500df8df8c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760940782 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.760940782
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2834640838
Short name T152
Test name
Test status
Simulation time 146296690 ps
CPU time 1.33 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 205416 kb
Host smart-bdf3b995-0481-45c1-bcb5-b52a60c7984f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834640838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2834640838
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4195816824
Short name T936
Test name
Test status
Simulation time 39083524 ps
CPU time 0.78 seconds
Started Jun 30 04:48:33 PM PDT 24
Finished Jun 30 04:48:34 PM PDT 24
Peak memory 205172 kb
Host smart-1cfec0b4-c9fb-4803-ba1b-f45ed09ddc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195816824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4195816824
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3486198436
Short name T944
Test name
Test status
Simulation time 64429226 ps
CPU time 2.45 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 213524 kb
Host smart-db8a7cec-9573-4f66-aefe-7c7cc52441ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486198436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3486198436
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3742242784
Short name T988
Test name
Test status
Simulation time 119704322 ps
CPU time 3.11 seconds
Started Jun 30 04:48:34 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 213796 kb
Host smart-a5e0defc-9a0e-48c6-a459-20d813992489
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742242784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3742242784
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4234599595
Short name T995
Test name
Test status
Simulation time 460357357 ps
CPU time 14.66 seconds
Started Jun 30 04:48:33 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 220128 kb
Host smart-4dd14d9b-e8c6-4c09-a004-74f7a72ccc3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234599595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.4234599595
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3330153449
Short name T999
Test name
Test status
Simulation time 602644254 ps
CPU time 3.08 seconds
Started Jun 30 04:48:35 PM PDT 24
Finished Jun 30 04:48:38 PM PDT 24
Peak memory 213604 kb
Host smart-5d7ea271-de8d-4c58-834c-c19ac168185b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330153449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3330153449
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2238257412
Short name T1040
Test name
Test status
Simulation time 66378648 ps
CPU time 4.23 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:47 PM PDT 24
Peak memory 205488 kb
Host smart-0d10f815-0c3b-486d-be44-57523cc99a1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238257412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
238257412
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2707186294
Short name T956
Test name
Test status
Simulation time 497408252 ps
CPU time 14.78 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 205524 kb
Host smart-d6f64464-8f59-4c09-bc5f-07697b914789
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707186294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
707186294
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3905233699
Short name T1004
Test name
Test status
Simulation time 111176655 ps
CPU time 1.06 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 205436 kb
Host smart-99e9125f-bac0-4221-b2f0-f063656a0520
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905233699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
905233699
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1368090252
Short name T1064
Test name
Test status
Simulation time 64260464 ps
CPU time 2.37 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 213684 kb
Host smart-af58cb13-ccaa-4b4c-9f6b-8fdca3fe133f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368090252 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1368090252
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2191657345
Short name T1049
Test name
Test status
Simulation time 175697737 ps
CPU time 1.57 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 205516 kb
Host smart-2eaa55af-53f6-4a0b-8bcd-107c1217e456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191657345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2191657345
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3463371954
Short name T989
Test name
Test status
Simulation time 10468540 ps
CPU time 0.73 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:43 PM PDT 24
Peak memory 205292 kb
Host smart-1c5e9460-412e-4354-ba5e-bbb970d379f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463371954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3463371954
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.834241404
Short name T1026
Test name
Test status
Simulation time 22966552 ps
CPU time 1.65 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:45 PM PDT 24
Peak memory 205380 kb
Host smart-80e11ec8-aba0-4991-bbcf-17e199779c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834241404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.834241404
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2558140043
Short name T984
Test name
Test status
Simulation time 88036375 ps
CPU time 3.13 seconds
Started Jun 30 04:48:44 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 213824 kb
Host smart-5324edc8-d039-4561-b9e0-6318d2def0cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558140043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2558140043
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.705338022
Short name T951
Test name
Test status
Simulation time 178338424 ps
CPU time 4.82 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 220372 kb
Host smart-9e0eed02-4b29-4ee0-82a7-5791ca09dc1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705338022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.705338022
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1896975809
Short name T992
Test name
Test status
Simulation time 250218628 ps
CPU time 2.38 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:46 PM PDT 24
Peak memory 221804 kb
Host smart-b4720867-c395-4c0e-b1c8-75fef010ca0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896975809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1896975809
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.300331617
Short name T945
Test name
Test status
Simulation time 143369662 ps
CPU time 5.42 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 214552 kb
Host smart-e56666c6-92e0-4782-989e-446d5c93dbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300331617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
300331617
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2329051297
Short name T996
Test name
Test status
Simulation time 61089878 ps
CPU time 1.24 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 213736 kb
Host smart-34a77849-14f6-4e14-8cdd-496bf2787511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329051297 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2329051297
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3114184013
Short name T1039
Test name
Test status
Simulation time 15485745 ps
CPU time 1.11 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 205328 kb
Host smart-2532a280-73b5-4588-b4c4-901cfe4ec3a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114184013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3114184013
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1848558919
Short name T1050
Test name
Test status
Simulation time 9459270 ps
CPU time 0.81 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:12 PM PDT 24
Peak memory 205256 kb
Host smart-a12fe399-9e5a-4bb0-9fc2-50ea27400577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848558919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1848558919
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1275731984
Short name T1005
Test name
Test status
Simulation time 97669139 ps
CPU time 2.86 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 205408 kb
Host smart-8619fd19-2f28-4ad5-8f1e-fb5f7dc5fd6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275731984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1275731984
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3914051129
Short name T1031
Test name
Test status
Simulation time 113587704 ps
CPU time 2.35 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 213860 kb
Host smart-b075efa8-f5ec-440b-a7d5-7aead8383bbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914051129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3914051129
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.47370000
Short name T979
Test name
Test status
Simulation time 659205479 ps
CPU time 8.88 seconds
Started Jun 30 04:49:15 PM PDT 24
Finished Jun 30 04:49:25 PM PDT 24
Peak memory 213800 kb
Host smart-d29b297a-9177-4938-ad06-db82274092ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47370000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
eymgr_shadow_reg_errors_with_csr_rw.47370000
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1255470571
Short name T962
Test name
Test status
Simulation time 200148438 ps
CPU time 5.79 seconds
Started Jun 30 04:49:08 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 213632 kb
Host smart-7053cedf-ed96-4085-9b0a-3727b7c47966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255470571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1255470571
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2566574224
Short name T399
Test name
Test status
Simulation time 62158219 ps
CPU time 1.99 seconds
Started Jun 30 04:49:13 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 213652 kb
Host smart-b636d644-8001-48ac-bc41-6ba67bc5a852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566574224 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2566574224
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2387721295
Short name T935
Test name
Test status
Simulation time 37663213 ps
CPU time 1.58 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 205288 kb
Host smart-81d9a4ce-1326-4f85-8d02-e2b1ac83394b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387721295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2387721295
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.258700591
Short name T925
Test name
Test status
Simulation time 10360161 ps
CPU time 0.75 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:12 PM PDT 24
Peak memory 205380 kb
Host smart-ef04a155-2097-40d8-a4ad-4b4d103666bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258700591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.258700591
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3935735654
Short name T970
Test name
Test status
Simulation time 44388211 ps
CPU time 1.94 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 213636 kb
Host smart-d59a9c52-220a-4565-9df4-f832aa8e837a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935735654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3935735654
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.39120739
Short name T1003
Test name
Test status
Simulation time 1338949941 ps
CPU time 10.03 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 213832 kb
Host smart-1c23183d-89fc-42b3-8bf4-15e3a5fdbcaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_shadow_reg_errors_with_csr_rw.39120739
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1077870640
Short name T941
Test name
Test status
Simulation time 229720887 ps
CPU time 2.78 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 215784 kb
Host smart-cb095da9-3dd9-4751-baa8-238597f0b749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077870640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1077870640
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.920176728
Short name T948
Test name
Test status
Simulation time 97490108 ps
CPU time 1.19 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 205592 kb
Host smart-ace92159-9a3f-406e-ae3d-7ba87c6e24fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920176728 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.920176728
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.955924649
Short name T939
Test name
Test status
Simulation time 60431955 ps
CPU time 1.14 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 205480 kb
Host smart-f80a6476-60b4-4b81-bf35-12085d7e054e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955924649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.955924649
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1067621729
Short name T982
Test name
Test status
Simulation time 10811340 ps
CPU time 0.81 seconds
Started Jun 30 04:49:14 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 205272 kb
Host smart-b5bd364c-006c-4ce9-bfbf-fa7e6318af12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067621729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1067621729
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3172279579
Short name T1007
Test name
Test status
Simulation time 182398631 ps
CPU time 2.84 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 205424 kb
Host smart-cbe5b4e0-917e-4acd-b4bb-0f45e2d43268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172279579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3172279579
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2205489088
Short name T1030
Test name
Test status
Simulation time 156316452 ps
CPU time 2.91 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:16 PM PDT 24
Peak memory 213892 kb
Host smart-4c317d17-b4cb-45c3-9934-8d1513021a66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205489088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2205489088
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.879887368
Short name T927
Test name
Test status
Simulation time 97861228 ps
CPU time 1.76 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 221240 kb
Host smart-36c4fb2a-9371-48b7-b5f9-70e430166950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879887368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.879887368
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.518325972
Short name T966
Test name
Test status
Simulation time 203593341 ps
CPU time 2.49 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 205476 kb
Host smart-562abd10-abf1-4c7c-a611-b40465a3462c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518325972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.518325972
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3092342535
Short name T1052
Test name
Test status
Simulation time 112217173 ps
CPU time 1.22 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:21 PM PDT 24
Peak memory 213792 kb
Host smart-df6ed21f-fa2f-4a30-83da-9f48b49e6b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092342535 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3092342535
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3191055552
Short name T1001
Test name
Test status
Simulation time 45355884 ps
CPU time 0.94 seconds
Started Jun 30 04:49:21 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 205264 kb
Host smart-0ce6e89a-3a57-45ab-9f07-707e0636e3ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191055552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3191055552
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2113620903
Short name T998
Test name
Test status
Simulation time 28823505 ps
CPU time 0.75 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 205280 kb
Host smart-2cacd34b-43d3-4081-918f-3628e42e97ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113620903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2113620903
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2195840078
Short name T961
Test name
Test status
Simulation time 34381863 ps
CPU time 2.06 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 205516 kb
Host smart-b199244e-daa3-4ae1-944d-80c06a15ce67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195840078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2195840078
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1766900401
Short name T1019
Test name
Test status
Simulation time 255710067 ps
CPU time 3.37 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 213932 kb
Host smart-b03c2557-d168-4168-af13-098fbb2759cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766900401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1766900401
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3795438725
Short name T122
Test name
Test status
Simulation time 737845558 ps
CPU time 4.44 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:16 PM PDT 24
Peak memory 219928 kb
Host smart-84f15c83-f394-4556-80b6-3089d063acad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795438725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3795438725
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.214456313
Short name T985
Test name
Test status
Simulation time 345341170 ps
CPU time 3.34 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 214672 kb
Host smart-09bf99c1-e29f-421d-a564-f8907ab28fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214456313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.214456313
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3450112965
Short name T1022
Test name
Test status
Simulation time 114414943 ps
CPU time 1.32 seconds
Started Jun 30 04:49:18 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 213548 kb
Host smart-2ad5fa18-bb83-4111-a2dd-1e483e83fb6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450112965 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3450112965
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2968777779
Short name T1065
Test name
Test status
Simulation time 73522201 ps
CPU time 1.17 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:21 PM PDT 24
Peak memory 205388 kb
Host smart-bed7564b-e494-47c9-925d-b54ce37cdd2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968777779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2968777779
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3064625465
Short name T1009
Test name
Test status
Simulation time 27066043 ps
CPU time 0.7 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:21 PM PDT 24
Peak memory 205308 kb
Host smart-d7956481-b22d-4626-9f91-3c452fb02111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064625465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3064625465
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1334409608
Short name T997
Test name
Test status
Simulation time 20373020 ps
CPU time 1.69 seconds
Started Jun 30 04:49:18 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 205336 kb
Host smart-bcb6f84e-308c-4153-aea7-6ad4501367e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334409608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1334409608
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2649345349
Short name T1036
Test name
Test status
Simulation time 81462748 ps
CPU time 2.18 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 214308 kb
Host smart-8332c861-f77f-4d5e-b33b-74404bc9fec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649345349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2649345349
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1462616715
Short name T1045
Test name
Test status
Simulation time 2041361740 ps
CPU time 4.52 seconds
Started Jun 30 04:49:18 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 220060 kb
Host smart-38a9182a-80e6-4840-9146-8850a78cf3c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462616715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1462616715
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2825544505
Short name T1000
Test name
Test status
Simulation time 117493315 ps
CPU time 4.35 seconds
Started Jun 30 04:49:18 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 213596 kb
Host smart-ff61633f-2c56-413c-bb19-d69b11e5a150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825544505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2825544505
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4102481605
Short name T1063
Test name
Test status
Simulation time 1268435363 ps
CPU time 4.85 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:25 PM PDT 24
Peak memory 205372 kb
Host smart-824777c4-fb10-4652-b8af-b58be11836af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102481605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.4102481605
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1086770459
Short name T1027
Test name
Test status
Simulation time 607285202 ps
CPU time 1.67 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:21 PM PDT 24
Peak memory 213632 kb
Host smart-b6faaf9f-6d5f-4ca1-9767-3ff7c7f979fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086770459 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1086770459
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3703068963
Short name T151
Test name
Test status
Simulation time 64834714 ps
CPU time 1.15 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:21 PM PDT 24
Peak memory 205384 kb
Host smart-a8bee093-03ca-49e8-8940-28cfdec16261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703068963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3703068963
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2306566821
Short name T1035
Test name
Test status
Simulation time 38364403 ps
CPU time 0.72 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:20 PM PDT 24
Peak memory 205280 kb
Host smart-1f404e15-9e45-47f0-93f5-64b091187ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306566821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2306566821
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3533272205
Short name T148
Test name
Test status
Simulation time 92258633 ps
CPU time 2.54 seconds
Started Jun 30 04:49:18 PM PDT 24
Finished Jun 30 04:49:21 PM PDT 24
Peak memory 205336 kb
Host smart-15e27e3c-e46d-4dd5-97f5-1844ce429f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533272205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3533272205
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.165461685
Short name T1025
Test name
Test status
Simulation time 156354915 ps
CPU time 2.72 seconds
Started Jun 30 04:49:21 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 213896 kb
Host smart-1db5cf5d-1c3f-4e43-9f34-da5549a651f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165461685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.165461685
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2256077544
Short name T947
Test name
Test status
Simulation time 369551806 ps
CPU time 13.07 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:33 PM PDT 24
Peak memory 213908 kb
Host smart-8c9d7b18-83b3-496b-8a9b-5e2b25b14dc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256077544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2256077544
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.201137247
Short name T949
Test name
Test status
Simulation time 186446561 ps
CPU time 2.12 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 213652 kb
Host smart-3196bbcd-3fb4-4c53-8584-ee71f1064b31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201137247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.201137247
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.306063040
Short name T398
Test name
Test status
Simulation time 133410376 ps
CPU time 1.88 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 213660 kb
Host smart-2a5e9700-5ac1-468c-9b9a-62e31a9f09b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306063040 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.306063040
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.830415436
Short name T930
Test name
Test status
Simulation time 53719102 ps
CPU time 0.97 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 205340 kb
Host smart-12dcd664-a038-4790-aaeb-82ba32159cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830415436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.830415436
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1894776463
Short name T1069
Test name
Test status
Simulation time 37570195 ps
CPU time 0.71 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 205280 kb
Host smart-6c5804a5-2979-4b74-a912-f5efb15cf428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894776463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1894776463
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3115171483
Short name T150
Test name
Test status
Simulation time 236676708 ps
CPU time 2.87 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 205756 kb
Host smart-c725aa9d-5061-4097-9b74-05645d678ea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115171483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3115171483
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3221815976
Short name T1059
Test name
Test status
Simulation time 288219477 ps
CPU time 2.86 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:24 PM PDT 24
Peak memory 213976 kb
Host smart-827538e9-7490-4902-a4d2-b70c76ae10ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221815976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3221815976
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2217657088
Short name T1072
Test name
Test status
Simulation time 1456546923 ps
CPU time 13.88 seconds
Started Jun 30 04:49:18 PM PDT 24
Finished Jun 30 04:49:33 PM PDT 24
Peak memory 222164 kb
Host smart-edb83167-1388-4f26-8915-f907786d0cac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217657088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2217657088
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.920148428
Short name T913
Test name
Test status
Simulation time 123891532 ps
CPU time 1.62 seconds
Started Jun 30 04:49:20 PM PDT 24
Finished Jun 30 04:49:23 PM PDT 24
Peak memory 213548 kb
Host smart-97e98f12-9a40-4fb9-823b-f8832b14f532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920148428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.920148428
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3925274974
Short name T919
Test name
Test status
Simulation time 146880639 ps
CPU time 5.34 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 213600 kb
Host smart-5c70e913-1d21-447c-a808-71aa4f4f3850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925274974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3925274974
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4058391429
Short name T920
Test name
Test status
Simulation time 272027291 ps
CPU time 1.55 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 213780 kb
Host smart-0187576a-b983-4fd1-b756-00c134127102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058391429 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4058391429
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1325782601
Short name T942
Test name
Test status
Simulation time 52352856 ps
CPU time 1.1 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:29 PM PDT 24
Peak memory 205404 kb
Host smart-8bd4375b-4256-4358-b5c7-4aa9c5b57055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325782601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1325782601
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2071786493
Short name T911
Test name
Test status
Simulation time 20689222 ps
CPU time 0.71 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205372 kb
Host smart-00e214b0-e55d-4ae4-a50e-7f55ab040320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071786493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2071786493
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1199017573
Short name T953
Test name
Test status
Simulation time 70962596 ps
CPU time 1.54 seconds
Started Jun 30 04:49:28 PM PDT 24
Finished Jun 30 04:49:31 PM PDT 24
Peak memory 205484 kb
Host smart-e49d8232-2ccf-4d5a-a33e-332c74e6764f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199017573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1199017573
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1328498470
Short name T1060
Test name
Test status
Simulation time 48452027 ps
CPU time 1.2 seconds
Started Jun 30 04:49:19 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 213964 kb
Host smart-5fad1cb4-7f7a-4cd0-9d3b-dc52533e8444
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328498470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1328498470
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3177527253
Short name T977
Test name
Test status
Simulation time 1908714054 ps
CPU time 14.62 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:41 PM PDT 24
Peak memory 220520 kb
Host smart-95be89d1-2fa4-4b3b-a2fc-053907927f78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177527253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3177527253
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.783629169
Short name T972
Test name
Test status
Simulation time 40348926 ps
CPU time 2.52 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 213616 kb
Host smart-cefaf527-bfec-45c2-86ff-312cb0f5e730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783629169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.783629169
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1862741824
Short name T980
Test name
Test status
Simulation time 96190175 ps
CPU time 1.59 seconds
Started Jun 30 04:49:29 PM PDT 24
Finished Jun 30 04:49:31 PM PDT 24
Peak memory 213656 kb
Host smart-029a7f09-221c-4628-8976-ddefdff7cb23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862741824 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1862741824
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3593532329
Short name T153
Test name
Test status
Simulation time 33943710 ps
CPU time 1.55 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205496 kb
Host smart-e1de6791-e40d-41fc-80da-cf7d980ff1d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593532329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3593532329
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1195702772
Short name T1033
Test name
Test status
Simulation time 8690478 ps
CPU time 0.71 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 205344 kb
Host smart-16469439-4186-4f15-91ad-a0f461cd3cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195702772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1195702772
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4140021440
Short name T155
Test name
Test status
Simulation time 84675106 ps
CPU time 1.63 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205484 kb
Host smart-7671ccb7-2d3d-45d1-a097-bf55139a8c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140021440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4140021440
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3594453588
Short name T960
Test name
Test status
Simulation time 168778132 ps
CPU time 1.8 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 213856 kb
Host smart-10d39b74-d184-459b-8f6f-9ea8e37f5174
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594453588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3594453588
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3793977622
Short name T1010
Test name
Test status
Simulation time 951362461 ps
CPU time 9.68 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:36 PM PDT 24
Peak memory 213836 kb
Host smart-9b38f283-1c03-467d-bf68-e7d01d2429b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793977622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3793977622
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4138317732
Short name T1023
Test name
Test status
Simulation time 57029128 ps
CPU time 1.86 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 216008 kb
Host smart-bbdfb954-288c-4f0f-bf14-f2f98033cd57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138317732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.4138317732
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.950035786
Short name T1047
Test name
Test status
Simulation time 249883037 ps
CPU time 6.82 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:32 PM PDT 24
Peak memory 205896 kb
Host smart-6da40fe2-cfe3-442e-a7c4-12144601a67c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950035786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.950035786
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1537599384
Short name T978
Test name
Test status
Simulation time 317759615 ps
CPU time 1.46 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205472 kb
Host smart-40738c0c-8cfd-4025-b1d4-b60d97dc831c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537599384 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1537599384
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4259515693
Short name T932
Test name
Test status
Simulation time 46795572 ps
CPU time 1.07 seconds
Started Jun 30 04:49:28 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 205456 kb
Host smart-a6a92777-51af-451f-8fa1-c94a6bcb50da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259515693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4259515693
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3683061066
Short name T1071
Test name
Test status
Simulation time 71065835 ps
CPU time 0.73 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205240 kb
Host smart-714ec9ad-34ea-49f0-a849-e854a6abb89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683061066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3683061066
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3170885707
Short name T149
Test name
Test status
Simulation time 91144443 ps
CPU time 3.62 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205404 kb
Host smart-4c2d30a3-a228-4e5b-bbb9-89feaf6d780e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170885707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3170885707
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1068241733
Short name T946
Test name
Test status
Simulation time 564335002 ps
CPU time 4.46 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:33 PM PDT 24
Peak memory 213812 kb
Host smart-7ea3ecad-cd0e-4588-836e-0ec6b51b5d04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068241733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1068241733
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.528686576
Short name T987
Test name
Test status
Simulation time 508607345 ps
CPU time 16.86 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 213996 kb
Host smart-3f3e29d7-c3a2-4eb6-bd01-f33ad20d6ddc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528686576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.528686576
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1896638030
Short name T921
Test name
Test status
Simulation time 77679944 ps
CPU time 2.38 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 213528 kb
Host smart-d1f6a16c-7400-43ca-9f17-e15361f88e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896638030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1896638030
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1541886444
Short name T169
Test name
Test status
Simulation time 55128853 ps
CPU time 2.65 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:31 PM PDT 24
Peak memory 205408 kb
Host smart-19d37914-f2ea-4d43-93ae-17b4a88f74ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541886444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1541886444
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2531078316
Short name T959
Test name
Test status
Simulation time 756722102 ps
CPU time 8.73 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 205424 kb
Host smart-c9ed45d3-ee7f-4d5f-b1da-50ebe0e9cd56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531078316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
531078316
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1606685223
Short name T1068
Test name
Test status
Simulation time 2236099005 ps
CPU time 14.67 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 205488 kb
Host smart-ddd1bdbd-8f1a-454a-8b2b-e3ea72c1c5fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606685223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
606685223
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3625818042
Short name T1046
Test name
Test status
Simulation time 62085891 ps
CPU time 1.03 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:44 PM PDT 24
Peak memory 205452 kb
Host smart-2afac1c1-27f5-4933-a2ac-96ce4bad1fb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625818042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
625818042
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1203943568
Short name T1021
Test name
Test status
Simulation time 60988053 ps
CPU time 1.96 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 213640 kb
Host smart-829210a1-7169-4aea-bad1-f0ad06334bea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203943568 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1203943568
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1429657359
Short name T1038
Test name
Test status
Simulation time 12522475 ps
CPU time 1.09 seconds
Started Jun 30 04:48:40 PM PDT 24
Finished Jun 30 04:48:44 PM PDT 24
Peak memory 205400 kb
Host smart-1a0b8d1d-defe-4c00-ba40-e41f1b81802c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429657359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1429657359
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3595621122
Short name T973
Test name
Test status
Simulation time 11540770 ps
CPU time 0.73 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:44 PM PDT 24
Peak memory 205364 kb
Host smart-10ec935a-0618-4181-8a2f-9014ca24dfc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595621122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3595621122
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2418776168
Short name T1043
Test name
Test status
Simulation time 61656342 ps
CPU time 1.73 seconds
Started Jun 30 04:48:49 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 205332 kb
Host smart-cec72d17-c379-4fa0-adf0-c2fe9077227b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418776168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2418776168
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3888239250
Short name T124
Test name
Test status
Simulation time 166421594 ps
CPU time 3.13 seconds
Started Jun 30 04:48:44 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 213912 kb
Host smart-6fb33000-85eb-494a-a1b0-879a53f23b84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888239250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3888239250
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2638589043
Short name T1008
Test name
Test status
Simulation time 169058658 ps
CPU time 9.26 seconds
Started Jun 30 04:48:43 PM PDT 24
Finished Jun 30 04:48:54 PM PDT 24
Peak memory 220456 kb
Host smart-16e98198-41b1-4162-ae91-14cf19b8701a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638589043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2638589043
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2381260108
Short name T1014
Test name
Test status
Simulation time 150132076 ps
CPU time 4.89 seconds
Started Jun 30 04:48:41 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 213564 kb
Host smart-3972c239-465a-4b64-942c-32dc48e9463c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381260108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2381260108
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1262039635
Short name T174
Test name
Test status
Simulation time 249385760 ps
CPU time 3.79 seconds
Started Jun 30 04:48:42 PM PDT 24
Finished Jun 30 04:48:47 PM PDT 24
Peak memory 213616 kb
Host smart-1e0f9984-5b9c-470f-945b-6eeeaab4271c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262039635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1262039635
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3754754078
Short name T937
Test name
Test status
Simulation time 20770807 ps
CPU time 0.73 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:29 PM PDT 24
Peak memory 205216 kb
Host smart-0ca164ea-398d-4a0c-885e-8a7998584b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754754078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3754754078
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3779917416
Short name T1075
Test name
Test status
Simulation time 22889477 ps
CPU time 0.81 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205548 kb
Host smart-27fce892-7daa-42d1-94b3-9c8aa55b318a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779917416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3779917416
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3322015064
Short name T1041
Test name
Test status
Simulation time 29892430 ps
CPU time 0.74 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 205352 kb
Host smart-906cf618-646f-43b6-a25f-189291820b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322015064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3322015064
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1755798346
Short name T954
Test name
Test status
Simulation time 11900036 ps
CPU time 0.75 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 205292 kb
Host smart-3d8516db-0b3d-47cc-811b-23bed75d04de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755798346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1755798346
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.487039323
Short name T1006
Test name
Test status
Simulation time 12554608 ps
CPU time 0.74 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 205272 kb
Host smart-5ba08aa7-4495-4704-a157-f26e1cb87a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487039323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.487039323
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.846169891
Short name T958
Test name
Test status
Simulation time 14425078 ps
CPU time 0.89 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205436 kb
Host smart-6b5323ae-6e05-4f43-82a2-bb9f4b83231f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846169891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.846169891
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1742289076
Short name T914
Test name
Test status
Simulation time 20737978 ps
CPU time 0.78 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205192 kb
Host smart-7f8cb0a9-411f-412d-8187-6c021232961f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742289076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1742289076
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1938942802
Short name T924
Test name
Test status
Simulation time 9530180 ps
CPU time 0.83 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205240 kb
Host smart-de9fdf09-3e8b-446b-b4ee-bed382b2f369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938942802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1938942802
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1467741005
Short name T1073
Test name
Test status
Simulation time 11870475 ps
CPU time 0.72 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 205308 kb
Host smart-a0bdc399-c6e6-47fb-96c7-468185b98f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467741005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1467741005
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3962326384
Short name T968
Test name
Test status
Simulation time 7928772 ps
CPU time 0.72 seconds
Started Jun 30 04:49:28 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 205268 kb
Host smart-20de09b9-0dbb-4a6d-b7cd-7dae6c0552b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962326384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3962326384
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3293636107
Short name T1067
Test name
Test status
Simulation time 191989810 ps
CPU time 7.36 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:56 PM PDT 24
Peak memory 205460 kb
Host smart-79646287-2d57-421b-a978-0b2385561c76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293636107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
293636107
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1789091851
Short name T1032
Test name
Test status
Simulation time 264414241 ps
CPU time 7.89 seconds
Started Jun 30 04:48:53 PM PDT 24
Finished Jun 30 04:49:01 PM PDT 24
Peak memory 205372 kb
Host smart-78a95722-fe9e-4c6e-9c85-ec8bc657d3f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789091851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
789091851
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3083907660
Short name T163
Test name
Test status
Simulation time 55774245 ps
CPU time 1.15 seconds
Started Jun 30 04:48:52 PM PDT 24
Finished Jun 30 04:48:54 PM PDT 24
Peak memory 205424 kb
Host smart-359a83c9-0e47-4ab8-a3cb-3b82a699cd69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083907660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
083907660
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1485996579
Short name T950
Test name
Test status
Simulation time 61901525 ps
CPU time 1.38 seconds
Started Jun 30 04:48:49 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 213628 kb
Host smart-94b6b9e0-659b-4bb6-8942-26634caa738b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485996579 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1485996579
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1797990096
Short name T1057
Test name
Test status
Simulation time 24331057 ps
CPU time 1.13 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:50 PM PDT 24
Peak memory 205416 kb
Host smart-093643ec-c23b-443c-8ea4-dee815292691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797990096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1797990096
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2354728145
Short name T1011
Test name
Test status
Simulation time 14264500 ps
CPU time 0.85 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:49 PM PDT 24
Peak memory 205372 kb
Host smart-103aeb29-ba45-47e0-965e-9acef3fe471e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354728145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2354728145
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4235002921
Short name T1056
Test name
Test status
Simulation time 196373958 ps
CPU time 1.79 seconds
Started Jun 30 04:48:53 PM PDT 24
Finished Jun 30 04:48:55 PM PDT 24
Peak memory 205344 kb
Host smart-4a0297b3-03d1-4baa-b179-ec6ee15e8292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235002921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4235002921
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3302700143
Short name T1044
Test name
Test status
Simulation time 79376919 ps
CPU time 1.75 seconds
Started Jun 30 04:48:49 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 213904 kb
Host smart-f24fc90b-0b32-4b00-97bd-94bd459d4c9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302700143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3302700143
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2346397561
Short name T963
Test name
Test status
Simulation time 556034902 ps
CPU time 6.63 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:56 PM PDT 24
Peak memory 214052 kb
Host smart-e648c5a8-4cb2-4aa6-a5a3-737781ca772f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346397561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2346397561
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4281499664
Short name T1062
Test name
Test status
Simulation time 432733842 ps
CPU time 4.5 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:53 PM PDT 24
Peak memory 213508 kb
Host smart-644ac87b-2765-471e-b961-8368acb75e32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281499664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4281499664
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4153786880
Short name T1048
Test name
Test status
Simulation time 408022057 ps
CPU time 9.37 seconds
Started Jun 30 04:48:52 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 213588 kb
Host smart-5eec5610-6e84-490d-95b8-89689ef8a265
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153786880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4153786880
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3499891240
Short name T912
Test name
Test status
Simulation time 65522317 ps
CPU time 0.86 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 205260 kb
Host smart-f845beaa-3713-41fc-b51b-6a69eb2da6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499891240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3499891240
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1211519702
Short name T1018
Test name
Test status
Simulation time 24172128 ps
CPU time 1.01 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:25 PM PDT 24
Peak memory 205372 kb
Host smart-33325cc0-7896-4be1-8a4b-be3e06701b8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211519702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1211519702
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2442594267
Short name T933
Test name
Test status
Simulation time 14911608 ps
CPU time 0.89 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 205272 kb
Host smart-1deb2bcc-8ae3-4c16-82d6-9a29bf97bebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442594267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2442594267
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1674597796
Short name T931
Test name
Test status
Simulation time 11543234 ps
CPU time 0.73 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:25 PM PDT 24
Peak memory 205260 kb
Host smart-73446135-4140-42c2-b584-be172e89ee90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674597796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1674597796
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2070503892
Short name T1024
Test name
Test status
Simulation time 11721826 ps
CPU time 0.85 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:30 PM PDT 24
Peak memory 205280 kb
Host smart-0590cde2-3619-4415-bd9f-46c386b1705a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070503892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2070503892
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3811947028
Short name T1017
Test name
Test status
Simulation time 39944313 ps
CPU time 0.75 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 205248 kb
Host smart-dfc32f52-5b6d-4b17-b136-58f7f0896397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811947028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3811947028
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.428102750
Short name T994
Test name
Test status
Simulation time 39066182 ps
CPU time 0.75 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 205308 kb
Host smart-a1d933ef-4832-4327-b297-f4e02d15dbf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428102750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.428102750
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2646785576
Short name T922
Test name
Test status
Simulation time 15948157 ps
CPU time 0.68 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 205368 kb
Host smart-28a7a9bc-7369-435b-a3c5-1478638b8bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646785576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2646785576
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2765254346
Short name T1016
Test name
Test status
Simulation time 16637937 ps
CPU time 0.78 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205216 kb
Host smart-931d6ea3-6b8a-430f-8530-8deafdf09d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765254346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2765254346
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.660733168
Short name T1079
Test name
Test status
Simulation time 10055509 ps
CPU time 0.73 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:29 PM PDT 24
Peak memory 205208 kb
Host smart-039a6ce4-2e2c-435b-902c-f89b89dbf217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660733168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.660733168
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.544229752
Short name T1012
Test name
Test status
Simulation time 449286766 ps
CPU time 10.76 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:49:07 PM PDT 24
Peak memory 205372 kb
Host smart-c44f1c56-256a-4070-b7b3-ce611bed524c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544229752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.544229752
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3274273795
Short name T400
Test name
Test status
Simulation time 3566521947 ps
CPU time 25.33 seconds
Started Jun 30 04:48:55 PM PDT 24
Finished Jun 30 04:49:22 PM PDT 24
Peak memory 205424 kb
Host smart-dd524770-9dec-4e92-aad9-a5eb45092a80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274273795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
274273795
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4097834328
Short name T1034
Test name
Test status
Simulation time 42154424 ps
CPU time 0.91 seconds
Started Jun 30 04:48:54 PM PDT 24
Finished Jun 30 04:48:55 PM PDT 24
Peak memory 205224 kb
Host smart-a86e5241-5432-40fd-8451-44d038ef12cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097834328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4
097834328
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.268636122
Short name T917
Test name
Test status
Simulation time 120548927 ps
CPU time 2.25 seconds
Started Jun 30 04:48:55 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 219596 kb
Host smart-5ac32d8d-533a-49c3-b5d5-a20e198fb323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268636122 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.268636122
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1986418290
Short name T1042
Test name
Test status
Simulation time 110189904 ps
CPU time 1.57 seconds
Started Jun 30 04:48:57 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 205388 kb
Host smart-e4fb71a8-2d28-408c-a8c2-ae7de5afe88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986418290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1986418290
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.628224944
Short name T975
Test name
Test status
Simulation time 12661147 ps
CPU time 0.77 seconds
Started Jun 30 04:48:47 PM PDT 24
Finished Jun 30 04:48:48 PM PDT 24
Peak memory 205304 kb
Host smart-d5be87f4-4367-45b6-b78e-06ada6f9eef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628224944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.628224944
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3372460691
Short name T147
Test name
Test status
Simulation time 395149548 ps
CPU time 2.64 seconds
Started Jun 30 04:48:59 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 205432 kb
Host smart-1c017944-a3f7-488b-81c4-54188b256cd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372460691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3372460691
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1817474798
Short name T121
Test name
Test status
Simulation time 288433592 ps
CPU time 1.97 seconds
Started Jun 30 04:48:49 PM PDT 24
Finished Jun 30 04:48:52 PM PDT 24
Peak memory 213940 kb
Host smart-1483551f-5201-468a-bd10-34702e859eae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817474798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1817474798
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1869537465
Short name T981
Test name
Test status
Simulation time 1439420111 ps
CPU time 9.59 seconds
Started Jun 30 04:48:47 PM PDT 24
Finished Jun 30 04:48:57 PM PDT 24
Peak memory 220832 kb
Host smart-1cd8dd9b-86f5-4f4a-a184-ff5dc5d1f9d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869537465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1869537465
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1187191996
Short name T943
Test name
Test status
Simulation time 110649035 ps
CPU time 2.13 seconds
Started Jun 30 04:48:48 PM PDT 24
Finished Jun 30 04:48:51 PM PDT 24
Peak memory 213716 kb
Host smart-7e884a4e-0e1d-4c0e-aac6-bcf9716fe9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187191996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1187191996
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3680774698
Short name T175
Test name
Test status
Simulation time 1217232154 ps
CPU time 5.35 seconds
Started Jun 30 04:48:52 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 214596 kb
Host smart-54712eb3-1d60-4c1a-a9ad-f3a4695e77ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680774698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3680774698
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3680710926
Short name T976
Test name
Test status
Simulation time 7060967 ps
CPU time 0.72 seconds
Started Jun 30 04:49:24 PM PDT 24
Finished Jun 30 04:49:26 PM PDT 24
Peak memory 205208 kb
Host smart-a25df945-586d-47d1-ad5a-b410d244295f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680710926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3680710926
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.195679955
Short name T918
Test name
Test status
Simulation time 28424383 ps
CPU time 0.71 seconds
Started Jun 30 04:49:26 PM PDT 24
Finished Jun 30 04:49:28 PM PDT 24
Peak memory 205172 kb
Host smart-05741074-88cd-4a1a-8dcc-769e1827a7c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195679955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.195679955
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1674002502
Short name T965
Test name
Test status
Simulation time 13506978 ps
CPU time 0.77 seconds
Started Jun 30 04:49:27 PM PDT 24
Finished Jun 30 04:49:29 PM PDT 24
Peak memory 205276 kb
Host smart-99d632f9-aa96-4a3c-a737-4a0578fc0284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674002502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1674002502
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.804758083
Short name T916
Test name
Test status
Simulation time 8229340 ps
CPU time 0.81 seconds
Started Jun 30 04:49:25 PM PDT 24
Finished Jun 30 04:49:27 PM PDT 24
Peak memory 205380 kb
Host smart-74ca00f5-5ed3-4f60-a6a2-5d6e1883d5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804758083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.804758083
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.74264988
Short name T964
Test name
Test status
Simulation time 35872435 ps
CPU time 0.81 seconds
Started Jun 30 04:49:34 PM PDT 24
Finished Jun 30 04:49:36 PM PDT 24
Peak memory 205252 kb
Host smart-811158c9-5f31-4cda-b0d2-5bbf6d5e4f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74264988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.74264988
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2250071274
Short name T957
Test name
Test status
Simulation time 34039321 ps
CPU time 0.84 seconds
Started Jun 30 04:49:31 PM PDT 24
Finished Jun 30 04:49:32 PM PDT 24
Peak memory 205308 kb
Host smart-7b106979-c65b-40ec-b3d3-19d27cb59268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250071274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2250071274
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2590650725
Short name T926
Test name
Test status
Simulation time 15722051 ps
CPU time 0.76 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:49:35 PM PDT 24
Peak memory 205284 kb
Host smart-4157aa77-3da7-4749-9818-5dac701fcfce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590650725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2590650725
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3650001862
Short name T938
Test name
Test status
Simulation time 21323419 ps
CPU time 0.83 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:49:34 PM PDT 24
Peak memory 205308 kb
Host smart-b8dd33eb-6c76-48e2-9e0d-859535847920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650001862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3650001862
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1692662416
Short name T1013
Test name
Test status
Simulation time 26692701 ps
CPU time 1.07 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:33 PM PDT 24
Peak memory 205452 kb
Host smart-6da98bcd-03c1-4f75-aae4-a21fddcc6910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692662416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1692662416
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.158951467
Short name T915
Test name
Test status
Simulation time 28268690 ps
CPU time 0.86 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:34 PM PDT 24
Peak memory 205420 kb
Host smart-a94aeba8-b738-43fc-bef2-51e2537e732b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158951467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.158951467
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.426697681
Short name T974
Test name
Test status
Simulation time 18474302 ps
CPU time 1.52 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 213692 kb
Host smart-31d9360b-3d7b-4fe9-86ea-c2b4bec1f36b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426697681 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.426697681
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2647913777
Short name T929
Test name
Test status
Simulation time 26014334 ps
CPU time 1.24 seconds
Started Jun 30 04:48:55 PM PDT 24
Finished Jun 30 04:48:57 PM PDT 24
Peak memory 205356 kb
Host smart-fb4d03d4-2ea0-4a6f-a7bd-e8828150e644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647913777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2647913777
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3764605268
Short name T986
Test name
Test status
Simulation time 15142067 ps
CPU time 0.81 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:48:57 PM PDT 24
Peak memory 205252 kb
Host smart-ac1d7e19-3cbe-4682-9418-c22db978f098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764605268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3764605268
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2250706899
Short name T1051
Test name
Test status
Simulation time 103447926 ps
CPU time 2.79 seconds
Started Jun 30 04:48:59 PM PDT 24
Finished Jun 30 04:49:02 PM PDT 24
Peak memory 205396 kb
Host smart-4e22bdee-40d5-448f-8c8a-0e347e208022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250706899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2250706899
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3577656150
Short name T952
Test name
Test status
Simulation time 296866519 ps
CPU time 2.72 seconds
Started Jun 30 04:48:57 PM PDT 24
Finished Jun 30 04:49:01 PM PDT 24
Peak memory 214060 kb
Host smart-f235710e-0c1f-494b-a56c-6c2dbd959740
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577656150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3577656150
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3249458710
Short name T127
Test name
Test status
Simulation time 374753379 ps
CPU time 7.19 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 213924 kb
Host smart-268d8e7d-b581-4711-be44-a65ac960c345
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249458710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3249458710
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3684734421
Short name T1029
Test name
Test status
Simulation time 665216126 ps
CPU time 3.43 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:49:00 PM PDT 24
Peak memory 213592 kb
Host smart-d0f2f07b-14b2-445b-b27f-ebf0541b5c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684734421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3684734421
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.669952093
Short name T971
Test name
Test status
Simulation time 120346727 ps
CPU time 0.95 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 205364 kb
Host smart-bc866e32-36ee-4c14-9708-88ab39226b28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669952093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.669952093
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2692637559
Short name T993
Test name
Test status
Simulation time 11636370 ps
CPU time 0.72 seconds
Started Jun 30 04:48:55 PM PDT 24
Finished Jun 30 04:48:57 PM PDT 24
Peak memory 205292 kb
Host smart-cdd562d9-e931-4bac-9df5-1d4d2b7e8fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692637559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2692637559
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1266221492
Short name T1037
Test name
Test status
Simulation time 33978161 ps
CPU time 1.53 seconds
Started Jun 30 04:48:55 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 205408 kb
Host smart-1de6d51c-5a72-4693-b7a3-04f0a9036f38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266221492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1266221492
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3158572637
Short name T1066
Test name
Test status
Simulation time 261743683 ps
CPU time 1.81 seconds
Started Jun 30 04:48:56 PM PDT 24
Finished Jun 30 04:48:58 PM PDT 24
Peak memory 213992 kb
Host smart-0d9c0423-7044-4e9d-be11-fede1de74c45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158572637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3158572637
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3969049741
Short name T125
Test name
Test status
Simulation time 167459800 ps
CPU time 7.32 seconds
Started Jun 30 04:48:57 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 213900 kb
Host smart-e4484201-60ec-4c19-91d7-763fd6598bf6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969049741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3969049741
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2466714044
Short name T1078
Test name
Test status
Simulation time 121327402 ps
CPU time 2.92 seconds
Started Jun 30 04:48:57 PM PDT 24
Finished Jun 30 04:49:01 PM PDT 24
Peak memory 213536 kb
Host smart-21bd2ed3-39a6-4615-9c3f-ba57128124c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466714044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2466714044
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1313040733
Short name T1020
Test name
Test status
Simulation time 46055556 ps
CPU time 1.49 seconds
Started Jun 30 04:49:03 PM PDT 24
Finished Jun 30 04:49:04 PM PDT 24
Peak memory 213648 kb
Host smart-796005d0-e811-4f77-8d25-57e54e3cae49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313040733 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1313040733
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.560887151
Short name T158
Test name
Test status
Simulation time 19870768 ps
CPU time 1.21 seconds
Started Jun 30 04:49:04 PM PDT 24
Finished Jun 30 04:49:06 PM PDT 24
Peak memory 205356 kb
Host smart-6b3e3a74-d0a3-40ae-a174-dd9d61b734e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560887151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.560887151
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.718345819
Short name T983
Test name
Test status
Simulation time 24738455 ps
CPU time 0.79 seconds
Started Jun 30 04:49:08 PM PDT 24
Finished Jun 30 04:49:09 PM PDT 24
Peak memory 205212 kb
Host smart-cf760bfa-d65f-417a-a1ee-ca97776fee63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718345819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.718345819
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2395659901
Short name T1074
Test name
Test status
Simulation time 45651340 ps
CPU time 2.09 seconds
Started Jun 30 04:49:04 PM PDT 24
Finished Jun 30 04:49:07 PM PDT 24
Peak memory 205424 kb
Host smart-8fbaf8d1-760a-442a-897b-4b35ffad5fcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395659901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2395659901
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1130893910
Short name T991
Test name
Test status
Simulation time 707412371 ps
CPU time 2.22 seconds
Started Jun 30 04:49:03 PM PDT 24
Finished Jun 30 04:49:06 PM PDT 24
Peak memory 218848 kb
Host smart-bf479cde-106c-4237-b80e-03b300abf761
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130893910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1130893910
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3091260987
Short name T126
Test name
Test status
Simulation time 646337432 ps
CPU time 7.62 seconds
Started Jun 30 04:49:07 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 213984 kb
Host smart-e56f1017-37db-4ee5-8438-68067a720291
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091260987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3091260987
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.959541350
Short name T967
Test name
Test status
Simulation time 97546634 ps
CPU time 2 seconds
Started Jun 30 04:49:07 PM PDT 24
Finished Jun 30 04:49:10 PM PDT 24
Peak memory 213652 kb
Host smart-d20ef126-1b95-44fa-a9b9-c6c757130174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959541350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.959541350
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2068222129
Short name T160
Test name
Test status
Simulation time 770891720 ps
CPU time 8.43 seconds
Started Jun 30 04:49:03 PM PDT 24
Finished Jun 30 04:49:12 PM PDT 24
Peak memory 216244 kb
Host smart-a6c63c14-04b2-44c6-bf39-cc5ad3950e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068222129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2068222129
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3254094995
Short name T1058
Test name
Test status
Simulation time 175620526 ps
CPU time 2.04 seconds
Started Jun 30 04:49:05 PM PDT 24
Finished Jun 30 04:49:07 PM PDT 24
Peak memory 213672 kb
Host smart-7db9812f-0615-4eee-bdee-414c9d6989b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254094995 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3254094995
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2570360700
Short name T928
Test name
Test status
Simulation time 13631195 ps
CPU time 1.26 seconds
Started Jun 30 04:49:03 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 205332 kb
Host smart-eb3704a2-8087-4564-938c-b9343b78a9de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570360700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2570360700
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.823828373
Short name T940
Test name
Test status
Simulation time 33465438 ps
CPU time 0.83 seconds
Started Jun 30 04:49:05 PM PDT 24
Finished Jun 30 04:49:06 PM PDT 24
Peak memory 205384 kb
Host smart-5bc35e18-4e63-41f2-9c4b-6423ba5ef42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823828373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.823828373
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3299210663
Short name T969
Test name
Test status
Simulation time 527446172 ps
CPU time 4.32 seconds
Started Jun 30 04:49:07 PM PDT 24
Finished Jun 30 04:49:12 PM PDT 24
Peak memory 205432 kb
Host smart-9971c63b-6c23-4361-b7f3-7f2ced0b1cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299210663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3299210663
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.975607945
Short name T1002
Test name
Test status
Simulation time 143093093 ps
CPU time 1.51 seconds
Started Jun 30 04:49:03 PM PDT 24
Finished Jun 30 04:49:05 PM PDT 24
Peak memory 213828 kb
Host smart-dcdf13e4-9b19-4d2c-b169-138bd3ae988f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975607945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.975607945
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.396213167
Short name T1054
Test name
Test status
Simulation time 212378912 ps
CPU time 5.36 seconds
Started Jun 30 04:49:02 PM PDT 24
Finished Jun 30 04:49:08 PM PDT 24
Peak memory 213896 kb
Host smart-ddc499fc-c7a7-43cf-b7ab-31f94d6355e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396213167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.396213167
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3534868757
Short name T1028
Test name
Test status
Simulation time 32374440 ps
CPU time 2.41 seconds
Started Jun 30 04:49:08 PM PDT 24
Finished Jun 30 04:49:11 PM PDT 24
Peak memory 213612 kb
Host smart-c1e9d95f-1594-4ffc-9754-3ee10c3f65a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534868757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3534868757
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1719394814
Short name T923
Test name
Test status
Simulation time 83425046 ps
CPU time 1.53 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:14 PM PDT 24
Peak memory 213568 kb
Host smart-e4bd9494-e9dd-452d-950a-f3c82d7be429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719394814 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1719394814
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3310901965
Short name T1076
Test name
Test status
Simulation time 32830743 ps
CPU time 1.04 seconds
Started Jun 30 04:49:10 PM PDT 24
Finished Jun 30 04:49:12 PM PDT 24
Peak memory 205252 kb
Host smart-1fc38282-8876-44d3-8103-3b40b5aafb12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310901965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3310901965
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3509282063
Short name T1077
Test name
Test status
Simulation time 14404765 ps
CPU time 0.73 seconds
Started Jun 30 04:49:02 PM PDT 24
Finished Jun 30 04:49:03 PM PDT 24
Peak memory 205268 kb
Host smart-e2a13d30-f552-4219-977b-2498d450c523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509282063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3509282063
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.507539562
Short name T1061
Test name
Test status
Simulation time 56366686 ps
CPU time 2.28 seconds
Started Jun 30 04:49:11 PM PDT 24
Finished Jun 30 04:49:15 PM PDT 24
Peak memory 205408 kb
Host smart-b51cc6e0-47b5-4942-ae99-d6f6ab092323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507539562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.507539562
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4124801877
Short name T1053
Test name
Test status
Simulation time 246809514 ps
CPU time 1.65 seconds
Started Jun 30 04:49:02 PM PDT 24
Finished Jun 30 04:49:04 PM PDT 24
Peak memory 213928 kb
Host smart-2bcab340-2cd3-4276-99c5-1e748abea0a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124801877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4124801877
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1544048024
Short name T1070
Test name
Test status
Simulation time 405314692 ps
CPU time 8.6 seconds
Started Jun 30 04:49:04 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 213836 kb
Host smart-81777bff-9cba-46a4-9bcb-efedaea557ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544048024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1544048024
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2702176238
Short name T934
Test name
Test status
Simulation time 114320884 ps
CPU time 4.37 seconds
Started Jun 30 04:49:08 PM PDT 24
Finished Jun 30 04:49:13 PM PDT 24
Peak memory 213616 kb
Host smart-237776a8-bcf1-443b-9f2f-03f688cb5317
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702176238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2702176238
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1772867185
Short name T1055
Test name
Test status
Simulation time 206974145 ps
CPU time 2.96 seconds
Started Jun 30 04:49:04 PM PDT 24
Finished Jun 30 04:49:07 PM PDT 24
Peak memory 214852 kb
Host smart-9c29ec8a-a26b-471e-a1ac-d1b74ddc2412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772867185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1772867185
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1030601409
Short name T537
Test name
Test status
Simulation time 15833346 ps
CPU time 0.79 seconds
Started Jun 30 05:43:38 PM PDT 24
Finished Jun 30 05:43:39 PM PDT 24
Peak memory 206056 kb
Host smart-c533bf87-f8c8-4f44-a4b9-215178c044c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030601409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1030601409
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2569367767
Short name T228
Test name
Test status
Simulation time 203419190 ps
CPU time 3.2 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:37 PM PDT 24
Peak memory 215060 kb
Host smart-772a0b70-1be5-426f-b007-2789e58d3144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569367767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2569367767
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.618136934
Short name T35
Test name
Test status
Simulation time 129473362 ps
CPU time 2.22 seconds
Started Jun 30 05:43:37 PM PDT 24
Finished Jun 30 05:43:39 PM PDT 24
Peak memory 215840 kb
Host smart-5105c05c-2a39-4bc2-9eca-3fe8d3862ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618136934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.618136934
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3529106690
Short name T842
Test name
Test status
Simulation time 618624401 ps
CPU time 2.62 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:54 PM PDT 24
Peak memory 218436 kb
Host smart-3fc0c9f7-130d-4de0-8e46-023c63743199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529106690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3529106690
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2521644820
Short name T609
Test name
Test status
Simulation time 40569010 ps
CPU time 3.17 seconds
Started Jun 30 05:43:37 PM PDT 24
Finished Jun 30 05:43:40 PM PDT 24
Peak memory 215016 kb
Host smart-2ead7789-ab1c-4a0e-aad3-c0ad4fe0c5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521644820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2521644820
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1275546337
Short name T663
Test name
Test status
Simulation time 97164015 ps
CPU time 2.74 seconds
Started Jun 30 05:43:36 PM PDT 24
Finished Jun 30 05:43:39 PM PDT 24
Peak memory 207056 kb
Host smart-800f096f-4f1e-4043-a724-ea288880f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275546337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1275546337
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2538262153
Short name T525
Test name
Test status
Simulation time 319825926 ps
CPU time 4.11 seconds
Started Jun 30 05:43:36 PM PDT 24
Finished Jun 30 05:43:41 PM PDT 24
Peak memory 207992 kb
Host smart-68c27a0d-8508-40f3-a075-4ae722d656e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538262153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2538262153
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3135394969
Short name T49
Test name
Test status
Simulation time 332113449 ps
CPU time 5.42 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:41 PM PDT 24
Peak memory 233672 kb
Host smart-a83e427f-bca8-48d1-9415-a3615fc3accf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135394969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3135394969
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1473751293
Short name T442
Test name
Test status
Simulation time 620779203 ps
CPU time 13.37 seconds
Started Jun 30 05:43:42 PM PDT 24
Finished Jun 30 05:43:56 PM PDT 24
Peak memory 208272 kb
Host smart-91f3d555-bf2a-403f-966b-ec0d2c85558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473751293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1473751293
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1420303095
Short name T897
Test name
Test status
Simulation time 50213864 ps
CPU time 2.45 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:38 PM PDT 24
Peak memory 207092 kb
Host smart-ba5bffe7-9760-47e1-bc05-d4f39a7f8ec8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420303095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1420303095
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1167443867
Short name T580
Test name
Test status
Simulation time 141756949 ps
CPU time 3.44 seconds
Started Jun 30 05:43:34 PM PDT 24
Finished Jun 30 05:43:38 PM PDT 24
Peak memory 208640 kb
Host smart-3828d529-f815-422a-867c-6124ff8bf43d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167443867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1167443867
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2608029876
Short name T749
Test name
Test status
Simulation time 84090451 ps
CPU time 1.97 seconds
Started Jun 30 05:43:37 PM PDT 24
Finished Jun 30 05:43:40 PM PDT 24
Peak memory 208712 kb
Host smart-be84a102-460b-4eb1-8078-033d2eb5b027
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608029876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2608029876
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.16643898
Short name T263
Test name
Test status
Simulation time 117725840 ps
CPU time 4.29 seconds
Started Jun 30 05:43:36 PM PDT 24
Finished Jun 30 05:43:40 PM PDT 24
Peak memory 218340 kb
Host smart-b799b48f-ac75-4057-8157-c651fdf3ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16643898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.16643898
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1583502816
Short name T409
Test name
Test status
Simulation time 239079234 ps
CPU time 5.35 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:39 PM PDT 24
Peak memory 208592 kb
Host smart-3e08b657-7d7c-4821-9c9e-68b71511fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583502816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1583502816
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.388971155
Short name T221
Test name
Test status
Simulation time 527913047 ps
CPU time 16.07 seconds
Started Jun 30 05:43:36 PM PDT 24
Finished Jun 30 05:43:53 PM PDT 24
Peak memory 222824 kb
Host smart-052886d2-7ed6-41cb-8b94-4c56524668e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388971155 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.388971155
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.848866035
Short name T560
Test name
Test status
Simulation time 1253979161 ps
CPU time 8.18 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:44 PM PDT 24
Peak memory 208464 kb
Host smart-75e36958-9aec-4800-a692-06d35ea2e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848866035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.848866035
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.270651817
Short name T860
Test name
Test status
Simulation time 113469673 ps
CPU time 1.88 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:35 PM PDT 24
Peak memory 208528 kb
Host smart-feab3a2d-8fb7-4ec3-8524-4ad40fd35441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270651817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.270651817
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4151988958
Short name T448
Test name
Test status
Simulation time 28161551 ps
CPU time 0.73 seconds
Started Jun 30 05:43:46 PM PDT 24
Finished Jun 30 05:43:47 PM PDT 24
Peak memory 205512 kb
Host smart-8fd1705e-c931-41c2-aac3-20b6a268b5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151988958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4151988958
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3186850146
Short name T36
Test name
Test status
Simulation time 38989548 ps
CPU time 1.57 seconds
Started Jun 30 05:43:41 PM PDT 24
Finished Jun 30 05:43:43 PM PDT 24
Peak memory 215544 kb
Host smart-6a09ed4f-bd0d-4639-8e1a-f7ccec10a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186850146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3186850146
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1489806896
Short name T81
Test name
Test status
Simulation time 245423090 ps
CPU time 3.01 seconds
Started Jun 30 05:43:41 PM PDT 24
Finished Jun 30 05:43:45 PM PDT 24
Peak memory 209488 kb
Host smart-f0f5d15b-5bb8-415a-be4d-1e99b0be2e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489806896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1489806896
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2592376367
Short name T709
Test name
Test status
Simulation time 52207265 ps
CPU time 3.42 seconds
Started Jun 30 05:43:41 PM PDT 24
Finished Jun 30 05:43:45 PM PDT 24
Peak memory 215452 kb
Host smart-292d0847-5a43-4425-9a2b-2e5cb914aa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592376367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2592376367
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3197842024
Short name T207
Test name
Test status
Simulation time 201027144 ps
CPU time 2.42 seconds
Started Jun 30 05:43:45 PM PDT 24
Finished Jun 30 05:43:48 PM PDT 24
Peak memory 219872 kb
Host smart-7470a8ab-5ff9-4118-ab33-2f00d4e158e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197842024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3197842024
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.877322889
Short name T496
Test name
Test status
Simulation time 64488987 ps
CPU time 2.53 seconds
Started Jun 30 05:43:41 PM PDT 24
Finished Jun 30 05:43:43 PM PDT 24
Peak memory 207724 kb
Host smart-08242b39-becb-4344-84f5-56761a566372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877322889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.877322889
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.244220382
Short name T13
Test name
Test status
Simulation time 1694054079 ps
CPU time 5.91 seconds
Started Jun 30 05:43:46 PM PDT 24
Finished Jun 30 05:43:52 PM PDT 24
Peak memory 233468 kb
Host smart-a63a332b-8ac4-4f76-92b0-583440e8f5bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244220382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.244220382
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.569651841
Short name T503
Test name
Test status
Simulation time 1184951072 ps
CPU time 8.56 seconds
Started Jun 30 05:43:42 PM PDT 24
Finished Jun 30 05:43:51 PM PDT 24
Peak memory 206884 kb
Host smart-9a963e3e-37ac-41f7-ae80-9549c0c6cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569651841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.569651841
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3131106842
Short name T762
Test name
Test status
Simulation time 278295861 ps
CPU time 2.8 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:39 PM PDT 24
Peak memory 206792 kb
Host smart-7a6995e5-9ba3-400c-800c-71c4304b33cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131106842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3131106842
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.670006391
Short name T511
Test name
Test status
Simulation time 559657679 ps
CPU time 4.81 seconds
Started Jun 30 05:43:36 PM PDT 24
Finished Jun 30 05:43:41 PM PDT 24
Peak memory 208520 kb
Host smart-06505f5d-a21a-4e33-b5df-0ec600a1a536
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670006391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.670006391
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3463197663
Short name T711
Test name
Test status
Simulation time 4867067380 ps
CPU time 31.75 seconds
Started Jun 30 05:43:38 PM PDT 24
Finished Jun 30 05:44:10 PM PDT 24
Peak memory 208204 kb
Host smart-d678f153-1aa8-44de-826c-0b4df14d93de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463197663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3463197663
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1197347325
Short name T363
Test name
Test status
Simulation time 1036112075 ps
CPU time 4.41 seconds
Started Jun 30 05:43:44 PM PDT 24
Finished Jun 30 05:43:49 PM PDT 24
Peak memory 216236 kb
Host smart-d2481dba-cf12-4cac-b799-cf41a8d57541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197347325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1197347325
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3444519578
Short name T656
Test name
Test status
Simulation time 707917200 ps
CPU time 6.72 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:42 PM PDT 24
Peak memory 206904 kb
Host smart-dce968ca-d3af-4e0a-9561-73930f9d924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444519578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3444519578
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3454039569
Short name T107
Test name
Test status
Simulation time 96586044 ps
CPU time 6.81 seconds
Started Jun 30 05:43:46 PM PDT 24
Finished Jun 30 05:43:53 PM PDT 24
Peak memory 222584 kb
Host smart-74385f83-4e2b-4409-bd9b-a887d552611a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454039569 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3454039569
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3912492724
Short name T678
Test name
Test status
Simulation time 165774512 ps
CPU time 3.73 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:47 PM PDT 24
Peak memory 218488 kb
Host smart-0991744b-602e-4492-88ae-863ff47cd27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912492724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3912492724
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3449699571
Short name T730
Test name
Test status
Simulation time 1841507438 ps
CPU time 12.57 seconds
Started Jun 30 05:43:44 PM PDT 24
Finished Jun 30 05:43:57 PM PDT 24
Peak memory 210964 kb
Host smart-90cdbcea-3715-4c0e-a528-bb44ac730a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449699571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3449699571
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.650565860
Short name T771
Test name
Test status
Simulation time 9438036 ps
CPU time 0.7 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:19 PM PDT 24
Peak memory 206052 kb
Host smart-02d4ae06-9ea9-49ff-ae3a-1128cdb46956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650565860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.650565860
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.601327289
Short name T670
Test name
Test status
Simulation time 213567730 ps
CPU time 2.89 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 207584 kb
Host smart-c6c63876-793c-4341-9934-bf877b26841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601327289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.601327289
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3511253048
Short name T80
Test name
Test status
Simulation time 171262834 ps
CPU time 2.68 seconds
Started Jun 30 05:44:19 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 208100 kb
Host smart-d7f461e9-957f-4b65-87e4-afa32ea0eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511253048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3511253048
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.870354674
Short name T611
Test name
Test status
Simulation time 179503739 ps
CPU time 2.13 seconds
Started Jun 30 05:44:21 PM PDT 24
Finished Jun 30 05:44:23 PM PDT 24
Peak memory 214348 kb
Host smart-9f969ffe-18f8-4c9b-86af-b5552f5e6c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870354674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.870354674
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.237314150
Short name T817
Test name
Test status
Simulation time 884109101 ps
CPU time 6.68 seconds
Started Jun 30 05:44:21 PM PDT 24
Finished Jun 30 05:44:28 PM PDT 24
Peak memory 222404 kb
Host smart-69d24141-aea1-45ec-bd45-bb6a5f7b4321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237314150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.237314150
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3842318587
Short name T680
Test name
Test status
Simulation time 368432217 ps
CPU time 3.18 seconds
Started Jun 30 05:44:19 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 216080 kb
Host smart-069067d0-596c-4168-95d1-ccc654a805b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842318587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3842318587
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2488444171
Short name T326
Test name
Test status
Simulation time 194164902 ps
CPU time 2.65 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 208700 kb
Host smart-c19173ba-bf5c-4b04-b7b1-5f560ccda7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488444171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2488444171
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3514328292
Short name T131
Test name
Test status
Simulation time 248143613 ps
CPU time 3.93 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 207040 kb
Host smart-71005be5-69ee-4038-a86e-40f839f3493c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514328292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3514328292
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.835665613
Short name T190
Test name
Test status
Simulation time 890355148 ps
CPU time 7.27 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:19 PM PDT 24
Peak memory 208100 kb
Host smart-89c14866-5e50-4cad-9015-7da18968e701
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835665613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.835665613
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1459201249
Short name T789
Test name
Test status
Simulation time 83719181 ps
CPU time 1.93 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:20 PM PDT 24
Peak memory 207972 kb
Host smart-635afe2e-faa1-4632-bab3-4b3541fca8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459201249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1459201249
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2924735023
Short name T567
Test name
Test status
Simulation time 119464685 ps
CPU time 3.19 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:15 PM PDT 24
Peak memory 208504 kb
Host smart-93789956-b433-4c7e-baf7-8f8385b543a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924735023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2924735023
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.402118352
Short name T548
Test name
Test status
Simulation time 131724530 ps
CPU time 5.83 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 207188 kb
Host smart-ec7d57ed-2834-4fa7-a42f-806e656ec30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402118352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.402118352
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3161842853
Short name T227
Test name
Test status
Simulation time 101775148 ps
CPU time 4.25 seconds
Started Jun 30 05:44:17 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 209540 kb
Host smart-517695d5-e635-4a8e-8cbe-8ffb502d5617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161842853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3161842853
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2712232252
Short name T577
Test name
Test status
Simulation time 14818477 ps
CPU time 0.93 seconds
Started Jun 30 05:44:35 PM PDT 24
Finished Jun 30 05:44:36 PM PDT 24
Peak memory 206156 kb
Host smart-7ec9dd20-575e-4e03-a4a9-f450b7ad307e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712232252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2712232252
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2318256254
Short name T681
Test name
Test status
Simulation time 39467776 ps
CPU time 1.99 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:21 PM PDT 24
Peak memory 214312 kb
Host smart-9a719757-dd07-4d4f-8ce3-848fb0e5c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318256254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2318256254
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.793024490
Short name T534
Test name
Test status
Simulation time 172360080 ps
CPU time 3.16 seconds
Started Jun 30 05:44:20 PM PDT 24
Finished Jun 30 05:44:23 PM PDT 24
Peak memory 214564 kb
Host smart-6aa6ba81-7eca-4948-af10-ac225f55d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793024490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.793024490
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1893432839
Short name T802
Test name
Test status
Simulation time 135035030 ps
CPU time 2.74 seconds
Started Jun 30 05:44:19 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 214344 kb
Host smart-4607c793-2536-42ce-928d-4658b8603505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893432839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1893432839
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1850573806
Short name T479
Test name
Test status
Simulation time 237311206 ps
CPU time 3.59 seconds
Started Jun 30 05:44:22 PM PDT 24
Finished Jun 30 05:44:26 PM PDT 24
Peak memory 209112 kb
Host smart-e5faf0e3-5665-44b7-b461-5b46fb5c79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850573806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1850573806
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3801915172
Short name T360
Test name
Test status
Simulation time 161192937 ps
CPU time 4.14 seconds
Started Jun 30 05:44:20 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 207292 kb
Host smart-e4984111-4cae-40df-82a0-0ce529eed3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801915172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3801915172
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2369106201
Short name T586
Test name
Test status
Simulation time 1377445519 ps
CPU time 8.93 seconds
Started Jun 30 05:44:17 PM PDT 24
Finished Jun 30 05:44:26 PM PDT 24
Peak memory 208592 kb
Host smart-7b7a8533-f5b4-4948-b3cb-d28febcc486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369106201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2369106201
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3298247089
Short name T705
Test name
Test status
Simulation time 579802634 ps
CPU time 4.42 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:23 PM PDT 24
Peak memory 208744 kb
Host smart-abc752e8-6386-4f70-8d17-43bba285377d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298247089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3298247089
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3486887256
Short name T570
Test name
Test status
Simulation time 404849858 ps
CPU time 3.78 seconds
Started Jun 30 05:44:21 PM PDT 24
Finished Jun 30 05:44:25 PM PDT 24
Peak memory 208612 kb
Host smart-85daf5c5-7d7c-4a10-a411-2e290633aa2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486887256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3486887256
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1791876116
Short name T412
Test name
Test status
Simulation time 62915073 ps
CPU time 2.47 seconds
Started Jun 30 05:44:19 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 207396 kb
Host smart-bbf7d690-f5e4-461f-b7b4-5fd1c21c5d8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791876116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1791876116
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1918508618
Short name T238
Test name
Test status
Simulation time 559605784 ps
CPU time 4.46 seconds
Started Jun 30 05:44:19 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 220384 kb
Host smart-b2204d47-7b40-415a-8a80-5726537bb42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918508618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1918508618
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3372640509
Short name T685
Test name
Test status
Simulation time 548115919 ps
CPU time 13.23 seconds
Started Jun 30 05:44:19 PM PDT 24
Finished Jun 30 05:44:32 PM PDT 24
Peak memory 206804 kb
Host smart-15921a82-8f9f-4612-aae6-44046c39efaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372640509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3372640509
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1548629501
Short name T890
Test name
Test status
Simulation time 13191499136 ps
CPU time 53.04 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 216468 kb
Host smart-4095c3d9-f8e0-4502-bcdb-eff950310884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548629501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1548629501
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1257132744
Short name T891
Test name
Test status
Simulation time 241629722 ps
CPU time 3.36 seconds
Started Jun 30 05:44:18 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 207228 kb
Host smart-4d793877-af73-4185-a4a5-59af09572106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257132744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1257132744
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.22977382
Short name T176
Test name
Test status
Simulation time 2621195532 ps
CPU time 20.14 seconds
Started Jun 30 05:44:16 PM PDT 24
Finished Jun 30 05:44:37 PM PDT 24
Peak memory 210940 kb
Host smart-4341a645-1280-44ca-ba21-a8bf10aa7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22977382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.22977382
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.114218264
Short name T455
Test name
Test status
Simulation time 34388063 ps
CPU time 0.74 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:44:27 PM PDT 24
Peak memory 206080 kb
Host smart-7a73cf81-2ee1-4d28-9b1f-235ec10714b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114218264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.114218264
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.201209642
Short name T354
Test name
Test status
Simulation time 562006499 ps
CPU time 8.92 seconds
Started Jun 30 05:44:35 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 216052 kb
Host smart-9f90eb4e-b7a2-40f1-8716-461bab2db600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201209642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.201209642
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2903023479
Short name T640
Test name
Test status
Simulation time 110480312 ps
CPU time 2.49 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:40 PM PDT 24
Peak memory 220124 kb
Host smart-2a43209f-83ed-49cb-9a74-667284682923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903023479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2903023479
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2886243828
Short name T346
Test name
Test status
Simulation time 159736222 ps
CPU time 2.33 seconds
Started Jun 30 05:44:25 PM PDT 24
Finished Jun 30 05:44:27 PM PDT 24
Peak memory 210248 kb
Host smart-207cd938-a631-4e0d-93cf-8f4dc24983f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886243828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2886243828
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3463045933
Short name T315
Test name
Test status
Simulation time 185294189 ps
CPU time 2.43 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:44:29 PM PDT 24
Peak memory 214224 kb
Host smart-d150a129-f860-4630-9e38-f8597ce67f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463045933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3463045933
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1152620864
Short name T596
Test name
Test status
Simulation time 169560265 ps
CPU time 7.76 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 215196 kb
Host smart-138a4c3f-ea31-45a5-8841-e7dda08b488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152620864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1152620864
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1075180440
Short name T497
Test name
Test status
Simulation time 785886346 ps
CPU time 9.88 seconds
Started Jun 30 05:44:34 PM PDT 24
Finished Jun 30 05:44:44 PM PDT 24
Peak memory 214512 kb
Host smart-ad7fd813-50e4-4670-8403-7c5ebbbc1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075180440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1075180440
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3107733402
Short name T113
Test name
Test status
Simulation time 38091256 ps
CPU time 2.44 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 208680 kb
Host smart-adfc2f2d-51da-4855-af42-411e12c0a50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107733402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3107733402
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.539830427
Short name T273
Test name
Test status
Simulation time 93421117 ps
CPU time 2.73 seconds
Started Jun 30 05:44:35 PM PDT 24
Finished Jun 30 05:44:38 PM PDT 24
Peak memory 208564 kb
Host smart-460cec9c-a508-46f1-a98e-37310defb252
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539830427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.539830427
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4065684911
Short name T112
Test name
Test status
Simulation time 85494278 ps
CPU time 2.03 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:40 PM PDT 24
Peak memory 207140 kb
Host smart-f2338bc8-c52e-4d60-a81d-191bafc2d68c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065684911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4065684911
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.353699063
Short name T750
Test name
Test status
Simulation time 205118092 ps
CPU time 3.6 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:49 PM PDT 24
Peak memory 208636 kb
Host smart-af2fd89d-6ab3-498f-84d3-36bee925be29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353699063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.353699063
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.397529501
Short name T668
Test name
Test status
Simulation time 59841583 ps
CPU time 1.98 seconds
Started Jun 30 05:44:34 PM PDT 24
Finished Jun 30 05:44:37 PM PDT 24
Peak memory 208188 kb
Host smart-5b9f5786-0e38-4a06-8069-60360a22db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397529501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.397529501
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1037152239
Short name T660
Test name
Test status
Simulation time 93585378 ps
CPU time 2.43 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:44:28 PM PDT 24
Peak memory 208420 kb
Host smart-48cefb8c-351f-4206-8896-c541c3ab3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037152239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1037152239
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.934319798
Short name T183
Test name
Test status
Simulation time 191544111 ps
CPU time 7.16 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:44:34 PM PDT 24
Peak memory 220528 kb
Host smart-7a55a190-11ac-4ab7-a5b6-36923f4a5eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934319798 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.934319798
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.940317120
Short name T838
Test name
Test status
Simulation time 127828058 ps
CPU time 1.41 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:38 PM PDT 24
Peak memory 210056 kb
Host smart-29d000e9-2846-4b32-b82a-f6023ae36162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940317120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.940317120
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.95622477
Short name T800
Test name
Test status
Simulation time 27295138 ps
CPU time 0.92 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 206184 kb
Host smart-22ca8b99-6fb9-4c2b-92ac-a475f4529d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95622477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.95622477
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1882823132
Short name T146
Test name
Test status
Simulation time 1580149137 ps
CPU time 82.7 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 215188 kb
Host smart-ce4ab64b-9f3b-4c02-9ed6-8745aa58af83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882823132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1882823132
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.824376651
Short name T827
Test name
Test status
Simulation time 49800773 ps
CPU time 3.63 seconds
Started Jun 30 05:44:35 PM PDT 24
Finished Jun 30 05:44:40 PM PDT 24
Peak memory 210524 kb
Host smart-5a38dcc3-811a-47ce-83c3-5c06305664cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824376651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.824376651
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1177885055
Short name T547
Test name
Test status
Simulation time 44547542 ps
CPU time 1.76 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 209864 kb
Host smart-c87cc7f7-9a92-4a85-86b2-e2e2ba7a68ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177885055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1177885055
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.159846293
Short name T277
Test name
Test status
Simulation time 82107107 ps
CPU time 1.99 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:40 PM PDT 24
Peak memory 214336 kb
Host smart-43fdbc8e-b501-43b5-9d9a-6d22341dbaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159846293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.159846293
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.221194758
Short name T793
Test name
Test status
Simulation time 310924942 ps
CPU time 3.63 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 206080 kb
Host smart-88755c01-246c-46e8-bf6c-0ec80a4d7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221194758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.221194758
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.606919036
Short name T682
Test name
Test status
Simulation time 126343242 ps
CPU time 5.7 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:43 PM PDT 24
Peak memory 215440 kb
Host smart-bd728143-d1f8-4f66-a0ea-09ded50c98c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606919036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.606919036
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2452659118
Short name T312
Test name
Test status
Simulation time 1738200201 ps
CPU time 50.6 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 217956 kb
Host smart-1ffade01-af22-44e3-9150-1f9d3432c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452659118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2452659118
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3190712607
Short name T699
Test name
Test status
Simulation time 289169588 ps
CPU time 4.72 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:44:31 PM PDT 24
Peak memory 208536 kb
Host smart-c4743cf3-0198-4fc1-aaf1-1e36af35bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190712607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3190712607
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2862346854
Short name T740
Test name
Test status
Simulation time 400337050 ps
CPU time 3.73 seconds
Started Jun 30 05:44:25 PM PDT 24
Finished Jun 30 05:44:29 PM PDT 24
Peak memory 206940 kb
Host smart-6424b2ab-4370-4cb3-bea5-bc8dd729b993
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862346854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2862346854
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3307926883
Short name T486
Test name
Test status
Simulation time 278818283 ps
CPU time 3.69 seconds
Started Jun 30 05:44:27 PM PDT 24
Finished Jun 30 05:44:31 PM PDT 24
Peak memory 208816 kb
Host smart-5a1241d2-df43-4a83-befb-742344ab0514
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307926883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3307926883
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.849012641
Short name T404
Test name
Test status
Simulation time 751452576 ps
CPU time 2.79 seconds
Started Jun 30 05:44:35 PM PDT 24
Finished Jun 30 05:44:38 PM PDT 24
Peak memory 206864 kb
Host smart-10b92278-2f0f-4347-94cf-27ed7c19dd24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849012641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.849012641
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2859992575
Short name T647
Test name
Test status
Simulation time 190389807 ps
CPU time 2.55 seconds
Started Jun 30 05:44:39 PM PDT 24
Finished Jun 30 05:44:42 PM PDT 24
Peak memory 218392 kb
Host smart-f36f9768-b461-4548-91a3-dabaae6c0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859992575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2859992575
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2336691053
Short name T471
Test name
Test status
Simulation time 176840995 ps
CPU time 3.79 seconds
Started Jun 30 05:44:26 PM PDT 24
Finished Jun 30 05:44:30 PM PDT 24
Peak memory 208412 kb
Host smart-559b44ff-7a53-4a73-82d1-32a719c62cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336691053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2336691053
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4154054463
Short name T304
Test name
Test status
Simulation time 1882745982 ps
CPU time 34.82 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:45:14 PM PDT 24
Peak memory 216952 kb
Host smart-a033b5dc-e6ca-46c5-8e6f-c593c28335fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154054463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4154054463
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.93361216
Short name T578
Test name
Test status
Simulation time 6864668845 ps
CPU time 40.11 seconds
Started Jun 30 05:44:27 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 209148 kb
Host smart-41e13731-c860-499d-9402-7fbdfb96eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93361216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.93361216
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3367338351
Short name T392
Test name
Test status
Simulation time 143652708 ps
CPU time 1.44 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 209864 kb
Host smart-fc564caf-40b8-4d8f-aca3-28410ba6a26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367338351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3367338351
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3726225658
Short name T467
Test name
Test status
Simulation time 21964545 ps
CPU time 1.03 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:42 PM PDT 24
Peak memory 206156 kb
Host smart-870eb52f-71b5-4fda-9573-e36a4e170ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726225658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3726225658
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3776345213
Short name T415
Test name
Test status
Simulation time 185071064 ps
CPU time 3.43 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:42 PM PDT 24
Peak memory 214548 kb
Host smart-d7f3e55a-d760-455a-97b2-e01e4859e02e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776345213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3776345213
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2483991055
Short name T18
Test name
Test status
Simulation time 228761355 ps
CPU time 2.81 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:41 PM PDT 24
Peak memory 208836 kb
Host smart-71f5a955-4d5c-46d4-b4b6-72d1d141d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483991055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2483991055
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.756941017
Short name T358
Test name
Test status
Simulation time 588730734 ps
CPU time 4.76 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:50 PM PDT 24
Peak memory 209536 kb
Host smart-bc6cd28b-16a8-443b-8482-ba13cd94343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756941017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.756941017
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2889026344
Short name T213
Test name
Test status
Simulation time 825934552 ps
CPU time 24.04 seconds
Started Jun 30 05:44:39 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 210436 kb
Host smart-9dc00bcb-0a0b-47d2-a03b-2cba8b4bd709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889026344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2889026344
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.610710539
Short name T815
Test name
Test status
Simulation time 64878797 ps
CPU time 2.88 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 208296 kb
Host smart-75f586b0-293c-400e-83dc-2186b6952ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610710539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.610710539
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3006802034
Short name T474
Test name
Test status
Simulation time 169372104 ps
CPU time 2.94 seconds
Started Jun 30 05:44:37 PM PDT 24
Finished Jun 30 05:44:40 PM PDT 24
Peak memory 206972 kb
Host smart-de9dd2e6-d901-4c07-aa5a-6432cf6836d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006802034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3006802034
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1963708704
Short name T370
Test name
Test status
Simulation time 91723769 ps
CPU time 2.06 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 208696 kb
Host smart-ab98b91c-3a09-4aca-873e-88de56db5d4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963708704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1963708704
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1528774558
Short name T742
Test name
Test status
Simulation time 335253924 ps
CPU time 3.62 seconds
Started Jun 30 05:44:43 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 208508 kb
Host smart-92041c4d-e7ce-4190-9997-abe648136611
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528774558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1528774558
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2695791016
Short name T735
Test name
Test status
Simulation time 261457568 ps
CPU time 1.92 seconds
Started Jun 30 05:44:45 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 207776 kb
Host smart-7f20b637-e21c-4824-876a-f1edb061fd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695791016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2695791016
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2306975843
Short name T462
Test name
Test status
Simulation time 389543970 ps
CPU time 3.01 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:49 PM PDT 24
Peak memory 207228 kb
Host smart-48da2339-9536-461c-847a-18b296e437aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306975843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2306975843
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1671889255
Short name T610
Test name
Test status
Simulation time 1951108699 ps
CPU time 26.92 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 215092 kb
Host smart-206cec22-5e4e-4a70-aeb5-fb9a1b9c788d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671889255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1671889255
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3515304080
Short name T368
Test name
Test status
Simulation time 391915792 ps
CPU time 4.94 seconds
Started Jun 30 05:44:34 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 210044 kb
Host smart-b5c61d59-bf22-4f7c-94c9-d360c4668b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515304080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3515304080
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4070028482
Short name T683
Test name
Test status
Simulation time 215704902 ps
CPU time 1.37 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:38 PM PDT 24
Peak memory 209624 kb
Host smart-2f41659d-3d49-45b7-b440-1704091eb783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070028482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4070028482
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3671033676
Short name T899
Test name
Test status
Simulation time 58780040 ps
CPU time 0.92 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:42 PM PDT 24
Peak memory 206152 kb
Host smart-0157f0d2-21a6-435c-930a-c7b402e4da9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671033676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3671033676
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.422844274
Short name T303
Test name
Test status
Simulation time 89625606 ps
CPU time 3.13 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:42 PM PDT 24
Peak memory 214332 kb
Host smart-9ae0e53d-9247-4046-bd41-95f83b912c08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422844274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.422844274
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3936482495
Short name T790
Test name
Test status
Simulation time 725868810 ps
CPU time 4.86 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 210148 kb
Host smart-402b838c-3fe1-47ec-9ab7-b294e53d8159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936482495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3936482495
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1038424164
Short name T788
Test name
Test status
Simulation time 351564962 ps
CPU time 5.01 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:47 PM PDT 24
Peak memory 219768 kb
Host smart-e3ad1fe0-72f7-4725-b2ba-0262f20b5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038424164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1038424164
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2861751763
Short name T96
Test name
Test status
Simulation time 116445631 ps
CPU time 2.33 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:41 PM PDT 24
Peak memory 219156 kb
Host smart-8d40ffc3-d09d-4965-a65f-0099adce96d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861751763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2861751763
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1912590605
Short name T722
Test name
Test status
Simulation time 40617002 ps
CPU time 2.7 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 214256 kb
Host smart-b1b34dc9-92af-492b-99d6-f6cc75fec1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912590605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1912590605
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1531679782
Short name T687
Test name
Test status
Simulation time 206645190 ps
CPU time 2.64 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 219016 kb
Host smart-ee388c0a-3c37-4683-abc8-d74ff542b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531679782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1531679782
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.729060193
Short name T288
Test name
Test status
Simulation time 106051015 ps
CPU time 3.94 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:43 PM PDT 24
Peak memory 207748 kb
Host smart-541a9ef5-bccd-4f50-945f-e44d20dec64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729060193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.729060193
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2256261785
Short name T468
Test name
Test status
Simulation time 470889794 ps
CPU time 2.37 seconds
Started Jun 30 05:44:39 PM PDT 24
Finished Jun 30 05:44:43 PM PDT 24
Peak memory 206844 kb
Host smart-68cba044-847d-40b5-a06d-653b06d62734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256261785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2256261785
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3922018923
Short name T631
Test name
Test status
Simulation time 491635368 ps
CPU time 2.79 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:41 PM PDT 24
Peak memory 206988 kb
Host smart-ca69565b-e14b-42d9-96d1-d3ca3ff4eb85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922018923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3922018923
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2864248216
Short name T675
Test name
Test status
Simulation time 75542105 ps
CPU time 3.62 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:47 PM PDT 24
Peak memory 208872 kb
Host smart-d8466e55-e3c4-4df0-a233-514a8c9e4b44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864248216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2864248216
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4149159011
Short name T654
Test name
Test status
Simulation time 636600698 ps
CPU time 22.29 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:45:04 PM PDT 24
Peak memory 208940 kb
Host smart-21d09bd3-7386-49a0-ad8b-7d4f9aa6a00f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149159011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4149159011
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2154200982
Short name T268
Test name
Test status
Simulation time 58996220 ps
CPU time 2.74 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 214332 kb
Host smart-af2c5d26-b2bf-43bb-8d71-8b28bff7c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154200982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2154200982
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1608271569
Short name T843
Test name
Test status
Simulation time 252145803 ps
CPU time 3.03 seconds
Started Jun 30 05:44:36 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 208648 kb
Host smart-b5301cd8-f725-40a1-9812-4d7b3443ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608271569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1608271569
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.587294397
Short name T643
Test name
Test status
Simulation time 1547998346 ps
CPU time 15.97 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 222764 kb
Host smart-81303ea6-0194-47e3-9142-218c15c184fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587294397 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.587294397
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2986185266
Short name T305
Test name
Test status
Simulation time 4049842099 ps
CPU time 58.16 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 210404 kb
Host smart-69fde0a2-3d5a-48e2-aa0f-b1437fd7755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986185266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2986185266
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1329744117
Short name T602
Test name
Test status
Simulation time 88710947 ps
CPU time 1.58 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:47 PM PDT 24
Peak memory 209716 kb
Host smart-c1ae658c-094b-4aec-8f35-8188f0e47f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329744117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1329744117
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3884911020
Short name T665
Test name
Test status
Simulation time 17443336 ps
CPU time 0.74 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:44 PM PDT 24
Peak memory 206056 kb
Host smart-8209fd64-4df6-40df-af6b-4a51be605f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884911020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3884911020
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1112047415
Short name T768
Test name
Test status
Simulation time 41317701 ps
CPU time 2.44 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:44 PM PDT 24
Peak memory 207512 kb
Host smart-3f196c11-47db-4a8b-860f-b677687e416a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112047415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1112047415
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1389758834
Short name T214
Test name
Test status
Simulation time 62720751 ps
CPU time 3.32 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 214332 kb
Host smart-2b80d4dd-04d8-41cc-9200-e863e534475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389758834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1389758834
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2120654170
Short name T869
Test name
Test status
Simulation time 774871485 ps
CPU time 24.59 seconds
Started Jun 30 05:44:43 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 214304 kb
Host smart-e7915ded-2db8-43e8-b1ae-9b1c66a738f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120654170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2120654170
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3625063395
Short name T382
Test name
Test status
Simulation time 377297414 ps
CPU time 3.26 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:46 PM PDT 24
Peak memory 208556 kb
Host smart-ca5aac15-5262-419f-8cc3-8fdfb408251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625063395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3625063395
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2954408417
Short name T712
Test name
Test status
Simulation time 56827901 ps
CPU time 3.08 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 208848 kb
Host smart-14fd636a-6fd8-41d2-9005-b2da01dd0060
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954408417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2954408417
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1883437147
Short name T625
Test name
Test status
Simulation time 1156757371 ps
CPU time 3.22 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 206984 kb
Host smart-52b99060-03a5-4bfe-8191-59d2038b144b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883437147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1883437147
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1445731374
Short name T271
Test name
Test status
Simulation time 2269484564 ps
CPU time 18.23 seconds
Started Jun 30 05:44:39 PM PDT 24
Finished Jun 30 05:44:59 PM PDT 24
Peak memory 216436 kb
Host smart-5dc00786-5eec-4c5e-aa39-36dc0bfd6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445731374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1445731374
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3194078595
Short name T620
Test name
Test status
Simulation time 64369880 ps
CPU time 1.61 seconds
Started Jun 30 05:44:38 PM PDT 24
Finished Jun 30 05:44:41 PM PDT 24
Peak memory 206840 kb
Host smart-aaa643fd-d804-474f-ba3a-552b63c2c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194078595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3194078595
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2094853318
Short name T895
Test name
Test status
Simulation time 1698543100 ps
CPU time 26.83 seconds
Started Jun 30 05:44:42 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 222312 kb
Host smart-3f7909e7-89f5-4016-9519-8301cb60d6d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094853318 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2094853318
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1603107877
Short name T595
Test name
Test status
Simulation time 140490392 ps
CPU time 2.83 seconds
Started Jun 30 05:44:40 PM PDT 24
Finished Jun 30 05:44:44 PM PDT 24
Peak memory 207860 kb
Host smart-d331260f-04de-46d5-ae7f-a0de1504ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603107877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1603107877
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4007726011
Short name T637
Test name
Test status
Simulation time 54576235 ps
CPU time 2.65 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:49 PM PDT 24
Peak memory 209948 kb
Host smart-5ae3607d-dd6a-44e5-99d4-ed4640a5cef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007726011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4007726011
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.639593219
Short name T362
Test name
Test status
Simulation time 401740984 ps
CPU time 7.86 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 214312 kb
Host smart-53ffd822-38f4-4e39-8d30-f64564dc6f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639593219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.639593219
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.184134739
Short name T691
Test name
Test status
Simulation time 1815609971 ps
CPU time 5.24 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 221780 kb
Host smart-10c76660-5fed-465d-87ef-486f348b9b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184134739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.184134739
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2240813537
Short name T829
Test name
Test status
Simulation time 66059335 ps
CPU time 3.14 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 209924 kb
Host smart-13adb409-aa9c-4c7a-905c-37d05acfe3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240813537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2240813537
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4128076533
Short name T294
Test name
Test status
Simulation time 33797001 ps
CPU time 2.13 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 214416 kb
Host smart-db28630f-c0f2-4c57-b808-57fac5a280f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128076533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4128076533
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2668810849
Short name T426
Test name
Test status
Simulation time 76206986 ps
CPU time 1.58 seconds
Started Jun 30 05:44:42 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 214276 kb
Host smart-53d37c36-0e50-433d-8542-3e91102ecda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668810849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2668810849
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.1656190489
Short name T796
Test name
Test status
Simulation time 55456747 ps
CPU time 2.36 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:51 PM PDT 24
Peak memory 207272 kb
Host smart-2215cab4-fd91-4079-9715-095b16a6904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656190489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1656190489
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3542435853
Short name T633
Test name
Test status
Simulation time 32233316 ps
CPU time 2.35 seconds
Started Jun 30 05:44:41 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 207204 kb
Host smart-fd274230-afef-4900-b1d6-079954653115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542435853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3542435853
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2776305557
Short name T140
Test name
Test status
Simulation time 131094622 ps
CPU time 2.5 seconds
Started Jun 30 05:44:44 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 208796 kb
Host smart-8b947698-cf9c-409b-919f-64480c82e58d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776305557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2776305557
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4011829016
Short name T328
Test name
Test status
Simulation time 236120702 ps
CPU time 6.79 seconds
Started Jun 30 05:44:42 PM PDT 24
Finished Jun 30 05:44:50 PM PDT 24
Peak memory 208284 kb
Host smart-4d59aa3f-817c-461a-b9dd-7243666cc6e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011829016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4011829016
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2630347151
Short name T376
Test name
Test status
Simulation time 254897043 ps
CPU time 3.1 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 206944 kb
Host smart-e61949ef-8363-4f51-a9a7-fefd2b7f7f7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630347151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2630347151
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.696081375
Short name T237
Test name
Test status
Simulation time 167662776 ps
CPU time 4.78 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 218340 kb
Host smart-ac3cc151-ef2f-4618-8d77-75b717f099ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696081375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.696081375
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2827407007
Short name T669
Test name
Test status
Simulation time 99529702 ps
CPU time 2.78 seconds
Started Jun 30 05:44:45 PM PDT 24
Finished Jun 30 05:44:49 PM PDT 24
Peak memory 206880 kb
Host smart-98bab03e-3ea6-48f4-9d9b-eb318bf9c564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827407007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2827407007
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.138956660
Short name T728
Test name
Test status
Simulation time 166203168 ps
CPU time 10.81 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 222612 kb
Host smart-f6ce5991-04fe-4ddd-8a07-a98d77ab856c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138956660 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.138956660
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2508473869
Short name T766
Test name
Test status
Simulation time 498585693 ps
CPU time 5.84 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 214300 kb
Host smart-cf3a786a-2daa-49fe-b064-a0ed8431cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508473869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2508473869
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.160032606
Short name T822
Test name
Test status
Simulation time 566283672 ps
CPU time 1.85 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:50 PM PDT 24
Peak memory 210096 kb
Host smart-e4c05791-7461-4e3e-8be5-8e087c5142ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160032606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.160032606
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.903507016
Short name T808
Test name
Test status
Simulation time 11697302 ps
CPU time 0.74 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 206060 kb
Host smart-7e8ea944-817b-48ba-b903-2815853fa3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903507016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.903507016
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3591883519
Short name T371
Test name
Test status
Simulation time 839341525 ps
CPU time 14.6 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 215408 kb
Host smart-7791b4d4-ca9b-44f5-87e0-e445a7cf72f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591883519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3591883519
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1354864514
Short name T230
Test name
Test status
Simulation time 327898817 ps
CPU time 4.01 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 219640 kb
Host smart-63ec1b72-6978-4aad-b043-6bdc06cbba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354864514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1354864514
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1994422161
Short name T387
Test name
Test status
Simulation time 1001293068 ps
CPU time 10.29 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:45:01 PM PDT 24
Peak memory 214344 kb
Host smart-b1e35341-ed62-4ccc-b60b-6ec0eba0ba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994422161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1994422161
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3222785021
Short name T235
Test name
Test status
Simulation time 211437258 ps
CPU time 3.59 seconds
Started Jun 30 05:44:50 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 220984 kb
Host smart-da625bf6-2b06-46dd-b1b8-3afa45d997ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222785021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3222785021
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3585801573
Short name T905
Test name
Test status
Simulation time 84136894 ps
CPU time 3.19 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 208984 kb
Host smart-d19149dc-4460-4b61-bd0a-efefa57a37a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585801573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3585801573
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.4189909424
Short name T809
Test name
Test status
Simulation time 131279528 ps
CPU time 5.82 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 214296 kb
Host smart-8850b292-2cd0-40a3-ad55-000d1a4e17fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189909424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4189909424
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.287321179
Short name T769
Test name
Test status
Simulation time 678558859 ps
CPU time 6.21 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 208176 kb
Host smart-bf5e3b71-2861-4f49-99cb-746434c731dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287321179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.287321179
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1311927680
Short name T2
Test name
Test status
Simulation time 126622756 ps
CPU time 2.05 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:51 PM PDT 24
Peak memory 208932 kb
Host smart-da0efe08-f53d-403b-bd45-e2fa2255c705
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311927680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1311927680
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2873060106
Short name T739
Test name
Test status
Simulation time 467309255 ps
CPU time 3.32 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 206948 kb
Host smart-ac7eac33-b676-4005-91d1-33520bc71fa2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873060106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2873060106
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.161033092
Short name T520
Test name
Test status
Simulation time 710093821 ps
CPU time 3.55 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 208596 kb
Host smart-a9a3a0b6-1c9c-442c-9626-8aa619e42939
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161033092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.161033092
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.85240924
Short name T436
Test name
Test status
Simulation time 52478125 ps
CPU time 2.69 seconds
Started Jun 30 05:44:54 PM PDT 24
Finished Jun 30 05:44:57 PM PDT 24
Peak memory 209696 kb
Host smart-070b4e8b-37b7-4feb-b0ec-e0f4531a05f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85240924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.85240924
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3027542242
Short name T859
Test name
Test status
Simulation time 493031203 ps
CPU time 2.55 seconds
Started Jun 30 05:44:50 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 206924 kb
Host smart-940c56ee-412b-42fb-844a-7e99f47f871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027542242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3027542242
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3336048047
Short name T650
Test name
Test status
Simulation time 782981777 ps
CPU time 8.92 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:57 PM PDT 24
Peak memory 214416 kb
Host smart-1e8f6005-b16e-4422-bf54-5602b3ae973a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336048047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3336048047
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2763755803
Short name T225
Test name
Test status
Simulation time 152715171 ps
CPU time 3.19 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:51 PM PDT 24
Peak memory 208844 kb
Host smart-fb998adf-1d80-407f-ac78-f9988455da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763755803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2763755803
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.693702035
Short name T483
Test name
Test status
Simulation time 70468901 ps
CPU time 1.82 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 210900 kb
Host smart-4692c57f-6623-40b9-a8d0-0dfa90a4b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693702035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.693702035
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3968434254
Short name T545
Test name
Test status
Simulation time 9833896 ps
CPU time 0.79 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 206052 kb
Host smart-5c80f27d-fbb9-4eee-9159-34770a094625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968434254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3968434254
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.495179249
Short name T20
Test name
Test status
Simulation time 709015734 ps
CPU time 4.8 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 209340 kb
Host smart-45837c60-4a91-4a1d-a87b-e539b8d51643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495179249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.495179249
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.415711280
Short name T313
Test name
Test status
Simulation time 212386619 ps
CPU time 3.84 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 207404 kb
Host smart-408f9aac-a912-4735-aa5c-49e4a414bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415711280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.415711280
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1161823708
Short name T94
Test name
Test status
Simulation time 90230025 ps
CPU time 2.93 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 209192 kb
Host smart-dc520f04-5a68-4ab9-8cca-88344cdb2407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161823708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1161823708
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2834568928
Short name T616
Test name
Test status
Simulation time 103788107 ps
CPU time 1.66 seconds
Started Jun 30 05:44:45 PM PDT 24
Finished Jun 30 05:44:48 PM PDT 24
Peak memory 214280 kb
Host smart-d9e286a1-3aaa-47ab-a869-2dd7e2b360de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834568928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2834568928
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.585015123
Short name T692
Test name
Test status
Simulation time 99033453 ps
CPU time 3.57 seconds
Started Jun 30 05:44:47 PM PDT 24
Finished Jun 30 05:44:51 PM PDT 24
Peak memory 206968 kb
Host smart-f7672dd6-efe0-4841-b5be-0a3b6a3975cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585015123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.585015123
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2181826542
Short name T674
Test name
Test status
Simulation time 988701575 ps
CPU time 7.85 seconds
Started Jun 30 05:44:50 PM PDT 24
Finished Jun 30 05:44:59 PM PDT 24
Peak memory 218472 kb
Host smart-863eeab7-57cf-43e9-90ca-20d6ad028cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181826542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2181826542
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3698347677
Short name T444
Test name
Test status
Simulation time 253743212 ps
CPU time 2.71 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 207076 kb
Host smart-1d269395-d69f-4e2f-b14f-c9baa710388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698347677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3698347677
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4160951290
Short name T779
Test name
Test status
Simulation time 72589490 ps
CPU time 2.74 seconds
Started Jun 30 05:44:48 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 208320 kb
Host smart-a994c0dd-032d-4908-962e-6c6dd085ca6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160951290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4160951290
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2043670140
Short name T587
Test name
Test status
Simulation time 57659767 ps
CPU time 3.06 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 208172 kb
Host smart-df27390a-56ff-4350-af6c-6598cc69c0cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043670140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2043670140
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4030946215
Short name T716
Test name
Test status
Simulation time 417567706 ps
CPU time 4 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 207636 kb
Host smart-aa0ffc4c-3835-4512-a720-d16572e3346d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030946215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4030946215
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.514817565
Short name T623
Test name
Test status
Simulation time 230898961 ps
CPU time 3.23 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 218304 kb
Host smart-c4914c30-e689-4a36-9e71-60a012498ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514817565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.514817565
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3519773878
Short name T608
Test name
Test status
Simulation time 99460054 ps
CPU time 2.67 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 206952 kb
Host smart-0a16afc8-e185-4b34-bf5e-6e0d66933f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519773878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3519773878
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.542320677
Short name T74
Test name
Test status
Simulation time 163913292 ps
CPU time 9.65 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 215080 kb
Host smart-9f6e1e77-ab80-47e9-937e-3426dc9227a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542320677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.542320677
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2035218040
Short name T286
Test name
Test status
Simulation time 546719394 ps
CPU time 4.63 seconds
Started Jun 30 05:44:49 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 222400 kb
Host smart-118233d4-0a46-4e59-8e82-03944a758251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035218040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2035218040
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.978126767
Short name T733
Test name
Test status
Simulation time 475421676 ps
CPU time 2.34 seconds
Started Jun 30 05:44:50 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 209728 kb
Host smart-9ae5e544-5238-4997-9b18-f68eee3d0c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978126767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.978126767
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4076857485
Short name T563
Test name
Test status
Simulation time 74338674 ps
CPU time 0.9 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:52 PM PDT 24
Peak memory 206176 kb
Host smart-e250b9d3-a035-4c1f-a5ee-2e8a5a94d39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076857485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4076857485
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4143867898
Short name T414
Test name
Test status
Simulation time 65624989 ps
CPU time 2.77 seconds
Started Jun 30 05:43:41 PM PDT 24
Finished Jun 30 05:43:44 PM PDT 24
Peak memory 214340 kb
Host smart-8a9e5449-8500-49fd-a9bd-68d525da7aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143867898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4143867898
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.352899899
Short name T422
Test name
Test status
Simulation time 716356062 ps
CPU time 3.04 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:46 PM PDT 24
Peak memory 207484 kb
Host smart-21677e04-40af-42bc-9c56-578d45ffa514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352899899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.352899899
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1059274096
Short name T295
Test name
Test status
Simulation time 468474778 ps
CPU time 5.98 seconds
Started Jun 30 05:43:45 PM PDT 24
Finished Jun 30 05:43:51 PM PDT 24
Peak memory 214312 kb
Host smart-1e22a678-edc8-490e-abc1-0112dcd778f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059274096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1059274096
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1782298771
Short name T848
Test name
Test status
Simulation time 439225861 ps
CPU time 5.25 seconds
Started Jun 30 05:43:45 PM PDT 24
Finished Jun 30 05:43:50 PM PDT 24
Peak memory 214972 kb
Host smart-db5c6d6b-a496-4545-b9d6-dcb41d2045ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782298771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1782298771
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3978214565
Short name T202
Test name
Test status
Simulation time 70779559 ps
CPU time 2.93 seconds
Started Jun 30 05:43:44 PM PDT 24
Finished Jun 30 05:43:48 PM PDT 24
Peak memory 207192 kb
Host smart-2e546256-7e0c-4417-81c9-45bd75e084eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978214565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3978214565
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.620404419
Short name T805
Test name
Test status
Simulation time 605412607 ps
CPU time 19.63 seconds
Started Jun 30 05:43:44 PM PDT 24
Finished Jun 30 05:44:04 PM PDT 24
Peak memory 219220 kb
Host smart-53fff22d-720a-431e-919b-c2c5ee9e72aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620404419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.620404419
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.399511070
Short name T12
Test name
Test status
Simulation time 758936251 ps
CPU time 6.81 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:58 PM PDT 24
Peak memory 229112 kb
Host smart-0e26c1b2-ec33-4d62-86ef-51b2479e48ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399511070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.399511070
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4225123568
Short name T17
Test name
Test status
Simulation time 69378561 ps
CPU time 2.54 seconds
Started Jun 30 05:43:45 PM PDT 24
Finished Jun 30 05:43:48 PM PDT 24
Peak memory 208612 kb
Host smart-28abd09b-39f2-49e7-ac96-40ba3c987f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225123568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4225123568
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1336237162
Short name T575
Test name
Test status
Simulation time 51943200 ps
CPU time 2.81 seconds
Started Jun 30 05:43:45 PM PDT 24
Finished Jun 30 05:43:48 PM PDT 24
Peak memory 208192 kb
Host smart-4bd77b3d-e80e-4896-9eab-8d054b95e083
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336237162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1336237162
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2643514272
Short name T491
Test name
Test status
Simulation time 45018168 ps
CPU time 2.27 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:46 PM PDT 24
Peak memory 207008 kb
Host smart-aaee708b-8e4a-4f86-82e6-219dd855e70b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643514272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2643514272
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3816471245
Short name T465
Test name
Test status
Simulation time 137047960 ps
CPU time 3.2 seconds
Started Jun 30 05:43:41 PM PDT 24
Finished Jun 30 05:43:44 PM PDT 24
Peak memory 208632 kb
Host smart-3c70a70c-fb33-4d18-a455-2cd2dd506ff2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816471245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3816471245
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1639754040
Short name T772
Test name
Test status
Simulation time 364906962 ps
CPU time 3.16 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:47 PM PDT 24
Peak memory 207620 kb
Host smart-dd4a10d5-ba5c-474b-bb43-054dfbf0483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639754040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1639754040
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1333827355
Short name T452
Test name
Test status
Simulation time 61294744 ps
CPU time 2.82 seconds
Started Jun 30 05:43:46 PM PDT 24
Finished Jun 30 05:43:49 PM PDT 24
Peak memory 206256 kb
Host smart-0e55cc38-0541-48e2-8d91-d708a904c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333827355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1333827355
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3130801866
Short name T689
Test name
Test status
Simulation time 691261175 ps
CPU time 6.33 seconds
Started Jun 30 05:43:43 PM PDT 24
Finished Jun 30 05:43:50 PM PDT 24
Peak memory 218460 kb
Host smart-3ab80fc2-aa82-4700-8348-111e39357b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130801866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3130801866
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1017909087
Short name T393
Test name
Test status
Simulation time 2070551971 ps
CPU time 16.1 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:44:08 PM PDT 24
Peak memory 211000 kb
Host smart-5beb3ae3-df4d-4f92-b22e-f590d34c80e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017909087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1017909087
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2831606664
Short name T615
Test name
Test status
Simulation time 36406902 ps
CPU time 0.89 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:00 PM PDT 24
Peak memory 206052 kb
Host smart-53f0e92f-fc9b-4815-a0c8-b8204cc9e31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831606664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2831606664
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.153999696
Short name T330
Test name
Test status
Simulation time 516644226 ps
CPU time 7.3 seconds
Started Jun 30 05:44:54 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 215012 kb
Host smart-f8c2dcbd-36a9-430b-8b17-1581f832eed8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153999696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.153999696
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3407607303
Short name T106
Test name
Test status
Simulation time 83161913 ps
CPU time 2.8 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:04 PM PDT 24
Peak memory 214672 kb
Host smart-26a77be6-07c3-43a7-96d1-b411f96b8774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407607303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3407607303
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3923160879
Short name T291
Test name
Test status
Simulation time 26618362 ps
CPU time 1.92 seconds
Started Jun 30 05:44:50 PM PDT 24
Finished Jun 30 05:44:53 PM PDT 24
Peak memory 214312 kb
Host smart-02ae75ed-3c15-4417-81e7-027e200f8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923160879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3923160879
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1988847930
Short name T778
Test name
Test status
Simulation time 120411610 ps
CPU time 2.63 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 215288 kb
Host smart-38c2507e-0763-4733-a798-e30c2bc60d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988847930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1988847930
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1253162931
Short name T879
Test name
Test status
Simulation time 38537751 ps
CPU time 2.22 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 214232 kb
Host smart-f28ddf25-1ccb-4fbb-9605-d51cf367330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253162931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1253162931
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4227466378
Short name T211
Test name
Test status
Simulation time 69141820 ps
CPU time 2.47 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 207076 kb
Host smart-a252ddf0-7b1c-4cf9-b122-65bd282e0e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227466378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4227466378
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.263754369
Short name T377
Test name
Test status
Simulation time 682801223 ps
CPU time 9.18 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 214344 kb
Host smart-54cb871b-3f5c-4f65-9b83-a9ed4a7f6e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263754369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.263754369
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3560175544
Short name T359
Test name
Test status
Simulation time 53412540 ps
CPU time 2.7 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 206960 kb
Host smart-2cc13193-ef2f-4914-8548-d6bd775d86e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560175544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3560175544
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1034943524
Short name T826
Test name
Test status
Simulation time 392742788 ps
CPU time 3.43 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 208280 kb
Host smart-c756ae5f-deaa-43e7-bd34-4d886e511413
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034943524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1034943524
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.960144754
Short name T841
Test name
Test status
Simulation time 580358996 ps
CPU time 5.22 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 208624 kb
Host smart-dd93d7c3-b3e1-4c43-af29-673ff0c14679
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960144754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.960144754
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3516595564
Short name T839
Test name
Test status
Simulation time 148074618 ps
CPU time 2.96 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 207084 kb
Host smart-96bd4c82-38c0-42d7-a4c4-467d307c4665
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516595564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3516595564
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2609123389
Short name T688
Test name
Test status
Simulation time 91454237 ps
CPU time 1.75 seconds
Started Jun 30 05:44:55 PM PDT 24
Finished Jun 30 05:44:57 PM PDT 24
Peak memory 207384 kb
Host smart-8bf528da-cc35-4608-bc06-5cd7a3720d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609123389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2609123389
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.790652644
Short name T763
Test name
Test status
Simulation time 30375754 ps
CPU time 2.18 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 208316 kb
Host smart-9f3a4800-e7a9-4895-8d5a-4d1eb242dd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790652644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.790652644
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.872870698
Short name T298
Test name
Test status
Simulation time 186001820 ps
CPU time 4.51 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 220248 kb
Host smart-54d9c69b-321c-49a3-9608-2a5699e1279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872870698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.872870698
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2408762109
Short name T199
Test name
Test status
Simulation time 1180911439 ps
CPU time 2.38 seconds
Started Jun 30 05:44:53 PM PDT 24
Finished Jun 30 05:44:56 PM PDT 24
Peak memory 210496 kb
Host smart-61f1c684-a1ae-4ad0-bddb-c055051b8ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408762109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2408762109
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2013503188
Short name T458
Test name
Test status
Simulation time 32663931 ps
CPU time 0.75 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 206036 kb
Host smart-fcc16d0c-15d5-4da9-86ca-23ed8962ce7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013503188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2013503188
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1571481445
Short name T408
Test name
Test status
Simulation time 29930654 ps
CPU time 1.78 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 222768 kb
Host smart-8fc04f64-b7ae-45fa-8fd7-f811e409a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571481445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1571481445
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2242036308
Short name T540
Test name
Test status
Simulation time 435515408 ps
CPU time 4.76 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 218500 kb
Host smart-2de9182f-bfe0-48be-a872-318cd18b213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242036308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2242036308
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3909141774
Short name T28
Test name
Test status
Simulation time 1324531808 ps
CPU time 8.78 seconds
Started Jun 30 05:44:56 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 221076 kb
Host smart-574581bb-cdd5-4e0c-b408-3fa80c781837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909141774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3909141774
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2644595834
Short name T342
Test name
Test status
Simulation time 184336923 ps
CPU time 4.44 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 221148 kb
Host smart-1c1b4eae-4da5-410b-b7b0-bf7dc6624aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644595834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2644595834
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4004092290
Short name T210
Test name
Test status
Simulation time 250736102 ps
CPU time 2.53 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:55 PM PDT 24
Peak memory 220764 kb
Host smart-47a5b729-bc96-419c-b7b5-12efa70f8cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004092290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4004092290
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1100658641
Short name T576
Test name
Test status
Simulation time 470059613 ps
CPU time 6.07 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:45:00 PM PDT 24
Peak memory 207612 kb
Host smart-a34d570f-aea2-4454-a46c-ee92e932e5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100658641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1100658641
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3047587080
Short name T14
Test name
Test status
Simulation time 38749297 ps
CPU time 2.28 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:00 PM PDT 24
Peak memory 206748 kb
Host smart-9a80c1f6-8244-44b7-8ea4-dd604e2c9f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047587080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3047587080
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.98820156
Short name T893
Test name
Test status
Simulation time 443132698 ps
CPU time 4.25 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 207080 kb
Host smart-082f26f2-289c-440f-b77d-4de05cc6bfd1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98820156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.98820156
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1091685349
Short name T773
Test name
Test status
Simulation time 124638974 ps
CPU time 3.7 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:57 PM PDT 24
Peak memory 208896 kb
Host smart-141fb3e3-b652-4bec-8cef-f993b68b00a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091685349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1091685349
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.976098690
Short name T513
Test name
Test status
Simulation time 140323939 ps
CPU time 4.05 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 208644 kb
Host smart-ae5863f4-b817-4198-a837-dd219a6e7e02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976098690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.976098690
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1078906362
Short name T850
Test name
Test status
Simulation time 3589886663 ps
CPU time 24.34 seconds
Started Jun 30 05:44:53 PM PDT 24
Finished Jun 30 05:45:19 PM PDT 24
Peak memory 209564 kb
Host smart-8a05252c-a59a-47f5-bd1f-dce918f6fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078906362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1078906362
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3346985047
Short name T727
Test name
Test status
Simulation time 480123222 ps
CPU time 3.63 seconds
Started Jun 30 05:44:54 PM PDT 24
Finished Jun 30 05:44:59 PM PDT 24
Peak memory 207044 kb
Host smart-c9fa777c-99f2-4077-9ade-f40b03197110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346985047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3346985047
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1970348198
Short name T792
Test name
Test status
Simulation time 1057336324 ps
CPU time 9.18 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 216396 kb
Host smart-f907c2f4-c75e-46c7-bfa0-fc8da5415305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970348198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1970348198
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.431538681
Short name T693
Test name
Test status
Simulation time 3361667476 ps
CPU time 56.75 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 214408 kb
Host smart-6fdd717c-fbd5-471f-843c-98020ac2f276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431538681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.431538681
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2418514565
Short name T652
Test name
Test status
Simulation time 62260623 ps
CPU time 1.63 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:45:04 PM PDT 24
Peak memory 209736 kb
Host smart-3cb26357-6a7b-45b9-a1c4-505e82d8e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418514565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2418514565
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.465867037
Short name T104
Test name
Test status
Simulation time 51685318 ps
CPU time 0.73 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 206056 kb
Host smart-e27442a8-c1da-4b24-9179-162ce50aaecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465867037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.465867037
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3587774315
Short name T428
Test name
Test status
Simulation time 31801483 ps
CPU time 2.88 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 214348 kb
Host smart-973e25cf-bfb6-4436-b7b9-6b37ed932b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587774315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3587774315
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2463408285
Short name T37
Test name
Test status
Simulation time 190846261 ps
CPU time 2.44 seconds
Started Jun 30 05:45:10 PM PDT 24
Finished Jun 30 05:45:13 PM PDT 24
Peak memory 221472 kb
Host smart-1615648c-1ffa-4ee6-a5a0-5f450439184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463408285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2463408285
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.33595297
Short name T761
Test name
Test status
Simulation time 215892826 ps
CPU time 2.43 seconds
Started Jun 30 05:44:54 PM PDT 24
Finished Jun 30 05:44:57 PM PDT 24
Peak memory 207228 kb
Host smart-9d1be0dd-ad4d-4f30-960f-76e119fc7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33595297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.33595297
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.440921863
Short name T542
Test name
Test status
Simulation time 324943611 ps
CPU time 3.07 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 214612 kb
Host smart-dd07b095-1e9a-4e1c-9e77-383fca8eeb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440921863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.440921863
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1834005979
Short name T3
Test name
Test status
Simulation time 52438205 ps
CPU time 1.59 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 214260 kb
Host smart-01bf4e9b-4ede-4397-925b-d4da7c5880f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834005979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1834005979
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1569691142
Short name T9
Test name
Test status
Simulation time 5377724813 ps
CPU time 15.46 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:15 PM PDT 24
Peak memory 209408 kb
Host smart-fadf800c-3795-4ebe-9182-8066fad4f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569691142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1569691142
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3353046263
Short name T247
Test name
Test status
Simulation time 1066922261 ps
CPU time 6.69 seconds
Started Jun 30 05:44:51 PM PDT 24
Finished Jun 30 05:44:59 PM PDT 24
Peak memory 222336 kb
Host smart-1f974029-7d62-4f29-bb98-ba7f405b3a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353046263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3353046263
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1228710352
Short name T612
Test name
Test status
Simulation time 1522008216 ps
CPU time 16.85 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:45:11 PM PDT 24
Peak memory 209092 kb
Host smart-eb75767b-f6b2-44a5-b9ff-b28d4a8814d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228710352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1228710352
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1179426864
Short name T639
Test name
Test status
Simulation time 122621834 ps
CPU time 4.09 seconds
Started Jun 30 05:44:52 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 206784 kb
Host smart-63565beb-79f5-40b2-8409-326db544323a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179426864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1179426864
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2575016462
Short name T327
Test name
Test status
Simulation time 226048111 ps
CPU time 7.46 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:45:09 PM PDT 24
Peak memory 208692 kb
Host smart-9370351f-c876-4072-ab46-d37a7b95b6bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575016462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2575016462
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.998460002
Short name T302
Test name
Test status
Simulation time 39440901 ps
CPU time 2.87 seconds
Started Jun 30 05:44:54 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 208916 kb
Host smart-93554d22-3e96-4431-ae8f-d87076bd2e53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998460002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.998460002
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4061665707
Short name T493
Test name
Test status
Simulation time 71099574 ps
CPU time 2.22 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:44:59 PM PDT 24
Peak memory 207752 kb
Host smart-37a377b4-80c4-4c1e-ad5f-ea4a08fab552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061665707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4061665707
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4151343882
Short name T604
Test name
Test status
Simulation time 386548268 ps
CPU time 3.3 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 206680 kb
Host smart-36aac5b9-3d6d-4958-89ec-c94f865d8400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151343882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4151343882
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.946632709
Short name T737
Test name
Test status
Simulation time 3334624243 ps
CPU time 5.99 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:06 PM PDT 24
Peak memory 207200 kb
Host smart-4b0332fe-cb1d-4bdf-9692-ca2e7c0c847a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946632709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.946632709
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2981109453
Short name T319
Test name
Test status
Simulation time 180807829 ps
CPU time 3.32 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 218432 kb
Host smart-04914c28-0de2-4bcd-9e24-2b87caf144ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981109453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2981109453
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2329954344
Short name T191
Test name
Test status
Simulation time 417926016 ps
CPU time 2.42 seconds
Started Jun 30 05:45:10 PM PDT 24
Finished Jun 30 05:45:13 PM PDT 24
Peak memory 210696 kb
Host smart-401adb6d-1a54-4ebc-b075-a6562d47b1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329954344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2329954344
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.990372941
Short name T630
Test name
Test status
Simulation time 12269228 ps
CPU time 0.71 seconds
Started Jun 30 05:45:09 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 206060 kb
Host smart-a80e7930-184c-4a52-92c4-0617309f1491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990372941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.990372941
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4125179014
Short name T401
Test name
Test status
Simulation time 227534677 ps
CPU time 4.34 seconds
Started Jun 30 05:45:09 PM PDT 24
Finished Jun 30 05:45:14 PM PDT 24
Peak memory 214332 kb
Host smart-40fd0661-bddb-42c1-8bcd-17c65da9763d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125179014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4125179014
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1575327286
Short name T33
Test name
Test status
Simulation time 122589804 ps
CPU time 3.03 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 221772 kb
Host smart-7adaec8c-ea65-492d-9b3c-a9d355425209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575327286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1575327286
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2352433219
Short name T690
Test name
Test status
Simulation time 36780208 ps
CPU time 1.98 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 209444 kb
Host smart-28d9545b-4cc7-40ff-b079-7c926b23c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352433219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2352433219
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1548014219
Short name T874
Test name
Test status
Simulation time 151330117 ps
CPU time 2.05 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 214284 kb
Host smart-e1f21faf-6f84-4731-8c75-fe866b9ce787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548014219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1548014219
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2236844330
Short name T807
Test name
Test status
Simulation time 31179076 ps
CPU time 2.29 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 217988 kb
Host smart-5f9a6dc3-9c20-488f-9efe-9902dd290152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236844330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2236844330
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1541869568
Short name T569
Test name
Test status
Simulation time 162828027 ps
CPU time 3.26 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 214428 kb
Host smart-1c98b6a8-7459-465e-9bc3-b7ed4b36fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541869568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1541869568
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1622431193
Short name T666
Test name
Test status
Simulation time 22807193 ps
CPU time 1.94 seconds
Started Jun 30 05:44:59 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 206956 kb
Host smart-426be571-af0e-4ae7-885d-8b30bc5a55e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622431193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1622431193
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2323348790
Short name T794
Test name
Test status
Simulation time 203195594 ps
CPU time 5.43 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:06 PM PDT 24
Peak memory 208380 kb
Host smart-01b77d74-ef23-42a8-82e9-5fe58ba98cad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323348790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2323348790
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2330109239
Short name T725
Test name
Test status
Simulation time 51947634 ps
CPU time 2.77 seconds
Started Jun 30 05:45:10 PM PDT 24
Finished Jun 30 05:45:13 PM PDT 24
Peak memory 207160 kb
Host smart-49a53550-1c68-45e0-baf8-443aa2b50dca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330109239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2330109239
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3382642096
Short name T881
Test name
Test status
Simulation time 8230319070 ps
CPU time 15.2 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:16 PM PDT 24
Peak memory 208000 kb
Host smart-02de2be4-5321-4652-8161-9760a2068b4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382642096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3382642096
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3392935647
Short name T834
Test name
Test status
Simulation time 104203694 ps
CPU time 2.13 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 208872 kb
Host smart-a3473bfd-df7d-4dec-b626-63701b2cd57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392935647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3392935647
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2107641002
Short name T476
Test name
Test status
Simulation time 1622764529 ps
CPU time 22.94 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 208528 kb
Host smart-e06d8e81-4bd4-423d-9c50-22e7c611d71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107641002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2107641002
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.758349932
Short name T203
Test name
Test status
Simulation time 40566193911 ps
CPU time 178.42 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:48:00 PM PDT 24
Peak memory 222580 kb
Host smart-3f0e48db-0b66-4af3-bc53-c7189d23e0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758349932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.758349932
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3457877657
Short name T162
Test name
Test status
Simulation time 792204633 ps
CPU time 10.89 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:09 PM PDT 24
Peak memory 222580 kb
Host smart-a1da2ec4-903b-4c35-aff7-a2a3ef4ff68e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457877657 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3457877657
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3902836338
Short name T406
Test name
Test status
Simulation time 101520155 ps
CPU time 4.23 seconds
Started Jun 30 05:45:09 PM PDT 24
Finished Jun 30 05:45:13 PM PDT 24
Peak memory 214428 kb
Host smart-0632cf0d-60a9-4432-83c8-409f05172398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902836338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3902836338
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3087604928
Short name T42
Test name
Test status
Simulation time 122282631 ps
CPU time 2.63 seconds
Started Jun 30 05:45:10 PM PDT 24
Finished Jun 30 05:45:13 PM PDT 24
Peak memory 210392 kb
Host smart-8c073340-6454-4f2b-88fe-83437f99f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087604928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3087604928
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.716469979
Short name T515
Test name
Test status
Simulation time 21962350 ps
CPU time 0.89 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 206064 kb
Host smart-182cc14d-86b3-4f57-9e09-cf9a6582d1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716469979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.716469979
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3259550824
Short name T324
Test name
Test status
Simulation time 942428983 ps
CPU time 54.11 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 215664 kb
Host smart-11b96bab-74ec-40e2-a5ee-1146371fb421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259550824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3259550824
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3186098453
Short name T831
Test name
Test status
Simulation time 259763454 ps
CPU time 4.63 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:06 PM PDT 24
Peak memory 210616 kb
Host smart-8bbb6c0d-4624-46ce-ba2d-9909967dc3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186098453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3186098453
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3891874067
Short name T91
Test name
Test status
Simulation time 406306277 ps
CPU time 2.28 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:02 PM PDT 24
Peak memory 214404 kb
Host smart-e55fe5f7-6664-4c69-b31c-15c96d55f324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891874067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3891874067
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.759590984
Short name T293
Test name
Test status
Simulation time 474538361 ps
CPU time 5.36 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 222356 kb
Host smart-b2bed3a7-8218-4697-8b0c-62895001b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759590984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.759590984
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1529639806
Short name T634
Test name
Test status
Simulation time 120765475 ps
CPU time 2.68 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 206688 kb
Host smart-6d4ff98a-433f-4a1d-bb32-caf3015d63d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529639806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1529639806
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2833541127
Short name T776
Test name
Test status
Simulation time 138731414 ps
CPU time 3.13 seconds
Started Jun 30 05:45:01 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 207492 kb
Host smart-0255eaba-1240-4796-99ca-b90fef66704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833541127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2833541127
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2943868682
Short name T245
Test name
Test status
Simulation time 2031113605 ps
CPU time 6.47 seconds
Started Jun 30 05:45:10 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 208832 kb
Host smart-33c884a4-b339-4a08-9051-a54c97c53fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943868682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2943868682
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2014801714
Short name T738
Test name
Test status
Simulation time 91388982 ps
CPU time 4.27 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 206964 kb
Host smart-af4baeb5-849f-4e1e-aac4-7460fd84d8ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014801714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2014801714
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2077958206
Short name T453
Test name
Test status
Simulation time 1129461230 ps
CPU time 32.19 seconds
Started Jun 30 05:44:57 PM PDT 24
Finished Jun 30 05:45:30 PM PDT 24
Peak memory 208360 kb
Host smart-507a9120-a257-465f-9286-ab714be3aff1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077958206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2077958206
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4032218019
Short name T867
Test name
Test status
Simulation time 111797504 ps
CPU time 4.61 seconds
Started Jun 30 05:45:00 PM PDT 24
Finished Jun 30 05:45:06 PM PDT 24
Peak memory 208588 kb
Host smart-8e20ff14-abeb-4319-836e-96d9a9060ab2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032218019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4032218019
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1063962201
Short name T487
Test name
Test status
Simulation time 70749690 ps
CPU time 2.74 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 208156 kb
Host smart-a9528abb-32a4-4326-afff-d8aea5d6917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063962201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1063962201
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.720321182
Short name T734
Test name
Test status
Simulation time 478070988 ps
CPU time 4.58 seconds
Started Jun 30 05:44:58 PM PDT 24
Finished Jun 30 05:45:03 PM PDT 24
Peak memory 208884 kb
Host smart-8478c53b-f8ac-433f-879b-4b8267cbf182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720321182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.720321182
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1182649903
Short name T182
Test name
Test status
Simulation time 268297201 ps
CPU time 9.62 seconds
Started Jun 30 05:45:03 PM PDT 24
Finished Jun 30 05:45:14 PM PDT 24
Peak memory 222552 kb
Host smart-745ddf0c-0287-4dc6-a6ac-9fa671406dc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182649903 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1182649903
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2637209996
Short name T494
Test name
Test status
Simulation time 611460760 ps
CPU time 4.67 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 214436 kb
Host smart-026113ec-cc07-42ab-b5df-1809617eaf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637209996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2637209996
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.4027276041
Short name T396
Test name
Test status
Simulation time 708516785 ps
CPU time 4.89 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:11 PM PDT 24
Peak memory 210808 kb
Host smart-e1e35619-9f27-4abf-9514-2279f45fccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027276041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.4027276041
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2227447543
Short name T546
Test name
Test status
Simulation time 18355941 ps
CPU time 0.75 seconds
Started Jun 30 05:45:03 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 206020 kb
Host smart-f47d2890-ae6d-43d7-a1fb-0edefe04e710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227447543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2227447543
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3958127156
Short name T269
Test name
Test status
Simulation time 132540773 ps
CPU time 7.97 seconds
Started Jun 30 05:45:03 PM PDT 24
Finished Jun 30 05:45:12 PM PDT 24
Peak memory 214864 kb
Host smart-6885f341-fe23-4acd-b1f2-f09654d446d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958127156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3958127156
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.992334693
Short name T45
Test name
Test status
Simulation time 73791848 ps
CPU time 2.84 seconds
Started Jun 30 05:45:07 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 209404 kb
Host smart-1e6e89d8-41ef-450d-9180-f9de1bb4b4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992334693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.992334693
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2425060688
Short name T239
Test name
Test status
Simulation time 29838080 ps
CPU time 2.28 seconds
Started Jun 30 05:45:04 PM PDT 24
Finished Jun 30 05:45:07 PM PDT 24
Peak memory 214352 kb
Host smart-77e6ae0a-08d7-4d60-9f38-d9599ebd27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425060688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2425060688
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.849598913
Short name T344
Test name
Test status
Simulation time 170274991 ps
CPU time 4.6 seconds
Started Jun 30 05:45:02 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 222340 kb
Host smart-8deb5bbd-1071-4ff3-9e45-7323b03783af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849598913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.849598913
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2367795626
Short name T66
Test name
Test status
Simulation time 198791298 ps
CPU time 5.42 seconds
Started Jun 30 05:45:06 PM PDT 24
Finished Jun 30 05:45:12 PM PDT 24
Peak memory 210324 kb
Host smart-baf66e8d-9fe8-4357-9884-af767eefe07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367795626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2367795626
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4076749836
Short name T844
Test name
Test status
Simulation time 5314980195 ps
CPU time 35.39 seconds
Started Jun 30 05:45:07 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 218728 kb
Host smart-82026d4d-0193-467f-8708-61d28b8fc6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076749836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4076749836
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.271168642
Short name T910
Test name
Test status
Simulation time 454483640 ps
CPU time 2.98 seconds
Started Jun 30 05:45:06 PM PDT 24
Finished Jun 30 05:45:09 PM PDT 24
Peak memory 206960 kb
Host smart-4882c66d-9801-4fbc-b2ca-00dc81038737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271168642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.271168642
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1233842476
Short name T110
Test name
Test status
Simulation time 205399700 ps
CPU time 2.87 seconds
Started Jun 30 05:45:03 PM PDT 24
Finished Jun 30 05:45:06 PM PDT 24
Peak memory 209052 kb
Host smart-250f799c-471b-4e1e-b529-3f7b996a3279
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233842476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1233842476
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2815635053
Short name T251
Test name
Test status
Simulation time 131552876 ps
CPU time 3.81 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 208732 kb
Host smart-3027968c-2931-477c-9abd-11c6afb13083
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815635053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2815635053
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1054368285
Short name T502
Test name
Test status
Simulation time 347322322 ps
CPU time 5.14 seconds
Started Jun 30 05:45:07 PM PDT 24
Finished Jun 30 05:45:12 PM PDT 24
Peak memory 208784 kb
Host smart-dfb00cb2-0d3d-494f-9e60-7bbcfa5ec1a3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054368285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1054368285
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.4146086387
Short name T765
Test name
Test status
Simulation time 490424053 ps
CPU time 3.66 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 207860 kb
Host smart-17b4e48f-9853-4081-8162-e1d35f0b0319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146086387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.4146086387
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1257223770
Short name T411
Test name
Test status
Simulation time 1610691124 ps
CPU time 18.22 seconds
Started Jun 30 05:45:04 PM PDT 24
Finished Jun 30 05:45:24 PM PDT 24
Peak memory 208648 kb
Host smart-b2813be8-56a5-40a5-b847-924200379100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257223770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1257223770
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1492182528
Short name T851
Test name
Test status
Simulation time 17031403864 ps
CPU time 62.34 seconds
Started Jun 30 05:45:06 PM PDT 24
Finished Jun 30 05:46:09 PM PDT 24
Peak memory 222468 kb
Host smart-74335f90-9830-4b0c-8db2-ea5604033302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492182528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1492182528
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4218686237
Short name T909
Test name
Test status
Simulation time 2124052491 ps
CPU time 33.99 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 208684 kb
Host smart-f7fe06e0-c4d4-4b3f-9802-ae71aedea6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218686237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4218686237
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3399118726
Short name T193
Test name
Test status
Simulation time 142178614 ps
CPU time 1.58 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 209988 kb
Host smart-54af43c9-4bec-4ca3-be40-b18563d79668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399118726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3399118726
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3361160823
Short name T440
Test name
Test status
Simulation time 42490058 ps
CPU time 0.74 seconds
Started Jun 30 05:45:14 PM PDT 24
Finished Jun 30 05:45:15 PM PDT 24
Peak memory 206052 kb
Host smart-15b48897-edeb-4b6a-938f-df9c3c1c5352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361160823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3361160823
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2437126468
Short name T419
Test name
Test status
Simulation time 29715726 ps
CPU time 2.46 seconds
Started Jun 30 05:45:13 PM PDT 24
Finished Jun 30 05:45:16 PM PDT 24
Peak memory 214696 kb
Host smart-cffea586-c44e-4a2b-a443-58f6908fdc0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437126468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2437126468
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.594683800
Short name T21
Test name
Test status
Simulation time 53096212 ps
CPU time 1.26 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 214804 kb
Host smart-2bdec516-0967-4bef-b964-06d0d1f0434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594683800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.594683800
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2700175671
Short name T72
Test name
Test status
Simulation time 29412219 ps
CPU time 2.32 seconds
Started Jun 30 05:45:12 PM PDT 24
Finished Jun 30 05:45:14 PM PDT 24
Peak memory 214300 kb
Host smart-50de0c53-a022-40a6-8af0-faa335328960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700175671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2700175671
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2406517108
Short name T317
Test name
Test status
Simulation time 84481249 ps
CPU time 2 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 214288 kb
Host smart-532b1c0a-6b6e-49a4-ac11-fa18f4517bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406517108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2406517108
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.18279044
Short name T59
Test name
Test status
Simulation time 125302331 ps
CPU time 4.88 seconds
Started Jun 30 05:45:13 PM PDT 24
Finished Jun 30 05:45:19 PM PDT 24
Peak memory 220944 kb
Host smart-dd12f642-7a24-4b07-9309-de17d542fd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18279044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.18279044
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.390501083
Short name T519
Test name
Test status
Simulation time 219995735 ps
CPU time 3.25 seconds
Started Jun 30 05:45:14 PM PDT 24
Finished Jun 30 05:45:18 PM PDT 24
Peak memory 209304 kb
Host smart-f11d333d-6430-46dd-98f9-cd9b1791bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390501083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.390501083
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2261091428
Short name T224
Test name
Test status
Simulation time 116893713 ps
CPU time 2.9 seconds
Started Jun 30 05:45:11 PM PDT 24
Finished Jun 30 05:45:14 PM PDT 24
Peak memory 207316 kb
Host smart-258aab36-81a0-4e66-893a-d1895d326b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261091428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2261091428
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.896486675
Short name T797
Test name
Test status
Simulation time 261067255 ps
CPU time 2.37 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 206920 kb
Host smart-aa9d143b-7adb-4595-8bf4-40bdb09ce5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896486675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.896486675
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2277801978
Short name T814
Test name
Test status
Simulation time 95032433 ps
CPU time 3.71 seconds
Started Jun 30 05:45:05 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 206932 kb
Host smart-fd4a0a4e-0ff1-413d-828f-82bde158438a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277801978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2277801978
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3562609672
Short name T565
Test name
Test status
Simulation time 249194893 ps
CPU time 3.23 seconds
Started Jun 30 05:45:06 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 208708 kb
Host smart-2d796c1c-5ea0-4e9d-9027-12fad279982b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562609672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3562609672
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1254379071
Short name T697
Test name
Test status
Simulation time 226132664 ps
CPU time 4.23 seconds
Started Jun 30 05:45:03 PM PDT 24
Finished Jun 30 05:45:08 PM PDT 24
Peak memory 208728 kb
Host smart-37ad24de-823d-4c2c-a41d-0a9332f3d440
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254379071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1254379071
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.687941031
Short name T262
Test name
Test status
Simulation time 73245446 ps
CPU time 2.31 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:18 PM PDT 24
Peak memory 209708 kb
Host smart-75f1de00-b32c-4c2f-8478-caef6e0c501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687941031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.687941031
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.257190527
Short name T38
Test name
Test status
Simulation time 751990789 ps
CPU time 2.82 seconds
Started Jun 30 05:45:07 PM PDT 24
Finished Jun 30 05:45:10 PM PDT 24
Peak memory 207196 kb
Host smart-135bdfbd-1f3a-4478-a6ea-f1e5b1baef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257190527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.257190527
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2921336970
Short name T218
Test name
Test status
Simulation time 1703485539 ps
CPU time 18.82 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:34 PM PDT 24
Peak memory 222584 kb
Host smart-94753589-33ba-4d51-a430-3444c0dff9dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921336970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2921336970
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1772166115
Short name T701
Test name
Test status
Simulation time 166883296 ps
CPU time 2.28 seconds
Started Jun 30 05:45:12 PM PDT 24
Finished Jun 30 05:45:15 PM PDT 24
Peak memory 210088 kb
Host smart-7140d484-f99a-4307-81b5-d46088d2d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772166115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1772166115
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1421175540
Short name T510
Test name
Test status
Simulation time 69544260 ps
CPU time 1.01 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 206120 kb
Host smart-83933d56-722b-4935-8c38-2173256be610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421175540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1421175540
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.403714914
Short name T145
Test name
Test status
Simulation time 53572249 ps
CPU time 3.68 seconds
Started Jun 30 05:45:17 PM PDT 24
Finished Jun 30 05:45:21 PM PDT 24
Peak memory 214332 kb
Host smart-bdda30a7-dec8-4704-a095-ea2735517047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403714914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.403714914
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3137180357
Short name T590
Test name
Test status
Simulation time 89958628 ps
CPU time 2.69 seconds
Started Jun 30 05:45:13 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 216972 kb
Host smart-83075ae0-7e53-4b1e-89b5-e2b33a2209a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137180357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3137180357
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.668503584
Short name T880
Test name
Test status
Simulation time 348549341 ps
CPU time 2.75 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:18 PM PDT 24
Peak memory 218260 kb
Host smart-4f490e05-8efa-4074-bd2d-6a57004d1e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668503584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.668503584
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.290664830
Short name T101
Test name
Test status
Simulation time 293941901 ps
CPU time 10.1 seconds
Started Jun 30 05:45:17 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 220872 kb
Host smart-015fc698-ac40-44c3-9019-8b3cdcf7f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290664830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.290664830
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3174615589
Short name T234
Test name
Test status
Simulation time 1207098117 ps
CPU time 6 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:21 PM PDT 24
Peak memory 214264 kb
Host smart-6e486e6c-3ee3-458d-9409-62ea18fe9a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174615589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3174615589
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.345391715
Short name T272
Test name
Test status
Simulation time 113801541 ps
CPU time 4.54 seconds
Started Jun 30 05:45:12 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 209800 kb
Host smart-bedcc000-cfd4-419e-b0b6-082f89b38909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345391715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.345391715
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2107761357
Short name T833
Test name
Test status
Simulation time 118520693 ps
CPU time 5.47 seconds
Started Jun 30 05:45:13 PM PDT 24
Finished Jun 30 05:45:19 PM PDT 24
Peak memory 209076 kb
Host smart-a2628077-80a7-4f49-a1cf-550d3226c4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107761357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2107761357
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.541132106
Short name T865
Test name
Test status
Simulation time 101786697 ps
CPU time 4.26 seconds
Started Jun 30 05:45:14 PM PDT 24
Finished Jun 30 05:45:19 PM PDT 24
Peak memory 207836 kb
Host smart-4e030e5c-79d0-4626-ba4e-5a9b42ba7eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541132106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.541132106
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2135331842
Short name T369
Test name
Test status
Simulation time 137772595 ps
CPU time 5.5 seconds
Started Jun 30 05:45:15 PM PDT 24
Finished Jun 30 05:45:21 PM PDT 24
Peak memory 208744 kb
Host smart-12083b17-642b-4878-90c3-1ce6c0d2297a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135331842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2135331842
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3737154952
Short name T267
Test name
Test status
Simulation time 768037104 ps
CPU time 8.25 seconds
Started Jun 30 05:45:14 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 209024 kb
Host smart-093d0a61-21b0-4e84-b25f-9a64ac8c85c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737154952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3737154952
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1532413602
Short name T514
Test name
Test status
Simulation time 35618957 ps
CPU time 2.33 seconds
Started Jun 30 05:45:12 PM PDT 24
Finished Jun 30 05:45:15 PM PDT 24
Peak memory 206980 kb
Host smart-9e25f7fb-cbaa-46ca-b479-5b9e34f9ba2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532413602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1532413602
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2979710357
Short name T673
Test name
Test status
Simulation time 4309210243 ps
CPU time 8.16 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 218660 kb
Host smart-5fb05726-bfd3-4b95-97c1-400b4ba1c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979710357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2979710357
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3227733483
Short name T717
Test name
Test status
Simulation time 576866414 ps
CPU time 3.42 seconds
Started Jun 30 05:45:12 PM PDT 24
Finished Jun 30 05:45:16 PM PDT 24
Peak memory 208692 kb
Host smart-c79ad8c8-d5f3-4f87-b262-2ba74d4ce266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227733483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3227733483
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2824366468
Short name T253
Test name
Test status
Simulation time 3234392956 ps
CPU time 21.07 seconds
Started Jun 30 05:45:17 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 215164 kb
Host smart-65f0d0fb-c9a3-4463-841a-3df72b523248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824366468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2824366468
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3047166842
Short name T821
Test name
Test status
Simulation time 2039037404 ps
CPU time 20.28 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 222528 kb
Host smart-b454a9f2-8e64-4629-b65e-d05b32ec1b11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047166842 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3047166842
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.230564294
Short name T539
Test name
Test status
Simulation time 54886110 ps
CPU time 3.51 seconds
Started Jun 30 05:45:13 PM PDT 24
Finished Jun 30 05:45:17 PM PDT 24
Peak memory 219436 kb
Host smart-e1717bd3-5010-4fdb-8ce1-59333f887953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230564294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.230564294
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.504099153
Short name T102
Test name
Test status
Simulation time 21297152 ps
CPU time 0.8 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:22 PM PDT 24
Peak memory 206036 kb
Host smart-4b8c1e61-7dc5-4bef-8920-907a47664b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504099153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.504099153
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1204015439
Short name T44
Test name
Test status
Simulation time 448436768 ps
CPU time 2.62 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 209196 kb
Host smart-c924edfc-17c4-4732-b38a-e722fd0d5415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204015439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1204015439
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4287824816
Short name T864
Test name
Test status
Simulation time 229013436 ps
CPU time 3.33 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 218260 kb
Host smart-f9d709d0-2563-473c-91cb-bb416d84684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287824816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4287824816
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4235582571
Short name T885
Test name
Test status
Simulation time 162605413 ps
CPU time 2.99 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 214588 kb
Host smart-c05fb9d9-0231-4fd7-9260-dab4008467b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235582571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4235582571
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1381660417
Short name T846
Test name
Test status
Simulation time 110548606 ps
CPU time 4.45 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:28 PM PDT 24
Peak memory 221028 kb
Host smart-4ab68d04-5281-4382-ba6d-7763b14f48ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381660417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1381660417
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.3415284276
Short name T603
Test name
Test status
Simulation time 112415323 ps
CPU time 3.1 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 208192 kb
Host smart-29adcb43-b20e-44b8-a742-52822b7b587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415284276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3415284276
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3361188131
Short name T729
Test name
Test status
Simulation time 42717167 ps
CPU time 2.35 seconds
Started Jun 30 05:45:24 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 207960 kb
Host smart-0f8bf0c1-2772-48b1-a65b-4b08eadb232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361188131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3361188131
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4117001667
Short name T832
Test name
Test status
Simulation time 118926400 ps
CPU time 3.98 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 206920 kb
Host smart-62fde155-e62d-4b5e-a423-3761bf1de133
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117001667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4117001667
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2062424647
Short name T524
Test name
Test status
Simulation time 225312318 ps
CPU time 3.04 seconds
Started Jun 30 05:45:19 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 208736 kb
Host smart-7baa95cc-4cb8-4a85-acb6-2bfe869cddbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062424647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2062424647
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.531139656
Short name T855
Test name
Test status
Simulation time 73851607 ps
CPU time 2.28 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 218356 kb
Host smart-b62edc11-e66c-4f0b-a8cf-c5763aa0ab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531139656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.531139656
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4227907767
Short name T437
Test name
Test status
Simulation time 1008886739 ps
CPU time 22.05 seconds
Started Jun 30 05:45:18 PM PDT 24
Finished Jun 30 05:45:41 PM PDT 24
Peak memory 208328 kb
Host smart-ef230db3-d311-499e-848d-c83504dda40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227907767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4227907767
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3620509179
Short name T901
Test name
Test status
Simulation time 1282922528 ps
CPU time 14.25 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 222424 kb
Host smart-2a9165c7-6d9d-401b-9bc0-d4c1c9dba80a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620509179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3620509179
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.4060522130
Short name T861
Test name
Test status
Simulation time 619424000 ps
CPU time 12.21 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 220272 kb
Host smart-731e4964-4599-489b-bc0e-dfe41af9b0c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060522130 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.4060522130
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3259864473
Short name T450
Test name
Test status
Simulation time 1001672391 ps
CPU time 6.85 seconds
Started Jun 30 05:45:18 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 208852 kb
Host smart-a7904fdb-a1c7-4ec0-8fdc-34721ab6f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259864473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3259864473
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2932076691
Short name T720
Test name
Test status
Simulation time 210450811 ps
CPU time 2.33 seconds
Started Jun 30 05:45:19 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 209724 kb
Host smart-0c390057-14d0-4a6a-a1af-1dbe5fce6b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932076691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2932076691
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1897429605
Short name T454
Test name
Test status
Simulation time 17872335 ps
CPU time 0.93 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 206072 kb
Host smart-ca82c093-de7d-4e29-848e-ff36dcdb5e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897429605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1897429605
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1640604765
Short name T430
Test name
Test status
Simulation time 218488749 ps
CPU time 12.32 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 215916 kb
Host smart-5010c987-4d76-4c4b-a68e-985544022be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640604765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1640604765
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3634595458
Short name T645
Test name
Test status
Simulation time 145058220 ps
CPU time 4.79 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 218404 kb
Host smart-e5e8775e-17bd-4c94-93dc-0f60d1c98943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634595458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3634595458
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2550711728
Short name T266
Test name
Test status
Simulation time 596236640 ps
CPU time 6.51 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:29 PM PDT 24
Peak memory 207620 kb
Host smart-e2774be1-f3df-409b-9b18-115bb21c8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550711728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2550711728
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2231949356
Short name T646
Test name
Test status
Simulation time 40613690 ps
CPU time 2.19 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 214500 kb
Host smart-5de1244b-eed3-471f-a376-2fe8ebc8c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231949356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2231949356
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2387386063
Short name T618
Test name
Test status
Simulation time 71870577 ps
CPU time 2.64 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:24 PM PDT 24
Peak memory 214264 kb
Host smart-586bd79c-72b3-453c-ac6a-c58c5dad0da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387386063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2387386063
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2095234578
Short name T870
Test name
Test status
Simulation time 131157237 ps
CPU time 2.45 seconds
Started Jun 30 05:45:23 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 214300 kb
Host smart-45fd5ff1-d24e-4faf-ad98-9443be6e30b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095234578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2095234578
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.502935178
Short name T329
Test name
Test status
Simulation time 255673534 ps
CPU time 3.4 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 207460 kb
Host smart-8dd2dfda-f13d-484d-a8b4-5a492a239299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502935178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.502935178
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.523860593
Short name T561
Test name
Test status
Simulation time 54608065 ps
CPU time 2.64 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 208324 kb
Host smart-b10b02c6-1224-474e-b47e-b1c046ecc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523860593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.523860593
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.9155314
Short name T241
Test name
Test status
Simulation time 63899950 ps
CPU time 3.39 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:24 PM PDT 24
Peak memory 208528 kb
Host smart-7559b617-3c7a-40ff-ae30-a3ba505afc81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9155314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.9155314
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.185582598
Short name T598
Test name
Test status
Simulation time 276569586 ps
CPU time 10.65 seconds
Started Jun 30 05:45:19 PM PDT 24
Finished Jun 30 05:45:30 PM PDT 24
Peak memory 208848 kb
Host smart-73e8384d-35df-4b4b-8e8f-6563c1433027
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185582598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.185582598
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3536164153
Short name T484
Test name
Test status
Simulation time 490156352 ps
CPU time 4.09 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 208436 kb
Host smart-76a2ebb4-99cb-4a4c-a8de-2c4fde3a93c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536164153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3536164153
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3291892855
Short name T900
Test name
Test status
Simulation time 25407139 ps
CPU time 1.97 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 218492 kb
Host smart-c05e797e-8067-4f8e-9ab5-af55b061cfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291892855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3291892855
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3277362662
Short name T721
Test name
Test status
Simulation time 1000033628 ps
CPU time 23.03 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 208072 kb
Host smart-e84b5c8d-c734-4c50-bd9e-b0031e9b5c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277362662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3277362662
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3770906274
Short name T456
Test name
Test status
Simulation time 238764471 ps
CPU time 2.99 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 208508 kb
Host smart-2fc3adb2-6360-48b5-a740-ffc4c386f36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770906274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3770906274
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2276027384
Short name T907
Test name
Test status
Simulation time 189905402 ps
CPU time 5.72 seconds
Started Jun 30 05:45:23 PM PDT 24
Finished Jun 30 05:45:30 PM PDT 24
Peak memory 207424 kb
Host smart-884b8fb3-8ba2-464b-95ee-5437287c4088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276027384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2276027384
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2284415034
Short name T566
Test name
Test status
Simulation time 182972850 ps
CPU time 2.35 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 209836 kb
Host smart-d1e9f3b3-3cd6-45bc-af40-b14ffcf6c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284415034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2284415034
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3090470507
Short name T532
Test name
Test status
Simulation time 22139375 ps
CPU time 0.73 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:51 PM PDT 24
Peak memory 206048 kb
Host smart-78728e20-437d-45f6-9fc4-f6147c9dfc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090470507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3090470507
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2349551297
Short name T73
Test name
Test status
Simulation time 980745971 ps
CPU time 25.22 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:44:18 PM PDT 24
Peak memory 214716 kb
Host smart-c12dff82-340d-4a23-9dfa-eab2b61dffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349551297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2349551297
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2435429973
Short name T460
Test name
Test status
Simulation time 45280160 ps
CPU time 2.48 seconds
Started Jun 30 05:43:49 PM PDT 24
Finished Jun 30 05:43:52 PM PDT 24
Peak memory 207448 kb
Host smart-f1a1b8b6-2f62-4a79-81cd-830d92055b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435429973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2435429973
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3611885945
Short name T621
Test name
Test status
Simulation time 298043048 ps
CPU time 2.67 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 214348 kb
Host smart-356698c3-7b2c-4abf-bed5-0dd1c826a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611885945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3611885945
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2761141415
Short name T825
Test name
Test status
Simulation time 105196822 ps
CPU time 2.08 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:53 PM PDT 24
Peak memory 214260 kb
Host smart-431e91c7-3c1b-45c0-b091-c67a796df9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761141415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2761141415
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1195152980
Short name T836
Test name
Test status
Simulation time 143519023 ps
CPU time 2.8 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:56 PM PDT 24
Peak memory 214348 kb
Host smart-7823341c-7b7f-4ad2-b128-a247c3b54809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195152980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1195152980
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2558515647
Short name T535
Test name
Test status
Simulation time 666257143 ps
CPU time 3.32 seconds
Started Jun 30 05:43:48 PM PDT 24
Finished Jun 30 05:43:52 PM PDT 24
Peak memory 207688 kb
Host smart-d5b81808-a3b8-4b6b-bf15-0a32388b2793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558515647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2558515647
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2205095426
Short name T139
Test name
Test status
Simulation time 191254449 ps
CPU time 6.37 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:59 PM PDT 24
Peak memory 206888 kb
Host smart-e067ddc9-d9f4-4b7a-a278-7e532d022374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205095426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2205095426
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.689985568
Short name T521
Test name
Test status
Simulation time 394565116 ps
CPU time 3.71 seconds
Started Jun 30 05:43:52 PM PDT 24
Finished Jun 30 05:43:57 PM PDT 24
Peak memory 208832 kb
Host smart-e764a051-aa03-428f-a5a0-86b90fc4dd0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689985568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.689985568
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2126200452
Short name T755
Test name
Test status
Simulation time 36509089 ps
CPU time 2.65 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 208924 kb
Host smart-57db6460-b873-4ef0-be93-129f693aa648
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126200452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2126200452
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3511492538
Short name T459
Test name
Test status
Simulation time 57646739 ps
CPU time 2.6 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 208124 kb
Host smart-50848d90-65f5-4163-bea1-34fc433580fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511492538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3511492538
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1886428768
Short name T381
Test name
Test status
Simulation time 100827385 ps
CPU time 2.58 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 209144 kb
Host smart-3528eb3f-0b33-436c-a342-fe052141cca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886428768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1886428768
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.821579519
Short name T482
Test name
Test status
Simulation time 236607835 ps
CPU time 2.75 seconds
Started Jun 30 05:43:48 PM PDT 24
Finished Jun 30 05:43:52 PM PDT 24
Peak memory 208748 kb
Host smart-a0db80aa-5467-4c02-b802-8961ce7bb32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821579519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.821579519
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2790755753
Short name T367
Test name
Test status
Simulation time 522789919 ps
CPU time 6.46 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:59 PM PDT 24
Peak memory 215828 kb
Host smart-cfe6aa6a-3f33-4d7c-a447-44cc9145c494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790755753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2790755753
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3397792861
Short name T783
Test name
Test status
Simulation time 870968821 ps
CPU time 6.92 seconds
Started Jun 30 05:43:52 PM PDT 24
Finished Jun 30 05:44:00 PM PDT 24
Peak memory 208568 kb
Host smart-b3afb93f-fa2e-4271-aaaf-60ab2d953d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397792861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3397792861
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2427922135
Short name T828
Test name
Test status
Simulation time 46218949 ps
CPU time 1.9 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:54 PM PDT 24
Peak memory 210068 kb
Host smart-88087281-9029-4c89-9916-f52e65f58862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427922135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2427922135
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2874678905
Short name T845
Test name
Test status
Simulation time 51763263 ps
CPU time 0.7 seconds
Started Jun 30 05:45:38 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 206052 kb
Host smart-39777636-228f-4a60-8a47-712ab4d9d325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874678905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2874678905
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2983230146
Short name T347
Test name
Test status
Simulation time 46292625 ps
CPU time 3.18 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 215148 kb
Host smart-16bd8524-44ad-48f4-9388-c7c2bc7df646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983230146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2983230146
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2384755779
Short name T523
Test name
Test status
Simulation time 63182574 ps
CPU time 1.28 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 209452 kb
Host smart-2a90da4c-2a3d-4829-89c1-d777bda5331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384755779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2384755779
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1128412817
Short name T724
Test name
Test status
Simulation time 1479929320 ps
CPU time 40.9 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:46:04 PM PDT 24
Peak memory 209520 kb
Host smart-016f3f46-9995-4317-84e7-e7e1ee95a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128412817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1128412817
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3621343542
Short name T380
Test name
Test status
Simulation time 344367247 ps
CPU time 2.95 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 214328 kb
Host smart-d3296b12-2bc6-4bc3-8e3c-3f1ede1c0546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621343542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3621343542
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.799469312
Short name T894
Test name
Test status
Simulation time 71339406 ps
CPU time 2.94 seconds
Started Jun 30 05:45:30 PM PDT 24
Finished Jun 30 05:45:34 PM PDT 24
Peak memory 222656 kb
Host smart-2775d18b-88a6-43bc-82c7-f42dea6bd277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799469312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.799469312
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2163085067
Short name T751
Test name
Test status
Simulation time 131273673 ps
CPU time 2.07 seconds
Started Jun 30 05:45:18 PM PDT 24
Finished Jun 30 05:45:21 PM PDT 24
Peak memory 207756 kb
Host smart-ff775cd6-0d2a-4b85-9d31-1ed422decb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163085067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2163085067
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1648854953
Short name T473
Test name
Test status
Simulation time 288633768 ps
CPU time 6.48 seconds
Started Jun 30 05:45:18 PM PDT 24
Finished Jun 30 05:45:26 PM PDT 24
Peak memory 208588 kb
Host smart-44c059a7-f2fe-4494-b84e-b8e4385df161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648854953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1648854953
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2763705345
Short name T589
Test name
Test status
Simulation time 87158185 ps
CPU time 3.01 seconds
Started Jun 30 05:45:18 PM PDT 24
Finished Jun 30 05:45:21 PM PDT 24
Peak memory 206768 kb
Host smart-05264a8a-5e10-4ca3-9f90-1b86f890abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763705345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2763705345
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3639598023
Short name T731
Test name
Test status
Simulation time 111693024 ps
CPU time 3.7 seconds
Started Jun 30 05:45:22 PM PDT 24
Finished Jun 30 05:45:28 PM PDT 24
Peak memory 208812 kb
Host smart-966f9c94-d8fe-41fd-bc06-b72def1f800d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639598023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3639598023
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3514678550
Short name T835
Test name
Test status
Simulation time 28842032 ps
CPU time 1.96 seconds
Started Jun 30 05:45:21 PM PDT 24
Finished Jun 30 05:45:25 PM PDT 24
Peak memory 207484 kb
Host smart-b87717be-8252-4156-b541-a4d81d7cddc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514678550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3514678550
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.367843636
Short name T301
Test name
Test status
Simulation time 35460222 ps
CPU time 2.51 seconds
Started Jun 30 05:45:23 PM PDT 24
Finished Jun 30 05:45:27 PM PDT 24
Peak memory 208572 kb
Host smart-b5638447-9421-423a-931f-33f1ea3ec834
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367843636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.367843636
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3871276882
Short name T507
Test name
Test status
Simulation time 142533099 ps
CPU time 2.27 seconds
Started Jun 30 05:45:27 PM PDT 24
Finished Jun 30 05:45:30 PM PDT 24
Peak memory 209112 kb
Host smart-fcb0757c-90d4-44e7-8fd8-4bfd72bedd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871276882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3871276882
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3483883138
Short name T741
Test name
Test status
Simulation time 35241732 ps
CPU time 2.4 seconds
Started Jun 30 05:45:20 PM PDT 24
Finished Jun 30 05:45:23 PM PDT 24
Peak memory 208628 kb
Host smart-19cb1a1d-2f5d-4e56-bcf3-ce73f42ca069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483883138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3483883138
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3842636445
Short name T246
Test name
Test status
Simulation time 1050933712 ps
CPU time 32.27 seconds
Started Jun 30 05:45:25 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 208492 kb
Host smart-0955193f-403f-4959-be7a-97c3c1afc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842636445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3842636445
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.770273033
Short name T40
Test name
Test status
Simulation time 131397012 ps
CPU time 2.39 seconds
Started Jun 30 05:45:25 PM PDT 24
Finished Jun 30 05:45:28 PM PDT 24
Peak memory 210044 kb
Host smart-25d00f6b-541c-4581-bb20-07a1195994be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770273033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.770273033
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.779466476
Short name T114
Test name
Test status
Simulation time 14390698 ps
CPU time 0.77 seconds
Started Jun 30 05:45:26 PM PDT 24
Finished Jun 30 05:45:28 PM PDT 24
Peak memory 206004 kb
Host smart-ceca6ceb-164f-4c37-9ce6-cddc73e66103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779466476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.779466476
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.204948544
Short name T22
Test name
Test status
Simulation time 51897142 ps
CPU time 1.38 seconds
Started Jun 30 05:45:30 PM PDT 24
Finished Jun 30 05:45:33 PM PDT 24
Peak memory 216084 kb
Host smart-758de95a-2408-4d2f-b558-0b34392f5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204948544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.204948544
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1535029779
Short name T308
Test name
Test status
Simulation time 163452481 ps
CPU time 3.14 seconds
Started Jun 30 05:45:27 PM PDT 24
Finished Jun 30 05:45:30 PM PDT 24
Peak memory 214376 kb
Host smart-5ea61a70-322d-4bfd-a9dd-05e1d662f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535029779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1535029779
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2903910004
Short name T619
Test name
Test status
Simulation time 154818702 ps
CPU time 3.27 seconds
Started Jun 30 05:45:27 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 222376 kb
Host smart-bf6fb069-f890-4229-9f12-8771c57e898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903910004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2903910004
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.4223066331
Short name T472
Test name
Test status
Simulation time 61535718 ps
CPU time 3.35 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 207728 kb
Host smart-aeec3988-f7c5-43a0-85ad-05ad5fe44c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223066331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.4223066331
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.430581111
Short name T198
Test name
Test status
Simulation time 1041974044 ps
CPU time 8.7 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:37 PM PDT 24
Peak memory 218352 kb
Host smart-377e05c2-1bd1-408c-b1c4-3bbadfbc5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430581111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.430581111
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1614640586
Short name T810
Test name
Test status
Simulation time 332322186 ps
CPU time 3.55 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 208352 kb
Host smart-45537199-7992-4a10-98cf-73a72a28db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614640586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1614640586
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3409843567
Short name T782
Test name
Test status
Simulation time 106811423 ps
CPU time 3.19 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 208976 kb
Host smart-331e443c-f2a3-4e5a-b21b-4dd9ed5a1c18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409843567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3409843567
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3176654842
Short name T559
Test name
Test status
Simulation time 217780324 ps
CPU time 3.68 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 206812 kb
Host smart-77e171a0-d0f2-4bf1-82bb-07efe54cc8c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176654842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3176654842
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1021634827
Short name T820
Test name
Test status
Simulation time 81737517 ps
CPU time 2.44 seconds
Started Jun 30 05:45:26 PM PDT 24
Finished Jun 30 05:45:29 PM PDT 24
Peak memory 206880 kb
Host smart-c41fbd26-88c9-48ff-8dad-5b885b7ccf37
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021634827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1021634827
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2869096771
Short name T531
Test name
Test status
Simulation time 488848767 ps
CPU time 5.69 seconds
Started Jun 30 05:45:30 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 208240 kb
Host smart-ecdc7c66-d343-4918-a0be-8622bbd93d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869096771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2869096771
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1342502600
Short name T187
Test name
Test status
Simulation time 70254424 ps
CPU time 2.76 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 208520 kb
Host smart-7d054c9c-428f-4cd3-9e73-d30d8a8df066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342502600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1342502600
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1510796344
Short name T375
Test name
Test status
Simulation time 1001536202 ps
CPU time 13.21 seconds
Started Jun 30 05:45:31 PM PDT 24
Finished Jun 30 05:45:45 PM PDT 24
Peak memory 214616 kb
Host smart-e9474416-cbff-4803-8c45-df71dd0c1c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510796344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1510796344
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.955007281
Short name T781
Test name
Test status
Simulation time 214544514 ps
CPU time 4.08 seconds
Started Jun 30 05:45:26 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 214328 kb
Host smart-f76f06f1-160d-486b-a510-94db58b94f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955007281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.955007281
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1891147592
Short name T391
Test name
Test status
Simulation time 402202427 ps
CPU time 7.43 seconds
Started Jun 30 05:45:27 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 211068 kb
Host smart-d3173a58-512f-4c38-8e12-a3e9997196cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891147592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1891147592
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2078574464
Short name T585
Test name
Test status
Simulation time 59384918 ps
CPU time 0.77 seconds
Started Jun 30 05:45:30 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 206064 kb
Host smart-29e87bd5-273a-4b99-b591-a419bfc3df16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078574464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2078574464
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.364000923
Short name T222
Test name
Test status
Simulation time 85348795 ps
CPU time 3.14 seconds
Started Jun 30 05:45:26 PM PDT 24
Finished Jun 30 05:45:29 PM PDT 24
Peak memory 214428 kb
Host smart-dec9e839-5090-4e68-80f0-6954a40b191b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364000923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.364000923
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3116287580
Short name T32
Test name
Test status
Simulation time 1642500223 ps
CPU time 4.32 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:37 PM PDT 24
Peak memory 214776 kb
Host smart-3efd782d-40a7-48be-94da-bf6df3df174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116287580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3116287580
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1764074461
Short name T713
Test name
Test status
Simulation time 223181171 ps
CPU time 4.68 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:34 PM PDT 24
Peak memory 214412 kb
Host smart-1272659e-712f-4a24-bbf3-2740569d92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764074461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1764074461
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3887162129
Short name T883
Test name
Test status
Simulation time 115758335 ps
CPU time 2.62 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:33 PM PDT 24
Peak memory 208732 kb
Host smart-4e4d0776-5831-4d49-8b9e-43ff2f71dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887162129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3887162129
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.933956911
Short name T341
Test name
Test status
Simulation time 41575920 ps
CPU time 2.02 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:34 PM PDT 24
Peak memory 214488 kb
Host smart-a1b5cf95-94b9-437d-adcf-b080aa1cc09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933956911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.933956911
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2954786485
Short name T632
Test name
Test status
Simulation time 58665580 ps
CPU time 2.43 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 214344 kb
Host smart-5ca9d9b6-45db-4a01-ae65-58f50d297c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954786485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2954786485
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3147487090
Short name T297
Test name
Test status
Simulation time 46446892 ps
CPU time 3.29 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:32 PM PDT 24
Peak memory 210652 kb
Host smart-39ca8cc3-e335-4472-9583-e1093be4ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147487090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3147487090
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.600801543
Short name T349
Test name
Test status
Simulation time 856468199 ps
CPU time 6.76 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 208624 kb
Host smart-5d9561cd-3a4d-47f7-bed9-7a613566d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600801543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.600801543
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.655555906
Short name T594
Test name
Test status
Simulation time 50206222 ps
CPU time 2.77 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:32 PM PDT 24
Peak memory 208744 kb
Host smart-2970d1c6-6d6f-4b8f-9d06-9caa6cd76bb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655555906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.655555906
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1001588600
Short name T457
Test name
Test status
Simulation time 45415915 ps
CPU time 2.27 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 208260 kb
Host smart-d74f3c61-5fb0-4e2c-8fa3-0eee9e867661
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001588600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1001588600
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3412160056
Short name T446
Test name
Test status
Simulation time 217475740 ps
CPU time 3.65 seconds
Started Jun 30 05:45:28 PM PDT 24
Finished Jun 30 05:45:33 PM PDT 24
Peak memory 206940 kb
Host smart-7b9e1d28-758c-4798-a22c-2a85fa32734c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412160056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3412160056
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3943854252
Short name T597
Test name
Test status
Simulation time 200391759 ps
CPU time 2.1 seconds
Started Jun 30 05:45:26 PM PDT 24
Finished Jun 30 05:45:29 PM PDT 24
Peak memory 207912 kb
Host smart-56c19cc7-e28d-4a9f-8cb2-4d558241f01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943854252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3943854252
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3557247851
Short name T111
Test name
Test status
Simulation time 223273587 ps
CPU time 2.7 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:32 PM PDT 24
Peak memory 206956 kb
Host smart-2a071fd0-c0d2-4914-93f4-6712983de6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557247851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3557247851
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2356365558
Short name T882
Test name
Test status
Simulation time 11848879930 ps
CPU time 48.14 seconds
Started Jun 30 05:45:30 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 222480 kb
Host smart-3c2bb86d-cf51-4d75-a8b6-0dd58dd610b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356365558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2356365558
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2610294584
Short name T593
Test name
Test status
Simulation time 206297191 ps
CPU time 5.04 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:34 PM PDT 24
Peak memory 218272 kb
Host smart-027b8eeb-71fd-453e-b356-7ccaabe38e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610294584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2610294584
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.896089068
Short name T599
Test name
Test status
Simulation time 52570817 ps
CPU time 1.79 seconds
Started Jun 30 05:45:29 PM PDT 24
Finished Jun 30 05:45:31 PM PDT 24
Peak memory 210092 kb
Host smart-fc11f2a6-3a23-4f2d-a635-fd18fde32c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896089068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.896089068
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.744205836
Short name T743
Test name
Test status
Simulation time 40786081 ps
CPU time 0.76 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 206052 kb
Host smart-e7039c8f-1f75-4346-a2c9-37244da92769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744205836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.744205836
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2363904295
Short name T427
Test name
Test status
Simulation time 981330186 ps
CPU time 12.74 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 215044 kb
Host smart-a1287c34-2035-4a2d-ba44-c1fe0ce6fc69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363904295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2363904295
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1605956423
Short name T774
Test name
Test status
Simulation time 89625110 ps
CPU time 2.38 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 209232 kb
Host smart-9a6ef813-2551-4dfe-99d8-a6f3be9e5498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605956423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1605956423
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1980703264
Short name T231
Test name
Test status
Simulation time 223467096 ps
CPU time 2.58 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 214324 kb
Host smart-4b8f319d-d300-496f-9598-d17af812a9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980703264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1980703264
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.715911062
Short name T759
Test name
Test status
Simulation time 88061745 ps
CPU time 4.1 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:41 PM PDT 24
Peak memory 214344 kb
Host smart-4736315e-9a5c-4337-98a0-aefaddebc480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715911062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.715911062
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.674993742
Short name T571
Test name
Test status
Simulation time 285591663 ps
CPU time 2.17 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 222376 kb
Host smart-80711edc-0936-44c0-84f1-08fdd3d80c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674993742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.674993742
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2258905890
Short name T636
Test name
Test status
Simulation time 1401925551 ps
CPU time 4.68 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:42 PM PDT 24
Peak memory 214308 kb
Host smart-6f477f2a-eb9b-4bed-aa95-7d79b4b8b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258905890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2258905890
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2728435624
Short name T287
Test name
Test status
Simulation time 297888809 ps
CPU time 5.24 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 214436 kb
Host smart-14c750d0-4122-4986-a0e7-edc37cc73089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728435624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2728435624
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2240900617
Short name T784
Test name
Test status
Simulation time 855161540 ps
CPU time 5.16 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 208056 kb
Host smart-1b05c013-574a-49ba-8fc4-18d485da98fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240900617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2240900617
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1626025256
Short name T714
Test name
Test status
Simulation time 67298593 ps
CPU time 3.5 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 208956 kb
Host smart-621419b3-e137-44a3-9652-5961e4379644
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626025256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1626025256
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.664481519
Short name T756
Test name
Test status
Simulation time 66780714 ps
CPU time 3.24 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:41 PM PDT 24
Peak memory 208720 kb
Host smart-ab5639d6-2e42-4bea-9180-4a70655441ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664481519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.664481519
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2770896613
Short name T506
Test name
Test status
Simulation time 846485500 ps
CPU time 3.58 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:41 PM PDT 24
Peak memory 206992 kb
Host smart-96024ab3-00e7-4ac3-aad9-49bbc61cb55d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770896613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2770896613
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.941372328
Short name T606
Test name
Test status
Simulation time 1302596541 ps
CPU time 12.21 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 208576 kb
Host smart-4cfad767-a38b-4b1d-95b2-05da87f2b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941372328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.941372328
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2340091169
Short name T533
Test name
Test status
Simulation time 1754496660 ps
CPU time 4.79 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 208604 kb
Host smart-2b5e6880-c8ea-487f-be6b-2d5b9214c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340091169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2340091169
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1644103323
Short name T185
Test name
Test status
Simulation time 451806918 ps
CPU time 8.15 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 218832 kb
Host smart-4c55868e-e4c7-40c1-850d-01cfadb25570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644103323 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1644103323
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.780114738
Short name T115
Test name
Test status
Simulation time 1002708293 ps
CPU time 4.6 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 207940 kb
Host smart-096c133b-f14a-4b76-b8dd-1b1b0a0cebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780114738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.780114738
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.159522237
Short name T906
Test name
Test status
Simulation time 19652768 ps
CPU time 0.87 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 206020 kb
Host smart-96bd7ed9-aeec-4c86-8b71-822aad0f0ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159522237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.159522237
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3447624664
Short name T435
Test name
Test status
Simulation time 193705038 ps
CPU time 3.88 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 214340 kb
Host smart-01417e9c-22f4-4d91-a1e3-6e0088eadea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447624664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3447624664
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3034337709
Short name T572
Test name
Test status
Simulation time 513969299 ps
CPU time 5.61 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 214680 kb
Host smart-53a61937-dfd2-4f3c-b583-2f893b5bb4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034337709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3034337709
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2878360612
Short name T274
Test name
Test status
Simulation time 37446800 ps
CPU time 1.43 seconds
Started Jun 30 05:45:31 PM PDT 24
Finished Jun 30 05:45:33 PM PDT 24
Peak memory 207216 kb
Host smart-c32a5788-3277-421f-aa22-7d007619b939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878360612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2878360612
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3625940
Short name T726
Test name
Test status
Simulation time 125136133 ps
CPU time 6.08 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 222476 kb
Host smart-50d0eec4-4186-4471-9e03-44f0eed75794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3625940
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4110871925
Short name T902
Test name
Test status
Simulation time 858602494 ps
CPU time 3.69 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 220304 kb
Host smart-57accf73-5a3e-4ff4-a95a-fe8033ebb324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110871925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4110871925
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2014714262
Short name T752
Test name
Test status
Simulation time 213453360 ps
CPU time 6.4 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 208280 kb
Host smart-ada7317b-6724-47a5-a34c-1d7ce83b4bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014714262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2014714262
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2911898933
Short name T264
Test name
Test status
Simulation time 292183648 ps
CPU time 3.06 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 206992 kb
Host smart-37d8a885-cf0e-45af-852c-00b57ce4c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911898933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2911898933
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.55768050
Short name T818
Test name
Test status
Simulation time 344767736 ps
CPU time 2.58 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:37 PM PDT 24
Peak memory 208564 kb
Host smart-52391d4f-656a-4fce-b663-b23e171aa140
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55768050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.55768050
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.69481528
Short name T629
Test name
Test status
Simulation time 165073661 ps
CPU time 2.6 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 208940 kb
Host smart-b81f3d4d-afc1-46fe-b82f-6bfe6c8d27af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69481528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.69481528
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3151685139
Short name T461
Test name
Test status
Simulation time 148282120 ps
CPU time 2.57 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 207460 kb
Host smart-f49374e0-2c82-4d7c-88a1-c04b969bf476
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151685139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3151685139
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4233567949
Short name T27
Test name
Test status
Simulation time 128351278 ps
CPU time 2.52 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 218356 kb
Host smart-06e9b48b-d4d1-4158-a318-b4b1744790c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233567949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4233567949
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1348450096
Short name T847
Test name
Test status
Simulation time 87730668 ps
CPU time 3.6 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 208056 kb
Host smart-115a1a8f-11aa-4fd1-8554-02ed2b432430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348450096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1348450096
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3961259213
Short name T764
Test name
Test status
Simulation time 192125063 ps
CPU time 7.6 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:41 PM PDT 24
Peak memory 214348 kb
Host smart-39f98888-1799-4813-ba2a-721884ca6add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961259213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3961259213
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3271625114
Short name T777
Test name
Test status
Simulation time 72834985 ps
CPU time 1.99 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:45:42 PM PDT 24
Peak memory 209936 kb
Host smart-714a87cb-20ec-4650-afa0-cfb25343abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271625114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3271625114
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2059744480
Short name T103
Test name
Test status
Simulation time 20880793 ps
CPU time 0.82 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 205992 kb
Host smart-5401350a-6f8e-4dac-80fe-6c80ceaa4f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059744480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2059744480
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.194418301
Short name T488
Test name
Test status
Simulation time 443235302 ps
CPU time 4.15 seconds
Started Jun 30 05:45:38 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 210340 kb
Host smart-7fb9c252-48d3-43ea-bda2-2311a8b88f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194418301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.194418301
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.518925843
Short name T522
Test name
Test status
Simulation time 412490748 ps
CPU time 2.73 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 218248 kb
Host smart-e01193fc-45ff-4825-8934-1dd89db508f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518925843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.518925843
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.26486607
Short name T316
Test name
Test status
Simulation time 223585082 ps
CPU time 3.63 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:37 PM PDT 24
Peak memory 214288 kb
Host smart-b451e560-2c6d-4e36-aa0e-1efd8fc1d8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26486607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.26486607
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.306759811
Short name T276
Test name
Test status
Simulation time 38983656 ps
CPU time 1.51 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 214264 kb
Host smart-53096fd8-8401-4159-9177-490b11df4b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306759811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.306759811
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1617802575
Short name T813
Test name
Test status
Simulation time 133014807 ps
CPU time 2.4 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 219372 kb
Host smart-f7c9b945-4ed6-48fa-bc91-33ebdb054bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617802575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1617802575
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1032775585
Short name T353
Test name
Test status
Simulation time 156234666 ps
CPU time 6.86 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 210368 kb
Host smart-5543ec3f-5d9a-48eb-9fbd-05cca7ffa889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032775585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1032775585
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2335492943
Short name T543
Test name
Test status
Simulation time 180133001 ps
CPU time 2.68 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 206944 kb
Host smart-75f0247d-236f-4e1a-af87-2c3da05d2a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335492943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2335492943
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1357582431
Short name T628
Test name
Test status
Simulation time 104335684 ps
CPU time 2.79 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 206832 kb
Host smart-e52f7b76-e7fd-42b3-906a-29d783f6c19a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357582431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1357582431
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4125911216
Short name T364
Test name
Test status
Simulation time 57929786 ps
CPU time 2.96 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 206968 kb
Host smart-2a500407-895f-42d7-bdb6-23ecaacec258
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125911216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4125911216
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2126183466
Short name T787
Test name
Test status
Simulation time 305025849 ps
CPU time 3.25 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:42 PM PDT 24
Peak memory 206956 kb
Host smart-20bd04ba-37c2-4f7d-ba06-b9359c4870e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126183466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2126183466
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3581694635
Short name T553
Test name
Test status
Simulation time 319140217 ps
CPU time 2.63 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 208420 kb
Host smart-4cd40776-77d5-4464-bfaf-46a833c5c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581694635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3581694635
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.604028086
Short name T516
Test name
Test status
Simulation time 93090860 ps
CPU time 1.89 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 208800 kb
Host smart-c194aeb5-c686-4d7e-869d-66af3265e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604028086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.604028086
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4150344371
Short name T314
Test name
Test status
Simulation time 344102032 ps
CPU time 12.64 seconds
Started Jun 30 05:45:33 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 222416 kb
Host smart-7832a435-6a61-4859-8a83-440ed2f1b577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150344371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4150344371
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3924309715
Short name T181
Test name
Test status
Simulation time 1937227735 ps
CPU time 19.56 seconds
Started Jun 30 05:45:39 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 222864 kb
Host smart-93e13483-5733-42e8-810c-bae5c24fda52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924309715 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3924309715
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2507069266
Short name T261
Test name
Test status
Simulation time 147951199 ps
CPU time 3.1 seconds
Started Jun 30 05:45:38 PM PDT 24
Finished Jun 30 05:45:42 PM PDT 24
Peak memory 210728 kb
Host smart-c214af6d-0b2b-4ef0-b6ad-641ec90545db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507069266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2507069266
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3637024665
Short name T46
Test name
Test status
Simulation time 129734256 ps
CPU time 2.16 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:37 PM PDT 24
Peak memory 210256 kb
Host smart-bc4f1bf8-3069-4acf-b03a-cabb743688ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637024665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3637024665
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3121765387
Short name T655
Test name
Test status
Simulation time 12869254 ps
CPU time 0.84 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:42 PM PDT 24
Peak memory 206044 kb
Host smart-1843e533-76ab-4aaa-92cf-b5007dcf9cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121765387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3121765387
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.410526633
Short name T648
Test name
Test status
Simulation time 134888244 ps
CPU time 2.94 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:41 PM PDT 24
Peak memory 208208 kb
Host smart-4acf1757-0022-451a-9842-669f68ee9557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410526633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.410526633
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.502040728
Short name T703
Test name
Test status
Simulation time 85532953 ps
CPU time 2.56 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 214324 kb
Host smart-e4e83728-db02-452e-95ca-c804f8537b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502040728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.502040728
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2031196647
Short name T695
Test name
Test status
Simulation time 32306451 ps
CPU time 1.67 seconds
Started Jun 30 05:45:32 PM PDT 24
Finished Jun 30 05:45:35 PM PDT 24
Peak memory 214272 kb
Host smart-13a7ba7e-f5c9-4f7d-87ca-976b6dd0d8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031196647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2031196647
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2589309284
Short name T824
Test name
Test status
Simulation time 124533762 ps
CPU time 3.57 seconds
Started Jun 30 05:45:31 PM PDT 24
Finished Jun 30 05:45:36 PM PDT 24
Peak memory 220304 kb
Host smart-85719b07-db29-4819-a256-87180de19b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589309284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2589309284
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.57178336
Short name T197
Test name
Test status
Simulation time 467934994 ps
CPU time 5.33 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 207480 kb
Host smart-4f8a48fe-a44e-4996-9b17-0e848223321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57178336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.57178336
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3579421127
Short name T337
Test name
Test status
Simulation time 428846284 ps
CPU time 3.94 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:39 PM PDT 24
Peak memory 206920 kb
Host smart-53fa1449-083f-46de-8f9b-6b172213f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579421127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3579421127
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3328061190
Short name T528
Test name
Test status
Simulation time 1971253505 ps
CPU time 5.12 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 206988 kb
Host smart-53779d93-3da4-4a33-a76e-c972783a6bdd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328061190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3328061190
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.911633531
Short name T799
Test name
Test status
Simulation time 310621800 ps
CPU time 3.91 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 207104 kb
Host smart-aa0ecae8-afb3-4bbe-b5cb-f97ae9b9b622
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911633531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.911633531
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3049790927
Short name T500
Test name
Test status
Simulation time 40228635 ps
CPU time 2.55 seconds
Started Jun 30 05:45:36 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 207380 kb
Host smart-2cbcb4a9-8aa2-4f4b-83c7-abb3a1743c2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049790927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3049790927
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3529826038
Short name T374
Test name
Test status
Simulation time 166515167 ps
CPU time 3.52 seconds
Started Jun 30 05:45:35 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 214336 kb
Host smart-17c7aab3-5922-4e03-a0a3-0b669636381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529826038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3529826038
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3566950946
Short name T745
Test name
Test status
Simulation time 161397440 ps
CPU time 2.48 seconds
Started Jun 30 05:45:34 PM PDT 24
Finished Jun 30 05:45:38 PM PDT 24
Peak memory 206132 kb
Host smart-56e016c3-a58d-468f-a467-0734b01068fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566950946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3566950946
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2735092965
Short name T672
Test name
Test status
Simulation time 66250159 ps
CPU time 3.54 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:50 PM PDT 24
Peak memory 216540 kb
Host smart-9fde5bcd-2db5-4a06-a535-e1e38c6be376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735092965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2735092965
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.995891062
Short name T888
Test name
Test status
Simulation time 334350872 ps
CPU time 5.56 seconds
Started Jun 30 05:45:37 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 207484 kb
Host smart-19e9c194-76f6-494e-8f68-2521d799fa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995891062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.995891062
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.18209863
Short name T394
Test name
Test status
Simulation time 52232743 ps
CPU time 2.4 seconds
Started Jun 30 05:45:40 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 210012 kb
Host smart-3fee0a64-4424-47e7-b0f8-952ed7fe252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18209863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.18209863
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.192385280
Short name T644
Test name
Test status
Simulation time 38253806 ps
CPU time 0.73 seconds
Started Jun 30 05:45:42 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 206076 kb
Host smart-f1d3800f-c64d-4770-b476-ff101746233f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192385280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.192385280
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3162319572
Short name T863
Test name
Test status
Simulation time 136954929 ps
CPU time 3.47 seconds
Started Jun 30 05:45:42 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 214372 kb
Host smart-231d6e9e-76b5-4385-b45a-21f3f5c9e32e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162319572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3162319572
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1662453437
Short name T536
Test name
Test status
Simulation time 153767018 ps
CPU time 2.58 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:54 PM PDT 24
Peak memory 209336 kb
Host smart-1bc3d24c-e9c2-401f-a6b9-6f010c933506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662453437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1662453437
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1567063166
Short name T504
Test name
Test status
Simulation time 384337839 ps
CPU time 2.96 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:45:49 PM PDT 24
Peak memory 209780 kb
Host smart-66a664e5-7e94-4718-887a-0f1c357fd59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567063166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1567063166
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2485480101
Short name T819
Test name
Test status
Simulation time 2438349026 ps
CPU time 5.56 seconds
Started Jun 30 05:45:42 PM PDT 24
Finished Jun 30 05:45:48 PM PDT 24
Peak memory 206156 kb
Host smart-9b373f49-5276-4a92-bc56-56cb104ff0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485480101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2485480101
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3893859909
Short name T206
Test name
Test status
Simulation time 252300345 ps
CPU time 3.16 seconds
Started Jun 30 05:45:43 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 214736 kb
Host smart-cc7f72de-6f41-4e34-b919-e1432483060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893859909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3893859909
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.893366109
Short name T310
Test name
Test status
Simulation time 2798385419 ps
CPU time 28.27 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 210124 kb
Host smart-0074351b-99d1-4a7f-a565-5d19af6f081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893366109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.893366109
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2830883031
Short name T884
Test name
Test status
Simulation time 501643638 ps
CPU time 4.28 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:45:49 PM PDT 24
Peak memory 207004 kb
Host smart-4b7c293e-f683-43f8-824b-1423faa7dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830883031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2830883031
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.604849004
Short name T649
Test name
Test status
Simulation time 351824211 ps
CPU time 1.78 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 207008 kb
Host smart-8da9df9a-7bc5-4d42-a362-3a12a836cb5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604849004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.604849004
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.100868373
Short name T335
Test name
Test status
Simulation time 41406462 ps
CPU time 2.36 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 208348 kb
Host smart-fa0b69c6-4a7f-4fa6-8e3f-0df75ecf91a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100868373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.100868373
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2044595224
Short name T641
Test name
Test status
Simulation time 2714292818 ps
CPU time 10.57 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:52 PM PDT 24
Peak memory 208572 kb
Host smart-aead582d-d87d-41e9-bdb7-e6aa26be595c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044595224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2044595224
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2663582410
Short name T529
Test name
Test status
Simulation time 173405206 ps
CPU time 2.77 seconds
Started Jun 30 05:45:44 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 214276 kb
Host smart-d1623c69-b467-4366-a744-6d677488baa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663582410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2663582410
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2819917492
Short name T438
Test name
Test status
Simulation time 607922706 ps
CPU time 3.16 seconds
Started Jun 30 05:45:43 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 208200 kb
Host smart-e7d48883-954c-4d71-886c-b328479f757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819917492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2819917492
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3252639810
Short name T676
Test name
Test status
Simulation time 244995297 ps
CPU time 4.69 seconds
Started Jun 30 05:45:42 PM PDT 24
Finished Jun 30 05:45:48 PM PDT 24
Peak memory 208564 kb
Host smart-ba3458b8-29a6-40ff-83c6-55cb02003f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252639810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3252639810
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1684934698
Short name T499
Test name
Test status
Simulation time 19930912 ps
CPU time 0.8 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 206064 kb
Host smart-7220f19b-f765-4fb9-8693-1d339481e449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684934698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1684934698
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2066774151
Short name T417
Test name
Test status
Simulation time 30662227 ps
CPU time 2.51 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:44 PM PDT 24
Peak memory 214288 kb
Host smart-087f76d1-80ae-4f11-b365-05e826f67678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066774151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2066774151
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2100056394
Short name T43
Test name
Test status
Simulation time 1021484859 ps
CPU time 4.95 seconds
Started Jun 30 05:45:40 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 208700 kb
Host smart-4ce784af-a101-43fe-b3f7-16ba08ebf6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100056394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2100056394
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3239361814
Short name T760
Test name
Test status
Simulation time 28467897 ps
CPU time 1.69 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:48 PM PDT 24
Peak memory 207692 kb
Host smart-cab27d7d-36eb-4143-97a3-0f2393d1f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239361814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3239361814
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2029521934
Short name T255
Test name
Test status
Simulation time 101803994 ps
CPU time 4.6 seconds
Started Jun 30 05:45:42 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 221228 kb
Host smart-3e335d15-2974-40c2-bd02-59dd4b167279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029521934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2029521934
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3481941524
Short name T849
Test name
Test status
Simulation time 125715198 ps
CPU time 3.24 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 214252 kb
Host smart-31096fa3-344c-4601-9154-9d6bc3645771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481941524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3481941524
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_random.435656049
Short name T584
Test name
Test status
Simulation time 256873899 ps
CPU time 6.55 seconds
Started Jun 30 05:45:40 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 218280 kb
Host smart-b535619e-9e08-4565-bb91-25147884fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435656049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.435656049
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2404462966
Short name T686
Test name
Test status
Simulation time 64998994 ps
CPU time 2.48 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:45:48 PM PDT 24
Peak memory 208656 kb
Host smart-48471f7c-a29e-4de5-83d9-65782ab4ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404462966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2404462966
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2879269282
Short name T289
Test name
Test status
Simulation time 150474107 ps
CPU time 4.19 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 207900 kb
Host smart-941d163c-f9a8-4350-9220-818e4d1b9550
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879269282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2879269282
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.945472346
Short name T896
Test name
Test status
Simulation time 198795715 ps
CPU time 2.71 seconds
Started Jun 30 05:45:43 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 207008 kb
Host smart-e8fd9785-5419-4485-8a48-21e17d074f5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945472346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.945472346
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.849301636
Short name T898
Test name
Test status
Simulation time 1193025243 ps
CPU time 7.45 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:49 PM PDT 24
Peak memory 208812 kb
Host smart-caff0cd0-6d45-4a51-bf21-ae9356e14827
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849301636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.849301636
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4030264128
Short name T748
Test name
Test status
Simulation time 154928509 ps
CPU time 2.09 seconds
Started Jun 30 05:45:44 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 207848 kb
Host smart-9e3dbb01-dfee-444e-b7a9-505507f0b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030264128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4030264128
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.741634241
Short name T795
Test name
Test status
Simulation time 55105741 ps
CPU time 2.53 seconds
Started Jun 30 05:45:43 PM PDT 24
Finished Jun 30 05:45:47 PM PDT 24
Peak memory 208772 kb
Host smart-a9c8b94e-534f-4bb4-b69d-64ba87f86bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741634241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.741634241
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2010693890
Short name T372
Test name
Test status
Simulation time 43527673870 ps
CPU time 78.53 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:47:04 PM PDT 24
Peak memory 216216 kb
Host smart-d82c11e9-60ba-46e1-921e-eb8ca485c323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010693890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2010693890
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3915888219
Short name T82
Test name
Test status
Simulation time 140422725 ps
CPU time 8.53 seconds
Started Jun 30 05:45:44 PM PDT 24
Finished Jun 30 05:45:53 PM PDT 24
Peak memory 222640 kb
Host smart-e1e57f59-a356-4a4c-b441-0a5635ae7d4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915888219 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3915888219
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1211297631
Short name T873
Test name
Test status
Simulation time 179393390 ps
CPU time 4.21 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:50 PM PDT 24
Peak memory 207648 kb
Host smart-bd2c0a0f-bdea-4d4b-8dc3-0a553c869cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211297631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1211297631
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.746961668
Short name T65
Test name
Test status
Simulation time 58221484 ps
CPU time 1.77 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:43 PM PDT 24
Peak memory 209788 kb
Host smart-910ef1c8-8c25-4c6d-bb66-9476eb017bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746961668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.746961668
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2143909463
Short name T892
Test name
Test status
Simulation time 174138341 ps
CPU time 0.93 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:49 PM PDT 24
Peak memory 206188 kb
Host smart-584576b6-82d0-4803-892b-45b923e0937f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143909463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2143909463
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.127296322
Short name T658
Test name
Test status
Simulation time 257914968 ps
CPU time 3.21 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 222328 kb
Host smart-c4b3b8b0-c699-4844-bdc3-8aac83c64cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127296322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.127296322
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2871873805
Short name T747
Test name
Test status
Simulation time 147287587 ps
CPU time 4.37 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:56 PM PDT 24
Peak memory 209012 kb
Host smart-0fb7b2d8-66a8-4cac-9e9d-ce8b1ab1df6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871873805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2871873805
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1734363045
Short name T710
Test name
Test status
Simulation time 1293932388 ps
CPU time 10.7 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 222428 kb
Host smart-49758401-39a1-4163-ac9a-1ef3ab291d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734363045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1734363045
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.78937013
Short name T71
Test name
Test status
Simulation time 318713154 ps
CPU time 4.05 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 214324 kb
Host smart-fbf3e93d-d2cc-48f4-9ee0-22436991c65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78937013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.78937013
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2877972271
Short name T351
Test name
Test status
Simulation time 182622181 ps
CPU time 6.15 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:45:57 PM PDT 24
Peak memory 210428 kb
Host smart-be20d2f2-8f3a-493f-905d-763c02063d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877972271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2877972271
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2202758053
Short name T385
Test name
Test status
Simulation time 141313268 ps
CPU time 3.33 seconds
Started Jun 30 05:45:46 PM PDT 24
Finished Jun 30 05:45:50 PM PDT 24
Peak memory 206872 kb
Host smart-d974308e-4ef4-48a7-8d5f-3d3411e4d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202758053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2202758053
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2835241666
Short name T624
Test name
Test status
Simulation time 378776051 ps
CPU time 4.04 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:56 PM PDT 24
Peak memory 208952 kb
Host smart-f1ce17f2-8afb-424b-835d-311218c8db7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835241666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2835241666
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1988373444
Short name T862
Test name
Test status
Simulation time 2764115774 ps
CPU time 4.36 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 207796 kb
Host smart-4159f8e4-2a6e-44db-83fb-ec6aa70d5cf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988373444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1988373444
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.48442488
Short name T505
Test name
Test status
Simulation time 938583388 ps
CPU time 5.55 seconds
Started Jun 30 05:45:52 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 208472 kb
Host smart-b468138b-5d07-4ff6-abb0-b364cb69b19f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48442488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.48442488
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1564858898
Short name T136
Test name
Test status
Simulation time 469749351 ps
CPU time 3.26 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 214348 kb
Host smart-e3c041f1-ac87-4457-99cb-52b2bf79f97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564858898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1564858898
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1101269790
Short name T16
Test name
Test status
Simulation time 2427751610 ps
CPU time 3.33 seconds
Started Jun 30 05:45:41 PM PDT 24
Finished Jun 30 05:45:46 PM PDT 24
Peak memory 208440 kb
Host smart-dcfd35ac-6a05-4053-bf97-85d7bd8ff975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101269790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1101269790
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3165372744
Short name T340
Test name
Test status
Simulation time 4062724487 ps
CPU time 45.01 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:46:37 PM PDT 24
Peak memory 216384 kb
Host smart-52db9f7e-0bbc-485d-89b7-5f53e1f2f84a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165372744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3165372744
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2620394495
Short name T184
Test name
Test status
Simulation time 479042537 ps
CPU time 16.65 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:46:11 PM PDT 24
Peak memory 222624 kb
Host smart-0233442e-d877-4cbf-93f2-30dd435d8aa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620394495 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2620394495
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2608841362
Short name T868
Test name
Test status
Simulation time 92520986 ps
CPU time 4.27 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:45:54 PM PDT 24
Peak memory 209600 kb
Host smart-a87acbed-bd90-48c1-a8f6-2d120b6ec43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608841362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2608841362
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.606404741
Short name T134
Test name
Test status
Simulation time 375323223 ps
CPU time 2.8 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 210468 kb
Host smart-e2038727-79e4-4277-b832-68210b902d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606404741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.606404741
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.836348771
Short name T489
Test name
Test status
Simulation time 31193380 ps
CPU time 1 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:43:59 PM PDT 24
Peak memory 206184 kb
Host smart-6e84d958-c23b-47c7-a2f3-f739ff8de7e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836348771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.836348771
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3887773538
Short name T373
Test name
Test status
Simulation time 2434870880 ps
CPU time 34.97 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:44:26 PM PDT 24
Peak memory 222448 kb
Host smart-9561542a-a098-4411-a3ff-81363d367479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887773538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3887773538
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.315619024
Short name T770
Test name
Test status
Simulation time 46805218 ps
CPU time 3.07 seconds
Started Jun 30 05:43:52 PM PDT 24
Finished Jun 30 05:43:56 PM PDT 24
Peak memory 214344 kb
Host smart-dbb927d3-3bad-4ac0-aa31-812453ca946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315619024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.315619024
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.692050602
Short name T694
Test name
Test status
Simulation time 50710036 ps
CPU time 1.91 seconds
Started Jun 30 05:43:48 PM PDT 24
Finished Jun 30 05:43:50 PM PDT 24
Peak memory 215300 kb
Host smart-ffba0c65-0bc6-4dfb-838b-6118cc4424f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692050602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.692050602
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1395385362
Short name T204
Test name
Test status
Simulation time 381739944 ps
CPU time 4.96 seconds
Started Jun 30 05:43:48 PM PDT 24
Finished Jun 30 05:43:54 PM PDT 24
Peak memory 220020 kb
Host smart-4a37bcc2-5271-44b0-b295-2cc09438e1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395385362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1395385362
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3850120569
Short name T383
Test name
Test status
Simulation time 61400926 ps
CPU time 3.19 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:54 PM PDT 24
Peak memory 208676 kb
Host smart-dfaabd7b-c4da-40af-9686-1cebcf218f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850120569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3850120569
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1442229280
Short name T477
Test name
Test status
Simulation time 81040986 ps
CPU time 3.29 seconds
Started Jun 30 05:43:49 PM PDT 24
Finished Jun 30 05:43:53 PM PDT 24
Peak memory 207272 kb
Host smart-46c93b91-04b6-4f55-900d-982262bc3fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442229280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1442229280
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1534363274
Short name T87
Test name
Test status
Simulation time 3113657622 ps
CPU time 24.71 seconds
Started Jun 30 05:43:48 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 208012 kb
Host smart-04750de9-e735-4610-9889-c0b042951234
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534363274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1534363274
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2165634019
Short name T635
Test name
Test status
Simulation time 139075176 ps
CPU time 3.77 seconds
Started Jun 30 05:43:48 PM PDT 24
Finished Jun 30 05:43:52 PM PDT 24
Peak memory 208652 kb
Host smart-842d3fd5-805b-43ad-b9ad-b38e4acbb1b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165634019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2165634019
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1701296267
Short name T823
Test name
Test status
Simulation time 35312474 ps
CPU time 2.58 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 208736 kb
Host smart-793047a8-7a96-4f77-a82e-98e6511a4a5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701296267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1701296267
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2184580354
Short name T133
Test name
Test status
Simulation time 154787173 ps
CPU time 4.41 seconds
Started Jun 30 05:43:51 PM PDT 24
Finished Jun 30 05:43:57 PM PDT 24
Peak memory 209940 kb
Host smart-892e6393-1826-421d-919a-4f2a008f36d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184580354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2184580354
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1656756962
Short name T651
Test name
Test status
Simulation time 571844990 ps
CPU time 15.17 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:44:06 PM PDT 24
Peak memory 208172 kb
Host smart-13558316-2639-4317-b9f7-a1a5ca5c8c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656756962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1656756962
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1099823948
Short name T544
Test name
Test status
Simulation time 2277203235 ps
CPU time 28.34 seconds
Started Jun 30 05:43:50 PM PDT 24
Finished Jun 30 05:44:19 PM PDT 24
Peak memory 208256 kb
Host smart-ea09d256-abfe-4d30-ac85-1ee294aa648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099823948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1099823948
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3413413953
Short name T463
Test name
Test status
Simulation time 85579621 ps
CPU time 1.02 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:45:50 PM PDT 24
Peak memory 206164 kb
Host smart-4bffee2a-85ab-4e7d-893a-6ac1d55ec70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413413953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3413413953
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.124683145
Short name T433
Test name
Test status
Simulation time 45246806 ps
CPU time 3.5 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:45:52 PM PDT 24
Peak memory 214372 kb
Host smart-03064ce0-add9-47b6-aa04-c8d245756aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124683145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.124683145
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3818607905
Short name T830
Test name
Test status
Simulation time 176992479 ps
CPU time 4.24 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:45:54 PM PDT 24
Peak memory 214700 kb
Host smart-4c10a6b0-84b9-475f-93ca-38d0eaeff47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818607905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3818607905
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3859939622
Short name T75
Test name
Test status
Simulation time 175047335 ps
CPU time 2.37 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:50 PM PDT 24
Peak memory 209632 kb
Host smart-ff50b889-ca8b-41aa-a1f0-53ddfe60d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859939622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3859939622
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.545443925
Short name T715
Test name
Test status
Simulation time 299173025 ps
CPU time 3.52 seconds
Started Jun 30 05:45:45 PM PDT 24
Finished Jun 30 05:45:49 PM PDT 24
Peak memory 222460 kb
Host smart-8642e9f3-b7b5-401f-9e17-f04ec6cd8ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545443925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.545443925
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2218402061
Short name T257
Test name
Test status
Simulation time 81405124 ps
CPU time 3.83 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:52 PM PDT 24
Peak memory 214232 kb
Host smart-fb0d1d15-d7e3-4e8b-8d9e-5e2c4967f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218402061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2218402061
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2509688019
Short name T853
Test name
Test status
Simulation time 395035257 ps
CPU time 5.14 seconds
Started Jun 30 05:45:52 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 222336 kb
Host smart-0c042cd9-b960-482d-8917-2fe663f5d06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509688019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2509688019
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3394143453
Short name T86
Test name
Test status
Simulation time 1320963666 ps
CPU time 12.33 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:46:03 PM PDT 24
Peak memory 209404 kb
Host smart-53703c63-b036-4e2a-a060-9c50d506bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394143453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3394143453
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1875273684
Short name T15
Test name
Test status
Simulation time 732895873 ps
CPU time 6.03 seconds
Started Jun 30 05:45:52 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 208024 kb
Host smart-b2f911fb-93f1-4bbe-ad4b-824e8204384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875273684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1875273684
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.187960120
Short name T872
Test name
Test status
Simulation time 334109199 ps
CPU time 3.86 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 208772 kb
Host smart-3badea67-9ea6-4883-875e-0dfba8d89951
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187960120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.187960120
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.560379379
Short name T568
Test name
Test status
Simulation time 178574702 ps
CPU time 5.12 seconds
Started Jun 30 05:46:02 PM PDT 24
Finished Jun 30 05:46:07 PM PDT 24
Peak memory 207784 kb
Host smart-6ca2b4ae-57f1-47a8-a01c-ca2782e99807
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560379379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.560379379
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1130310510
Short name T638
Test name
Test status
Simulation time 618572354 ps
CPU time 6.54 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 208560 kb
Host smart-1457fda0-b844-4898-adf1-8e645478a8cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130310510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1130310510
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3863614088
Short name T423
Test name
Test status
Simulation time 289170160 ps
CPU time 3.24 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 209456 kb
Host smart-f39b3bf4-2130-4480-abdc-2641df8ef0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863614088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3863614088
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3851647713
Short name T700
Test name
Test status
Simulation time 36005885 ps
CPU time 2.03 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:45:56 PM PDT 24
Peak memory 206776 kb
Host smart-de8d188e-c492-4743-858d-d533fcebcf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851647713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3851647713
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2194922518
Short name T167
Test name
Test status
Simulation time 1156861963 ps
CPU time 23.12 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 222620 kb
Host smart-6e60963f-2316-4b4b-b129-ea3d1b49486a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194922518 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2194922518
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2350029881
Short name T410
Test name
Test status
Simulation time 4648062681 ps
CPU time 7.95 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 208376 kb
Host smart-deaa6136-2562-491b-a547-ff1460e11635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350029881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2350029881
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1861869656
Short name T389
Test name
Test status
Simulation time 46592223 ps
CPU time 1.47 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:53 PM PDT 24
Peak memory 209676 kb
Host smart-9a5188bf-7ec1-40f2-b9b1-ab150034273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861869656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1861869656
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.672331358
Short name T451
Test name
Test status
Simulation time 21214402 ps
CPU time 0.74 seconds
Started Jun 30 05:46:19 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 205928 kb
Host smart-bbd6d857-3540-4c00-8319-23c571b18afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672331358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.672331358
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.4136016473
Short name T431
Test name
Test status
Simulation time 100697856 ps
CPU time 3.93 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:56 PM PDT 24
Peak memory 215528 kb
Host smart-dcec9a4c-b143-4ca7-95c9-59534b6fe402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136016473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.4136016473
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3244932014
Short name T614
Test name
Test status
Simulation time 378674695 ps
CPU time 4.69 seconds
Started Jun 30 05:45:52 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 214288 kb
Host smart-56518c53-eb7b-43d2-a2a3-3ce532f37940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244932014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3244932014
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3316372380
Short name T68
Test name
Test status
Simulation time 63253924 ps
CPU time 2.78 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 218512 kb
Host smart-bc78b231-2642-454f-b547-ce946a9ed44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316372380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3316372380
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2848991114
Short name T97
Test name
Test status
Simulation time 4426508214 ps
CPU time 43.49 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:46:36 PM PDT 24
Peak memory 214388 kb
Host smart-8e96fcb4-e718-4da4-a8a7-0c980cc5d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848991114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2848991114
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1273384825
Short name T292
Test name
Test status
Simulation time 68518895 ps
CPU time 2.47 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:45:53 PM PDT 24
Peak memory 214268 kb
Host smart-e788ef5b-7895-46eb-a501-f7c914b01718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273384825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1273384825
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4195005373
Short name T664
Test name
Test status
Simulation time 349777992 ps
CPU time 3.46 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:45:56 PM PDT 24
Peak memory 215592 kb
Host smart-f7fae2ce-db23-4e17-8959-fcf8e8b02046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195005373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4195005373
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1263468941
Short name T613
Test name
Test status
Simulation time 82120506 ps
CPU time 3.75 seconds
Started Jun 30 05:45:49 PM PDT 24
Finished Jun 30 05:45:54 PM PDT 24
Peak memory 209200 kb
Host smart-7ff01a80-5fe7-428e-8c7d-87a1b2e8ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263468941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1263468941
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.217034154
Short name T552
Test name
Test status
Simulation time 26970752 ps
CPU time 2.22 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 208600 kb
Host smart-aa1ef244-81ab-490b-8e41-eeb848a19b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217034154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.217034154
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2773356980
Short name T284
Test name
Test status
Simulation time 51076588 ps
CPU time 2.71 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 208680 kb
Host smart-c4bc5a19-e1cb-42e6-b926-d9c548e73e08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773356980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2773356980
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2082245458
Short name T732
Test name
Test status
Simulation time 76320939 ps
CPU time 3.39 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 208660 kb
Host smart-a88eb84f-ec5d-441f-85d4-e0345914e9d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082245458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2082245458
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.957414446
Short name T407
Test name
Test status
Simulation time 1411047931 ps
CPU time 35.86 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:54 PM PDT 24
Peak memory 208268 kb
Host smart-4dd70506-7f3f-4993-b1cf-22a16af5553c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957414446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.957414446
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3509562842
Short name T617
Test name
Test status
Simulation time 191865361 ps
CPU time 2.41 seconds
Started Jun 30 05:45:51 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 207792 kb
Host smart-0521b677-bb0b-4c5c-acce-435b8c0cf693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509562842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3509562842
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2507698606
Short name T707
Test name
Test status
Simulation time 493693661 ps
CPU time 4.4 seconds
Started Jun 30 05:46:14 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 208444 kb
Host smart-5eedf166-1fe9-4d03-8ff7-5ae310686d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507698606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2507698606
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.327510757
Short name T77
Test name
Test status
Simulation time 3757341785 ps
CPU time 77.76 seconds
Started Jun 30 05:45:44 PM PDT 24
Finished Jun 30 05:47:03 PM PDT 24
Peak memory 222640 kb
Host smart-f4056f80-e39f-40b6-9afc-eaf233b1c5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327510757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.327510757
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.732886179
Short name T564
Test name
Test status
Simulation time 454573203 ps
CPU time 9.06 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 209312 kb
Host smart-af35aadb-ff65-4b53-a517-f2aa023ed299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732886179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.732886179
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3230152813
Short name T583
Test name
Test status
Simulation time 544416335 ps
CPU time 3.45 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:45:51 PM PDT 24
Peak memory 209996 kb
Host smart-8e938f5a-65bd-47b9-aaba-cf5b4f44fc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230152813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3230152813
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4140175078
Short name T554
Test name
Test status
Simulation time 13486700 ps
CPU time 0.74 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 206056 kb
Host smart-5d9e0f5d-c84b-4331-8293-141a1b55ae96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140175078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4140175078
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1419243374
Short name T558
Test name
Test status
Simulation time 98225417 ps
CPU time 2.76 seconds
Started Jun 30 05:45:59 PM PDT 24
Finished Jun 30 05:46:03 PM PDT 24
Peak memory 209720 kb
Host smart-3dd42b19-3986-4819-9d8e-acf73ceb48d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419243374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1419243374
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1930789176
Short name T260
Test name
Test status
Simulation time 110294235 ps
CPU time 3.4 seconds
Started Jun 30 05:45:58 PM PDT 24
Finished Jun 30 05:46:02 PM PDT 24
Peak memory 214336 kb
Host smart-cde66a7d-4098-4cf4-9e82-903ce8c077a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930789176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1930789176
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2374915014
Short name T642
Test name
Test status
Simulation time 128771795 ps
CPU time 4.06 seconds
Started Jun 30 05:45:54 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 214556 kb
Host smart-2bf5cdb0-83ee-4309-92b4-8419976e4b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374915014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2374915014
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.413487684
Short name T201
Test name
Test status
Simulation time 97604283 ps
CPU time 3.3 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 209656 kb
Host smart-b0a9ddf3-3a3b-48e8-9b23-d13ce9c9d860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413487684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.413487684
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.682845969
Short name T816
Test name
Test status
Simulation time 225563201 ps
CPU time 3.89 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:12 PM PDT 24
Peak memory 209196 kb
Host smart-9a591240-b356-4368-af2e-a36598a7259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682845969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.682845969
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1544408155
Short name T333
Test name
Test status
Simulation time 1590512148 ps
CPU time 22.49 seconds
Started Jun 30 05:45:47 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 208968 kb
Host smart-1b001a73-2663-49f9-a11c-658b099a762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544408155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1544408155
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3805764848
Short name T517
Test name
Test status
Simulation time 182406985 ps
CPU time 3.12 seconds
Started Jun 30 05:45:48 PM PDT 24
Finished Jun 30 05:45:52 PM PDT 24
Peak memory 208648 kb
Host smart-7e5e4020-ef02-4e77-a012-6aa1931742b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805764848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3805764848
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3618072717
Short name T339
Test name
Test status
Simulation time 90179198 ps
CPU time 2.76 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:54 PM PDT 24
Peak memory 207784 kb
Host smart-e2b27ec3-3773-4d0a-b43c-60fc578d0b6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618072717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3618072717
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2558445467
Short name T653
Test name
Test status
Simulation time 2013321299 ps
CPU time 14.29 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:32 PM PDT 24
Peak memory 207948 kb
Host smart-c5c1014f-0502-4554-8b6b-2e25638ad134
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558445467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2558445467
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2766020676
Short name T189
Test name
Test status
Simulation time 80868493 ps
CPU time 3.02 seconds
Started Jun 30 05:45:55 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 208904 kb
Host smart-cb64cdb2-2947-4e05-b24f-f1822bcb3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766020676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2766020676
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2312668090
Short name T591
Test name
Test status
Simulation time 68424109 ps
CPU time 2.98 seconds
Started Jun 30 05:45:50 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 208692 kb
Host smart-91d2a96e-9f14-40c8-af73-f4ccf43d0629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312668090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2312668090
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2157339734
Short name T475
Test name
Test status
Simulation time 695388188 ps
CPU time 13.69 seconds
Started Jun 30 05:45:55 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 216540 kb
Host smart-ffd8b468-5cce-443b-a0a6-a84185a65081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157339734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2157339734
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3586099103
Short name T757
Test name
Test status
Simulation time 527386323 ps
CPU time 20.41 seconds
Started Jun 30 05:45:54 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 222652 kb
Host smart-38d4438c-2997-4589-894f-196dbdef0906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586099103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3586099103
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3866439201
Short name T661
Test name
Test status
Simulation time 270959238 ps
CPU time 5.78 seconds
Started Jun 30 05:45:57 PM PDT 24
Finished Jun 30 05:46:03 PM PDT 24
Peak memory 207980 kb
Host smart-626ff159-c6e6-4d58-a7c8-49f9f75e1f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866439201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3866439201
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2180545841
Short name T485
Test name
Test status
Simulation time 166534852 ps
CPU time 2.31 seconds
Started Jun 30 05:45:55 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 210304 kb
Host smart-d13c0999-190c-4df8-bf75-20154e3cf69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180545841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2180545841
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2067009061
Short name T186
Test name
Test status
Simulation time 29044047 ps
CPU time 0.73 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:45:55 PM PDT 24
Peak memory 206064 kb
Host smart-1c373ee2-a8fb-4e0e-9afb-9f31f5a4c6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067009061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2067009061
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.158537327
Short name T416
Test name
Test status
Simulation time 49467387 ps
CPU time 3.77 seconds
Started Jun 30 05:45:56 PM PDT 24
Finished Jun 30 05:46:01 PM PDT 24
Peak memory 214812 kb
Host smart-80783528-2ab5-4251-97c0-cfde33a789d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158537327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.158537327
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.341523148
Short name T627
Test name
Test status
Simulation time 58321569 ps
CPU time 1.69 seconds
Started Jun 30 05:45:56 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 214384 kb
Host smart-67f03afe-6aac-43a3-9292-c649e350effe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341523148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.341523148
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3329410195
Short name T56
Test name
Test status
Simulation time 107618985 ps
CPU time 1.85 seconds
Started Jun 30 05:45:58 PM PDT 24
Finished Jun 30 05:46:01 PM PDT 24
Peak memory 209308 kb
Host smart-fb591ab3-1b4e-4177-ada6-dfe6ba297426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329410195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3329410195
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1135959907
Short name T280
Test name
Test status
Simulation time 273261050 ps
CPU time 4.42 seconds
Started Jun 30 05:45:55 PM PDT 24
Finished Jun 30 05:46:01 PM PDT 24
Peak memory 214288 kb
Host smart-2f97d4d8-3a15-4538-9036-625e4b009655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135959907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1135959907
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2494927763
Short name T744
Test name
Test status
Simulation time 98172169 ps
CPU time 2.16 seconds
Started Jun 30 05:45:59 PM PDT 24
Finished Jun 30 05:46:02 PM PDT 24
Peak memory 214284 kb
Host smart-0eb1736f-790c-4ff8-bcc6-6a838894aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494927763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2494927763
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1822516516
Short name T63
Test name
Test status
Simulation time 47346202 ps
CPU time 2.96 seconds
Started Jun 30 05:45:56 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 214400 kb
Host smart-9495f99a-021f-4343-b0d4-dbb700ea780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822516516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1822516516
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1365540590
Short name T334
Test name
Test status
Simulation time 7062584359 ps
CPU time 43.12 seconds
Started Jun 30 05:46:00 PM PDT 24
Finished Jun 30 05:46:44 PM PDT 24
Peak memory 209760 kb
Host smart-9c8b7713-90ce-4252-8fa7-fff63b053b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365540590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1365540590
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.724805535
Short name T886
Test name
Test status
Simulation time 39069761 ps
CPU time 1.8 seconds
Started Jun 30 05:45:59 PM PDT 24
Finished Jun 30 05:46:02 PM PDT 24
Peak memory 207196 kb
Host smart-6f01d2fc-5193-4786-912a-a63db54d1e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724805535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.724805535
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2525577377
Short name T403
Test name
Test status
Simulation time 201171757 ps
CPU time 5.47 seconds
Started Jun 30 05:45:55 PM PDT 24
Finished Jun 30 05:46:02 PM PDT 24
Peak memory 208196 kb
Host smart-51353af2-4296-498c-8c1e-69735f4cd49b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525577377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2525577377
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1754426386
Short name T767
Test name
Test status
Simulation time 6531018432 ps
CPU time 67.03 seconds
Started Jun 30 05:45:58 PM PDT 24
Finished Jun 30 05:47:06 PM PDT 24
Peak memory 208820 kb
Host smart-3e4596f5-3e98-4ea8-9e57-b18e0399c3d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754426386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1754426386
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1072464928
Short name T696
Test name
Test status
Simulation time 273209359 ps
CPU time 2.71 seconds
Started Jun 30 05:45:57 PM PDT 24
Finished Jun 30 05:46:00 PM PDT 24
Peak memory 206888 kb
Host smart-1550c71b-08c4-4a11-8412-e4e016dceccd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072464928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1072464928
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4150490008
Short name T684
Test name
Test status
Simulation time 49231675 ps
CPU time 2.36 seconds
Started Jun 30 05:45:58 PM PDT 24
Finished Jun 30 05:46:01 PM PDT 24
Peak memory 206984 kb
Host smart-c5e10556-0006-4e32-a1fb-2073d9e3ff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150490008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4150490008
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.631227096
Short name T441
Test name
Test status
Simulation time 107750403 ps
CPU time 2.71 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:45:57 PM PDT 24
Peak memory 207824 kb
Host smart-f7c5bdd0-79d2-4363-b6c5-4fe29e54e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631227096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.631227096
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.226016355
Short name T76
Test name
Test status
Simulation time 262531851 ps
CPU time 8.32 seconds
Started Jun 30 05:45:58 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 216684 kb
Host smart-673d9662-2100-439a-9047-36c23618cbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226016355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.226016355
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3741402341
Short name T242
Test name
Test status
Simulation time 576566155 ps
CPU time 5.37 seconds
Started Jun 30 05:45:56 PM PDT 24
Finished Jun 30 05:46:02 PM PDT 24
Peak memory 218272 kb
Host smart-d84f4eda-9af0-4f38-8fee-556a3586a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741402341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3741402341
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3465626724
Short name T852
Test name
Test status
Simulation time 709441405 ps
CPU time 6.91 seconds
Started Jun 30 05:45:52 PM PDT 24
Finished Jun 30 05:46:00 PM PDT 24
Peak memory 211156 kb
Host smart-38afafeb-dc00-4b5a-ab32-f6426ca3d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465626724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3465626724
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2211013669
Short name T657
Test name
Test status
Simulation time 13115985 ps
CPU time 0.77 seconds
Started Jun 30 05:46:00 PM PDT 24
Finished Jun 30 05:46:01 PM PDT 24
Peak memory 206016 kb
Host smart-b9fde4bd-4038-408b-89e8-8fbace87ad68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211013669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2211013669
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2657920799
Short name T311
Test name
Test status
Simulation time 53585639 ps
CPU time 3.84 seconds
Started Jun 30 05:45:59 PM PDT 24
Finished Jun 30 05:46:03 PM PDT 24
Peak memory 214372 kb
Host smart-9a8dbb2b-f41a-4805-8721-da8f84eae183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657920799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2657920799
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2989056902
Short name T19
Test name
Test status
Simulation time 233711068 ps
CPU time 3.5 seconds
Started Jun 30 05:46:00 PM PDT 24
Finished Jun 30 05:46:04 PM PDT 24
Peak memory 219576 kb
Host smart-e2ad559e-1c4d-4cda-84b1-6c1d874bf648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989056902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2989056902
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3879542746
Short name T538
Test name
Test status
Simulation time 397353077 ps
CPU time 11.6 seconds
Started Jun 30 05:46:03 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 210140 kb
Host smart-c628c0ee-1e74-4752-9e44-73139985f4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879542746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3879542746
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4031879289
Short name T100
Test name
Test status
Simulation time 123583069 ps
CPU time 4.1 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 214736 kb
Host smart-8d7d569b-3edc-4c54-a153-de2406bf88f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031879289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4031879289
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1121803731
Short name T343
Test name
Test status
Simulation time 303981145 ps
CPU time 3.38 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:04 PM PDT 24
Peak memory 214244 kb
Host smart-52473562-b774-4a6a-ad20-3b633c7e8c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121803731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1121803731
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.3270423216
Short name T421
Test name
Test status
Simulation time 94200278 ps
CPU time 4.28 seconds
Started Jun 30 05:45:54 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 209108 kb
Host smart-e4fd915c-4c71-46f7-a747-360e3a1780e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270423216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3270423216
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1479625069
Short name T492
Test name
Test status
Simulation time 1122330574 ps
CPU time 20.01 seconds
Started Jun 30 05:45:53 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 208300 kb
Host smart-27529a49-e2e4-4891-8aaa-a73ff3f9c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479625069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1479625069
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4031773101
Short name T607
Test name
Test status
Simulation time 63758254 ps
CPU time 2.41 seconds
Started Jun 30 05:45:56 PM PDT 24
Finished Jun 30 05:45:59 PM PDT 24
Peak memory 207144 kb
Host smart-5276f6ce-d17d-4094-bebf-5cb0de30f7b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031773101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4031773101
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.87805653
Short name T240
Test name
Test status
Simulation time 526811876 ps
CPU time 6.25 seconds
Started Jun 30 05:45:58 PM PDT 24
Finished Jun 30 05:46:04 PM PDT 24
Peak memory 208676 kb
Host smart-fd09ca74-5faf-4d0c-80bb-865d60db5183
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87805653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.87805653
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.130344733
Short name T490
Test name
Test status
Simulation time 382872494 ps
CPU time 9.28 seconds
Started Jun 30 05:46:00 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 208832 kb
Host smart-f07d79db-1ae8-40c9-bb5d-8c657e9b7ac1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130344733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.130344733
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3307992173
Short name T132
Test name
Test status
Simulation time 60835764 ps
CPU time 2.45 seconds
Started Jun 30 05:46:05 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 209996 kb
Host smart-746fb287-2b59-4ee8-b890-8dd813f7908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307992173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3307992173
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3909098006
Short name T803
Test name
Test status
Simulation time 50448464 ps
CPU time 2.56 seconds
Started Jun 30 05:45:54 PM PDT 24
Finished Jun 30 05:45:58 PM PDT 24
Peak memory 208004 kb
Host smart-bb46fdaa-b97d-4470-b338-139525f00048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909098006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3909098006
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3184034417
Short name T322
Test name
Test status
Simulation time 619935471 ps
CPU time 15.38 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:23 PM PDT 24
Peak memory 215136 kb
Host smart-dda05dd6-1e8e-425e-8db3-ddfca356fdf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184034417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3184034417
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1541078931
Short name T243
Test name
Test status
Simulation time 904692460 ps
CPU time 9.51 seconds
Started Jun 30 05:46:03 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 214328 kb
Host smart-fdb2b7ce-28e3-4ec1-a631-eb4d6a51e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541078931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1541078931
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4196205618
Short name T195
Test name
Test status
Simulation time 57746480 ps
CPU time 2.34 seconds
Started Jun 30 05:46:06 PM PDT 24
Finished Jun 30 05:46:09 PM PDT 24
Peak memory 209992 kb
Host smart-897b657e-a0df-4f1e-bb4b-4a272539ef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196205618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4196205618
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3808809571
Short name T758
Test name
Test status
Simulation time 23128980 ps
CPU time 0.91 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 206084 kb
Host smart-81cfaa83-e046-4b0a-b930-9e64749978e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808809571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3808809571
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3945887820
Short name T418
Test name
Test status
Simulation time 299292204 ps
CPU time 8.88 seconds
Started Jun 30 05:46:06 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 214340 kb
Host smart-412f1a89-6c1a-4a1d-9592-a5f73729377a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945887820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3945887820
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.242299724
Short name T702
Test name
Test status
Simulation time 90897344 ps
CPU time 3.49 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:05 PM PDT 24
Peak memory 220224 kb
Host smart-26056e41-087b-4d83-bef1-04674976ad0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242299724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.242299724
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.4215091257
Short name T878
Test name
Test status
Simulation time 272394544 ps
CPU time 2.85 seconds
Started Jun 30 05:46:05 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 208364 kb
Host smart-e17df7be-e6ad-43ca-a2b9-90efb211bd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215091257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4215091257
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1402647298
Short name T233
Test name
Test status
Simulation time 101340259 ps
CPU time 1.9 seconds
Started Jun 30 05:46:03 PM PDT 24
Finished Jun 30 05:46:06 PM PDT 24
Peak memory 214524 kb
Host smart-311cb410-7151-424a-bbad-12a286fa0e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402647298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1402647298
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_random.3974942842
Short name T386
Test name
Test status
Simulation time 127386027 ps
CPU time 2.43 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:11 PM PDT 24
Peak memory 208036 kb
Host smart-b6ef7ffb-d7d3-49bb-98d7-878de7996e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974942842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3974942842
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3179163139
Short name T332
Test name
Test status
Simulation time 5340361453 ps
CPU time 17.43 seconds
Started Jun 30 05:46:03 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 208584 kb
Host smart-81949240-86b2-4440-9868-8a4d9fbf6b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179163139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3179163139
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2078417621
Short name T541
Test name
Test status
Simulation time 490440210 ps
CPU time 3.95 seconds
Started Jun 30 05:46:04 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 208940 kb
Host smart-2c47805a-86b9-409b-a1e8-baad4236f422
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078417621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2078417621
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.334200055
Short name T402
Test name
Test status
Simulation time 469386132 ps
CPU time 6.91 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:08 PM PDT 24
Peak memory 207960 kb
Host smart-8deba852-1aaf-4214-b3ee-625382f92168
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334200055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.334200055
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2352279018
Short name T753
Test name
Test status
Simulation time 722920481 ps
CPU time 2.79 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:05 PM PDT 24
Peak memory 207000 kb
Host smart-9bc138e0-377b-42df-80db-5941c2846873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352279018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2352279018
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2077263701
Short name T336
Test name
Test status
Simulation time 79201712 ps
CPU time 3.97 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:06 PM PDT 24
Peak memory 210300 kb
Host smart-1909f7d4-b9a3-4568-806b-351b1f3ed133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077263701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2077263701
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3834182996
Short name T470
Test name
Test status
Simulation time 60366893 ps
CPU time 2.81 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 208236 kb
Host smart-4394fef4-e85c-4cf1-abc8-62ee335b0023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834182996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3834182996
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.940567129
Short name T129
Test name
Test status
Simulation time 226340851 ps
CPU time 11.23 seconds
Started Jun 30 05:45:59 PM PDT 24
Finished Jun 30 05:46:11 PM PDT 24
Peak memory 222572 kb
Host smart-0a86c19a-4f61-4640-b123-56341c441636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940567129 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.940567129
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3160751405
Short name T677
Test name
Test status
Simulation time 145604261 ps
CPU time 5.53 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:23 PM PDT 24
Peak memory 208852 kb
Host smart-2cc64993-70f5-46f6-bb12-d8c257ca4af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160751405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3160751405
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3700932708
Short name T866
Test name
Test status
Simulation time 92595287 ps
CPU time 0.73 seconds
Started Jun 30 05:46:23 PM PDT 24
Finished Jun 30 05:46:24 PM PDT 24
Peak memory 206036 kb
Host smart-49832ea9-76c5-497c-acac-76e25fd1b352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700932708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3700932708
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1797566310
Short name T424
Test name
Test status
Simulation time 206139893 ps
CPU time 11.69 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 215696 kb
Host smart-28a77b68-bb53-47be-818f-9355ce4df55c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797566310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1797566310
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2046884242
Short name T105
Test name
Test status
Simulation time 306634074 ps
CPU time 3.4 seconds
Started Jun 30 05:46:13 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 219588 kb
Host smart-03863d1b-bd66-4709-9d6b-ebc143c21ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046884242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2046884242
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.825878292
Short name T775
Test name
Test status
Simulation time 74932422 ps
CPU time 2.72 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 218664 kb
Host smart-cc3e5e05-cd36-4227-943a-a9c1c597f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825878292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.825878292
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2828204959
Short name T92
Test name
Test status
Simulation time 90866105 ps
CPU time 4.15 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:20 PM PDT 24
Peak memory 209680 kb
Host smart-d3452f0e-e6f6-478d-8b1e-44c0db84cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828204959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2828204959
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3529843872
Short name T278
Test name
Test status
Simulation time 51178097 ps
CPU time 2.43 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:11 PM PDT 24
Peak memory 214280 kb
Host smart-a460724f-d7f0-4aee-ab0c-99f3994315f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529843872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3529843872
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.54713169
Short name T208
Test name
Test status
Simulation time 318418526 ps
CPU time 2.82 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 209180 kb
Host smart-9b7998e0-a0b5-4ed2-ba1b-0bdf40b07a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54713169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.54713169
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_sideload.606068588
Short name T138
Test name
Test status
Simulation time 221562016 ps
CPU time 2.16 seconds
Started Jun 30 05:45:59 PM PDT 24
Finished Jun 30 05:46:02 PM PDT 24
Peak memory 208728 kb
Host smart-9de57211-9b9a-4975-87a9-00ed9e577d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606068588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.606068588
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.84565918
Short name T840
Test name
Test status
Simulation time 64037819 ps
CPU time 2.56 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 208712 kb
Host smart-ed9cf892-201e-4ab9-accf-f258f83d3918
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84565918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.84565918
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3107932873
Short name T141
Test name
Test status
Simulation time 71336113 ps
CPU time 3.48 seconds
Started Jun 30 05:46:05 PM PDT 24
Finished Jun 30 05:46:09 PM PDT 24
Peak memory 207976 kb
Host smart-5001ebd1-ec9a-4595-a987-568dc968bfb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107932873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3107932873
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1066728744
Short name T904
Test name
Test status
Simulation time 120155327 ps
CPU time 3.24 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:05 PM PDT 24
Peak memory 208656 kb
Host smart-956881fb-d25e-499d-924d-2a65a68ed51c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066728744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1066728744
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2665443721
Short name T229
Test name
Test status
Simulation time 175851861 ps
CPU time 4.14 seconds
Started Jun 30 05:46:10 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 209472 kb
Host smart-2c87c085-b504-4fd9-87dc-a317fad792b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665443721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2665443721
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2907693501
Short name T877
Test name
Test status
Simulation time 671810457 ps
CPU time 13.37 seconds
Started Jun 30 05:46:01 PM PDT 24
Finished Jun 30 05:46:15 PM PDT 24
Peak memory 208476 kb
Host smart-82ec665e-d901-4988-94f8-2f67c18b3c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907693501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2907693501
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1274630391
Short name T306
Test name
Test status
Simulation time 323864771 ps
CPU time 3.49 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:12 PM PDT 24
Peak memory 209380 kb
Host smart-66ff26bd-1f71-47e7-8726-571e8cd5e64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274630391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1274630391
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.136724248
Short name T388
Test name
Test status
Simulation time 180829173 ps
CPU time 4 seconds
Started Jun 30 05:46:15 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 209980 kb
Host smart-90cba1cd-2b4e-414c-8ac3-bb4f2ba1898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136724248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.136724248
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1532581781
Short name T791
Test name
Test status
Simulation time 28092831 ps
CPU time 0.82 seconds
Started Jun 30 05:46:15 PM PDT 24
Finished Jun 30 05:46:16 PM PDT 24
Peak memory 206064 kb
Host smart-faf62ea6-0d64-452f-9730-ceeaf8164af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532581781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1532581781
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3186396120
Short name T429
Test name
Test status
Simulation time 6596848928 ps
CPU time 50.36 seconds
Started Jun 30 05:46:15 PM PDT 24
Finished Jun 30 05:47:06 PM PDT 24
Peak memory 222460 kb
Host smart-ae1b316b-c7bc-4b40-a43a-adac86561cc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186396120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3186396120
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3864787458
Short name T31
Test name
Test status
Simulation time 690487091 ps
CPU time 4.7 seconds
Started Jun 30 05:46:06 PM PDT 24
Finished Jun 30 05:46:11 PM PDT 24
Peak memory 209632 kb
Host smart-30d30ce4-2197-4d16-830a-274c73772840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864787458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3864787458
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.521800457
Short name T26
Test name
Test status
Simulation time 26683838 ps
CPU time 2.03 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 208316 kb
Host smart-c63481a8-a843-4d40-9f17-b20fba94bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521800457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.521800457
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1308089560
Short name T281
Test name
Test status
Simulation time 80642446 ps
CPU time 2.55 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 214380 kb
Host smart-306aa5eb-8e2d-4cdb-92b8-85225c4d10e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308089560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1308089560
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3737297554
Short name T698
Test name
Test status
Simulation time 323809575 ps
CPU time 3.84 seconds
Started Jun 30 05:46:19 PM PDT 24
Finished Jun 30 05:46:23 PM PDT 24
Peak memory 214356 kb
Host smart-dcbd8cab-0df4-4d74-bf20-39dc69e0e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737297554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3737297554
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3426397506
Short name T283
Test name
Test status
Simulation time 5607961707 ps
CPU time 20.46 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:29 PM PDT 24
Peak memory 218404 kb
Host smart-f2bb290e-a9cf-46d3-ac8a-9661b572a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426397506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3426397506
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.970359125
Short name T248
Test name
Test status
Simulation time 49092582 ps
CPU time 2.68 seconds
Started Jun 30 05:46:10 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 208524 kb
Host smart-2f9c138f-7e55-4ab0-8355-ce28267a9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970359125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.970359125
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4086338766
Short name T785
Test name
Test status
Simulation time 108551840 ps
CPU time 2.98 seconds
Started Jun 30 05:46:13 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 206996 kb
Host smart-0ab020f0-c88b-42cf-bf30-29ad5630f933
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086338766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4086338766
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.82710439
Short name T871
Test name
Test status
Simulation time 162864242 ps
CPU time 6.21 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 208576 kb
Host smart-b31fa9e2-e687-492d-85d2-331f1964749d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82710439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.82710439
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4183249124
Short name T51
Test name
Test status
Simulation time 486845793 ps
CPU time 2.55 seconds
Started Jun 30 05:46:13 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 208756 kb
Host smart-9fd98176-ea76-4289-8a7e-b2dfaff7b0bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183249124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4183249124
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4229544328
Short name T876
Test name
Test status
Simulation time 188968951 ps
CPU time 3.17 seconds
Started Jun 30 05:46:14 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 208392 kb
Host smart-36db43d2-7e84-4a7d-b733-0fddcc74df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229544328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4229544328
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2969737565
Short name T447
Test name
Test status
Simulation time 57568115 ps
CPU time 2.51 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:10 PM PDT 24
Peak memory 206844 kb
Host smart-69e2d8a3-c8e5-41ab-b829-175fcc2ddde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969737565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2969737565
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.239700318
Short name T309
Test name
Test status
Simulation time 1508509798 ps
CPU time 36.38 seconds
Started Jun 30 05:46:07 PM PDT 24
Finished Jun 30 05:46:44 PM PDT 24
Peak memory 214900 kb
Host smart-8b035cca-e585-4364-b0f6-fba38f56bb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239700318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.239700318
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3966257850
Short name T325
Test name
Test status
Simulation time 180547773 ps
CPU time 6.21 seconds
Started Jun 30 05:46:06 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 214368 kb
Host smart-442d9abe-1f1f-4b48-95b1-6559f9170f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966257850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3966257850
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1174000087
Short name T397
Test name
Test status
Simulation time 155137862 ps
CPU time 2.31 seconds
Started Jun 30 05:46:08 PM PDT 24
Finished Jun 30 05:46:11 PM PDT 24
Peak memory 210172 kb
Host smart-f96cab29-e525-4b38-ae48-5de288f4e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174000087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1174000087
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3851938401
Short name T854
Test name
Test status
Simulation time 37472829 ps
CPU time 0.91 seconds
Started Jun 30 05:46:12 PM PDT 24
Finished Jun 30 05:46:14 PM PDT 24
Peak memory 206020 kb
Host smart-6ba12563-33b0-4e0e-a901-dd8004f9de38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851938401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3851938401
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.700302682
Short name T296
Test name
Test status
Simulation time 225237074 ps
CPU time 4.69 seconds
Started Jun 30 05:46:13 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 215492 kb
Host smart-5a490b68-78e0-4479-a3af-c5055321cf16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700302682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.700302682
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3050437019
Short name T801
Test name
Test status
Simulation time 220851899 ps
CPU time 2.78 seconds
Started Jun 30 05:46:09 PM PDT 24
Finished Jun 30 05:46:12 PM PDT 24
Peak memory 209448 kb
Host smart-ed702351-ca9b-475f-96a5-4bd70ae747e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050437019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3050437019
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.789996122
Short name T24
Test name
Test status
Simulation time 118776922 ps
CPU time 4.76 seconds
Started Jun 30 05:46:12 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 220908 kb
Host smart-67e08573-2db6-4d6c-a64a-489f725eeebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789996122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.789996122
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1861780479
Short name T600
Test name
Test status
Simulation time 68292210 ps
CPU time 2.03 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:14 PM PDT 24
Peak memory 214568 kb
Host smart-46a4cba2-ce0b-443d-978b-e550c78da9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861780479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1861780479
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3631442504
Short name T285
Test name
Test status
Simulation time 36690150 ps
CPU time 2.29 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 207920 kb
Host smart-9e943b1e-f94e-4f08-9147-0aab7d6b3890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631442504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3631442504
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.662819643
Short name T282
Test name
Test status
Simulation time 725817770 ps
CPU time 6.61 seconds
Started Jun 30 05:46:10 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 214344 kb
Host smart-1877ba2f-06a0-4d39-aa90-85124e3cb0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662819643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.662819643
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1500275802
Short name T667
Test name
Test status
Simulation time 445430070 ps
CPU time 6.71 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 208284 kb
Host smart-8f789586-2cc7-4a42-878d-d50d369fc825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500275802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1500275802
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1264358973
Short name T562
Test name
Test status
Simulation time 51679805 ps
CPU time 2.67 seconds
Started Jun 30 05:46:10 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 208736 kb
Host smart-23330378-b723-4257-b59a-fd7bc31f36cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264358973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1264358973
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4165471276
Short name T704
Test name
Test status
Simulation time 91489769 ps
CPU time 4.03 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 208876 kb
Host smart-d9133635-0152-47af-bbc7-d1566f2e6947
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165471276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4165471276
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1402861850
Short name T405
Test name
Test status
Simulation time 186316597 ps
CPU time 5.88 seconds
Started Jun 30 05:46:12 PM PDT 24
Finished Jun 30 05:46:18 PM PDT 24
Peak memory 206944 kb
Host smart-33c3b479-81ad-4088-a913-cc5b68eb2b5f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402861850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1402861850
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2672123334
Short name T270
Test name
Test status
Simulation time 363334625 ps
CPU time 8.36 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:26 PM PDT 24
Peak memory 208192 kb
Host smart-75c638d1-702c-4f6f-af7d-26a79d46e856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672123334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2672123334
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2187138436
Short name T858
Test name
Test status
Simulation time 306754868 ps
CPU time 3.24 seconds
Started Jun 30 05:46:10 PM PDT 24
Finished Jun 30 05:46:14 PM PDT 24
Peak memory 207336 kb
Host smart-918240a1-f268-45e7-991f-bec6b6be5ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187138436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2187138436
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.4290458029
Short name T135
Test name
Test status
Simulation time 4440816107 ps
CPU time 47.55 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:59 PM PDT 24
Peak memory 209696 kb
Host smart-da258426-aa3a-491b-a1ed-78779a3dfda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290458029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4290458029
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.660837135
Short name T194
Test name
Test status
Simulation time 456119455 ps
CPU time 4.87 seconds
Started Jun 30 05:46:11 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 211012 kb
Host smart-64cb83cc-c1ec-44e7-a84c-ae31ae281ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660837135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.660837135
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2084349524
Short name T908
Test name
Test status
Simulation time 78061410 ps
CPU time 0.74 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:20 PM PDT 24
Peak memory 206052 kb
Host smart-e078e17b-b3d0-4003-a988-3da9925f03d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084349524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2084349524
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1005907633
Short name T804
Test name
Test status
Simulation time 9004818324 ps
CPU time 29.82 seconds
Started Jun 30 05:46:22 PM PDT 24
Finished Jun 30 05:46:52 PM PDT 24
Peak memory 222872 kb
Host smart-4585bd6c-a05a-4e86-827c-9f8055b4100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005907633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1005907633
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3920043909
Short name T62
Test name
Test status
Simulation time 93844050 ps
CPU time 2.07 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 209808 kb
Host smart-74b9ccd8-cdfb-4aa9-8c98-714c20b53a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920043909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3920043909
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.803746508
Short name T258
Test name
Test status
Simulation time 55612238 ps
CPU time 1.82 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 214288 kb
Host smart-48e1b50f-b487-4e7d-9fac-58c46c5981a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803746508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.803746508
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3118168110
Short name T736
Test name
Test status
Simulation time 616074094 ps
CPU time 2.68 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 214252 kb
Host smart-91817290-0e4a-440a-8574-e8f694df1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118168110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3118168110
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2056291378
Short name T212
Test name
Test status
Simulation time 114398847 ps
CPU time 5.57 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:23 PM PDT 24
Peak memory 214304 kb
Host smart-527868c5-050f-40cd-ae41-ac957043e810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056291378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2056291378
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2365290251
Short name T812
Test name
Test status
Simulation time 376246155 ps
CPU time 2.67 seconds
Started Jun 30 05:46:20 PM PDT 24
Finished Jun 30 05:46:24 PM PDT 24
Peak memory 207592 kb
Host smart-6ad75e0e-1de2-47db-8f7c-0de06b3664e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365290251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2365290251
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1725903963
Short name T137
Test name
Test status
Simulation time 39517804 ps
CPU time 2.8 seconds
Started Jun 30 05:46:16 PM PDT 24
Finished Jun 30 05:46:19 PM PDT 24
Peak memory 208860 kb
Host smart-6f02cbf6-5e08-471b-8e42-b5dc54d83d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725903963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1725903963
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2199452518
Short name T662
Test name
Test status
Simulation time 205835485 ps
CPU time 2.96 seconds
Started Jun 30 05:46:18 PM PDT 24
Finished Jun 30 05:46:22 PM PDT 24
Peak memory 206804 kb
Host smart-50b82cd4-4a3f-40f7-8342-6e1ece57a09d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199452518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2199452518
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3858268501
Short name T348
Test name
Test status
Simulation time 155095328 ps
CPU time 4.43 seconds
Started Jun 30 05:46:22 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 208424 kb
Host smart-ff16ed31-6d2c-48f8-954f-f0083aee738c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858268501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3858268501
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3137047411
Short name T581
Test name
Test status
Simulation time 654643640 ps
CPU time 13.64 seconds
Started Jun 30 05:46:21 PM PDT 24
Finished Jun 30 05:46:35 PM PDT 24
Peak memory 208804 kb
Host smart-788af819-dd27-494b-a52d-7e3e890cb5b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137047411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3137047411
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1841169620
Short name T719
Test name
Test status
Simulation time 619452521 ps
CPU time 5.61 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:24 PM PDT 24
Peak memory 208716 kb
Host smart-793b627a-d6a8-447a-9fc1-7b2160203924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841169620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1841169620
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3938369035
Short name T205
Test name
Test status
Simulation time 3626948552 ps
CPU time 21.41 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:40 PM PDT 24
Peak memory 216464 kb
Host smart-d98d73d9-d165-43d5-8446-74e9ac7a01be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938369035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3938369035
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1601375876
Short name T601
Test name
Test status
Simulation time 273618233 ps
CPU time 8.16 seconds
Started Jun 30 05:46:21 PM PDT 24
Finished Jun 30 05:46:30 PM PDT 24
Peak memory 209164 kb
Host smart-cdb315df-17f7-4dad-a9ec-a959e3fbd6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601375876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1601375876
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4179154504
Short name T47
Test name
Test status
Simulation time 173847136 ps
CPU time 3.31 seconds
Started Jun 30 05:46:17 PM PDT 24
Finished Jun 30 05:46:21 PM PDT 24
Peak memory 210068 kb
Host smart-ebbec608-6217-4eca-b0e3-71329b321b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179154504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4179154504
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3947477255
Short name T556
Test name
Test status
Simulation time 13860067 ps
CPU time 0.77 seconds
Started Jun 30 05:43:58 PM PDT 24
Finished Jun 30 05:43:59 PM PDT 24
Peak memory 206064 kb
Host smart-1e12efa0-ce96-4c73-b4e9-fee829a9d1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947477255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3947477255
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.585532278
Short name T887
Test name
Test status
Simulation time 110521492 ps
CPU time 2.86 seconds
Started Jun 30 05:43:56 PM PDT 24
Finished Jun 30 05:43:59 PM PDT 24
Peak memory 214728 kb
Host smart-861abb25-d657-49f4-9272-8b9da703be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585532278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.585532278
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3791814652
Short name T509
Test name
Test status
Simulation time 293830303 ps
CPU time 3.75 seconds
Started Jun 30 05:43:58 PM PDT 24
Finished Jun 30 05:44:03 PM PDT 24
Peak memory 208820 kb
Host smart-3f2ebfab-54f9-46d4-a33b-e96c6a452365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791814652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3791814652
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3409787148
Short name T93
Test name
Test status
Simulation time 108170831 ps
CPU time 4.93 seconds
Started Jun 30 05:43:55 PM PDT 24
Finished Jun 30 05:44:00 PM PDT 24
Peak memory 209320 kb
Host smart-5f42de03-4671-4df7-a3a7-b7bbead7bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409787148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3409787148
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3214288430
Short name T259
Test name
Test status
Simulation time 84624829 ps
CPU time 3.38 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:02 PM PDT 24
Peak memory 216996 kb
Host smart-c51d9447-e98c-4dc1-90a1-143f9d6e47fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214288430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3214288430
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3063421507
Short name T903
Test name
Test status
Simulation time 171141815 ps
CPU time 1.87 seconds
Started Jun 30 05:43:59 PM PDT 24
Finished Jun 30 05:44:01 PM PDT 24
Peak memory 206684 kb
Host smart-1d6fbece-6f9d-4d3a-88e0-e6a4c8131840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063421507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3063421507
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4287691112
Short name T299
Test name
Test status
Simulation time 55294337 ps
CPU time 3.65 seconds
Started Jun 30 05:43:58 PM PDT 24
Finished Jun 30 05:44:02 PM PDT 24
Peak memory 209856 kb
Host smart-b8f8f7f9-d5c8-4f91-8d29-dcbde6277f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287691112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4287691112
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.503751390
Short name T480
Test name
Test status
Simulation time 115390398 ps
CPU time 2.45 seconds
Started Jun 30 05:43:59 PM PDT 24
Finished Jun 30 05:44:02 PM PDT 24
Peak memory 206884 kb
Host smart-c79a799c-3805-4bc7-a78d-c0109846693f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503751390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.503751390
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3040446906
Short name T226
Test name
Test status
Simulation time 797221460 ps
CPU time 9.17 seconds
Started Jun 30 05:43:58 PM PDT 24
Finished Jun 30 05:44:08 PM PDT 24
Peak memory 209188 kb
Host smart-8b96c033-1f22-4b7d-a5b5-9833dbc9836c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040446906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3040446906
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3276424054
Short name T526
Test name
Test status
Simulation time 108902253 ps
CPU time 4.47 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:03 PM PDT 24
Peak memory 208552 kb
Host smart-41008bda-51fb-4a74-ba7e-6312b6311470
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276424054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3276424054
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.335966584
Short name T574
Test name
Test status
Simulation time 646537449 ps
CPU time 5.67 seconds
Started Jun 30 05:43:56 PM PDT 24
Finished Jun 30 05:44:03 PM PDT 24
Peak memory 208832 kb
Host smart-426f2034-320d-436d-a4d7-ff6e276dc199
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335966584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.335966584
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.974182925
Short name T378
Test name
Test status
Simulation time 179748754 ps
CPU time 4.93 seconds
Started Jun 30 05:43:58 PM PDT 24
Finished Jun 30 05:44:03 PM PDT 24
Peak memory 214280 kb
Host smart-26b71d94-f4f0-4ee8-b61d-f27ade4ab498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974182925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.974182925
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2332761039
Short name T449
Test name
Test status
Simulation time 53590960 ps
CPU time 1.88 seconds
Started Jun 30 05:43:59 PM PDT 24
Finished Jun 30 05:44:01 PM PDT 24
Peak memory 206952 kb
Host smart-3ba8fd14-4178-40df-9908-7c1269c0b845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332761039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2332761039
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1842421053
Short name T331
Test name
Test status
Simulation time 286912346 ps
CPU time 6.38 seconds
Started Jun 30 05:43:55 PM PDT 24
Finished Jun 30 05:44:02 PM PDT 24
Peak memory 207244 kb
Host smart-37243e03-36c3-4779-babf-c174194965ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842421053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1842421053
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3994839965
Short name T555
Test name
Test status
Simulation time 77749201 ps
CPU time 2.46 seconds
Started Jun 30 05:43:56 PM PDT 24
Finished Jun 30 05:44:00 PM PDT 24
Peak memory 210420 kb
Host smart-160a3c9a-4d74-4372-826b-b566dfb54270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994839965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3994839965
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3576953426
Short name T557
Test name
Test status
Simulation time 17117238 ps
CPU time 0.71 seconds
Started Jun 30 05:44:02 PM PDT 24
Finished Jun 30 05:44:03 PM PDT 24
Peak memory 206068 kb
Host smart-35506235-99c6-4e72-8c07-0bd5d2febf86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576953426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3576953426
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2080122345
Short name T321
Test name
Test status
Simulation time 436285106 ps
CPU time 4.35 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:09 PM PDT 24
Peak memory 218472 kb
Host smart-0224d95f-f3f8-4b65-b4ff-416b22ef313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080122345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2080122345
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2365796387
Short name T708
Test name
Test status
Simulation time 255254670 ps
CPU time 3.4 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:08 PM PDT 24
Peak memory 208660 kb
Host smart-055a2126-447f-42c5-b66f-96e29c5780bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365796387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2365796387
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2826918726
Short name T88
Test name
Test status
Simulation time 131943309 ps
CPU time 5.34 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:10 PM PDT 24
Peak memory 221492 kb
Host smart-1470762b-385d-4fc9-9b78-95d340d85e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826918726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2826918726
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1164265215
Short name T379
Test name
Test status
Simulation time 172742387 ps
CPU time 2.41 seconds
Started Jun 30 05:44:05 PM PDT 24
Finished Jun 30 05:44:07 PM PDT 24
Peak memory 214384 kb
Host smart-7a35b36d-7893-4b65-874f-210955a5686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164265215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1164265215
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3073695695
Short name T481
Test name
Test status
Simulation time 293478068 ps
CPU time 2.72 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 220312 kb
Host smart-94584ca6-ddce-43d2-8717-75a015ca4d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073695695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3073695695
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3352303063
Short name T236
Test name
Test status
Simulation time 455166706 ps
CPU time 5.19 seconds
Started Jun 30 05:44:02 PM PDT 24
Finished Jun 30 05:44:08 PM PDT 24
Peak memory 219136 kb
Host smart-8ac6482f-6b54-440c-b5d8-11e434f4fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352303063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3352303063
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3861136651
Short name T659
Test name
Test status
Simulation time 92525299 ps
CPU time 2.13 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:00 PM PDT 24
Peak memory 208548 kb
Host smart-2bcd8e66-dd7a-4cda-af26-b1479256a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861136651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3861136651
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.418876390
Short name T4
Test name
Test status
Simulation time 34198664 ps
CPU time 2.41 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:00 PM PDT 24
Peak memory 208672 kb
Host smart-998b738a-8259-4411-ac03-f4da4555011d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418876390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.418876390
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.203760800
Short name T679
Test name
Test status
Simulation time 170388169 ps
CPU time 3.17 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:01 PM PDT 24
Peak memory 208464 kb
Host smart-533ae1dd-a7e7-4bb4-acf8-ac48dafb2ac5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203760800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.203760800
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1807925487
Short name T466
Test name
Test status
Simulation time 463505775 ps
CPU time 3.81 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:01 PM PDT 24
Peak memory 207004 kb
Host smart-4464f730-c205-4168-a2ee-1db4260e9150
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807925487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1807925487
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.24888385
Short name T811
Test name
Test status
Simulation time 866605712 ps
CPU time 12.47 seconds
Started Jun 30 05:44:04 PM PDT 24
Finished Jun 30 05:44:17 PM PDT 24
Peak memory 209292 kb
Host smart-a25145ca-5774-49e5-abd4-8a577fb5c3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24888385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.24888385
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3293323258
Short name T857
Test name
Test status
Simulation time 163131170 ps
CPU time 3.84 seconds
Started Jun 30 05:43:57 PM PDT 24
Finished Jun 30 05:44:02 PM PDT 24
Peak memory 208064 kb
Host smart-f20625fa-9493-4bfb-a055-834ecf03d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293323258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3293323258
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2891037008
Short name T188
Test name
Test status
Simulation time 240127894 ps
CPU time 8.71 seconds
Started Jun 30 05:44:03 PM PDT 24
Finished Jun 30 05:44:12 PM PDT 24
Peak memory 214648 kb
Host smart-fa9d98a4-4a5e-42c6-b2b7-83e4d5383609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891037008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2891037008
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1317880045
Short name T307
Test name
Test status
Simulation time 8696566468 ps
CPU time 26.96 seconds
Started Jun 30 05:44:03 PM PDT 24
Finished Jun 30 05:44:30 PM PDT 24
Peak memory 222308 kb
Host smart-34bb993c-2c67-4cc5-b561-6f0570ec573f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317880045 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1317880045
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2392543744
Short name T495
Test name
Test status
Simulation time 566550800 ps
CPU time 4.99 seconds
Started Jun 30 05:44:05 PM PDT 24
Finished Jun 30 05:44:10 PM PDT 24
Peak memory 209780 kb
Host smart-290859af-afb2-4773-8af6-d9ac516fac66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392543744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2392543744
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4059121322
Short name T164
Test name
Test status
Simulation time 187929134 ps
CPU time 2 seconds
Started Jun 30 05:44:03 PM PDT 24
Finished Jun 30 05:44:05 PM PDT 24
Peak memory 209792 kb
Host smart-320cd7ae-1859-469e-8ddc-121d86512c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059121322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4059121322
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2471762407
Short name T579
Test name
Test status
Simulation time 33125572 ps
CPU time 0.79 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 206056 kb
Host smart-42ca4efd-946e-43ce-a086-d54b26b38bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471762407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2471762407
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4158450019
Short name T250
Test name
Test status
Simulation time 170958878 ps
CPU time 3.19 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 209636 kb
Host smart-dc83a681-99d0-4c9d-826f-cdf4943344a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158450019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4158450019
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4163340706
Short name T806
Test name
Test status
Simulation time 68113272 ps
CPU time 2.8 seconds
Started Jun 30 05:44:02 PM PDT 24
Finished Jun 30 05:44:05 PM PDT 24
Peak memory 207460 kb
Host smart-11ae0a1c-efd3-48bc-9094-519752067abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163340706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4163340706
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2192404100
Short name T256
Test name
Test status
Simulation time 58026250 ps
CPU time 3.18 seconds
Started Jun 30 05:44:03 PM PDT 24
Finished Jun 30 05:44:07 PM PDT 24
Peak memory 222432 kb
Host smart-1b768d1b-0ee5-4cc5-b74c-da555fe1115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192404100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2192404100
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.585527751
Short name T518
Test name
Test status
Simulation time 184132360 ps
CPU time 2.08 seconds
Started Jun 30 05:44:01 PM PDT 24
Finished Jun 30 05:44:04 PM PDT 24
Peak memory 214816 kb
Host smart-7a38f421-1bcd-4a12-ad10-473ab8da460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585527751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.585527751
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.377497411
Short name T837
Test name
Test status
Simulation time 235022390 ps
CPU time 5.53 seconds
Started Jun 30 05:44:05 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 214416 kb
Host smart-f3418ebc-4051-423f-a495-1e71da909fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377497411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.377497411
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1097639148
Short name T290
Test name
Test status
Simulation time 391215984 ps
CPU time 4.84 seconds
Started Jun 30 05:44:01 PM PDT 24
Finished Jun 30 05:44:06 PM PDT 24
Peak memory 206792 kb
Host smart-568c1ef3-0af6-43c7-b0b8-5567edba363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097639148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1097639148
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.462662187
Short name T527
Test name
Test status
Simulation time 88945461 ps
CPU time 2.42 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 206992 kb
Host smart-f3c80f6d-52f7-44de-a6ce-937f958f7d9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462662187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.462662187
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1238682541
Short name T445
Test name
Test status
Simulation time 209765975 ps
CPU time 5.89 seconds
Started Jun 30 05:44:05 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 208864 kb
Host smart-a7044217-e21e-4617-b432-782888e337ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238682541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1238682541
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4024740675
Short name T875
Test name
Test status
Simulation time 168759756 ps
CPU time 2.62 seconds
Started Jun 30 05:44:07 PM PDT 24
Finished Jun 30 05:44:09 PM PDT 24
Peak memory 206964 kb
Host smart-d26bfc4c-b825-46bc-ba7d-f7e32c5e821a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024740675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4024740675
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1712345263
Short name T856
Test name
Test status
Simulation time 18136160 ps
CPU time 1.62 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 208260 kb
Host smart-9d741f5e-4bc2-40e3-aeb2-a3b27570f872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712345263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1712345263
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.4044561590
Short name T6
Test name
Test status
Simulation time 204480998 ps
CPU time 2.74 seconds
Started Jun 30 05:44:02 PM PDT 24
Finished Jun 30 05:44:05 PM PDT 24
Peak memory 206732 kb
Host smart-84c7c460-6267-4c2e-bdb6-aa22d67a987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044561590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4044561590
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3871186435
Short name T338
Test name
Test status
Simulation time 741722843 ps
CPU time 18.13 seconds
Started Jun 30 05:44:05 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 208032 kb
Host smart-0a3e9111-4186-49f6-a74c-44e3401895f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871186435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3871186435
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1568960970
Short name T723
Test name
Test status
Simulation time 139918435 ps
CPU time 3.12 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 210220 kb
Host smart-e951c62d-8c69-4acd-befc-9de0e28573f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568960970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1568960970
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1874416878
Short name T508
Test name
Test status
Simulation time 24834958 ps
CPU time 0.82 seconds
Started Jun 30 05:44:12 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 206036 kb
Host smart-9deabd47-9c5f-4aff-9a59-a828a96e48eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874416878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1874416878
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.459872935
Short name T252
Test name
Test status
Simulation time 190542471 ps
CPU time 4.18 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:16 PM PDT 24
Peak memory 215620 kb
Host smart-f4301316-a8be-429d-aeb7-e7e3a8fada6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459872935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.459872935
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.683956643
Short name T469
Test name
Test status
Simulation time 147504271 ps
CPU time 2.66 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 216740 kb
Host smart-83156b79-ae4d-4222-a5d3-192f157076d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683956643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.683956643
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.876076372
Short name T622
Test name
Test status
Simulation time 1063641640 ps
CPU time 3.94 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 207432 kb
Host smart-1d8924cb-1747-46d2-96b5-5ab03e1965a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876076372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.876076372
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.715493929
Short name T99
Test name
Test status
Simulation time 3866007057 ps
CPU time 36.82 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:45 PM PDT 24
Peak memory 222540 kb
Host smart-dacb4f65-c56a-46fa-957a-cedc2d71bc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715493929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.715493929
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3601635784
Short name T318
Test name
Test status
Simulation time 648490717 ps
CPU time 3.71 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:16 PM PDT 24
Peak memory 207044 kb
Host smart-eff66af3-ed2d-4712-a559-39388bb190a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601635784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3601635784
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2520284519
Short name T215
Test name
Test status
Simulation time 63128374 ps
CPU time 3.14 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 214320 kb
Host smart-6d6b96d0-7934-4ae1-9b26-f0e75e101d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520284519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2520284519
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4088236861
Short name T551
Test name
Test status
Simulation time 286779945 ps
CPU time 6.33 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:18 PM PDT 24
Peak memory 208124 kb
Host smart-4a96d03f-c821-40df-b57b-0d13db4647d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088236861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4088236861
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4251663185
Short name T384
Test name
Test status
Simulation time 68369936 ps
CPU time 2.91 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 206900 kb
Host smart-4a3fafce-a832-4840-8d9d-7772bd691550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251663185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4251663185
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4111829089
Short name T350
Test name
Test status
Simulation time 183397695 ps
CPU time 2.9 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 207540 kb
Host smart-11ce5de4-655f-4715-ae23-e266dd8e0ddd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111829089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4111829089
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3576265942
Short name T592
Test name
Test status
Simulation time 667593180 ps
CPU time 5.84 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:18 PM PDT 24
Peak memory 208000 kb
Host smart-6185d675-5c40-49f4-a259-e5dae04215aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576265942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3576265942
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1743565040
Short name T626
Test name
Test status
Simulation time 779921339 ps
CPU time 8.59 seconds
Started Jun 30 05:44:12 PM PDT 24
Finished Jun 30 05:44:21 PM PDT 24
Peak memory 208852 kb
Host smart-f921d88b-8ce6-4bbf-a7bd-848f7752e140
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743565040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1743565040
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2934473522
Short name T573
Test name
Test status
Simulation time 45369185 ps
CPU time 2.23 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 208468 kb
Host smart-a02ceda8-5de1-4ba4-940f-ebba02c031bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934473522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2934473522
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1276685172
Short name T718
Test name
Test status
Simulation time 146144991 ps
CPU time 3.32 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 207884 kb
Host smart-911749a6-8f95-4c35-977a-14b87865c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276685172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1276685172
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.520535913
Short name T366
Test name
Test status
Simulation time 154743434 ps
CPU time 4.03 seconds
Started Jun 30 05:44:13 PM PDT 24
Finished Jun 30 05:44:17 PM PDT 24
Peak memory 209980 kb
Host smart-8e3e0f5c-29f2-4432-beb7-0cedab86df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520535913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.520535913
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4020004556
Short name T889
Test name
Test status
Simulation time 37912418 ps
CPU time 2.05 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 208596 kb
Host smart-90704bfb-94d0-4133-9178-28e21f57dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020004556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4020004556
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.905612969
Short name T786
Test name
Test status
Simulation time 35633205 ps
CPU time 0.91 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 206040 kb
Host smart-3ac7582b-92fe-47d5-93ac-e46b25869d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905612969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.905612969
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4137697008
Short name T144
Test name
Test status
Simulation time 410293792 ps
CPU time 22.54 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:33 PM PDT 24
Peak memory 215004 kb
Host smart-37169725-34ba-4df3-b48c-0796052361e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137697008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4137697008
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.827524275
Short name T275
Test name
Test status
Simulation time 1836345417 ps
CPU time 9.55 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:18 PM PDT 24
Peak memory 208564 kb
Host smart-130ccdf5-678a-4980-a271-2cfa29f3fbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827524275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.827524275
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3965016280
Short name T41
Test name
Test status
Simulation time 424545737 ps
CPU time 3.01 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 221588 kb
Host smart-ff034272-b668-4029-a20f-c7e3d71810ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965016280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3965016280
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2565313970
Short name T582
Test name
Test status
Simulation time 408250763 ps
CPU time 5.03 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:17 PM PDT 24
Peak memory 213960 kb
Host smart-41e2cd8b-6b84-4ba9-bd68-39892ba17f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565313970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2565313970
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4087250072
Short name T69
Test name
Test status
Simulation time 97152068 ps
CPU time 3.34 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 209808 kb
Host smart-f04cda87-c3a6-40b2-a78f-9d64b9d9da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087250072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4087250072
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.608357339
Short name T478
Test name
Test status
Simulation time 421177103 ps
CPU time 4.74 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 208868 kb
Host smart-67795466-f9cb-4c54-a02b-c338c806323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608357339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.608357339
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.516551853
Short name T780
Test name
Test status
Simulation time 1184866868 ps
CPU time 22.4 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:34 PM PDT 24
Peak memory 209064 kb
Host smart-a2aeeaa3-d4c6-454c-9b70-1c48022d0af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516551853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.516551853
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1552967057
Short name T549
Test name
Test status
Simulation time 953238355 ps
CPU time 23 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:33 PM PDT 24
Peak memory 208860 kb
Host smart-eda55962-3226-4e3a-a7ce-f4815f5be04a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552967057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1552967057
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.172294265
Short name T605
Test name
Test status
Simulation time 98585285 ps
CPU time 2.01 seconds
Started Jun 30 05:44:08 PM PDT 24
Finished Jun 30 05:44:11 PM PDT 24
Peak memory 208728 kb
Host smart-6bb25b80-aef2-4131-956f-6e12feb4b458
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172294265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.172294265
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3953905632
Short name T798
Test name
Test status
Simulation time 805031723 ps
CPU time 27.19 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:38 PM PDT 24
Peak memory 208260 kb
Host smart-7b44f435-dad1-4e6b-b6ea-1ae1f62bf9c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953905632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3953905632
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.4129290753
Short name T530
Test name
Test status
Simulation time 157911148 ps
CPU time 3.38 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:13 PM PDT 24
Peak memory 208940 kb
Host smart-56a41d57-c0c9-4ff7-9556-80b7989c0370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129290753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.4129290753
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1824410311
Short name T550
Test name
Test status
Simulation time 389471988 ps
CPU time 4.37 seconds
Started Jun 30 05:44:09 PM PDT 24
Finished Jun 30 05:44:15 PM PDT 24
Peak memory 208412 kb
Host smart-8e4d8071-8dff-499c-b78b-c3dc3eefcbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824410311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1824410311
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2454520464
Short name T501
Test name
Test status
Simulation time 49293107 ps
CPU time 0.89 seconds
Started Jun 30 05:44:12 PM PDT 24
Finished Jun 30 05:44:14 PM PDT 24
Peak memory 206004 kb
Host smart-2347e278-9601-4487-84e7-5f4e09cf503a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454520464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2454520464
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3247131359
Short name T200
Test name
Test status
Simulation time 1360513494 ps
CPU time 27.21 seconds
Started Jun 30 05:44:10 PM PDT 24
Finished Jun 30 05:44:39 PM PDT 24
Peak memory 221244 kb
Host smart-01adbd6d-e981-47a1-b781-9be20a795bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247131359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3247131359
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1853334059
Short name T249
Test name
Test status
Simulation time 270606197 ps
CPU time 8.97 seconds
Started Jun 30 05:44:12 PM PDT 24
Finished Jun 30 05:44:22 PM PDT 24
Peak memory 214400 kb
Host smart-d51c6d5d-4259-4523-a66b-3a6afed9d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853334059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1853334059
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2675142866
Short name T395
Test name
Test status
Simulation time 215017551 ps
CPU time 3.25 seconds
Started Jun 30 05:44:11 PM PDT 24
Finished Jun 30 05:44:15 PM PDT 24
Peak memory 210124 kb
Host smart-6101a2a6-0476-439a-89b9-778d6034e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675142866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2675142866
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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