Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T3	1		T43	1		T44	1
auto[OpGenId]	13	1			T61	1		T62	1		T126	1
auto[OpGenSwOut]	20	1			T4	1		T43	1		T51	1
auto[OpGenHwOut]	32	1			T4	1		T5	1		T6	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1619	1			T46	1		T43	1		T51	1
auto[StInit]	118	1			T3	1		T46	1		T43	1
auto[StCreatorRootKey]	57	1			T4	1		T46	1		T43	2
auto[StOwnerIntKey]	44	1			T4	1		T64	1		T39	1
auto[StOwnerKey]	34	1			T35	1		T4	1		T46	1
auto[StDisabled]	517	1			T34	1		T61	1		T4	5
auto[StInvalid]	50	1			T13	1		T26	1		T47	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3414

1

T1

1

T2

1

T3

1

auto[1]

115

1

T3

1

T61

1

T4

2

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1615	1			T46	1		T43	1		T51	1
auto[StReset]	auto[1]	4	1			T22	1		T23	1		T49	1
auto[StInit]	auto[0]	50	1			T46	1		T36	1		T57	1
auto[StInit]	auto[1]	68	1			T3	1		T43	1		T51	1
auto[StCreatorRootKey]	auto[0]	35	1			T46	1		T43	1		T53	1
auto[StCreatorRootKey]	auto[1]	22	1			T4	1		T43	1		T76	1
auto[StOwnerIntKey]	auto[0]	31	1			T64	1		T39	1		T56	1
auto[StOwnerIntKey]	auto[1]	13	1			T4	1		T57	1		T58	1
auto[StOwnerKey]	auto[0]	28	1			T35	1		T4	1		T46	1
auto[StOwnerKey]	auto[1]	6	1			T5	1		T44	1		T196	1
auto[StDisabled]	auto[0]	515	1			T34	1		T4	5		T46	6
auto[StDisabled]	auto[1]	2	1			T61	1		T197	1		-	-
auto[StInvalid]	auto[0]	50	1			T13	1		T26	1		T47	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpAdvance]]	0	1	1
[auto[StDisabled]]	[auto[OpGenSwOut]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	2	1			T49	1		T50	1		-	-
auto[StReset]	auto[OpGenSwOut]	1	1			T22	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T23	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	28	1			T3	1		T43	1		T45	1
auto[StInit]	auto[OpGenId]	5	1			T62	1		T29	1		T166	1
auto[StInit]	auto[OpGenSwOut]	12	1			T51	1		T5	1		T60	1
auto[StInit]	auto[OpGenHwOut]	23	1			T5	1		T6	1		T45	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T27	1		T28	1		T115	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T126	1		T198	1		T199	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T4	1		T43	1		T76	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T124	1		T200	1		T201	1
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T57	1		T183	1		T69	1
auto[StOwnerIntKey]	auto[OpGenId]	4	1			T202	1		T203	1		T204	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T4	1		T58	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	3	1			T44	1		T196	1		T205	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T5	1		T206	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T207	1		-	-		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T61	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T197	1		-	-		-	-