Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5011

1

T1

4

T2

1

T3

1

auto[1]

602

1

T2

1

T14

5

T16

6

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5011

1

T1

4

T2

1

T3

1

auto[1]

602

1

T2

1

T14

5

T16

6

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5047

1

T1

4

T3

1

T13

4

auto[1]

566

1

T2

2

T16

4

T34

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5047

1

T1

4

T3

1

T13

4

auto[1]

566

1

T2

2

T16

4

T34

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	431	1			T17	2		T61	1		T4	2
auto[OpGenId]	1209	1			T1	3		T2	1		T18	1
auto[OpGenSwOut]	1198	1			T13	1		T16	3		T17	3
auto[OpGenHwOut]	2697	1			T1	1		T2	1		T3	1
auto[OpDisable]	78	1			T4	1		T5	1		T6	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	431	1			T17	2		T61	1		T4	2
auto[OpGenId]	1209	1			T1	3		T2	1		T18	1
auto[OpGenSwOut]	1198	1			T13	1		T16	3		T17	3
auto[OpGenHwOut]	2697	1			T1	1		T2	1		T3	1
auto[OpDisable]	78	1			T4	1		T5	1		T6	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5038

1

T1

4

T3

1

T13

4

auto[1]

575

1

T2

2

T15

2

T16

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5038

1

T1

4

T3

1

T13

4

auto[1]

575

1

T2

2

T15

2

T16

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5326

1

T1

4

T2

2

T3

1

auto[1]

287

1

T16

2

T75

7

T135

5

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1934	1			T1	1		T2	2		T3	1
auto[1]	784	1			T15	2		T18	1		T34	2
auto[2]	760	1			T13	1		T14	1		T15	1
auto[3]	719	1			T1	2		T13	1		T14	2
auto[4]	336	1			T15	1		T17	1		T19	1
auto[5]	359	1			T17	1		T19	1		T20	1
auto[6]	370	1			T1	1		T14	1		T15	1
auto[7]	351	1			T13	1		T14	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1416	1			T1	1		T13	1		T14	2
clear_one[1]	784	1			T15	2		T18	1		T34	2
clear_one[2]	760	1			T13	1		T14	1		T15	1
clear_one[3]	719	1			T1	2		T13	1		T14	2
clear_none	1934	1			T1	1		T2	2		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1090	1			T3	1		T15	1		T16	1
auto[StInit]	689	1			T14	1		T15	1		T17	4
auto[StCreatorRootKey]	611	1			T2	1		T14	1		T15	1
auto[StOwnerIntKey]	548	1			T1	1		T14	1		T15	1
auto[StOwnerKey]	476	1			T14	1		T15	1		T19	1
auto[StDisabled]	1925	1			T1	3		T2	1		T14	4
auto[StInvalid]	274	1			T13	4		T26	5		T47	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1090	1			T3	1		T15	1		T16	1
auto[StInit]	689	1			T14	1		T15	1		T17	4
auto[StCreatorRootKey]	611	1			T2	1		T14	1		T15	1
auto[StOwnerIntKey]	548	1			T1	1		T14	1		T15	1
auto[StOwnerKey]	476	1			T14	1		T15	1		T19	1
auto[StDisabled]	1925	1			T1	3		T2	1		T14	4
auto[StInvalid]	274	1			T13	4		T26	5		T47	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T212	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	189	1			T34	1		T189	1		T4	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	184	1			T16	1		T189	1		T46	4
auto[0]	auto[StReset]	auto[OpGenHwOut]	273	1			T3	1		T15	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	53	1			T61	1		T46	1		T51	1
auto[0]	auto[StInit]	auto[OpGenId]	87	1			T46	1		T43	1		T5	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	110	1			T4	1		T46	1		T43	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	178	1			T14	1		T20	1		T4	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	19	1			T4	1		T6	3		T176	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	44	1			T2	1		T118	1		T4	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T18	1		T75	1		T64	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	90	1			T43	1		T81	1		T213	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	18	1			T4	1		T46	1		T51	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T1	1		T51	1		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T5	1		T45	1		T214	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	67	1			T14	1		T5	1		T45	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T123	1		T104	1		T215	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T51	1		T75	1		T176	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T190	1		T216	1		T96	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T193	1		T72	1		T6	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T51	1		T195	1		T45	1
auto[0]	auto[StDisabled]	auto[OpGenId]	57	1			T4	2		T51	1		T5	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T16	2		T4	1		T5	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	180	1			T2	1		T14	1		T16	2
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T4	1		T68	1		T217	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T84	1		T218	1		T219	1
auto[0]	auto[StInvalid]	auto[OpGenId]	28	1			T26	2		T47	1		T52	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T48	1		T220	1		T221	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T13	1		T47	1		T220	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T222	1		T45	1		T223	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	24	1			T34	1		T51	1		T5	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	55	1			T34	1		T51	1		T44	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T30	1		T210	1		T224	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T179	1		T122	1		T111	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T5	1		T225	1		T166	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T15	1		T226	1		T227	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T46	1		T228	2		T225	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	18	1			T104	1		T229	1		T230	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T46	1		T231	1		T232	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T15	1		T61	1		T193	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T80	1		T233	1		T234	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T74	1		T195	1		T235	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T46	1		T194	1		T236	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T193	1		T6	1		T237	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T238	3		T239	1		-	-
auto[1]	auto[StOwnerKey]	auto[OpGenId]	24	1			T74	1		T194	1		T122	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T62	1		T96	1		T240	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T20	1		T5	1		T241	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T46	1		T5	1		T104	1
auto[1]	auto[StDisabled]	auto[OpGenId]	77	1			T61	1		T4	2		T6	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T18	1		T4	1		T51	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	176	1			T4	2		T46	1		T237	1
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T45	2		T242	1		T243	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T244	1		T245	1		T246	2
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T79	1		T220	1		T221	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T247	2		T248	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T48	1		T55	1		T249	1
auto[2]	auto[StReset]	auto[OpGenId]	22	1			T34	1		T46	1		T5	2
auto[2]	auto[StReset]	auto[OpGenSwOut]	16	1			T17	1		T4	1		T44	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T4	1		T44	1		T6	2
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T136	1		T120	1		T238	1
auto[2]	auto[StInit]	auto[OpGenId]	5	1			T64	1		T250	1		T251	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	17	1			T17	1		T4	1		T6	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	29	1			T46	1		T25	1		T192	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T45	1		T136	1		T179	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T6	1		T252	1		T96	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T46	1		T5	1		T183	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T19	1		T64	1		T227	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T120	1		T253	1		T254	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T46	1		T51	1		T255	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T44	1		T256	1		T111	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T72	1		T191	1		T257	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T112	1		T253	1		T258	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	17	1			T5	1		T259	1		T251	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T61	1		T45	1		T260	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T14	1		T4	1		T261	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	23	1			T51	1		T75	1		T236	1
auto[2]	auto[StDisabled]	auto[OpGenId]	60	1			T18	1		T118	1		T46	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T4	1		T46	1		T43	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	178	1			T15	1		T16	1		T18	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T111	1		T262	1		T115	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	10	1			T48	2		T263	1		T84	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T26	1		T47	1		T263	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T13	1		T82	1		T264	2
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T26	1		T82	1		T265	1
auto[3]	auto[StReset]	auto[OpGenId]	23	1			T4	1		T45	1		T223	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	17	1			T4	1		T5	1		T45	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	43	1			T4	1		T46	1		T6	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T17	1		T51	1		T183	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T24	1		T266	1		T267	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	6	1			T268	1		T124	1		T69	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T19	1		T51	1		T178	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T269	1		T182	1		T270	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T6	1		T271	1		T272	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T112	1		T33	1		T273	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T16	1		T20	1		T237	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T274	1		T275	1		T276	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T62	1		T125	1		T113	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T34	1		T51	1		T6	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T19	1		T261	1		T277	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T6	1		T45	1		T272	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T140	1		T125	1		T278	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T64	1		T113	1		T279	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T15	1		T19	1		T6	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	21	1			T195	1		T269	2		T280	1
auto[3]	auto[StDisabled]	auto[OpGenId]	65	1			T1	2		T46	1		T45	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T61	1		T46	1		T51	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T14	2		T15	1		T20	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T6	1		T68	1		T205	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T52	1		T94	1		T264	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T26	1		T264	1		T83	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T85	1		T265	1		T83	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T13	1		T79	1		T281	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T282	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T45	1		T140	1		T283	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	4	1			T51	1		T284	1		T285	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T76	1		T177	1		T180	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T209	1		T286	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T86	1		T287	1		T288	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T17	1		T70	2		T289	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T114	1		T278	1		T290	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T114	1		T291	2		T87	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T6	1		T292	1		T293	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T45	1		T223	1		T58	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T261	1		T111	1		T294	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T64	1		T295	1		T228	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T81	1		T114	1		T200	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T6	1		T272	1		T296	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T15	1		T241	1		T294	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T297	1		T86	1		T298	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	3	1			T46	1		T199	1		T299	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T136	1		T300	1		T228	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T136	1		T301	1		T178	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T46	1		T176	1		T122	4
auto[4]	auto[StDisabled]	auto[OpGenId]	36	1			T43	1		T51	2		T5	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T5	1		T176	1		T122	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T19	1		T193	1		T5	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T223	1		T66	1		T302	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T303	1		T304	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T305	1		T306	1		T307	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T265	1		T308	1		T309	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T47	1		T52	1		T310	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T45	1		T283	1		T112	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T214	1		T311	1		T244	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	32	1			T51	1		T6	1		T190	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T17	1		T120	1		T112	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T312	1		T205	1		T313	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	10	1			T46	1		T269	1		T96	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T193	1		T257	1		T180	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T5	1		T135	1		T314	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T242	1		T250	1		T315	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T135	1		T112	1		T316	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T189	1		T72	1		T191	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T125	1		T287	1		T206	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T135	1		T182	1		T279	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T231	1		T198	1		T317	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T20	1		T301	1		T227	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T51	1		T175	1		T318	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T51	1		T135	2		T319	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T5	1		T213	1		T192	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T6	2		T96	1		T112	1
auto[5]	auto[StDisabled]	auto[OpGenId]	17	1			T51	1		T5	1		T6	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T6	2		T125	2		T267	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T19	1		T51	1		T5	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T6	1		T320	1		T321	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T47	1		T322	1		T245	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T55	1		T303	1		T323	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T324	1		T325	1		T326	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T263	1		T322	1		T305	1
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T123	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T45	1		T183	1		T166	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T4	1		T6	1		T327	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T180	1		T328	1		T90	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T123	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T329	1		T70	1		T330	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T190	1		T252	1		T317	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T5	1		T331	1		T243	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T279	1		T332	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T4	1		T195	1		T123	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T214	1		T334	1		T284	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T14	1		T123	1		T335	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T336	1		T337	1		T224	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T51	1		T5	1		T6	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T121	1		T242	1		T125	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T61	1		T43	1		T213	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T46	1		T6	1		T255	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T4	1		T5	1		T179	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T191	1		T227	1		T96	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T216	1		T338	1		T339	1
auto[6]	auto[StDisabled]	auto[OpGenId]	20	1			T5	1		T45	1		T194	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T5	1		T6	1		T222	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T1	1		T15	1		T74	1
auto[6]	auto[StDisabled]	auto[OpDisable]	8	1			T5	1		T231	1		T69	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T48	1		T94	1		T82	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T82	1		T311	1		T340	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T52	1		T220	1		T310	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T85	2		T305	1		T341	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T74	1		T57	1		T85	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T264	1		T196	1		T342	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	24	1			T331	1		T328	1		T266	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T343	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	8	1			T140	1		T214	1		T125	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T96	1		T344	1		T185	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T345	1		T346	1		T90	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T136	1		T140	1		T202	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T51	1		T64	1		T347	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T34	1		T46	1		T348	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T5	1		T45	1		T121	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T75	1		T136	1		T349	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T4	1		T104	1		T259	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T297	1		T170	1		T288	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T190	1		T350	1		T96	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T185	1		T351	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T222	1		T352	1		T353	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T45	2		T111	1		T115	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T226	1		T90	1		T294	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T214	1		T125	1		T354	1
auto[7]	auto[StDisabled]	auto[OpGenId]	31	1			T135	1		T45	1		T111	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T4	1		T5	1		T195	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T14	1		T15	1		T118	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T355	1		T356	1		T357	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T323	1		T358	2		T326	1
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T84	1		T341	1		T306	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T52	1		T221	1		T305	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T13	1		T94	1		T324	2

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1416

1

T1

1

T13

1

T14

2

clear_one[1]

auto[0]

auto[0]

auto[0]

441

1

T15

1

T34

2

T4

2

clear_one[1]

auto[0]

auto[0]

auto[1]

138

1

T15

1

T18

1

T61

2

clear_one[1]

auto[0]

auto[1]

auto[0]

174

1

T20

1

T4

1

T46

1

clear_one[1]

auto[0]

auto[1]

auto[1]

31

1

T4

2

T46

1

T68

2

clear_one[2]

auto[0]

auto[0]

auto[0]

444

1

T13

1

T17

2

T34

1

clear_one[2]

auto[0]

auto[0]

auto[1]

136

1

T15

1

T193

1

T72

2

clear_one[2]

auto[1]

auto[0]

auto[0]

133

1

T14

1

T16

1

T19

2

clear_one[2]

auto[1]

auto[0]

auto[1]

47

1

T18

2

T51

3

T75

7

clear_one[3]

auto[0]

auto[0]

auto[0]

427

1

T1

2

T13

1

T15

2

clear_one[3]

auto[0]

auto[1]

auto[0]

122

1

T34

1

T20

2

T61

1

clear_one[3]

auto[1]

auto[0]

auto[0]

133

1

T14

2

T16

1

T19

2

clear_one[3]

auto[1]

auto[1]

auto[0]

37

1

T75

1

T112

1

T58

2

clear_none

auto[0]

auto[0]

auto[0]

1398

1

T1

1

T3

1

T13

1

clear_none

auto[0]

auto[0]

auto[1]

136

1

T4

1

T193

2

T72

2

clear_none

auto[0]

auto[1]

auto[0]

124

1

T20

2

T191

1

T300

1

clear_none

auto[0]

auto[1]

auto[1]

24

1

T2

1

T4

1

T43

1

clear_none

auto[1]

auto[0]

auto[0]

158

1

T14

2

T18

1

T19

1

clear_none

auto[1]

auto[0]

auto[1]

40

1

T51

1

T45

2

T179

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T16

1

T195

1

T104

1

clear_none

auto[1]

auto[1]

auto[1]

23

1

T2

1

T16

3

T45

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1361	1			T1	1		T13	1		T14	2
clear_all	auto[1]	55	1			T135	5		T136	2		T176	3
clear_one[1]	auto[0]	736	1			T15	2		T18	1		T34	2
clear_one[1]	auto[1]	48	1			T122	1		T228	2		T238	8
clear_one[2]	auto[0]	696	1			T13	1		T14	1		T15	1
clear_one[2]	auto[1]	64	1			T75	6		T136	1		T120	6
clear_one[3]	auto[0]	690	1			T1	2		T13	1		T14	2
clear_one[3]	auto[1]	29	1			T269	3		T295	2		T280	4
clear_none	auto[0]	1843	1			T1	1		T2	2		T3	1
clear_none	auto[1]	91	1			T16	2		T75	1		T120	4