Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11829

1

T1

9

T2

12

T3

4

auto[Attestation]

8005

1

T1

4

T2

10

T3

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2880	1			T1	4		T2	4		T3	2
auto[Aes]	3601	1			T2	4		T3	1		T14	8
auto[Kmac]	3522	1			T1	2		T2	3		T13	2
auto[Otbn]	3540	1			T1	1		T2	5		T15	10

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8122	1			T1	8		T2	8		T3	1
auto[OpGenId]	6291	1			T1	6		T2	6		T3	2
auto[OpGenSwOut]	6214	1			T1	4		T2	8		T3	2
auto[OpGenHwOut]	7329	1			T1	3		T2	8		T3	1
auto[OpDisable]	158	1			T4	1		T46	3		T5	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11219

1

T1

8

T2

13

T3

1

auto[OpDoneFail]

16895

1

T1

13

T2

17

T3

5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6898	1			T1	1		T2	1		T3	4
auto[StInit]	3923	1			T1	3		T2	3		T3	2
auto[StCreatorRootKey]	3303	1			T1	1		T2	6		T14	2
auto[StOwnerIntKey]	2965	1			T1	2		T2	3		T14	2
auto[StOwnerKey]	2577	1			T1	3		T2	3		T14	2
auto[StDisabled]	8448	1			T1	11		T2	14		T14	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	349	1			T3	1		T13	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T17	1		T77	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T18	1		T119	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	78	1			T119	1		T4	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T61	1		T46	1		T51	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	246	1			T1	2		T18	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	350	1			T17	1		T34	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	111	1			T26	1		T46	2		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T4	3		T51	3		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T51	1		T135	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T61	1		T5	3		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	234	1			T2	1		T119	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	343	1			T13	1		T34	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	95	1			T4	2		T46	1		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T2	1		T189	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T2	1		T118	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T119	1		T5	3		T111	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	244	1			T16	1		T4	2		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	317	1			T16	2		T117	1		T119	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	107	1			T4	1		T5	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T34	1		T46	2		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T61	1		T5	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	71	1			T1	1		T18	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	230	1			T16	1		T18	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	92	1			T4	2		T46	3		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T3	1		T17	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	90	1			T2	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	78	1			T34	1		T117	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T51	2		T190	1		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	222	1			T2	1		T18	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	89	1			T4	4		T46	3		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	131	1			T17	1		T26	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T4	2		T46	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T18	1		T46	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	72	1			T77	1		T4	1		T135	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	234	1			T2	1		T77	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	75	1			T4	1		T46	3		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	86	1			T1	1		T4	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	69	1			T34	1		T117	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	63	1			T46	1		T51	2		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T4	1		T5	2		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	213	1			T117	1		T61	1		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	74	1			T4	3		T46	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T16	1		T18	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	83	1			T46	1		T43	1		T75	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T46	2		T44	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T34	2		T5	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	240	1			T2	2		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	277	1			T16	1		T34	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	81	1			T46	1		T51	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T6	1		T64	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T61	1		T51	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T1	1		T34	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T2	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T3	1		T16	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	110	1			T14	1		T17	2		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	117	1			T16	1		T18	1		T189	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	100	1			T51	1		T5	3		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	99	1			T2	1		T16	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	300	1			T2	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	514	1			T13	1		T17	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T20	1		T4	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T2	1		T189	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	99	1			T61	1		T191	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	93	1			T16	1		T34	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	317	1			T1	1		T16	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	487	1			T15	2		T34	2		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T17	1		T26	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	132	1			T189	1		T193	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T15	1		T35	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T5	1		T72	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	313	1			T15	3		T34	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T4	3		T46	3		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	95	1			T17	1		T43	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T5	1		T64	1		T194	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T4	1		T46	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T34	1		T4	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	202	1			T1	1		T2	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	69	1			T4	2		T43	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T19	1		T26	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	104	1			T14	1		T19	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	123	1			T14	1		T16	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	74	1			T14	1		T5	2		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	293	1			T14	3		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T4	4		T51	4		T5	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	145	1			T17	1		T35	2		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	116	1			T20	1		T189	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T34	1		T20	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T4	1		T44	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	278	1			T20	2		T118	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	75	1			T4	2		T46	2		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	129	1			T2	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	98	1			T2	1		T15	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T4	1		T193	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T15	1		T18	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T2	1		T15	1		T16	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T18	1		T119	2		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	722	1			T1	2		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	231	1			T61	1		T4	3		T51	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	702	1			T2	1		T17	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T2	2		T118	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	700	1			T13	1		T16	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	215	1			T1	1		T18	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	666	1			T16	3		T18	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	212	1			T34	1		T117	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	447	1			T2	2		T3	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	204	1			T18	1		T77	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	465	1			T2	1		T17	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	173	1			T34	1		T117	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	391	1			T1	1		T117	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	232	1			T34	2		T46	3		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	438	1			T2	2		T16	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	178	1			T1	1		T34	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	579	1			T2	1		T16	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	296	1			T2	1		T16	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	914	1			T2	1		T3	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	291	1			T2	1		T16	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	978	1			T1	1		T13	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	299	1			T15	1		T35	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	946	1			T15	5		T17	1		T34	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	163	1			T34	1		T4	2		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	372	1			T1	1		T2	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	287	1			T14	3		T16	1		T19	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	502	1			T14	3		T18	1		T19	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T34	1		T20	2		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	503	1			T17	1		T20	2		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	263	1			T2	1		T15	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	481	1			T2	2		T15	2		T16	2