Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3069

1

T1

4

T2

6

T13

4

auto[1]

278

1

T16

2

T75

13

T135

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T4	3		T46	3		T51	1
auto[134217728:268435455]	101	1			T1	1		T2	2		T26	1
auto[268435456:402653183]	106	1			T16	1		T43	1		T6	1
auto[402653184:536870911]	114	1			T16	1		T17	1		T18	1
auto[536870912:671088639]	81	1			T4	1		T51	2		T5	1
auto[671088640:805306367]	96	1			T17	1		T189	1		T4	1
auto[805306368:939524095]	106	1			T26	2		T43	1		T51	1
auto[939524096:1073741823]	115	1			T4	2		T46	2		T5	1
auto[1073741824:1207959551]	111	1			T2	1		T4	1		T46	1
auto[1207959552:1342177279]	104	1			T13	1		T16	1		T46	1
auto[1342177280:1476395007]	103	1			T13	1		T46	2		T75	1
auto[1476395008:1610612735]	103	1			T2	1		T16	1		T18	1
auto[1610612736:1744830463]	102	1			T1	1		T2	1		T13	1
auto[1744830464:1879048191]	96	1			T16	1		T17	1		T4	1
auto[1879048192:2013265919]	106	1			T61	1		T4	1		T43	1
auto[2013265920:2147483647]	110	1			T2	1		T5	3		T6	2
auto[2147483648:2281701375]	104	1			T1	1		T16	1		T4	1
auto[2281701376:2415919103]	109	1			T34	2		T4	1		T46	1
auto[2415919104:2550136831]	119	1			T46	1		T51	1		T5	2
auto[2550136832:2684354559]	115	1			T16	1		T34	1		T26	1
auto[2684354560:2818572287]	110	1			T46	1		T51	1		T5	4
auto[2818572288:2952790015]	100	1			T18	1		T34	1		T46	1
auto[2952790016:3087007743]	97	1			T4	1		T46	1		T5	1
auto[3087007744:3221225471]	106	1			T26	1		T46	2		T51	4
auto[3221225472:3355443199]	121	1			T16	1		T34	1		T4	1
auto[3355443200:3489660927]	96	1			T34	1		T4	2		T46	1
auto[3489660928:3623878655]	103	1			T26	1		T46	2		T51	1
auto[3623878656:3758096383]	98	1			T34	1		T61	1		T189	1
auto[3758096384:3892314111]	106	1			T4	2		T46	1		T75	1
auto[3892314112:4026531839]	101	1			T13	1		T51	1		T195	1
auto[4026531840:4160749567]	92	1			T61	1		T46	1		T5	2
auto[4160749568:4294967295]	111	1			T1	1		T16	1		T34	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T4	3		T46	3		T51	1
auto[0:134217727]	auto[1]	9	1			T135	1		T122	1		T296	1
auto[134217728:268435455]	auto[0]	93	1			T1	1		T2	2		T26	1
auto[134217728:268435455]	auto[1]	8	1			T214	1		T343	2		T385	1
auto[268435456:402653183]	auto[0]	98	1			T16	1		T43	1		T6	1
auto[268435456:402653183]	auto[1]	8	1			T121	1		T296	1		T215	1
auto[402653184:536870911]	auto[0]	106	1			T16	1		T17	1		T18	1
auto[402653184:536870911]	auto[1]	8	1			T75	1		T228	1		T215	1
auto[536870912:671088639]	auto[0]	78	1			T4	1		T51	2		T5	1
auto[536870912:671088639]	auto[1]	3	1			T389	1		T288	1		T403	1
auto[671088640:805306367]	auto[0]	91	1			T17	1		T189	1		T4	1
auto[671088640:805306367]	auto[1]	5	1			T122	1		T367	1		T384	1
auto[805306368:939524095]	auto[0]	97	1			T26	2		T43	1		T51	1
auto[805306368:939524095]	auto[1]	9	1			T269	1		T397	1		T296	1
auto[939524096:1073741823]	auto[0]	110	1			T4	2		T46	2		T5	1
auto[939524096:1073741823]	auto[1]	5	1			T123	1		T258	1		T384	2
auto[1073741824:1207959551]	auto[0]	103	1			T2	1		T4	1		T46	1
auto[1073741824:1207959551]	auto[1]	8	1			T176	3		T388	1		T404	1
auto[1207959552:1342177279]	auto[0]	92	1			T13	1		T16	1		T46	1
auto[1207959552:1342177279]	auto[1]	12	1			T176	1		T122	1		T238	1
auto[1342177280:1476395007]	auto[0]	95	1			T13	1		T46	2		T76	2
auto[1342177280:1476395007]	auto[1]	8	1			T75	1		T238	1		T383	1
auto[1476395008:1610612735]	auto[0]	94	1			T2	1		T16	1		T18	1
auto[1476395008:1610612735]	auto[1]	9	1			T123	1		T214	1		T238	1
auto[1610612736:1744830463]	auto[0]	101	1			T1	1		T2	1		T13	1
auto[1610612736:1744830463]	auto[1]	1	1			T228	1		-	-		-	-
auto[1744830464:1879048191]	auto[0]	88	1			T16	1		T17	1		T4	1
auto[1744830464:1879048191]	auto[1]	8	1			T122	2		T238	1		T215	1
auto[1879048192:2013265919]	auto[0]	93	1			T61	1		T4	1		T43	1
auto[1879048192:2013265919]	auto[1]	13	1			T122	1		T238	1		T280	1
auto[2013265920:2147483647]	auto[0]	105	1			T2	1		T5	3		T6	2
auto[2013265920:2147483647]	auto[1]	5	1			T385	1		T258	1		T330	1
auto[2147483648:2281701375]	auto[0]	93	1			T1	1		T16	1		T4	1
auto[2147483648:2281701375]	auto[1]	11	1			T135	1		T269	1		T238	1
auto[2281701376:2415919103]	auto[0]	100	1			T34	2		T4	1		T46	1
auto[2281701376:2415919103]	auto[1]	9	1			T75	2		T214	1		T343	1
auto[2415919104:2550136831]	auto[0]	110	1			T46	1		T51	1		T5	2
auto[2415919104:2550136831]	auto[1]	9	1			T75	1		T280	1		T386	1
auto[2550136832:2684354559]	auto[0]	98	1			T34	1		T26	1		T4	1
auto[2550136832:2684354559]	auto[1]	17	1			T16	1		T75	4		T136	1
auto[2684354560:2818572287]	auto[0]	105	1			T46	1		T51	1		T5	4
auto[2684354560:2818572287]	auto[1]	5	1			T120	1		T122	1		T343	1
auto[2818572288:2952790015]	auto[0]	94	1			T18	1		T34	1		T46	1
auto[2818572288:2952790015]	auto[1]	6	1			T122	1		T389	2		T258	1
auto[2952790016:3087007743]	auto[0]	87	1			T4	1		T46	1		T5	1
auto[2952790016:3087007743]	auto[1]	10	1			T295	2		T214	1		T366	1
auto[3087007744:3221225471]	auto[0]	100	1			T26	1		T46	2		T51	4
auto[3087007744:3221225471]	auto[1]	6	1			T214	1		T282	1		T388	1
auto[3221225472:3355443199]	auto[0]	104	1			T34	1		T4	1		T43	1
auto[3221225472:3355443199]	auto[1]	17	1			T16	1		T176	1		T269	1
auto[3355443200:3489660927]	auto[0]	86	1			T34	1		T4	2		T46	1
auto[3355443200:3489660927]	auto[1]	10	1			T75	1		T384	1		T351	1
auto[3489660928:3623878655]	auto[0]	89	1			T26	1		T46	2		T51	1
auto[3489660928:3623878655]	auto[1]	14	1			T75	1		T120	2		T122	1
auto[3623878656:3758096383]	auto[0]	90	1			T34	1		T61	1		T189	1
auto[3623878656:3758096383]	auto[1]	8	1			T75	1		T120	1		T176	2
auto[3758096384:3892314111]	auto[0]	96	1			T4	2		T46	1		T6	2
auto[3758096384:3892314111]	auto[1]	10	1			T75	1		T176	1		T122	1
auto[3892314112:4026531839]	auto[0]	95	1			T13	1		T51	1		T195	1
auto[3892314112:4026531839]	auto[1]	6	1			T269	1		T386	1		T389	1
auto[4026531840:4160749567]	auto[0]	80	1			T61	1		T46	1		T5	2
auto[4026531840:4160749567]	auto[1]	12	1			T122	2		T296	2		T343	1
auto[4160749568:4294967295]	auto[0]	102	1			T1	1		T16	1		T34	1
auto[4160749568:4294967295]	auto[1]	9	1			T176	1		T384	1		T314	1